JP2016171455A - Solid state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image pickup device which can image an image having a wide dynamic range.SOLUTION: According to one embodiment, a solid state image pickup device having a first semiconductor chip and a second semiconductor chip is provided. In the first semiconductor chip, a plurality of pixel groups are arranged. The pixel group includes a plurality of pixels. On the second semiconductor chip, the first semiconductor chip is laminated. In the second semiconductor chip, a plurality of pixel control blocks are arranged. The pixel control block includes an A/D conversion circuit. The A/D conversion circuit is electrically connected to an output of the pixel group.SELECTED DRAWING: Figure 5

Description

  The present embodiment relates to a solid-state imaging device.

  Solid-state imaging devices such as CMOS sensors are used in various applications such as digital still cameras, video movies, and surveillance cameras. In applications such as digital cameras, video movies, and surveillance cameras, the following imaging characteristics are required. That is, it is possible to capture with a high S / N when capturing a dark subject, and to have an image output resolution even when capturing a sufficiently bright subject. As described above, when a dark subject is imaged and the S / N is good and a bright subject can be imaged, an image with a wide dynamic range can be captured and viewed with human eyes. There is an advantage that a natural reproduction similar to the above can be realized. However, there is a strong demand for reducing the size of the imaging optical system, while a demand for high resolution is also increasing at the same time, and the pixel size tends to be reduced. Therefore, it is possible to obtain an image having a wide dynamic range as described above. It has become difficult.

Japanese Patent No. 4277216

  An object of one embodiment is to provide a solid-state imaging device that can capture an image with a wide dynamic range.

  According to one embodiment, a solid-state imaging device having a first semiconductor chip and a second semiconductor chip is provided. A plurality of pixel groups are arranged on the first semiconductor chip. The pixel group includes a plurality of pixels. The first semiconductor chip is stacked on the second semiconductor chip. The second semiconductor chip has a plurality of pixel control blocks. The pixel control block includes an A / D conversion circuit. The A / D conversion circuit is electrically connected to the output of the pixel group.

1 is a cross-sectional view illustrating a configuration of an imaging system to which a solid-state imaging device according to an embodiment is applied. 1 is a block diagram showing a configuration of an imaging system to which a solid-state imaging device according to an embodiment is applied. 1 is a circuit diagram showing a configuration of a solid-state imaging device according to an embodiment. Sectional drawing which shows the laminated structure of the solid-state imaging device concerning embodiment. FIG. 3 is an exploded perspective view illustrating a stacked configuration of the solid-state imaging device according to the embodiment. 1 is a block diagram illustrating a configuration of a solid-state imaging device according to an embodiment. The figure which shows the sub-frame accumulation | storage period in embodiment. The figure which shows the structure of the pixel and pixel control block in embodiment. FIG. 3 is a circuit diagram illustrating a configuration of a pixel in the embodiment. The wave form diagram which shows the operation | movement of the pixel in embodiment. The figure which shows operation | movement of the pixel control block in embodiment. The figure which shows operation | movement of the pixel control block in embodiment. The figure which shows operation | movement of the pixel control block in embodiment. The figure which shows operation | movement of the pixel control block in embodiment. The disassembled perspective view which shows the laminated structure of the solid-state imaging device concerning the modification of embodiment. The circuit diagram which shows the structure of the shared several pixel in the other modification of embodiment. The wave form diagram which shows operation | movement of the shared several pixel in the other modification of embodiment. Sectional drawing which shows the laminated structure of the solid-state imaging device concerning the other modification of embodiment. The disassembled perspective view which shows the laminated structure of the solid-state imaging device concerning the other modification of embodiment. The block diagram which shows the structure of the solid-state imaging device in the other modification of embodiment. The figure which shows the structure of the pixel in the other modification of embodiment, a pixel control block, and a logic block. The disassembled perspective view which shows the laminated structure of the solid-state imaging device concerning the other modification of embodiment.

  Exemplary embodiments of a solid-state imaging device will be described below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(Embodiment)
A solid-state imaging device according to an embodiment will be described. The solid-state imaging device is applied to the imaging system shown in FIGS. 1 and 2, for example. 1 and 2 are diagrams illustrating a schematic configuration of an imaging system. In FIG. 1, the optical axis is indicated by OP.

  The imaging system 1 may be, for example, a digital camera, a digital video camera, or the like, or a camera module applied to an electronic device (for example, a mobile terminal with a camera). As shown in FIG. 2, the imaging system 1 includes an imaging unit 2 and a post-processing unit 3. The imaging unit 2 is, for example, a camera module. The imaging unit 2 includes an imaging optical system 4 and a solid-state imaging device 5. The post-processing unit 3 includes an ISP (Image Signal Processor) 6, a storage unit 7, and a display unit 8.

  The imaging optical system 4 includes a photographing lens 47, a half mirror 43, a mechanical shutter 46, a lens 44, a prism 45, and a viewfinder 48. The photographing lens 47 includes photographing lenses 47a and 47b, a diaphragm (not shown), and a lens driving mechanism 47c. The aperture is disposed between the photographic lens 47a and the photographic lens 47b, and adjusts the amount of light guided to the photographic lens 47b. In FIG. 1, the case where the photographing lens 47 includes two photographing lenses 47a and 47b is exemplarily shown, but the photographing lens 47 may include a large number of photographing lenses.

  The solid-state imaging device 5 is disposed on the planned imaging plane of the photographic lens 47. For example, the photographic lens 47 refracts incident light, guides it to the imaging surface of the solid-state imaging device 5 via the half mirror 43 and the mechanical shutter 46, and places an image of the subject on the imaging surface (imaging region IR) of the solid-state imaging device 5. Form. The solid-state imaging device 5 generates an image signal corresponding to the subject image.

  As shown in FIG. 3, the solid-state imaging device 5 includes an image sensor 10 and a signal processing circuit 11. FIG. 3 is a diagram illustrating a circuit configuration of the solid-state imaging device. The image sensor 10 may be, for example, a CMOS image sensor or other amplification type solid-state imaging device. The image sensor 10 includes a pixel array 12 and a peripheral circuit 13. The peripheral circuit 13 selects a pixel in the pixel array 12 and reads a signal from the selected pixel. The peripheral circuit 13 transfers the read signal to the signal processing circuit 11.

  In the solid-state imaging device 5, for example, when capturing a moving image, it is desired to improve the quality of a reproduced image. For example, the solid-state imaging device 5 is used in various applications such as a digital still camera, a video movie, and a surveillance camera. In applications such as digital cameras, video movies, and surveillance cameras, the following imaging characteristics are required.

  That is, it is possible to capture with a high S / N when capturing a dark subject, and to have an image output resolution even when capturing a sufficiently bright subject. As described above, when a dark subject is imaged and the S / N is good and a bright subject can be imaged, an image with a wide dynamic range can be captured and viewed with human eyes. There is an advantage that a natural reproduction similar to the above can be realized. However, the demand for reducing the chip size is strong, while the demand for increasing the number of pixels is also increasing at the same time, and the pixel size tends to be reduced. Therefore, it is difficult to obtain an image having a wide dynamic range as described above. It is becoming.

  Therefore, in the present embodiment, the pixel array 12 is divided into a plurality of pixel groups, and electrode junctions can be arranged under each pixel group by stacking chips using substrate bonding, and charge accumulation is performed for each pixel group. By controlling the period and / or the signal gain, both the reduction of the chip size and the increase of the dynamic range are achieved.

  Specifically, as shown in FIGS. 4 and 5, the solid-state imaging device 5 includes a semiconductor chip CH1, a semiconductor chip CH2, and a semiconductor chip CHsp. FIG. 4 is a cross-sectional view illustrating a stacked configuration of the solid-state imaging device 5. FIG. 5 is an exploded perspective view showing a stacked configuration of the solid-state imaging device 5.

  The semiconductor chip CH1 is stacked on the semiconductor chip CH2. As shown in FIG. 4, the semiconductor chip CH1 and the semiconductor chip CH2 are bonded by substrate bonding. The semiconductor chip CH1 and the semiconductor chip CH2 are bonded to each other on the surface side, and the electrodes EL can be bonded (for example, Cu—Cu bonding). Each of the semiconductor chip CH1 and the semiconductor chip CH2 has a multilayer wiring structure formed on the surface side, and has an electrode EL whose surface is exposed on the uppermost wiring layer.

  Of the components in the solid-state imaging device 5 shown in FIG. 3, the pixel array 12 is arranged on the semiconductor chip CH1. That is, since the semiconductor chip CH1 is not provided with other components (peripheral circuit 13 and signal processing circuit 11) in the solid-state imaging device 5, the chip size is suppressed while reducing the pixel size even when the number of pixels is increased. Can be easily reduced. In other words, the chip size can be easily reduced while ensuring the pixel array size of each pixel P.

  For example, as shown in FIG. 5, a plurality of pixel groups PG (1,1) to PG (p, q) are arranged on the semiconductor chip CH1. The plurality of pixel groups PG (1,1) to PG (p, q) are arranged in the row direction and the column direction in the pixel array 12, and constitute, for example, p rows and q columns. p and q are integers of 2 or more, respectively. Each pixel group PG (1,1) has a plurality of pixels P (1,1) to P (m, n). The plurality of pixels P (1,1) to P (m, n) are arranged in the row direction and the column direction in the pixel group PG, and form m rows and n columns, for example. m and n are integers of 2 or more, respectively, and FIG. 5 illustrates the case where m = 4 and n = 3. Although not shown, each pixel P has a back-illuminated pixel configuration (see FIG. 4).

  Of the components in the solid-state imaging device 5 shown in FIG. 3, the peripheral circuit 13 is arranged on the semiconductor chip CH2. For example, a plurality of pixel control blocks PBK (1, 1) to PBK (p, q) are arranged on the semiconductor chip CH2. The plurality of pixel control blocks PBK (1,1) to PBK (p, q) correspond to the plurality of pixel groups PG (1,1) to PG (p, q). The plurality of pixel control blocks PBK (1,1) to PBK (p, q) are arranged in the row direction and the column direction in the peripheral circuit 13, and constitute, for example, p rows and q columns. p and q are integers of 2 or more, respectively.

  Of the components in the solid-state imaging device 5 shown in FIG. 3, the signal processing circuit 11 is arranged on the semiconductor chip CHsp. For example, as shown in FIG. 5, a logic circuit 11a, a frame memory 11b, and an I / O circuit 11c are arranged in the semiconductor chip CHsp. The logic circuit 11a supplies a control signal to each pixel control block PBK, and the frame memory 11b holds data (one frame image data) transferred from each pixel control block PBK in accordance with the control signal.

  In this configuration, as shown in FIG. 6, it is possible to improve the degree of parallelism between the control for each pixel P and the signal reading from each pixel P. FIG. 6 is a block diagram illustrating a configuration of the solid-state imaging device. That is, the pixel control block PBK can sequentially read signals from the selected pixel P among the plurality of pixels P in the corresponding pixel group PG, and can control each of the plurality of pixels P in the pixel group PG. . Further, control operations by the plurality of pixel control blocks PBK can be performed in parallel with each other.

  Thereby, the charge accumulation period of the pixel P and / or the period required for feedback control of the gain of the signal of the pixel P can be easily shortened according to the signal read from the pixel P in the pixel control block PBK. For example, the 1-frame accumulation period Tf provided for obtaining the 1-frame image shown in FIG. 7A is divided into N (N is an integer of 2 or more) as shown in FIG. The accumulation period (Tf) / N. The pixel control block PBK can control each pixel P in the pixel group PG in units of subframe periods (Tf) / N, and divides one frame of data into N subframes of data. Can be read out. FIG. 7A shows a one-frame storage period, and FIG. 7B shows a sub-frame storage period.

  For example, the pixel P and the pixel control block PBK are configured as shown in FIG. FIG. 8 is a diagram illustrating the configuration of the pixel P and the pixel control block PBK.

  The pixel P includes a photoelectric conversion unit 50, a charge storage unit 60, and a pixel amplification circuit 70. The photoelectric conversion unit 50 generates a charge corresponding to light. The charge storage unit 60 stores the charge generated by the photoelectric conversion unit 50. The pixel amplifier circuit 70 generates and amplifies a voltage corresponding to the charge stored in the charge storage unit 60, and outputs a signal corresponding to the amplified voltage.

  The output terminal of each pixel P in the pixel group PG can be shared, and each pixel P has a shared output terminal (not shown), an electrode EL of the semiconductor chip CH1, and an electrode EL ( 4) and can be connected to the input terminal of the pixel control block PBK. Further, the control terminal of each pixel P in the pixel group PG can be shared, and each pixel P has a shared control terminal (not shown), an electrode EL of the semiconductor chip CH1, and an electrode EL ( It can be connected to the supply terminal of the control signal of the pixel control block PBK via (see FIG. 4).

  The pixel P is configured so as to be able to output a signal (with a non-destructive readout structure) while keeping the accumulated signal (charge) in a non-destructive state. That is, when the pixel amplifier circuit 70 generates a voltage corresponding to the charge stored in the charge storage unit 60, the charge storage unit 60 can continue to store the charge. The charge storage unit 60 can continue the charge storage operation until instructed by the control signal 1 to release the charge storage from the pixel control block PBK.

  For example, the pixel P includes a photoelectric conversion unit 50, a charge storage unit 60, and a pixel amplification circuit 70 as illustrated in FIG. FIG. 9 is a circuit diagram illustrating a configuration of the pixel P. The photoelectric conversion unit 50 includes a photodiode PD.

  The charge storage unit 60 includes a charge holding unit 61, a transfer unit 62, and a reset unit 63. The charge holding unit 61 includes a storage diode SD.

  The reset unit 63 resets the charge in the charge holding unit 61. The reset unit 63 includes, for example, a reset transistor M2, and an active level (for example, H level) control signal φReset2 (control signal 1) from the pixel control block PBK via the feedback line 141 (see FIG. 8) and the reset control line 65. Is turned on when the signal is received by the gate to reset the charge of the charge holding unit 61. Thereby, the charge accumulation operation of the charge accumulation unit 60 can be completed. For example, in the case illustrated in FIG. 10, the charge accumulation operation of the charge accumulation unit 60 can be completed by changing φReset2 (control signal 1) from L to H at timing t3. FIG. 10 is a waveform diagram showing the operation of the pixel P. For example, when φReset2 is changed from L → H at the end of the signal accumulation period of the subframe, the charge accumulation operation of the charge accumulation unit 60 can be completed.

  The reset unit 63 receives a non-active level (for example, L level) control signal φReset2 (control signal 1) from the pixel control block PBK via the feedback line 141 (see FIG. 8) and the reset control line 65 at the gate. By turning off, the resetting of the charge of the charge holding unit 61 is cancelled. Thereby, the charge accumulation operation of the charge accumulation unit 60 can be started. For example, in the case illustrated in FIG. 10, the charge accumulation operation of the charge accumulation unit 60 can be started by changing φReset2 (control signal 1) from H → L at timing t4. For example, the charge accumulation operation of the charge accumulation unit 60 can be started by changing φReset2 from H → L at the start of the signal accumulation period of the subframe.

  As indicated by a broken line with respect to the control signal φReset2 (control signal 1) in FIG. 10, when the control signal φReset2 (control signal 1) is maintained at the L level, the charge holding unit 61 is not reset, and the charge accumulation unit 60 charge accumulation operations are continued.

  The transfer unit 62 transfers the charge of the photoelectric conversion unit 50 to the charge holding unit 61. The transfer unit 62 transfers the charge of the photoelectric conversion unit 50 to the charge holding unit 61 during a period when the charge holding unit 61 is not reset. The transfer unit 62 includes, for example, a transfer transistor M1, and when the gate receives an active level control signal φRead (control signal 3) from the pixel control block PBK via the feedback line 147 (see FIG. 8) and the transfer control line 66. When turned on, the charge of the photodiode PD is transferred to the storage diode SD. The transfer unit 62 is electrically turned off from the photodiode PD and the storage diode SD by turning off when receiving the non-active level control signal φRead at the gate. For example, in the case shown in FIG. 10, the charge of the photoelectric conversion unit 50 can be transferred to the charge holding unit 61 by changing φRead (control signal 3) from L to H at timing t1, and φRead at timing t2. When (control signal 3) changes from H → L, transfer of the charge of the photoelectric conversion unit 50 to the charge holding unit 61 can be completed. For example, the charge of the photoelectric conversion unit 50 can be transferred to the charge holding unit 61 to be completed just before the end of the signal accumulation period of the subframe.

  As illustrated in FIG. 9, the pixel amplifier circuit 70 includes a charge-voltage conversion unit 71, a transmission unit 77, an output unit 72, a selection unit 73, and a reset unit 74.

  The transmission unit 77 transmits a charge corresponding to the charge held in the charge holding unit 61 to the charge voltage conversion unit 71. Transmission unit 77 includes a floating gate FG. The floating gate FG has one end capacitively coupled to the charge holding unit 61 and the other end electrically connected to the charge voltage conversion unit 71. The charge-voltage converter 71 converts the transmitted charge into a voltage. The charge voltage conversion unit 71 includes a floating diffusion FD. The floating diffusion FD can hold a voltage using its parasitic capacitance. The output unit 72 outputs a signal corresponding to the voltage of the charge-voltage conversion unit 71 to the signal line SL. The output unit 72 includes an amplifying transistor M3, and performs a source follower operation together with a current source (not shown) connected to the signal line SL so that a signal corresponding to the voltage of the floating diffusion FD received at the gate is supplied to the source side. Output to the signal line SL. That is, since the signal is capacitively transmitted from the charge holding unit 61 to the transmission unit 77 and transmitted from the transmission unit 77 to the charge-voltage conversion unit 71, the charge is generated while the signal is output from the output unit 72 to the signal line SL. The signal (charge) held in the holding unit 61 can be maintained in a non-destructive state. In addition, since the charge holding unit 61 is separated from the output unit 72 (amplification transistor M3) in a DC manner as compared with the charge-voltage conversion unit 71, the charge holding unit 61 is not easily affected by noise associated with the operation of the output unit 72. Thereby, the S / N ratio of the signal output to the signal line SL can be improved.

  The selection unit 73 puts the pixel P into a selected state or a non-selected state. The selection unit 73 includes, for example, a selection transistor M4, and when the gate receives an active level (for example, H level) control signal φAddress1 from the pixel control block PBK via a feedback line (not shown) and the selection control line 76. The pixel P is selected by turning it on, and turned off when the gate receives a non-active level (for example, L level) control signal φAddress1. The reset unit 74 resets the charge / voltage conversion unit 71. The reset unit 74 includes, for example, a reset transistor M5, and when a gate receives an active level (for example, H level) control signal φReset1 from the pixel control block PBK via a feedback line (not shown) and the reset control line 78. The charge voltage conversion unit 71 is reset by turning it on, and the reset of the charge voltage conversion unit 71 is released by turning it off when a non-active level (for example, L level) control signal φReset1 is received at the gate.

  The pixel amplifier circuit 70 is configured to be able to control its gain. While the pixel amplifier circuit 70 is instructed by the control signal 2 to maintain the steady state gain from the pixel control block PBK, the gain is controlled to the first gain. While the pixel amplifier circuit 70 is instructed by the control signal 2 to lower the gain from the steady state from the pixel control block PBK, the gain is controlled to the second gain. The second gain is a gain lower than the first gain.

  The pixel amplifier circuit 70 further includes a gain adjustment unit 75 as shown in FIG. The gain adjustment unit 75 adjusts the gain of the transmission unit 77 (floating gate FG). The gain adjustment unit 75 includes a switch 751 and a capacitive element 752. The switch 751 connects one end of the capacitor 752 to the floating gate FG. When the switch 751 is turned on, one end of the capacitor 752 is connected to the floating gate FG, the load capacity of the floating gate FG is increased, and the gain of the floating gate FG is decreased. When the switch 751 is turned off, one end of the capacitor 752 is electrically cut off from the floating gate FG, and the load capacity of the floating gate FG is reduced to increase the gain of the floating gate FG.

  The switch 751 includes, for example, a transistor M6, and receives a non-active level (for example, L level) control signal φGain (control signal 2) from the pixel control block PBK via the feedback line 143 (see FIG. 8) and the gain control line 79. By turning off when received by the gate, the gain of the floating gate FG is increased. As a result, the gain of the pixel amplifier circuit 70 is controlled to the first gain.

  The switch 751 receives, for example, an active level (for example, H level) control signal φGain (control signal 2) from the pixel control block PBK via the feedback line 143 (see FIG. 8) and the gain control line 79 at the gate. By turning on, the gain of the floating gate FG is lowered. As a result, the gain of the pixel amplifier circuit 70 is controlled to the second gain.

  The operation of the pixel P will be described in detail. FIG. 10 shows an example of operation driving of the pixel P. At the operation timing shown in FIG. 10, before the signal electrons are read from the light receiving unit (photodiode PD) to the storage diode SD, the reset transistor M5 (φReset1) is turned on to change the potential of the floating diffusion FD to the reference potential. Then, the reset transistor M5 (φReset1) is turned off again. Thereafter, the reference signal level is read from the floating diffusion FD via the amplification transistor M3. Thereafter, the transfer transistor M1 (φRead) is turned on to transfer the charge of the photodiode PD to the storage diode SD. A signal output in a state where signal charges are accumulated in the storage diode SD is read out through the pixel amplifier circuit 70. By taking the difference between the signal read in the subsequent circuit and the reference signal level, the output offset noise of the amplification transistor M3 and the kTC noise generated in the floating diffusion FD are removed. After the signal reading is completed, the control circuit 140 (FIG. 8) performs a signal level test. As a result, if it is determined that the signal accumulation in the pixel P is completed and the signal charge is discharged, the reset transistor Control signal 1 (φReset2) is applied so that M2 is turned on, and the signal charge accumulated in storage diode SD is discharged. At this time, the control signal 3 (φRead) is applied to the transfer transistor M1 so as to be turned off. When it is determined by the signal test in the control circuit 140 that the signal accumulation in the pixel P is continued, the control signal 1 (φReset2) that turns off the reset transistor M2 is applied and accumulated in the storage diode SD. The signal charge is held in the storage diode SD as it is, and signal accumulation in the storage diode SD is continued without destroying the signal charge.

  Further, when it is determined that the signal accumulation is continued, the following operation may be performed. That is, when the signal level is verified in the control circuit 140 (FIG. 8) and it is determined that the signal accumulation in the pixel P is continued as a result, the control signal 1 (φReset2) that turns off the reset transistor M2 However, the signal charge stored in the storage diode SD may be transferred to the photodiode PD and the signal storage may be continued in the photodiode PD. During the period from t3 to t4, an H potential is applied to the transfer transistor M1 (φRead) so as to be in an ON state (a dotted waveform of φRead shown in FIG. 10). In this way, the signal charge accumulated in the storage diode SD is transferred to the photodiode PD, and signal accumulation is continued in the photodiode PD after the transfer transistor M1 is turned off.

  Returning to FIG. 8, the pixel control block PBK includes a gain amplifier 110, an A / D conversion circuit (ADC) 120, a pixel block memory 130, and a control circuit 140. The gain amplifier 110 is connected to the input terminal of the pixel control block PBK via the signal line 111 and is connected to the input of the ADC 120 via the signal line 112. The ADC 120 is connected to the output of the gain amplifier 110 via the signal line 112 and is connected to the pixel block memory 130 via the signal line 121. That is, the ADC 120 is electrically connected to the output terminal of the pixel group PG. The gain amplifier 110 is electrically connected between the output terminal of the pixel group PG and the ADC 120. The pixel block memory 130 is connected to the output of the ADC 120 via the signal line 121, and is connected to the input of the control circuit 140 via the signal line 131. The pixel block memory 130 stores the value of the signal (digital signal) output from the ADC 120 for each subframe accumulation period.

  The control circuit 140 is connected to the pixel block memory 130 via the signal line 131. The control circuit 140 is connected to the charge storage unit 60 of each pixel P of the pixel group PG via the feedback line 141. The control circuit 140 supplies a control signal 1 (φReset2) to the charge storage unit 60 of the pixel P via the feedback line 141. The control circuit 140 is connected to the pixel amplification circuit 70 of each pixel P of the pixel group PG via the feedback line 143. The control circuit 140 supplies a control signal 2 (φGain) to the pixel amplification circuit 70 of the pixel P via the feedback line 143. The control circuit 140 is connected to the charge storage unit 60 of each pixel P of the pixel group PG via the feedback line 147. The control circuit 140 supplies a control signal 3 (φRead) to the charge storage unit 60 of the pixel P via the feedback line 147. The control circuit 140 is connected to the gain amplifier 110 via the feedback line 144. The control circuit 140 is connected to the ADC 120 via the feedback line 142. The control circuit 140 is connected to the logic circuit 11a via the control line 145. The control circuit 140 receives a control signal from the logic circuit 11a via the control line 145. The control circuit 140 is connected to the frame memory 11b via the data line 146. The control circuit 140 outputs data to the frame memory 11b via the data line 146.

  The control circuit 140 includes a comparator 140a and a logic circuit 140b. The comparator 140a is configured to compare signal values for each subframe accumulation period stored in the pixel block memory 130 with each other. Alternatively, the comparator 140a may be configured to compare a signal value for each subframe accumulation period stored in the pixel block memory 130 with a reference value. The logic circuit 140b generates the control signal 1, the control signal 2, and the control signal 3 according to the comparison result of the comparator 140a.

  For example, as shown in FIG. 11, the control circuit 140 can perform subject motion detection determination and adaptively control the charge accumulation operation of the pixel P. FIG. 11 is a diagram illustrating the operation of the pixel control block PBK. The control circuit 140 controls the ADC 120 so as to adjust the bit gradation to an appropriate gradation according to the number N of subframes within one frame accumulation period. Further, the pixel control block PBK reads a signal from the pixel P in a non-destructive state. The control circuit 140 detects the movement of the subject by comparing the signal value in the subframe accumulation period of interest with the signal value in the previous subframe accumulation period. The control circuit 140 obtains a signal representative value (for example, median value) for each pixel control block for each of the subframe accumulation period of interest and the previous subframe accumulation period. The control circuit 140 determines that the subject is stationary if the difference between the two is within a predetermined range, and determines that the subject is moving if the difference between the two is outside the predetermined range. The subject motion detection determination is performed in parallel between the plurality of pixel control blocks in the solid-state imaging device 5.

  The control circuit 140 of the pixel control block PBK in which the motion is detected instructs the control signal 1 to cancel the charge accumulation, and completes the charge accumulation operation of the charge accumulation unit 60 of each pixel P. Further, the control circuit 140 stores each signal of each subframe accumulation period in the frame memory 11b separately until the movement stops. Accordingly, the charge accumulation operation can be repeatedly performed in the sub-frame accumulation period shorter than the one-frame accumulation period for the area in which the movement in the entire image is detected. Can be improved. That is, sub-frame data with a short signal accumulation time and no motion blur can be sequentially output.

  The control circuit 140 of the pixel control block PBK whose motion is not detected instructs the control signal 1 to continue the charge accumulation, and continues the charge accumulation operation of the charge accumulation unit 60 of each pixel P. The control circuit 140 overwrites the signal of each subframe accumulation period on the frame memory 11b until motion is detected. However, when the signal of any pixel P is saturated, the control circuit 140 instructs the control signal 1 to cancel the charge accumulation, and completes the charge accumulation operation of the charge accumulation unit 60 of each pixel P. Thereby, the detection accuracy of the subject motion detection determination can be increased.

  Alternatively, for example, as illustrated in FIG. 12, the control circuit 140 can perform dynamic range constraint determination for signal readout and adaptively control the charge accumulation operation of the pixel P. FIG. 12 is a diagram illustrating the operation of the pixel control block PBK. FIG. 12 illustrates the case where the number of subframes N = 8. At the timing when (Tf) / 8 has elapsed from the start of the frame accumulation period Tf, the control circuit 140 compares the signal value with the reference value. The reference value is a reference value corresponding to the maximum input range of the ADC 120.

  When the signal value is equal to or greater than the reference value (for example, in case 1), the control circuit 140 determines that there is no room in the signal reading dynamic range, and instructs the control signal 1 to cancel the charge accumulation, The charge accumulation operation of the charge accumulation unit 60 of each pixel P is completed.

  When the signal value is less than the reference value (for example, in cases 2 and 3), the control circuit 140 determines that there is a margin in the dynamic range of signal readout and instructs the control signal 1 to continue the charge accumulation. Then, the charge accumulation operation of the charge accumulation unit 60 of each pixel P is continued. Accordingly, the charge accumulation period can be extended without being restricted by the dynamic range of any one of the photoelectric conversion unit 50, the charge accumulation unit 60, and the signal line SL (see FIG. 8). Can improve. Further, since the dynamic range constraint determination of signal readout is performed and the charge accumulation operation of the pixel P is adaptively controlled for each pixel control block PBK, each pixel is compared with the case where the charge accumulation period is equally controlled on the screen. An appropriate charge accumulation period can be set for each control block PBK. In other words, since the charge accumulation period can be extended in the pixel that captures the low-light subject, the S / N of the low-light subject in the reproduced image is improved. As a result, wide dynamic range and high S / N can be realized at the same time.

  In this case, the control circuit 140 may estimate how much room is available. The control circuit 140 compares the value obtained by multiplying the signal value by N times the number of subframes (in this case, 8 times) with the reference value. When the value obtained by multiplying the signal value by N is less than the reference value, the control circuit 140 determines that there is a margin in the dynamic range of signal readout over one frame accumulation period, and performs signal readout until the final subframe accumulation period. You may stop. Further, when the reference value is 1 / K of the maximum input range of the ADC 120 (K is an integer of 2 or more), signal reading is stopped over the K frame accumulation period, and a signal is output at the end of the K frame accumulation period. It is good also as operation to read out.

  At this time, the control circuit 140 may change the bit gradation of the ADC 120 for each pixel control block PBK depending on the number of subframes to be read. For example, the bit gradation may be lowered when the number of subframe readings is large and the signal amount is small with respect to the input range of the ADC 120.

  Alternatively, for example, as illustrated in FIG. 13, the control circuit 140 can perform dynamic range constraint determination for signal readout and adaptively control the gain of the pixel amplification circuit 70 of the pixel P and the gain of the gain amplifier 110. FIG. 13 is a diagram illustrating the operation of the pixel control block PBK.

  The control circuit 140 compares the output signal during the subframe accumulation period with the reference value. When the control circuit 140 determines that the signal is larger than the maximum input range of the ADC 120 (see FIG. 12) at the end of one frame accumulation period according to the comparison result, the control circuit 140 uses the control signal 1 to indicate the charge accumulation unit 60 of each pixel P. The charge accumulation operation is completed (see FIG. 8), and the gain of the pixel amplifier circuit 70 is decreased from the first gain to the second gain by the control signal 1, and the voltage amplification gain of the gain amplifier 110 is decreased. Do at least one.

  For example, as in case 4 indicated by a solid line in FIG. 14, when the signal level reaches the maximum input range of the ADC 120 in a quarter of one frame accumulation period Tf, the charge accumulation unit 60 of each pixel P is controlled by the control signal 1. The charge accumulation operation is completed (see FIG. 8), and the gain of the pixel amplification circuit 70 is changed from the first gain to the second gain by the control signal 1 so that the gain of the signal becomes 1/3 of the current gain. And at least one of lowering the voltage amplification gain of the gain amplifier 110 is performed. FIG. 14 is a diagram illustrating the operation of the pixel control block PBK. As a result, it is possible to reach the maximum input range of the ADC 120 at the end of one frame accumulation period, as in the case 4 ′ shown by the alternate long and short dash line in FIG. 14. Then, at the start of the next one frame accumulation period, the charge accumulation operation of the charge accumulation unit 60 of each pixel P is completed by the control signal 1 (see FIG. 8), and the signal gain is reduced to ¼ of the current gain. Thus, at least one of lowering the gain of the pixel amplifier circuit 70 from the first gain to the second gain and lowering the voltage amplification gain of the gain amplifier 110 is performed by the control signal 1. As a result, in the next one frame accumulation period, the maximum input range of the ADC 120 can be reached at the end of the one frame accumulation period, as in case 6 indicated by a solid line in FIG.

  For example, as in case 5 indicated by a solid line in FIG. 14, when the signal level reaches the maximum input range of the ADC 120 in a half of one frame accumulation period Tf, the charge accumulation unit 60 of each pixel P is controlled by the control signal 1. (See FIG. 8) and the signal gain is maintained. As a result, the maximum input range of the ADC 120 can be reached at the end of one frame accumulation period, as in the case 5 ′ indicated by the alternate long and short dash line in FIG. 14. Then, at the start of the next one frame accumulation period, the charge accumulation operation of the charge accumulation unit 60 of each pixel P is completed by the control signal 1 (see FIG. 8), and the signal gain is reduced to ½ of the current gain. Thus, at least one of lowering the gain of the pixel amplifier circuit 70 from the first gain to the second gain and lowering the voltage amplification gain of the gain amplifier 110 is performed by the control signal 1. As a result, in the next one frame accumulation period, the maximum input range of the ADC 120 can be reached at the end of the one frame accumulation period, as in case 6 indicated by a solid line in FIG.

  This allows the pixel P to perform a charge accumulation operation without being restricted by the dynamic range of any one of the photoelectric conversion unit 50, the charge accumulation unit 60, and the signal line SL (see FIG. 8). Almost all signal charges obtained by photoelectric conversion can be used. As a result, a signal with a wide dynamic range can be obtained. In addition, since the dynamic range constraint judgment operation for signal readout is adaptively performed for each pixel control block, an optimal accumulation time is set for each pixel control block as compared to the case where the accumulation time is controlled equally on the screen. be able to. Thereby, both a wide dynamic range and a high S / N can be realized at the same time.

  Note that the control of the pixel / pixel control block can be performed in combination as appropriate. Thereby, when the subject is stationary, the signal accumulation time can be maximized. On the other hand, when the subject moves, the signal accumulation time can be shortened. It is possible to obtain a high-resolution image with no image. In addition, the noise in the dark can be reduced and high S / N can be realized while effectively utilizing the dynamic range of the pixel and analog circuit for each pixel control block or for each pixel. In addition, when one frame signal is divided and read into a plurality of sub-frames and combined in a subsequent memory to reconstruct one screen, the bit accuracy of the ADC 120 can be reduced. When the signal accumulation time in the pixel is extended and sampling by sub-frame reading is not performed, the operation of the ADC 120 can be stopped, so that power consumption can be reduced.

  As described above, in the embodiment, in the solid-state imaging device 5, the pixel array 12 is divided into a plurality of pixel groups PG, and electrode junction points are arranged under each pixel group PG by stacking chips using substrate bonding. The charge accumulation period and / or the signal gain is controlled for each pixel group PG. Although the pixel array 12 is arranged on the semiconductor chip CH1, the other sizes (peripheral circuit 13 and signal processing circuit 11) in the solid-state imaging device 5 are not arranged, so that the pixel size is increased even when the number of pixels is increased. It is possible to easily reduce the chip size while suppressing the reduction in size. In other words, the chip size can be easily reduced while ensuring the pixel array size of each pixel P. Further, by stacking the chips using substrate bonding, the degree of parallelism between the control of each pixel P and the reading of the signal from each pixel P between the pixel P in the semiconductor chip CH1 and the pixel control block PBK in the semiconductor chip CH2. Can be improved. Accordingly, the charge accumulation period of the pixel and / or the gain of the pixel signal can be adaptively controlled in units of subframe accumulation periods obtained by dividing one frame accumulation period into N, so that the signal dynamic range can be easily expanded. Therefore, it is possible to achieve both reduction in chip size and high dynamic range.

  In addition, since the charge accumulation period of the pixel and / or the gain of the pixel signal can be adaptively controlled in units of subframe accumulation periods obtained by dividing one frame accumulation period into N, the S / N ratio can be improved, and the moving object distortion during moving object imaging It is possible to provide a high-quality image that reduces image quality.

  In the embodiment, in the pixel amplification circuit 70 of each pixel P, the floating gate FG has one end capacitively coupled to the charge holding unit 61 and the other end electrically connected to the charge voltage conversion unit 71. . As a result, a signal can be capacitively transmitted from the charge holding unit 61 to the floating gate FG, and can be transmitted from the floating gate FG to the charge-voltage conversion unit 71. The signal (charge) held in the holding unit 61 can be maintained in a non-destructive state. In addition, since each pixel P has such a non-destructive readout structure, the charge accumulation period of the pixel and / or the unit of the subframe accumulation period and / or the state in which the charge (signal) is retained in each pixel P is maintained. Application control of the gain of the pixel signal can be performed.

  The frame memory 11b may be substituted for the pixel block memory 130 (see FIG. 8) in each pixel control block PBK. In this case, as shown in FIG. 15, the frame memory 11b may be omitted from the semiconductor chip CHsp ′. FIG. 15 is an exploded perspective view showing a stacked configuration of the solid-state imaging device 5.

  Alternatively, as shown in FIG. 16, a plurality of pixels Pi to P- (i + 3) may be configured to share the control signal 1, the control signal 2, and the control signal 3. FIG. 16 is a circuit diagram showing a configuration of a plurality of shared pixels Pi to P- (i + 3). The plurality of pixels Pi to P- (i + 3) share a configuration other than the transmission units 77-i to 77- (i + 3) in the pixel amplifier circuit 70. Thereby, the control signal 2 common to the plurality of pixels Pi to P- (i + 3) is supplied to the gain adjusting unit 75. As shown in FIG. 17, the control signal 1 and the control signal 3 are one transistor selected from the transistors M11, M21, M31, and M41 and the transistor M13 when the selection signals φSelecti to φSelecti + 3 are alternatively set to the active level. , M23, M33, M43 and one transistor selected from the transistors M12, M22, M32, M42 are turned on, so that any of the charge storage units 60a-i to 60a- (i + 3) Selectively supplied.

  At this time, if it is determined by signal verification in the control circuit 140 that the signal accumulation in the pixel P is completed and the signal charge is discharged, the control signal 1 (φReset2) is applied so that the reset transistor M2 is turned on. The signal charge accumulated in the diode SD is discharged. At this time, the control signal 3 (φRead) is applied to the transfer transistor M1 so as to be turned off. When it is determined by the signal test in the control circuit 140 that the signal accumulation in the pixel P is continued, the control signal 1 (φReset2) that turns off the reset transistor M2 is applied and accumulated in the storage diode SD. The signal charge is held in the storage diode SD as it is, and signal accumulation in the storage diode SD is continued without destroying the signal charge.

  Further, when it is determined that the signal accumulation is continued, the following operation may be performed. That is, when the signal level is verified in the control circuit 140 (FIG. 8) and it is determined that the signal accumulation in the pixel P is continued as a result, the control signal 1 (φReset2) that turns off the reset transistor M2 However, the signal charge stored in the storage diode SD may be transferred to the photodiode PD and the signal storage may be continued in the photodiode PD. During the period from t3 to t4, an H potential is applied to the transfer transistor M1 (φRead) so as to be in an ON state (a dotted waveform of φRead shown in FIG. 17). In this way, the signal charge accumulated in the storage diode SD is transferred to the photodiode PD, and signal accumulation is continued in the photodiode PD after the transfer transistor is turned off.

  Further, the transfer units 77-i to 77- (i + 3) have the charge accumulation units 60a-i to 60a- (i + 3) when the selection signals φSelecti to φSelecti + 3 from the pixel control block PBK are alternatively set to the active level. The charge corresponding to any one of the signals is transferred to the charge-voltage converter 71. The selection signals φSelecti to φSelecti + 3 may be supplied from the pixel control block PBK, or may be supplied from a drive circuit provided on the sensor chip. FIG. 17 is a waveform diagram showing the operation of a plurality of shared pixels Pi to P- (i + 3).

  In this way, since the control signal 1, the control signal 2, and the control signal 3 are shared by the plurality of pixels Pi to P- (i + 3), the plurality of pixels Pi to P- (i + 3) and the pixel control block PBK are shared. The number of electrodes EL (see FIG. 4) provided for the control signal 1, the control signal 2, and the control signal 3 can be reduced. This makes it easier to reduce the area of the semiconductor chips CH1 and CH2. The configuration in which the amplification transistor M3 is shared by the plurality of photodiodes PD is not limited to the configuration in which the amplification transistor M3 is shared by the four photodiodes PD shown in the present modification. For example, the amplification is performed by two photodiodes PD. A configuration in which the transistor M3 is shared or a configuration in which the amplification transistor M3 is shared by eight photodiodes PD is also possible.

  Alternatively, as illustrated in FIG. 18, the solid-state imaging device 5 may be configured by further stacking the semiconductor chip CH3 in addition to the semiconductor chip CH1 and the semiconductor chip CH2. FIG. 18 is a cross-sectional view illustrating a stacked configuration of the solid-state imaging device 5. In this case, although the semiconductor chip CH1 and the semiconductor chip CH2 can easily shorten the electrode pitch by substrate bonding, the semiconductor chip CH2 and the semiconductor chip CH3 are bump bonding, so that the electrode pitch needs to be longer than the substrate bonding. Therefore, as shown in FIGS. 19 to 21, the array of the pixel control blocks in the semiconductor chip CH2 is divided into a plurality of pixel control block groups PBKG, and the control circuit 140 (see FIG. 8) in the pixel control block PBK is pixel-controlled. A logic block LBK including a control circuit 140a shared by the block group PBKG is provided, and the logic block LBK is arranged on the semiconductor chip CH3. Thereby, the parallelism of the control with respect to each pixel P and the reading of the signal from each pixel P can be further improved among the pixel P, the pixel control block PBK, and the logic block LBK. FIG. 19 is an exploded perspective view showing a stacked configuration of the solid-state imaging device 5. FIG. 20 is a block diagram illustrating a configuration of the solid-state imaging device 5. FIG. 21 is a diagram illustrating a configuration of the pixel P, the pixel control block PBK, and the logic block LBK.

  At this time, the frame memory 11b may be substituted for the pixel block memory 130 (see FIG. 21) in each pixel control block PBK. In this case, as shown in FIG. 22, the frame memory 11b may be omitted from the semiconductor chip CHsp ′. FIG. 22 is an exploded perspective view showing a stacked configuration of the solid-state imaging device 5.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  5 Solid-state imaging device, CH1, CH2, CH3, CHsp semiconductor chip.

Claims (9)

A first semiconductor chip in which a plurality of pixel groups including a plurality of pixels are arranged;
A second semiconductor chip in which a plurality of pixel control blocks including an A / D conversion circuit are stacked and the first semiconductor chip is electrically connected to an output of the pixel group;
A solid-state imaging device. The solid-state imaging device according to claim 1, wherein the pixel control block further includes a gain amplifier electrically connected between an output of the pixel group and the A / D conversion circuit. The solid-state imaging device according to claim 1, wherein the pixel control block further includes a control circuit that is connected to an output of the A / D conversion circuit and controls a charge accumulation period of each pixel of the pixel group. The second semiconductor chip has a plurality of pixel control block groups including a plurality of pixel control blocks,
The solid-state imaging device
A control circuit in which the first semiconductor chip and the second semiconductor chip are stacked, connected to the output of the pixel control block group, and controls a charge accumulation period of each pixel of the pixel group via the pixel control block group The solid-state imaging device according to claim 1, further comprising: a third semiconductor chip in which a plurality of logic blocks including a plurality of logic blocks are arranged. The pixel control block further includes a gain amplifier electrically connected between the output of the pixel group and the A / D conversion circuit,
The solid-state imaging device according to claim 3, wherein the control circuit controls a gain of the gain amplifier. The pixel group includes a pixel amplification circuit,
The solid-state imaging device according to claim 3, wherein the control circuit controls a gain of the pixel amplification circuit. Each of the plurality of pixels is
A photoelectric conversion unit;
A charge storage unit that stores the charge of the photoelectric conversion unit;
A pixel amplification circuit that outputs a signal corresponding to the charge in the charge storage unit;
The solid-state imaging device according to claim 1, comprising: The charge storage unit
A charge holding unit;
A transfer unit that transfers the charge of the photoelectric conversion unit to the charge holding unit;
A reset unit for resetting the charge of the charge holding unit;
Have
The pixel amplification circuit includes:
A charge-voltage converter,
A floating gate having one end capacitively coupled to the charge holding unit and the other end electrically connected to the charge voltage conversion unit;
An output unit that outputs a signal corresponding to the voltage of the charge-voltage converter;
The solid-state imaging device according to claim 7. The pixel amplification circuit includes:
A capacitive element;
A switch for connecting one end of the capacitive element to the floating gate;
The solid-state imaging device according to claim 8, further comprising:

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