WO2020202286A1 - Display device and method for manufacturing display device - Google Patents

Display device and method for manufacturing display device Download PDF

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Publication number
WO2020202286A1
WO2020202286A1 PCT/JP2019/014101 JP2019014101W WO2020202286A1 WO 2020202286 A1 WO2020202286 A1 WO 2020202286A1 JP 2019014101 W JP2019014101 W JP 2019014101W WO 2020202286 A1 WO2020202286 A1 WO 2020202286A1
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Prior art keywords
insulating film
display device
electrode
transistor
layer
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PCT/JP2019/014101
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French (fr)
Japanese (ja)
Inventor
真仁 佐野
浩英 見村
一篤 伊東
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シャープ株式会社
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Priority to PCT/JP2019/014101 priority Critical patent/WO2020202286A1/en
Publication of WO2020202286A1 publication Critical patent/WO2020202286A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements

Definitions

  • the present invention relates to a display device and a method for manufacturing the display device.
  • Patent Document 1 describes a step of forming a part of an oxide semiconductor layer into a conductor by plasma treatment or the like after forming a gate electrode in a manufacturing process of a top gate type thin film transistor of an organic EL display device provided with a TFT substrate. It is disclosed.
  • the display device is a display device including a plurality of first transistors, and each of the first transistors includes a gate electrode containing Cu, a gate insulating film superimposing on the gate electrode, and the like.
  • An oxide semiconductor layer including a channel region facing each other via the gate insulating film, a source region and a drain region that are provided so as to sandwich the channel region and are exposed from the gate insulating film, and at least the gate electrode.
  • the inorganic protective insulating film includes an inorganic protective insulating film that partially covers the oxide semiconductor layer and the interlayer insulating film that covers the inorganic protective insulating film, and the inorganic protective insulating film covers the end face of the gate electrode in the channel length direction and covers the channel. It is provided at a position consistent with the gate insulating film in the long direction.
  • the display device manufacturing method is a display device manufacturing method including a transistor forming step of forming a plurality of transistors, and the transistor forming step patterns an oxide semiconductor layer on a substrate.
  • FIG. It is sectional drawing which shows the example of the structure in the display area of the display device which concerns on Embodiment 1.
  • FIG. It is the schematic plan view of the display device which concerns on Embodiment 1.
  • FIG. It is a top view which shows the example of the structure in the display area of the TFT layer which concerns on Embodiment 1.
  • FIG. It is a flowchart for demonstrating the manufacturing method of the display device which concerns on Embodiment 1.
  • It is a flowchart for demonstrating the manufacturing method of the TFT layer which concerns on Embodiment 1.
  • FIG. It is another process sectional view for demonstrating the manufacturing method of the TFT layer which concerns on Embodiment 1.
  • FIG. It is another process sectional view for demonstrating the manufacturing method of the TFT layer which concerns on Embodiment 1.
  • FIG. It is an equivalent circuit diagram which shows an example of the pixel circuit of the display device which concerns on Embodiment 2.
  • FIG. It is sectional drawing which shows the example of the structure in the pixel circuit of the TFT layer which concerns on Embodiment 2.
  • FIG. It is sectional drawing which shows the example of the structure in the pixel circuit of the TFT layer which concerns on modification 1.
  • FIG. It is a top view which shows the structural example
  • FIG. 2 is a schematic plan view of the display device 2 according to the present embodiment.
  • the display device 2 is a top-emission type display device that emits light upward, and includes a display area DA having a plurality of sub-pixels and a light emitting element for each sub-pixel, and a display area. It is provided with a frame area NA formed around the DA.
  • a routing wiring TL may be drawn out from each wiring of the display area DA to the frame region NA, and the routing wiring TL may be connected to a terminal portion T formed in the frame region NA.
  • FIG. 1 is a cross-sectional view showing an example of the structure of the display device 2 according to the present embodiment in the display area DA, and is a cross-sectional view taken along the line AA of FIG.
  • the display device 2 has a structure in which each layer is laminated on the base material 4.
  • the display device 2 includes a base coat layer 6, a TFT layer (thin film transistor layer) 8, and a light emitting element layer 10 in this order from the base material 4 side.
  • the display device 2 may be provided with a sealing layer on the upper layer of the light emitting element layer 10, and may be further provided with a functional film or the like including a circularly polarizing plate or the like on the sealing layer.
  • the base coat layer 6 is a layer that prevents moisture and impurities from reaching the TFT layer 8 or the light emitting element layer 10 when the display device 2 is used.
  • the base coat layer 6 can be composed of, for example, a silicon oxide film, a silicon nitride film, a silicon nitride film, or a laminated film thereof formed by CVD.
  • FIG. 3 is a plan view of the TFT layer 8.
  • the AA line shown in FIG. 3 corresponds to the AA line shown in FIG. Further, in FIG. 3, the light emitting element layer 10 and the interlayer insulating film 20 described later are not shown.
  • the TFT layer 8 includes a plurality of thin film transistors, and each light emitting element of the light emitting element layer 10 described later includes a thin film transistor.
  • the first transistor particularly the drive transistor T1 involved in driving the light emitting element is shown.
  • Each of the drive transistors T1 includes an oxide semiconductor layer 16, a gate insulating film 14, a gate electrode 12, an inorganic protective insulating film 18, and a TFT electrode layer 28 in this order from the lower layer.
  • the TFT layer 8 further includes an interlayer insulating film 20 that covers the oxide semiconductor layer 16 and the inorganic protective insulating film 18.
  • Each of the drive transistors T1 is a top gate type thin film transistor.
  • An oxide semiconductor layer 16 is formed on the lower layer side of the gate electrode 12, which overlaps with the gate electrode 12, via a gate insulating film 14.
  • the gate electrode 12 contains Cu with low resistance, and may have, for example, a laminated structure having Ti in the lower layer and Cu in the upper layer.
  • the width of Ti is larger than the width of Cu
  • the width of the gate insulating film 14 is larger than the width of Ti.
  • the oxide semiconductor layer 16 includes a channel region 22, a source region 24, and a drain region 26.
  • the channel region 22 faces the gate electrode 12 via the gate insulating film 14.
  • the source region 24 and the drain region 26 are formed at positions sandwiching the channel region 22, and are exposed from the gate insulating film 14 in a plan view.
  • the oxide semiconductor contained in the oxide semiconductor layer 16 may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion.
  • Examples of the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface.
  • the oxide semiconductor layer 16 may have a laminated structure of two or more layers.
  • the oxide semiconductor layer 16 may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, it may contain a plurality of crystalline oxide semiconductor layers having different crystal structures. Further, a plurality of amorphous oxide semiconductor layers may be contained.
  • the oxide semiconductor layer 16 may contain at least one metal element among, for example, In, Ga and Zn.
  • the oxide semiconductor layer 16 includes, for example, an In—Ga—Zn—O-based semiconductor (for example, indium gallium zinc oxide).
  • Such an oxide semiconductor layer 16 can be formed from an oxide semiconductor film containing an In—Ga—Zn—O based semiconductor.
  • the In-Ga-Zn-O-based semiconductor may be amorphous or crystalline.
  • a crystalline In—Ga—Zn—O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable.
  • the crystal structure of crystalline In-Ga-Zn-O-based semiconductors is disclosed in, for example, JP-A-2014-007399, JP-A-2012-134475, JP-A-2014-209727, and the like described above. ing. For reference, all the disclosure contents of JP2012-134475 and JP2014-209727 are incorporated herein by reference.
  • a TFT having an In—Ga—Zn—O semiconductor layer has high mobility (more than 20 times that of a—SiTFT) and low leakage current (less than 1/100 of that of a—SiTFT).
  • the oxide semiconductor layer 16 may contain another oxide semiconductor instead of the In—Ga—Zn—O-based semiconductor.
  • In-Sn-Zn-O-based semiconductor for example In 2 O 3 -SnO 2 -ZnO; InSnZnO
  • the In—Sn—Zn—O semiconductor is a ternary oxide of In (indium), Sn (tin) and Zn (zinc).
  • the oxide semiconductor layer 16 is an In—Al—Zn—O system semiconductor, an In—Al—Sn—Zn—O system semiconductor, a Zn—O system semiconductor, an In—Zn—O system semiconductor, a Zn—Ti—O.
  • System semiconductors Cd-Ge-O system semiconductors, Cd-Pb-O system semiconductors, CdO (cadmium oxide), Mg-Zn-O system semiconductors, In-Ga-Sn-O system semiconductors, In-Ga-O system semiconductors , Zr-In-Zn-O series semiconductor, Hf-In-Zn-O series semiconductor, Al-Ga-Zn-O series semiconductor, Ga-Zn-O series semiconductor, In-Ga-Zn-Sn-O series semiconductor , InGaO 3 (ZnO) 5 , zinc oxide (Mg x Zn 1-x O), zinc oxide cadmium (Cd x Zn 1-x O), and the like may be contained.
  • ZnO amorphous (amorphous) to which one or more of group 1 elements, group 13 elements, group 14 elements, group 15 elements, group 17 elements, and the like are added.
  • a state, a polycrystalline state, a microcrystalline state in which an amorphous state and a polycrystalline state are mixed, or a state in which no impurity element is added can be used.
  • the inorganic protective insulating film 18 covers at least a part of the gate electrode 12 in a plan view.
  • the inorganic protective insulating film 18 covers the end face of the gate electrode 12 in the channel length direction of the channel region 22 of the oxide semiconductor layer 16.
  • the inorganic protective insulating film 18 is preferably formed in an island shape for each drive transistor T1 so as to cover the entire gate electrode 12.
  • the TFT electrode layer 28 includes a source electrode 28S that is electrically connected to the source region 24 of the oxide semiconductor layer 16 and a drain electrode 28D that is electrically connected to the drain region 26 of the oxide semiconductor layer 16.
  • the source region 24 and the source electrode 28S are electrically connected to each other via a source contact portion 30S formed in the opening of the interlayer insulating film 20.
  • the drain region 26 and the drain electrode 28D are electrically connected via a drain contact portion 30D formed in the opening of the interlayer insulating film 20.
  • the gate insulating film 14 is preferably a silicon oxide film.
  • the silicon oxide film has a smaller dielectric constant than the silicon nitride film. Therefore, in the present embodiment, since the gate insulating film 14 is made of a silicon oxide film, the parasitic capacitance between the gate insulating film 14 and other wiring is reduced. Further, since the gate insulating film 14 is made of a silicon oxide film, the gate insulating film 14 does not contain hydrogen, so that damage to the oxide semiconductor layer 16 can be reduced.
  • the interlayer insulating film 20 may be a silicon nitride film, and the inorganic protective insulating film 18 may be a silicon oxide film or a silicon nitride film.
  • the light emitting element layer 10 includes a flattening film 32, a first electrode 34, an edge cover 36, a functional layer 38, and a second electrode 40 from the lower layer.
  • a plurality of light emitting elements including a first electrode 34, a functional layer 38, and a second electrode 40 are formed in the light emitting element layer 10.
  • Each of the light emitting elements includes an island-shaped first electrode 34 and a functional layer 38 formed for each light emitting element, and a second electrode 40 commonly formed for the light emitting element.
  • a part of the functional layer 38 may be formed in common with the light emitting element.
  • the flattening film 32 flattens the upper layer of the interlayer insulating film 20 and may contain a photosensitive organic material such as polyimide or acrylic.
  • the first electrode 34 is formed in an island shape for each light emitting element, and is electrically connected to the source electrode 28S of the drive transistor T1 via the first electrode contact portion 42 formed in the opening of the flattening film 32. ..
  • the first electrode 34 may be, for example, an anode, and may have a structure having light reflectivity, such as a laminated structure of ITO (Indium Tin Oxide) and an alloy containing Ag.
  • the edge cover 36 is formed at a position that covers each end of the first electrode 34.
  • the edge cover 36 partitions the functional layer 38 so that the functional layer 38 is formed for each light emitting element.
  • the functional layer 38 includes at least a light emitting layer, and the light emitting layer is formed in an island shape for each light emitting element.
  • the functional layer 38 may include a charge injection layer, a charge transport layer, or a charge block layer.
  • the second electrode 40 is formed in common to all light emitting elements.
  • the second electrode 40 may be, for example, a cathode, or may be made of a translucent conductive material such as MgAg alloy (ultra-thin film), ITO (Indium Tin Oxide), or IZO (Indium Zinc Oxide). ..
  • the light emitting element included in the light emitting element layer 10 may be an organic light emitting diode (OLED) element.
  • OLED organic light emitting diode
  • a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are laminated as the functional layer 38 on the surface where the first electrode 34 is exposed from the edge cover 36. You may.
  • the light emitting element included in the light emitting element layer 10 is an OLED element
  • holes and electrons are recombined in the light emitting layer of the functional layer 38 by the driving current between the first electrode 34 and the second electrode 40.
  • Light is emitted from the light emitting layer when the resulting excitons fall to the ground state.
  • the second electrode 40 has translucency and the first electrode 34 has light reflectivity, the light emitted from the light emitting layer goes upward, so that the display device 2 becomes a top emission type display device. ..
  • the light emitting element layer 10 is not limited to the case where it includes an OLED element, and may include an inorganic light emitting diode element or a quantum dot light emitting diode element as a light emitting element.
  • FIG. 4 is a flowchart showing each manufacturing process of the display device 2 according to the present embodiment.
  • the base coat layer 6 is formed on a translucent base material (for example, a mother glass substrate) (step S1).
  • a conventionally known method can be adopted for forming the base coat layer 6.
  • FIG. 5 is a flowchart showing a process of forming the TFT layer 8 in the present embodiment.
  • 6 to 9 are process cross-sectional views for explaining the forming step of the TFT layer 8 in more detail, which is carried out based on the flowchart of FIG.
  • the process sectional view at the position corresponding to FIG. 1 is shown.
  • step S1 By executing step S1, the structure shown in FIG. 6A is obtained.
  • step S2 first, as shown in FIG. 6B, the oxide semiconductor layer 16P before the conductor formation treatment is formed on the upper layer of the base coat layer 6 (step S11).
  • the oxide semiconductor layer 16P may be formed, for example, by forming a film of an oxide semiconductor material and patterning it.
  • a gate insulating film 14 is formed on the base coat layer 6 and the oxide semiconductor layer 16P (step S12).
  • the formation of the gate insulating film 14 may be carried out by low temperature CVD or the like.
  • the gate electrode 12 is formed on the upper layer of the gate insulating film 14 (step S13).
  • the gate electrode 12 may be obtained by forming a metal material containing Cu on the upper layer of the gate insulating film 14 by a sputtering method and then patterning it by an etching method.
  • an inorganic protective insulating film 18 is formed on the upper layers of the gate insulating film 14 and the gate electrode 12 (step S14).
  • the film formation of the inorganic protective insulating film 18 may be carried out by low temperature CVD or the like.
  • step S15 the gate insulating film 14 and the inorganic protective insulating film 18 are formed by patterning together.
  • step S15 first, as shown in FIG. 7B, a resist mask 44 is formed on the upper layer of the inorganic protective insulating film 18.
  • the resist mask 44 is formed at a position where it overlaps with the gate electrode 12, and in particular, is formed so as to overlap with a position where the channel region 22 is formed in the oxide semiconductor layer 16P.
  • the gate insulating film 14 and the inorganic protective insulating film 18 are etched at once by a wet etching method, a dry etching method, or the like. As a result, the portion of the oxide semiconductor layer 16P that sandwiches the portion that overlaps with the resist mask 44, including the portion that overlaps with the gate electrode 12, is exposed from the gate insulating film 14.
  • the gate insulating film 14 and the inorganic protective insulating film 18 are simultaneously etched. Therefore, in the present embodiment, a pattern in which the gate insulating film 14 and the inorganic protective insulating film 18 match is formed by patterning.
  • the inorganic protective insulating film 18 is provided at a position consistent with the gate insulating film 14 in the above-mentioned channel length direction.
  • the gate insulating film 14 and the inorganic protective insulating film 18 are aligned means that the gate insulating film 14 and the inorganic protective insulating film 18 are layers formed by patterning in the same resist pattern. Shown. That is, in the present specification, "the two layers are aligned” does not mean that the two layers are exactly the same, and includes a dimensional deviation of about several ⁇ m caused by a difference in etching rate or the like.
  • the resist mask 44 may be appropriately removed. In this way, the same resist mask 44 can be used to match the patterning shapes of the upper gate insulating film 14 and the inorganic protective insulating film 18. As a result, both can be accurately aligned while simplifying the process.
  • the side surfaces of the two target layers are flush with each other in the vertical direction, but also the side surfaces of the two layers continuously form an inclined surface such as a tapered shape.
  • the side surfaces of the two layers continuously form an inclined surface such as a tapered shape.
  • the etching between the gate insulating film 14 and the inorganic protective insulating film 18 is performed. Differences in rates, etc. may occur.
  • the lateral displacement of about 2 ⁇ m to 3 ⁇ m between the gate insulating film 14 and the inorganic protective insulating film 18 due to the difference is included.
  • step S16 irradiation of plasma such as hydrogen plasma is executed from above each layer on the base material 4 (step S16).
  • the plasma irradiation carried out in step S16 may be carried out by a conventionally known method as long as the irradiated oxide semiconductor layer 16P has an oxygen defect and is made into a conductor.
  • step S16 the oxide semiconductor layer 16P exposed from the gate insulating film 14 is made into a conductor.
  • a source region 24 and a drain region 26 are formed at positions exposed from the gate insulating film 14 of the oxide semiconductor layer 16P.
  • the portion of the oxide semiconductor layer 16P that is not exposed from the gate insulating film 14 and overlaps with the gate insulating film 14 is the channel region 22.
  • the oxide semiconductor layer 16 including the channel region 22, the source region 24, and the drain region 26 is obtained.
  • Step S17 the material of the interlayer insulating film 20 is applied from above each layer on the base material 4 (step S17).
  • Step S17 may be performed by applying, for example, a photosensitive organic material containing polyimide, acrylic or the like by a conventionally known method.
  • the source contact hole 46S and the drain contact hole 46D shown in FIG. 9A are formed on the interlayer insulating film 20 by photoetching or the like (step S18).
  • the source contact hole 46S is formed at a position where it overlaps with a part of the source region 24, and the drain contact hole 46D is formed at a position where it overlaps with a part of the drain region 26.
  • the TFT electrode layer 28 is formed (step S19).
  • a source contact portion 30S that electrically connects the source region 24 and the source electrode 28S is formed.
  • the drain electrode 28D of the TFT electrode layer 28 is formed.
  • the drive transistor T1 shown in FIG. 9B is formed.
  • the thin film transistor included in the TFT layer 8 may be formed at the same time in step S2.
  • step S3 the light emitting element layer 10 is formed (step S3).
  • a method for forming each layer of the light emitting element layer 10 a conventionally known method can be adopted.
  • step S3 a step of forming a circularly polarizing plate on the light emitting element layer 10 via a sealing layer may be performed.
  • the laminate including the base material, the base coat layer 6, the TFT layer 8, the light emitting element layer 10, and the circularly polarizing plate is divided to obtain a plurality of individual pieces (step S4).
  • an electronic circuit board for example, an IC chip
  • step S5 an electronic circuit board
  • the above-mentioned translucent glass substrate may be used as the base material 4 as it is.
  • step S5 the lower surface of the base coat layer 6 is irradiated with laser light through the translucent support substrate to reduce the bonding force between the base material and the base coat layer 6, and the base material is peeled from the base coat layer 6.
  • a lower surface film such as a PET film is attached to the lower surface of the base coat layer 6 to form a base material 4.
  • a flexible display device 2 can be obtained.
  • step S13 plasma irradiation is executed on the oxide semiconductor layer 16 exposed from the gate insulating film 14 in step S16.
  • step S16 plasma irradiation is executed in a state where at least a part of the gate electrode 12, particularly the end face of the gate electrode 12 in the channel length direction is covered with the inorganic protective insulating film 18.
  • the gate electrode 12 contains low-resistance Cu
  • the amount of plasma irradiation to the gate electrode 12 can be reduced, and the generation of electrostatic discharge from the gate electrode 12 can be reduced. Therefore, the damage to the channel region 22 of the oxide semiconductor layer 16 due to the electrostatic discharge from the gate electrode 12 is reduced, and the yield in the manufacturing process of the display device 2 is improved.
  • the vertical direction on the drawing is the column direction
  • the horizontal direction on the drawing is the row direction
  • the diagonal direction is based on the row direction and the column direction.
  • the row direction may have a parallel relationship with one edge (one side) of the display device, an orthogonal relationship, or an oblique relationship.
  • the sub-pixel (sub-pixel) is the minimum display configuration that is driven independently.
  • the same layer indicates that the layer is formed by the same process, and includes the same material.
  • the display device 2 according to the present embodiment has the same layer structure as the display device 2 according to the previous embodiment.
  • the display device 2 according to the present embodiment has a configuration as compared with the display device 2 according to the previous embodiment only in that the TFT layer 8 includes a pixel circuit for each sub-pixel included in the display device 2. different.
  • FIG. 10 is a circuit diagram showing a configuration example of a sub-pixel SP included in the display device 2 according to the present embodiment.
  • FIG. 11 is a plan view for explaining the pixel circuit included in the sub-pixel SP according to the present embodiment in more detail, and is a plan view showing the pixel circuit in more detail with respect to the region B of FIG.
  • FIG. 12 is a cross-sectional view for explaining the pixel circuit included in the sub-pixel SP according to the present embodiment in more detail.
  • FIG. 12A is a cross-sectional view taken along the line CC of FIG. 11, and
  • FIG. 12B is a cross-sectional view taken along the line DD of FIG.
  • FIG. 11 for the sake of simplicity of illustration, only the members of the same layer as the oxide semiconductor layer 16, the gate electrode 12, and the TFT electrode layer 28 are extracted and shown in the TFT layer 8. .. Further, in FIG. 11, only the outer shape of the inorganic protective insulating film 18 is shown by a two-dot chain line. Further, FIG. 12 illustrates only the base coat layer 6 and the TFT layer 8 among the members of the display device 2.
  • the TFT layer 8 is provided with a plurality of data line DLs extending in the column direction and a plurality of scanning signal lines SC extending in the row direction, and the sub-pixel SP is the data line DL and the scanning signal line SC.
  • a high-level power supply VDD for driving the organic EL element is supplied to each sub-pixel SP via the first power supply voltage line VL1, and a low-level power supply VSS is supplied via the second power supply voltage line VL2. It is supplied and the initialization voltage is supplied via the initialization power line IL.
  • a potential signal corresponding to the display gradation data is supplied from the data line DL to each sub-pixel connected to the scanning signal line SC.
  • the sub-pixel SP includes a pixel circuit formed on the TFT layer 8 of FIG. 1 and a light emitting element formed on the light emitting element layer 10 of FIG.
  • the pixel circuit includes a drive transistor T1, a write transistor T2, an initialization transistor T3, and a capacitance Cp.
  • the first transistor described in the previous embodiment includes the writing transistor T2 in addition to the driving transistor T1.
  • Each transistor included in the pixel circuit may have the same layer structure as the drive transistor T1 in the previous embodiment.
  • the scanning signal line SC, the initialization power supply line IL, and the first capacitance electrode Cp1 are formed in the same layer as the gate electrode 12 of the TFT layer 8. Further, the data signal line DL, the first power supply voltage line VL1, and the second capacitance electrode Cp2 are formed in the same layer as the TFT electrode layer 28 of the TFT layer 8.
  • the gate electrode of the drive transistor T1 connected to the control terminal of the drive transistor T1 is connected to the source electrode of the write transistor T2 and the first capacitance electrode Cp1 which is one electrode of the capacitance Cp.
  • the first capacitance electrode Cp1 serves as a gate electrode of the drive transistor T1.
  • a high level power supply VDD is supplied from the first power supply voltage line VL1 to the drain electrode of the drive transistor T1.
  • the source electrode of the drive transistor T1 is connected to the source electrode of the initialization transistor T3 and the second capacitance electrode Cp2 which is the other electrode of the capacitance Cp, and is connected to the first electrode 34 of the light emitting element layer 10.
  • the second capacitance electrode Cp2 faces the gate electrode of the drive transistor T1 via the interlayer insulating film 20.
  • the capacitance Cp sandwiches the inorganic protective insulating film 18 between the interlayer insulating film 20 and the first capacitance electrode Cp1.
  • the gate electrode of the writing transistor T2 is connected to the scanning signal line SC and the gate electrode of the initialization transistor T3.
  • a part of the scanning signal line SC serves as a gate electrode of the writing transistor T2 and the initialization transistor T3.
  • the gate electrode included in the control line such as the scanning signal line SC extending the display region DA, refers to a region of the control line that overlaps with the channel region 22 via the gate insulating film 14.
  • the drain electrode of the writing transistor T2 is connected to the data signal line DL.
  • the drain electrode of the initialization transistor T3 is connected to the initialization power line IL.
  • a low level power supply VSS is supplied from the second power supply voltage line VL2 to the second electrode 40 of the light emitting element layer 10.
  • the source region 24 of the write transistor T2 and the first capacitance electrode Cp1 are connected to the first connection wiring 48 of the same layer as the TFT electrode layer 28 of the TFT layer 8. It is connected.
  • the drain region 26 of the initialization transistor T3 and the initialization power supply line IL are connected by a second connection wiring 50, which is the same layer as the TFT electrode layer 28 of the TFT layer 8.
  • the source electrode and the drain electrode are exchanged depending on the operation.
  • the TFT electrode layer 28 further includes a first contact portion CN1 and a second contact portion CN2.
  • the first contact portion CN1 electrically connects a member of the same layer as the TFT electrode layer 28 and a member of the same layer as the oxide semiconductor layer 16.
  • the second contact portion CN2 electrically connects the member of the same layer as the TFT electrode layer 28 and the member of the same layer as the gate electrode 12.
  • the initialization power supply line IL in the same layer as the gate electrode 12 may be formed on the gate insulating film 14 directly formed on the base coat layer 6. Further, as shown in FIG. 12, the inorganic protective insulating film 18 may cover at least the end face of the initialization power line IL. Since the inorganic protective insulating film 18 is also formed on the initialization power supply line IL, the parasitic capacitance between the initialization power supply line IL and other wiring can be reduced.
  • a data signal including gradation value data related to the light emitting element of the sub-pixel SP is applied to the data signal line DL. Further, a plurality of scanning signal lines SC are sequentially scanned. Here, at the time when the scanning signal line SC corresponding to the sub-pixel SP is scanned, the data signal applied to the data signal line DL is written to the capacitance Cp via the writing transistor T2. As a result, the drive transistor T1 drives the light emitting element of the sub-pixel SP based on the gradation value data included in the data signal written in the capacitance Cp.
  • the data signal written in the capacitance Cp is initialized by applying the initialization voltage from the initialization power supply line IL to the capacitance Cp via the initialization transistor T3.
  • the display device 2 according to the present embodiment may be manufactured by the same manufacturing method as the manufacturing method of the display device 2 according to the previous embodiment.
  • the display device 2 also includes the inorganic protective insulating film 18 at a position of each transistor in the channel length direction so as to cover the end face of the gate electrode 12. Therefore, for the same reason as described above, the yield in the manufacturing process of the display device 2 is improved.
  • the inorganic protective insulating film 18 and the interlayer insulating film 20 are preferably silicon nitride films.
  • the dielectric constant of the two layers is higher than that in the case where the inorganic protective insulating film 18 and the interlayer insulating film 20 are silicon oxide films, so that the electric capacity of the capacitance Cp can be improved. Therefore, the areas of the first capacitance electrode Cp1 and the second capacitance electrode Cp2 of the capacitance Cp can be reduced.
  • FIG. 13 is a plan view for explaining the pixel circuit included in the sub-pixel SP according to the present modification in more detail, and is a plan view corresponding to FIG.
  • FIG. 14 is a cross-sectional view for explaining the pixel circuit included in the sub-pixel SP according to the present modification in more detail.
  • 14 (a) is a cross-sectional view taken along the line CC of FIG. 13
  • FIG. 14 (b) is a cross-sectional view taken along the line DD of FIG.
  • FIG. 13 in order to clearly show the formation position of the inorganic protective insulating film 18, only the inorganic protective insulating film 18 is hatched.
  • the display device 2 according to this modification is different only in that the formation position of the inorganic protective insulating film 18 is different from that of the display device 2 according to the above-described embodiment.
  • the inorganic protective insulating film 18 is not formed at a position covering the first capacitance electrode Cp1 as shown in FIGS. 13 and 14 (a). Therefore, the first capacitance electrode Cp1 is in contact with the interlayer insulating film 20 as shown in FIG. 14A.
  • an inorganic protective insulating film 18 is formed at a position of the gate electrode 12 of the drive transistor T1 that covers the end face in the channel length direction.
  • the inorganic protective insulating film 18 is not formed at a position where it overlaps with a part of the gate electrode 12 of the drive transistor T1.
  • the inorganic protective insulating film 18 is formed in an island shape on the source region 24 side and the drain region 26 side of the gate electrode 12 of the drive transistor T1, respectively. Has been done.
  • the display device 2 includes a drive transistor T1 as a second transistor in which a part of the gate electrode 12 overlapping the channel region 22 of the first transistor is in contact with the interlayer insulating film 20.
  • the display device 2 according to the present modification may be manufactured by the same manufacturing method as the manufacturing method of the display device 2 according to each of the above-described embodiments.
  • the patterning of the gate insulating film 14 in which the inorganic protective insulating film 18 is not formed may be etched using the gate insulating film as a mask pattern at the overlapping positions.
  • the inorganic protective insulating film 18 is not formed between the first capacitance electrode Cp1 and the second capacitance electrode Cp2, and the first capacitance electrode Cp1 that overlaps with the second capacitance electrode Cp2 is interposed. It comes into contact with the insulating film 20. Therefore, the electric capacity of the capacitance Cp can be further improved, and the areas of the first capacitance electrode Cp1 and the second capacitance electrode Cp2 of the capacitance Cp can be reduced.
  • the inorganic protective insulating film 18 is not formed at the position where it overlaps with a part of the gate electrode 12 that overlaps with the channel region 22 of the drive transistor T1, and is in contact with the interlayer insulating film.
  • the inorganic protective insulating film 18 is formed at a position covering the end surface of the gate electrode 12 in the channel length direction of the drive transistor T1. Therefore, the electrostatic discharge from the gate electrode 12 in the drive transistor T1 is reduced to the extent that a defect in the channel region 22 does not occur.
  • FIG. 15 is a plan view for explaining the pixel circuit included in the sub-pixel SP according to the present modification in more detail, and is a plan view corresponding to FIGS. 11 and 13.
  • FIG. 15 as in FIG. 13, only the inorganic protective insulating film 18 is hatched and shown.
  • the display device 2 according to the present modification is different only in that the formation position of the inorganic protective insulating film 18 is different from that of the display device 2 according to the previous modification.
  • the inorganic protective insulating film 18 is commonly formed on the source region side 24 and the drain region side 26 of the gate electrode 12 of the drive transistor T1 as shown in FIG. Has been done.
  • the inorganic protective insulating film 18 is formed in an island shape at positions covering all of the gate electrodes 12 of the writing transistor T2 and the initialization transistor T3. It is formed. In other words, the inorganic protective insulating film 18 is formed in an island shape at a position covering the entire region of the scanning signal line SC that overlaps with the channel region 22 via the gate insulating film 14. Therefore, at least a part of the scanning signal line SC that does not overlap with the channel region 22 comes into contact with the interlayer insulating film 20.
  • the inorganic protective insulating film 18 is formed at a position covering the end face of the gate electrode 12 in the channel length direction of each transistor. Therefore, the electrostatic discharge from the gate electrode 12 in each transistor is reduced.
  • the electro-optical element included in the display device according to each of the above-described embodiments is not particularly limited.
  • the display device according to each embodiment may include, for example, an OLED (Organic Light Emitting Diode) as an electro-optical element. Therefore, the display device according to each embodiment may be, for example, an organic EL (Electro Luminescence) display provided with an OLED. Further, the display device according to each embodiment may be an inorganic EL display provided with an inorganic light emitting diode as an electro-optical element. Further, the display device according to each embodiment may be a QLED display provided with a QLED (Quantum dot Light Emitting Diode) as an electro-optical element.
  • OLED Organic Light Emitting Diode
  • the display device according to each embodiment may be, for example, an organic EL (Electro Luminescence) display provided with an OLED.
  • the display device according to each embodiment may be an inorganic EL display provided with an inorganic light emitting
  • the present invention is not limited to the above-described embodiments, and embodiments obtained by appropriately combining the technical means disclosed in the different embodiments are also included in the technical scope of the present invention. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

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Abstract

A display device (2) includes a plurality of first transistors (T1). Each of the first transistors comprises: a gate electrode (12) that contains Cu; a gate insulating film (14) that overlaps with the gate electrode; a channel region (22) that faces the gate electrode with the gate insulating film interposed therebetween; an oxide semiconductor layer (16) that sandwiches the channel region, the oxide semiconductor layer including a source region (24) and a drain region (26) that are exposed from the gate insulating film; an inorganic insulating protective film (18) that covers at least a portion of the gate electrode; and an interlayer insulating film (20) that covers the oxide semiconductor layer and the inorganic insulating protective film. The inorganic insulating protective film is provided so as to cover the end surface of the gate electrode in the channel length direction and to conform to the gate insulating film in the channel length direction.

Description

表示デバイス、表示デバイスの製造方法Display device, manufacturing method of display device
　本発明は、表示デバイス、ならびに、当該表示デバイスの製造方法に関する。 The present invention relates to a display device and a method for manufacturing the display device.
　特許文献１には、ＴＦＴ基板を備えた有機ＥＬ表示装置の、トップゲート型の薄膜トランジスタの製造工程において、ゲート電極形成後、プラズマ処理等により、酸化物半導体層の一部を導体化する工程が開示されている。 Patent Document 1 describes a step of forming a part of an oxide semiconductor layer into a conductor by plasma treatment or the like after forming a gate electrode in a manufacturing process of a top gate type thin film transistor of an organic EL display device provided with a TFT substrate. It is disclosed.
特開２０１６－１２９４号公報（２０１６年１月７日公開）Japanese Unexamined Patent Publication No. 2016-1294 (published on January 7, 2016)
　特許文献１に開示された、薄膜トランジスタの製造工程において、ゲート電極に、Ｃｕのような低抵抗の金属を使用した場合、プラズマ処理を行う際、当該ゲート電極から静電気放電が生じやすく、酸化物半導体層のチャネル領域にダメージを与える場合がある。 When a low-resistance metal such as Cu is used for the gate electrode in the manufacturing process of the thin film transistor disclosed in Patent Document 1, electrostatic discharge is likely to occur from the gate electrode during plasma treatment, and the oxide semiconductor May damage the channel area of the layer.
　本発明の一態様に係る表示デバイスは、複数の第１トランジスタを含む表示デバイスであって、前記第１トランジスタのそれぞれは、Ｃｕを含むゲート電極と、前記ゲート電極と重畳するゲート絶縁膜と、前記ゲート絶縁膜を介して対向するチャネル領域と、該チャネル領域を挟むように設けられるとともに、前記ゲート絶縁膜から露出するソース領域およびドレイン領域とを含む酸化物半導体層と、前記ゲート電極の少なくとも一部を覆う無機保護絶縁膜と、前記酸化物半導体層および前記無機保護絶縁膜を覆う層間絶縁膜とを含み、前記無機保護絶縁膜は、チャネル長方向の前記ゲート電極の端面を覆い、チャネル長方向において前記ゲート絶縁膜と整合する位置に設けられる。 The display device according to one aspect of the present invention is a display device including a plurality of first transistors, and each of the first transistors includes a gate electrode containing Cu, a gate insulating film superimposing on the gate electrode, and the like. An oxide semiconductor layer including a channel region facing each other via the gate insulating film, a source region and a drain region that are provided so as to sandwich the channel region and are exposed from the gate insulating film, and at least the gate electrode. The inorganic protective insulating film includes an inorganic protective insulating film that partially covers the oxide semiconductor layer and the interlayer insulating film that covers the inorganic protective insulating film, and the inorganic protective insulating film covers the end face of the gate electrode in the channel length direction and covers the channel. It is provided at a position consistent with the gate insulating film in the long direction.
　本発明の一態様に係る表示デバイスの製造方法は、複数のトランジスタを形成するトランジスタ形成工程を含む表示デバイスの製造方法であって、前記トランジスタ形成工程は、基材上に酸化物半導体層をパターニングして形成する工程と、ゲート絶縁膜を成膜する工程と、前記ゲート絶縁膜の上層に、Ｃｕを含むゲート電極をパターニングして形成する工程と、無機保護絶縁膜を成膜する工程と、前記酸化物半導体層の一部が露出するように、前記ゲート絶縁膜と前記無機保護絶縁膜とが整合するパターンをパターニングする工程と、露出した前記酸化物半導体層にプラズマを照射する工程と、層間絶縁膜を成膜する工程と、を含む。 The display device manufacturing method according to one aspect of the present invention is a display device manufacturing method including a transistor forming step of forming a plurality of transistors, and the transistor forming step patterns an oxide semiconductor layer on a substrate. A step of forming a gate insulating film, a step of patterning and forming a gate electrode containing Cu on the upper layer of the gate insulating film, and a step of forming an inorganic protective insulating film. A step of patterning a pattern in which the gate insulating film and the inorganic protective insulating film match so that a part of the oxide semiconductor layer is exposed, and a step of irradiating the exposed oxide semiconductor layer with plasma. It includes a step of forming an interlayer insulating film.
　本発明の一態様によれば、ゲート電極からの静電気放電を低減し、酸化物半導体層のチャネル領域へのダメージを低減した、表示デバイスの製造方法を提供でき、当該製造方法の歩留まりの改善につながる。 According to one aspect of the present invention, it is possible to provide a method for manufacturing a display device in which electrostatic discharge from the gate electrode is reduced and damage to the channel region of the oxide semiconductor layer is reduced, and the yield of the manufacturing method can be improved. Connect.
実施形態１に係る表示デバイスの、表示領域における構造の例を示す断面図である。It is sectional drawing which shows the example of the structure in the display area of the display device which concerns on Embodiment 1. FIG. 実施形態１に係る表示デバイスの概略平面図である。It is the schematic plan view of the display device which concerns on Embodiment 1. FIG. 実施形態１に係るＴＦＴ層の、表示領域における構造の例を示す平面図である。It is a top view which shows the example of the structure in the display area of the TFT layer which concerns on Embodiment 1. FIG. 実施形態１に係る表示デバイスの製造方法を説明するためのフローチャートである。It is a flowchart for demonstrating the manufacturing method of the display device which concerns on Embodiment 1. 実施形態１に係るＴＦＴ層の製造方法を説明するためのフローチャートである。It is a flowchart for demonstrating the manufacturing method of the TFT layer which concerns on Embodiment 1. 実施形態１に係るＴＦＴ層の製造方法を説明するための工程断面図である。It is a process sectional view for demonstrating the manufacturing method of the TFT layer which concerns on Embodiment 1. FIG. 実施形態１に係るＴＦＴ層の製造方法を説明するための他の工程断面図である。It is another process sectional view for demonstrating the manufacturing method of the TFT layer which concerns on Embodiment 1. FIG. 実施形態１に係るＴＦＴ層の製造方法を説明するための他の工程断面図である。It is another process sectional view for demonstrating the manufacturing method of the TFT layer which concerns on Embodiment 1. FIG. 実施形態１に係るＴＦＴ層の製造方法を説明するための他の工程断面図である。It is another process sectional view for demonstrating the manufacturing method of the TFT layer which concerns on Embodiment 1. FIG. 実施形態２に係る表示デバイスの画素回路の一例を示す等価回路図である。It is an equivalent circuit diagram which shows an example of the pixel circuit of the display device which concerns on Embodiment 2. FIG. 実施形態２に係る表示デバイスの画素回路の構成例を示す平面図である。It is a top view which shows the structural example of the pixel circuit of the display device which concerns on Embodiment 2. FIG. 実施形態２に係るＴＦＴ層の、画素回路における構造の例を示す断面図である。It is sectional drawing which shows the example of the structure in the pixel circuit of the TFT layer which concerns on Embodiment 2. 変形例１に係る表示デバイスの画素回路の構成例を示す平面図である。It is a top view which shows the structural example of the pixel circuit of the display device which concerns on modification 1. FIG. 変形例１に係るＴＦＴ層の、画素回路における構造の例を示す断面図である。It is sectional drawing which shows the example of the structure in the pixel circuit of the TFT layer which concerns on modification 1. FIG. 変形例２および３に係る表示デバイスの画素回路の構成例を示す平面図である。It is a top view which shows the structural example of the pixel circuit of the display device which concerns on modification 2 and 3.
　〔実施形態１〕
　図２は、本実施形態に係る表示デバイス２の概略平面図である。本実施形態においては、表示デバイス２は、上方に向けて発光するトップエミッション型の表示デバイスであり、複数のサブ画素を備え、当該サブ画素ごとに発光素子を備えた表示領域ＤＡと、表示領域ＤＡの周囲に形成された額縁領域ＮＡとを備える。表示領域ＤＡの各配線から、額縁領域ＮＡに、引き回し配線ＴＬが引き出され、引き回し配線ＴＬが、額縁領域ＮＡに形成された端子部Ｔと接続してもよい。 [Embodiment 1]
FIG. 2 is a schematic plan view of the display device 2 according to the present embodiment. In the present embodiment, the display device 2 is a top-emission type display device that emits light upward, and includes a display area DA having a plurality of sub-pixels and a light emitting element for each sub-pixel, and a display area. It is provided with a frame area NA formed around the DA. A routing wiring TL may be drawn out from each wiring of the display area DA to the frame region NA, and the routing wiring TL may be connected to a terminal portion T formed in the frame region NA.
　図１は、本実施形態に係る表示デバイス２の、表示領域ＤＡにおける構造の例を示す断面図であり、図２のＡ－Ａ線矢視断面図である。表示デバイス２は、基材４上に各層が積層された構造を備えている。表示デバイス２は、基材４側から順に、ベースコート層６、ＴＦＴ層（薄膜トランジスタ層）８、および発光素子層１０を備える。表示デバイス２は、発光素子層１０の上層に、封止層を備えていてもよく、さらに、当該封止層上に、円偏光板等を含む機能フィルム等を備えていてもよい。 FIG. 1 is a cross-sectional view showing an example of the structure of the display device 2 according to the present embodiment in the display area DA, and is a cross-sectional view taken along the line AA of FIG. The display device 2 has a structure in which each layer is laminated on the base material 4. The display device 2 includes a base coat layer 6, a TFT layer (thin film transistor layer) 8, and a light emitting element layer 10 in this order from the base material 4 side. The display device 2 may be provided with a sealing layer on the upper layer of the light emitting element layer 10, and may be further provided with a functional film or the like including a circularly polarizing plate or the like on the sealing layer.
　基材４の材料としては、例えば、ポリエチレンテレフタレート（ＰＥＴ）が挙げられる。ベースコート層６は、表示デバイス２の使用時に、水分や不純物が、ＴＦＴ層８または発光素子層１０に到達することを防ぐ層である。ベースコート層６は、例えば、ＣＶＤにより形成される、酸化シリコン膜、窒化シリコン膜、あるいは酸窒化シリコン膜、またはこれらの積層膜で構成することができる。 Examples of the material of the base material 4 include polyethylene terephthalate (PET). The base coat layer 6 is a layer that prevents moisture and impurities from reaching the TFT layer 8 or the light emitting element layer 10 when the display device 2 is used. The base coat layer 6 can be composed of, for example, a silicon oxide film, a silicon nitride film, a silicon nitride film, or a laminated film thereof formed by CVD.
　本実施形態に係る表示デバイス２のＴＦＴ層８の各層について、図１に加え、図３を参照して説明する。図３は、ＴＦＴ層８についての平面図である。図３に示すＡ－Ａ線は、図２に示すＡ－Ａ線と対応している。また、図３においては、発光素子層１０、および後述する層間絶縁膜２０の図示を省略している。 Each layer of the TFT layer 8 of the display device 2 according to the present embodiment will be described with reference to FIG. 3 in addition to FIG. FIG. 3 is a plan view of the TFT layer 8. The AA line shown in FIG. 3 corresponds to the AA line shown in FIG. Further, in FIG. 3, the light emitting element layer 10 and the interlayer insulating film 20 described later are not shown.
　ＴＦＴ層８は、複数の薄膜トランジスタを備え、後述する発光素子層１０の発光素子ごとに、薄膜トランジスタを備えている。図１においては、複数の薄膜トランジスタの内、第１トランジスタ、特に、当該発光素子の駆動に関わる、駆動トランジスタＴ１を図示している。 The TFT layer 8 includes a plurality of thin film transistors, and each light emitting element of the light emitting element layer 10 described later includes a thin film transistor. In FIG. 1, among a plurality of thin film transistors, the first transistor, particularly the drive transistor T1 involved in driving the light emitting element is shown.
　駆動トランジスタＴ１のそれぞれは、下層から順に、酸化物半導体層１６と、ゲート絶縁膜１４と、ゲート電極１２と、無機保護絶縁膜１８と、ＴＦＴ電極層２８とを備える。 Each of the drive transistors T1 includes an oxide semiconductor layer 16, a gate insulating film 14, a gate electrode 12, an inorganic protective insulating film 18, and a TFT electrode layer 28 in this order from the lower layer.
　さらに、ＴＦＴ層８は、酸化物半導体層１６と無機保護絶縁膜１８とを覆う、層間絶縁膜２０をさらに含む。 Further, the TFT layer 8 further includes an interlayer insulating film 20 that covers the oxide semiconductor layer 16 and the inorganic protective insulating film 18.
　駆動トランジスタＴ１のそれぞれは、トップゲート型の薄膜トランジスタである。ゲート電極１２と重畳する、ゲート電極１２の下層側には、ゲート絶縁膜１４を介して、酸化物半導体層１６が形成されている。 Each of the drive transistors T1 is a top gate type thin film transistor. An oxide semiconductor layer 16 is formed on the lower layer side of the gate electrode 12, which overlaps with the gate electrode 12, via a gate insulating film 14.
　ゲート電極１２は、低抵抗のＣｕを含み、例えば、下層にＴｉ、上層にＣｕを備えた積層構造を備えていてもよい。本実施形態において、例えば、Ｔｉの幅はＣｕの幅よりも大きく、ゲート絶縁膜１４の幅はＴｉの幅よりも大きい。 The gate electrode 12 contains Cu with low resistance, and may have, for example, a laminated structure having Ti in the lower layer and Cu in the upper layer. In the present embodiment, for example, the width of Ti is larger than the width of Cu, and the width of the gate insulating film 14 is larger than the width of Ti.
　酸化物半導体層１６は、チャネル領域２２と、ソース領域２４と、ドレイン領域２６とを備える。チャネル領域２２は、ゲート絶縁膜１４を介して、ゲート電極１２と対向する。ソース領域２４と、ドレイン領域２６とは、チャネル領域２２を挟む位置に形成されるとともに、平面視において、ゲート絶縁膜１４から露出している。 The oxide semiconductor layer 16 includes a channel region 22, a source region 24, and a drain region 26. The channel region 22 faces the gate electrode 12 via the gate insulating film 14. The source region 24 and the drain region 26 are formed at positions sandwiching the channel region 22, and are exposed from the gate insulating film 14 in a plan view.
　酸化物半導体層１６に含まれる酸化物半導体は、アモルファス酸化物半導体であってもよいし、結晶質部分を有する結晶質酸化物半導体であってもよい。結晶質酸化物半導体としては、多結晶酸化物半導体、微結晶酸化物半導体、ｃ軸が層面に概ね垂直に配向した結晶質酸化物半導体などが挙げられる。 The oxide semiconductor contained in the oxide semiconductor layer 16 may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface.
　酸化物半導体層１６は、２層以上の積層構造を有していてもよい。酸化物半導体層１６が積層構造を有する場合には、酸化物半導体層１６は、非晶質酸化物半導体層と結晶質酸化物半導体層とを含んでいてもよい。あるいは、結晶構造の異なる複数の結晶質酸化物半導体層を含んでいてもよい。また、複数の非晶質酸化物半導体層を含んでいてもよい。 The oxide semiconductor layer 16 may have a laminated structure of two or more layers. When the oxide semiconductor layer 16 has a laminated structure, the oxide semiconductor layer 16 may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, it may contain a plurality of crystalline oxide semiconductor layers having different crystal structures. Further, a plurality of amorphous oxide semiconductor layers may be contained.
　非晶質酸化物半導体および上記の各結晶質酸化物半導体の材料、構造、成膜方法、積層構造を有する酸化物半導体層の構成などは、例えば特開２０１４－００７３９９号公報に記載されている。参考のために、特開２０１４－００７３９９号公報の開示内容の全てを本明細書に援用する。 The materials, structures, film forming methods, configurations of oxide semiconductor layers having a laminated structure, etc. of the amorphous oxide semiconductor and each of the above crystalline oxide semiconductors are described in, for example, Japanese Patent Application Laid-Open No. 2014-007399. .. For reference, all the disclosure contents of Japanese Patent Application Laid-Open No. 2014-007399 are incorporated herein by reference.
　酸化物半導体層１６は、例えば、Ｉｎ、ＧａおよびＺｎのうち少なくとも１種の金属元素を含んでもよい。本実施形態では、酸化物半導体層１６は、例えば、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体（例えば酸化インジウムガリウム亜鉛）を含む。ここで、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体は、Ｉｎ（インジウム）、Ｇａ（ガリウム）、Ｚｎ（亜鉛）の三元系酸化物であって、Ｉｎ、ＧａおよびＺｎの割合（組成比）は特に限定されず、例えばＩｎ：Ｇａ：Ｚｎ＝２：２：１、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１、Ｉｎ：Ｇａ：Ｚｎ＝１：１：２等を含む。このような酸化物半導体層１６は、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体を含む酸化物半導体膜から形成され得る。 The oxide semiconductor layer 16 may contain at least one metal element among, for example, In, Ga and Zn. In the present embodiment, the oxide semiconductor layer 16 includes, for example, an In—Ga—Zn—O-based semiconductor (for example, indium gallium zinc oxide). Here, the In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio of In, Ga, and Zn (composition ratio). Is not particularly limited, and includes, for example, In: Ga: Zn = 2: 2: 1, In: Ga: Zn = 1: 1: 1, In: Ga: Zn = 1: 1: 2, and the like. Such an oxide semiconductor layer 16 can be formed from an oxide semiconductor film containing an In—Ga—Zn—O based semiconductor.
　Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体は、アモルファスでもよいし、結晶質でもよい。結晶質Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体としては、ｃ軸が層面に概ね垂直に配向した結晶質Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体が好ましい。 The In-Ga-Zn-O-based semiconductor may be amorphous or crystalline. As the crystalline In—Ga—Zn—O-based semiconductor, a crystalline In—Ga—Zn—O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable.
　なお、結晶質Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体の結晶構造は、例えば、上述した特開２０１４－００７３９９号公報、特開２０１２－１３４４７５号公報、特開２０１４－２０９７２７号公報などに開示されている。参考のために、特開２０１２－１３４４７５号公報および特開２０１４－２０９７２７号公報の開示内容の全てを本明細書に援用する。 The crystal structure of crystalline In-Ga-Zn-O-based semiconductors is disclosed in, for example, JP-A-2014-007399, JP-A-2012-134475, JP-A-2014-209727, and the like described above. ing. For reference, all the disclosure contents of JP2012-134475 and JP2014-209727 are incorporated herein by reference.
　Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体層を有するＴＦＴは、高い移動度（ａ－ＳｉＴＦＴに比べ２０倍超）および低いリーク電流（ａ－ＳｉＴＦＴに比べ１００分の１未満）を有しているため、駆動トランジスタＴ１に対し、好適に用いられる。 Because a TFT having an In—Ga—Zn—O semiconductor layer has high mobility (more than 20 times that of a—SiTFT) and low leakage current (less than 1/100 of that of a—SiTFT). , Is preferably used for the drive transistor T1.
　酸化物半導体層１６は、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体の代わりに、他の酸化物半導体を含んでいてもよい。例えばＩｎ－Ｓｎ－Ｚｎ－Ｏ系半導体（例えばＩｎ２Ｏ３－ＳｎＯ２－ＺｎＯ；ＩｎＳｎＺｎＯ）を含んでもよい。Ｉｎ－Ｓｎ－Ｚｎ－Ｏ系半導体は、Ｉｎ（インジウム）、Ｓｎ（スズ）およびＺｎ（亜鉛）の三元系酸化物である。 The oxide semiconductor layer 16 may contain another oxide semiconductor instead of the In—Ga—Zn—O-based semiconductor. For example In-Sn-Zn-O-based semiconductor (for example In 2 O 3 -SnO 2 -ZnO; InSnZnO) may contain. The In—Sn—Zn—O semiconductor is a ternary oxide of In (indium), Sn (tin) and Zn (zinc).
　あるいは、酸化物半導体層１６は、Ｉｎ－Ａｌ－Ｚｎ－Ｏ系半導体、Ｉｎ－Ａｌ－Ｓｎ－Ｚｎ－Ｏ系半導体、Ｚｎ－Ｏ系半導体、Ｉｎ－Ｚｎ－Ｏ系半導体、Ｚｎ－Ｔｉ－Ｏ系半導体、Ｃｄ－Ｇｅ－Ｏ系半導体、Ｃｄ－Ｐｂ－Ｏ系半導体、ＣｄＯ（酸化カドミウム）、Ｍｇ－Ｚｎ－Ｏ系半導体、Ｉｎ－Ｇａ－Ｓｎ－Ｏ系半導体、Ｉｎ－Ｇａ－Ｏ系半導体、Ｚｒ－Ｉｎ－Ｚｎ－Ｏ系半導体、Ｈｆ－Ｉｎ－Ｚｎ－Ｏ系半導体、Ａｌ－Ｇａ－Ｚｎ－Ｏ系半導体、Ｇａ－Ｚｎ－Ｏ系半導体、Ｉｎ－Ｇａ－Ｚｎ－Ｓｎ－Ｏ系半導体、ＩｎＧａＯ３（ＺｎＯ）５、酸化マグネシウム亜鉛（ＭｇｘＺｎ１－ｘＯ）、酸化カドミウム亜鉛（ＣｄｘＺｎ１－ｘＯ）などを含んでいてもよい。 Alternatively, the oxide semiconductor layer 16 is an In—Al—Zn—O system semiconductor, an In—Al—Sn—Zn—O system semiconductor, a Zn—O system semiconductor, an In—Zn—O system semiconductor, a Zn—Ti—O. System semiconductors, Cd-Ge-O system semiconductors, Cd-Pb-O system semiconductors, CdO (cadmium oxide), Mg-Zn-O system semiconductors, In-Ga-Sn-O system semiconductors, In-Ga-O system semiconductors , Zr-In-Zn-O series semiconductor, Hf-In-Zn-O series semiconductor, Al-Ga-Zn-O series semiconductor, Ga-Zn-O series semiconductor, In-Ga-Zn-Sn-O series semiconductor , InGaO 3 (ZnO) 5 , zinc oxide (Mg x Zn 1-x O), zinc oxide cadmium (Cd x Zn 1-x O), and the like may be contained.
　Ｚｎ－Ｏ系半導体としては、１族元素、１３族元素、１４族元素、１５族元素または１７族元素等のうち一種、または複数種の不純物元素が添加されたＺｎＯの非晶質（アモルファス）状態、多結晶状態または非晶質状態と多結晶状態が混在する微結晶状態のもの、または何も不純物元素が添加されていないものを用いることができる。 As the Zn—O-based semiconductor, ZnO amorphous (amorphous) to which one or more of group 1 elements, group 13 elements, group 14 elements, group 15 elements, group 17 elements, and the like are added. A state, a polycrystalline state, a microcrystalline state in which an amorphous state and a polycrystalline state are mixed, or a state in which no impurity element is added can be used.
　無機保護絶縁膜１８は、平面視において、ゲート電極１２の少なくとも一部を覆う。特に、無機保護絶縁膜１８は、酸化物半導体層１６のチャネル領域２２のチャネル長方向における、ゲート電極１２の端面を覆う。図１に示すように、本実施形態においては、無機保護絶縁膜１８が、ゲート電極１２の全体を覆うように、駆動トランジスタＴ１ごとに、島状に形成されることが好ましい。 The inorganic protective insulating film 18 covers at least a part of the gate electrode 12 in a plan view. In particular, the inorganic protective insulating film 18 covers the end face of the gate electrode 12 in the channel length direction of the channel region 22 of the oxide semiconductor layer 16. As shown in FIG. 1, in the present embodiment, the inorganic protective insulating film 18 is preferably formed in an island shape for each drive transistor T1 so as to cover the entire gate electrode 12.
　なお、図３においては、ゲート電極１２と無機保護絶縁膜１８との位置関係をより詳細に示すため、発光素子層１０、および層間絶縁膜２０の図示を省略している。 Note that in FIG. 3, in order to show the positional relationship between the gate electrode 12 and the inorganic protective insulating film 18 in more detail, the light emitting element layer 10 and the interlayer insulating film 20 are not shown.
　ＴＦＴ電極層２８は、酸化物半導体層１６のソース領域２４と電気的に接続するソース電極２８Ｓと、酸化物半導体層１６のドレイン領域２６と電気的に接続するドレイン電極２８Ｄとを備える。ソース領域２４とソース電極２８Ｓとは、層間絶縁膜２０の開口に形成された、ソースコンタクト部３０Ｓを介して電気的に接続されている。同様に、ドレイン領域２６とドレイン電極２８Ｄとは、層間絶縁膜２０の開口に形成された、ドレインコンタクト部３０Ｄを介して電気的に接続されている。 The TFT electrode layer 28 includes a source electrode 28S that is electrically connected to the source region 24 of the oxide semiconductor layer 16 and a drain electrode 28D that is electrically connected to the drain region 26 of the oxide semiconductor layer 16. The source region 24 and the source electrode 28S are electrically connected to each other via a source contact portion 30S formed in the opening of the interlayer insulating film 20. Similarly, the drain region 26 and the drain electrode 28D are electrically connected via a drain contact portion 30D formed in the opening of the interlayer insulating film 20.
　ゲート絶縁膜１４は、シリコン酸化膜であることが好ましい。シリコン酸化膜は、シリコン窒化膜と比較して、誘電率が小さい。このため、本実施形態においては、ゲート絶縁膜１４がシリコン酸化膜からなることにより、ゲート絶縁膜１４と他の配線との寄生容量が低減される。また、ゲート絶縁膜１４がシリコン酸化膜からなることにより、ゲート絶縁膜１４が水素を含まないため、酸化物半導体層１６へのダメージを低減できる。また、層間絶縁膜２０は、シリコン窒化膜であってもよく、無機保護絶縁膜１８は、シリコン酸化膜、または、シリコン窒化膜であってもよい。 The gate insulating film 14 is preferably a silicon oxide film. The silicon oxide film has a smaller dielectric constant than the silicon nitride film. Therefore, in the present embodiment, since the gate insulating film 14 is made of a silicon oxide film, the parasitic capacitance between the gate insulating film 14 and other wiring is reduced. Further, since the gate insulating film 14 is made of a silicon oxide film, the gate insulating film 14 does not contain hydrogen, so that damage to the oxide semiconductor layer 16 can be reduced. Further, the interlayer insulating film 20 may be a silicon nitride film, and the inorganic protective insulating film 18 may be a silicon oxide film or a silicon nitride film.
　発光素子層１０は、下層から、平坦化膜３２、第１電極３４、エッジカバー３６、機能層３８、および、第２電極４０を備える。発光素子層１０には、第１電極３４と、機能層３８と、第２電極４０とを含む、複数の発光素子が形成される。発光素子のそれぞれは、当該発光素子ごとに形成される島状の第１電極３４および機能層３８と、当該発光素子に共通に形成される第２電極４０とを含む。なお、機能層３８の一部は、発光素子に共通に形成されていてもよい。 The light emitting element layer 10 includes a flattening film 32, a first electrode 34, an edge cover 36, a functional layer 38, and a second electrode 40 from the lower layer. A plurality of light emitting elements including a first electrode 34, a functional layer 38, and a second electrode 40 are formed in the light emitting element layer 10. Each of the light emitting elements includes an island-shaped first electrode 34 and a functional layer 38 formed for each light emitting element, and a second electrode 40 commonly formed for the light emitting element. A part of the functional layer 38 may be formed in common with the light emitting element.
　平坦化膜３２は、層間絶縁膜２０の上層を平坦化し、例えば、ポリイミド、アクリル等の感光性有機材料を含んでいてもよい。 The flattening film 32 flattens the upper layer of the interlayer insulating film 20 and may contain a photosensitive organic material such as polyimide or acrylic.
　第１電極３４は、発光素子ごとに島状に形成され、駆動トランジスタＴ１のソース電極２８Ｓと、平坦化膜３２の開口に形成された、第１電極コンタクト部４２を介して電気的に接続する。第１電極３４は、例えば、アノードであってもよく、例えば、ＩＴＯ（Indium Tin Oxide）とＡｇを含む合金との積層構造等、光反射性を有する構造を有していてもよい。 The first electrode 34 is formed in an island shape for each light emitting element, and is electrically connected to the source electrode 28S of the drive transistor T1 via the first electrode contact portion 42 formed in the opening of the flattening film 32. .. The first electrode 34 may be, for example, an anode, and may have a structure having light reflectivity, such as a laminated structure of ITO (Indium Tin Oxide) and an alloy containing Ag.
　エッジカバー３６は、第１電極３４のそれぞれの端部を覆う位置に形成される。エッジカバー３６は、機能層３８が、発光素子ごとに形成されるように、機能層３８を区画する。 The edge cover 36 is formed at a position that covers each end of the first electrode 34. The edge cover 36 partitions the functional layer 38 so that the functional layer 38 is formed for each light emitting element.
　機能層３８は、少なくとも発光層を備え、当該発光層は、発光素子ごとに島状に形成されている。機能層３８は、電荷注入層、電荷輸送層、または電荷ブロック層を備えていてもよい。 The functional layer 38 includes at least a light emitting layer, and the light emitting layer is formed in an island shape for each light emitting element. The functional layer 38 may include a charge injection layer, a charge transport layer, or a charge block layer.
　第２電極４０は、全ての発光素子に共通に形成されている。第２電極４０は、例えば、カソードであってもよく、ＭｇＡｇ合金（極薄膜）、ＩＴＯ（Indium Tin Oxide）、ＩＺＯ（Indium Zinc Oxide）等の透光性の導電材で構成されていてもよい。 The second electrode 40 is formed in common to all light emitting elements. The second electrode 40 may be, for example, a cathode, or may be made of a translucent conductive material such as MgAg alloy (ultra-thin film), ITO (Indium Tin Oxide), or IZO (Indium Zinc Oxide). ..
　発光素子層１０の備える発光素子は、有機発光ダイオード（ＯＬＥＤ）素子であってもよい。この場合、第１電極３４がエッジカバー３６から露出する面上には、機能層３８として、例えば、正孔注入層、正孔輸送層、発光層、電子輸送層、電子注入層が積層されていてもよい。 The light emitting element included in the light emitting element layer 10 may be an organic light emitting diode (OLED) element. In this case, for example, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are laminated as the functional layer 38 on the surface where the first electrode 34 is exposed from the edge cover 36. You may.
　発光素子層１０の備える発光素子が、ＯＬＥＤ素子である場合には、第１電極３４および第２電極４０間の駆動電流によって、正孔と電子が機能層３８の発光層内において再結合する。これによって生じたエキシトンが基底状態に落ちることによって、発光層から光が放出される。第２電極４０が透光性を有し、第１電極３４が光反射性を有する場合、発光層から放出された光は上方に向かうため、表示デバイス２は、トップエミッション型の表示デバイスとなる。 When the light emitting element included in the light emitting element layer 10 is an OLED element, holes and electrons are recombined in the light emitting layer of the functional layer 38 by the driving current between the first electrode 34 and the second electrode 40. Light is emitted from the light emitting layer when the resulting excitons fall to the ground state. When the second electrode 40 has translucency and the first electrode 34 has light reflectivity, the light emitted from the light emitting layer goes upward, so that the display device 2 becomes a top emission type display device. ..
　発光素子層１０は、ＯＬＥＤ素子を備える場合に限られず、無機発光ダイオード素子あるいは量子ドット発光ダイオード素子を、発光素子として備えていてもよい。 The light emitting element layer 10 is not limited to the case where it includes an OLED element, and may include an inorganic light emitting diode element or a quantum dot light emitting diode element as a light emitting element.
　次に、図４を参照し、本実施形態に係る表示デバイス２の製造方法について詳細に説明する。図４は、本実施形態に係る表示デバイス２の各製造工程を示すフローチャートである。 Next, with reference to FIG. 4, the manufacturing method of the display device 2 according to the present embodiment will be described in detail. FIG. 4 is a flowchart showing each manufacturing process of the display device 2 according to the present embodiment.
　はじめに、透光性の基材（例えば、マザーガラス基板）上にベースコート層６を形成する（ステップＳ１）。ベースコート層６の形成は、従来公知の手法を採用できる。 First, the base coat layer 6 is formed on a translucent base material (for example, a mother glass substrate) (step S1). A conventionally known method can be adopted for forming the base coat layer 6.
　次いで、ベースコート層６の上層にＴＦＴ層８を形成する（ステップＳ２）。ステップＳ２における、ＴＦＴ層８の各層の形成方法について、図５から図９を参照して、より詳細に説明する。図５は、本実施形態における、ＴＦＴ層８の形成工程について示すフローチャートである。図６から図９は、図５のフローチャートに基づいて実施される、ＴＦＴ層８の形成工程をより詳細に説明するための工程断面図である。なお、図６から図９においては、何れも、図１に対応する位置における工程断面図を示している。 Next, the TFT layer 8 is formed on the upper layer of the base coat layer 6 (step S2). The method of forming each layer of the TFT layer 8 in step S2 will be described in more detail with reference to FIGS. 5 to 9. FIG. 5 is a flowchart showing a process of forming the TFT layer 8 in the present embodiment. 6 to 9 are process cross-sectional views for explaining the forming step of the TFT layer 8 in more detail, which is carried out based on the flowchart of FIG. In addition, in each of FIGS. 6 to 9, the process sectional view at the position corresponding to FIG. 1 is shown.
　ステップＳ１の実行により、図６の（ａ）に示す構造が得られる。ステップＳ２においては、始めに、図６の（ｂ）に示すように、導体化処理を行う前の酸化物半導体層１６Ｐを、ベースコート層６の上層に形成する（ステップＳ１１）。酸化物半導体層１６Ｐは、例えば、酸化物半導体材料の膜を成膜し、パターニングすることにより形成してもよい。 By executing step S1, the structure shown in FIG. 6A is obtained. In step S2, first, as shown in FIG. 6B, the oxide semiconductor layer 16P before the conductor formation treatment is formed on the upper layer of the base coat layer 6 (step S11). The oxide semiconductor layer 16P may be formed, for example, by forming a film of an oxide semiconductor material and patterning it.
　次いで、図６の（ｃ）に示すように、ベースコート層６および酸化物半導体層１６Ｐの上層に、ゲート絶縁膜１４を成膜する（ステップＳ１２）。ゲート絶縁膜１４の成膜は、低温ＣＶＤ等によって実施してもよい。 Next, as shown in FIG. 6C, a gate insulating film 14 is formed on the base coat layer 6 and the oxide semiconductor layer 16P (step S12). The formation of the gate insulating film 14 may be carried out by low temperature CVD or the like.
　次いで、図６の（ｄ）に示すように、ゲート絶縁膜１４の上層に、ゲート電極１２を形成する（ステップＳ１３）。ゲート電極１２は、Ｃｕを含む金属材料を、ゲート絶縁膜１４の上層にスパッタ法により成膜した後、エッチング法によりパターニングすることにより得られてもよい。 Next, as shown in FIG. 6D, the gate electrode 12 is formed on the upper layer of the gate insulating film 14 (step S13). The gate electrode 12 may be obtained by forming a metal material containing Cu on the upper layer of the gate insulating film 14 by a sputtering method and then patterning it by an etching method.
　次いで、図７の（ａ）に示すように、ゲート絶縁膜１４およびゲート電極１２の上層に、無機保護絶縁膜１８を成膜する（ステップＳ１４）。無機保護絶縁膜１８の成膜は、低温ＣＶＤ等によって実施してもよい。 Next, as shown in FIG. 7A, an inorganic protective insulating film 18 is formed on the upper layers of the gate insulating film 14 and the gate electrode 12 (step S14). The film formation of the inorganic protective insulating film 18 may be carried out by low temperature CVD or the like.
　次いで、ゲート絶縁膜１４と、無機保護絶縁膜１８とを、併せてパターニングすることにより形成する（ステップＳ１５）。ステップＳ１５においては、はじめに、図７の（ｂ）に示すように、無機保護絶縁膜１８の上層に、レジストマスク４４を形成する。レジストマスク４４は、ゲート電極１２と重畳する位置に形成され、特に、酸化物半導体層１６Ｐのうち、チャネル領域２２を形成する位置と重畳するように形成される。次いで、レジストマスク４４が形成された状態において、ゲート絶縁膜１４と無機保護絶縁膜１８とを、ウエットエッチング法またはドライエッチング法等により、一度にエッチングする。これにより、酸化物半導体層１６Ｐのうち、ゲート電極１２と重畳する部分を含む、レジストマスク４４と重畳する部分を挟む部分が、ゲート絶縁膜１４から露出する。 Next, the gate insulating film 14 and the inorganic protective insulating film 18 are formed by patterning together (step S15). In step S15, first, as shown in FIG. 7B, a resist mask 44 is formed on the upper layer of the inorganic protective insulating film 18. The resist mask 44 is formed at a position where it overlaps with the gate electrode 12, and in particular, is formed so as to overlap with a position where the channel region 22 is formed in the oxide semiconductor layer 16P. Next, in the state where the resist mask 44 is formed, the gate insulating film 14 and the inorganic protective insulating film 18 are etched at once by a wet etching method, a dry etching method, or the like. As a result, the portion of the oxide semiconductor layer 16P that sandwiches the portion that overlaps with the resist mask 44, including the portion that overlaps with the gate electrode 12, is exposed from the gate insulating film 14.
　単一のレジストマスク４４の存在下において、ゲート絶縁膜１４と無機保護絶縁膜１８とが同時にエッチングされる。このため、本実施形態においては、ゲート絶縁膜１４と無機保護絶縁膜１８とが整合するパターンを、パターニングにより形成する。特に、無機保護絶縁膜１８は、上述したチャネル長方向において、ゲート絶縁膜１４と整合する位置に設けられている。 In the presence of a single resist mask 44, the gate insulating film 14 and the inorganic protective insulating film 18 are simultaneously etched. Therefore, in the present embodiment, a pattern in which the gate insulating film 14 and the inorganic protective insulating film 18 match is formed by patterning. In particular, the inorganic protective insulating film 18 is provided at a position consistent with the gate insulating film 14 in the above-mentioned channel length direction.
　ここで、「ゲート絶縁膜１４と無機保護絶縁膜１８とが整合する」とは、ゲート絶縁膜１４と無機保護絶縁膜１８とが、同一のレジストパターンにおけるパターニングによって形成された層であることを示す。すなわち、本明細書において、「２層が整合する」とは、当該２層が厳密に一致することを意味せず、エッチングレートの違い等によって生じる、数μｍ程度の寸法のズレも含まれる。 Here, "the gate insulating film 14 and the inorganic protective insulating film 18 are aligned" means that the gate insulating film 14 and the inorganic protective insulating film 18 are layers formed by patterning in the same resist pattern. Shown. That is, in the present specification, "the two layers are aligned" does not mean that the two layers are exactly the same, and includes a dimensional deviation of about several μm caused by a difference in etching rate or the like.
　ゲート絶縁膜１４と無機保護絶縁膜１８とのエッチングが完了した後、レジストマスク４４は適宜除去すればよい。このように、同じレジストマスク４４を用い、上部のゲート絶縁膜１４と無機保護絶縁膜１８とのパターニング形状を整合させることができる。これによって、工程を簡略化しつつ、両者を精度良く位置合わせすることができる。 After the etching of the gate insulating film 14 and the inorganic protective insulating film 18 is completed, the resist mask 44 may be appropriately removed. In this way, the same resist mask 44 can be used to match the patterning shapes of the upper gate insulating film 14 and the inorganic protective insulating film 18. As a result, both can be accurately aligned while simplifying the process.
　また、本実施形態においては、対象とする２つの層の側面が垂直方向に面一である場合だけでなく、その２つの層の側面が連続してテーパー形状等の傾斜面をなす場合をも含み、厳密に側面が一致することに限定するものではない。例えば、無機保護絶縁膜１８が、ウエットエッチングにより形成されると共に、ゲート絶縁膜１４が、ドライエッチング等により形成される場合のように、ゲート絶縁膜１４と無機保護絶縁膜１８との間のエッチングレート等の差異が生じる場合がある。本実施形態においては、当該差異による、ゲート絶縁膜１４と無機保護絶縁膜１８との間の、２μｍ～３μｍ程度の側面のずれを含む。 Further, in the present embodiment, not only the side surfaces of the two target layers are flush with each other in the vertical direction, but also the side surfaces of the two layers continuously form an inclined surface such as a tapered shape. Including, it is not limited to strictly matching aspects. For example, as in the case where the inorganic protective insulating film 18 is formed by wet etching and the gate insulating film 14 is formed by dry etching or the like, the etching between the gate insulating film 14 and the inorganic protective insulating film 18 is performed. Differences in rates, etc. may occur. In the present embodiment, the lateral displacement of about 2 μm to 3 μm between the gate insulating film 14 and the inorganic protective insulating film 18 due to the difference is included.
　次いで、図７の（ｃ）に示すように、基材４上の各層の上方から、水素プラズマ等のプラズマの照射を実行する（ステップＳ１６）。ステップＳ１６において実施されるプラズマ照射は、照射された酸化物半導体層１６Ｐに酸素欠陥が生じ、導体化される限り、従来公知の手法により実施されてもよい。 Next, as shown in FIG. 7 (c), irradiation of plasma such as hydrogen plasma is executed from above each layer on the base material 4 (step S16). The plasma irradiation carried out in step S16 may be carried out by a conventionally known method as long as the irradiated oxide semiconductor layer 16P has an oxygen defect and is made into a conductor.
　ステップＳ１６により、ゲート絶縁膜１４から露出した酸化物半導体層１６Ｐが導体化される。これにより、図８の（ａ）に示すように、酸化物半導体層１６Ｐの、ゲート絶縁膜１４から露出した位置に、ソース領域２４とドレイン領域２６とが形成される。なお、酸化物半導体層１６Ｐの、ゲート絶縁膜１４から露出しない、ゲート絶縁膜１４と重畳する部分は、チャネル領域２２となる。これにより、チャネル領域２２、ソース領域２４、およびドレイン領域２６を含む酸化物半導体層１６が得られる。 In step S16, the oxide semiconductor layer 16P exposed from the gate insulating film 14 is made into a conductor. As a result, as shown in FIG. 8A, a source region 24 and a drain region 26 are formed at positions exposed from the gate insulating film 14 of the oxide semiconductor layer 16P. The portion of the oxide semiconductor layer 16P that is not exposed from the gate insulating film 14 and overlaps with the gate insulating film 14 is the channel region 22. As a result, the oxide semiconductor layer 16 including the channel region 22, the source region 24, and the drain region 26 is obtained.
　次いで、図８の（ｂ）に示すように、層間絶縁膜２０の材料を、基材４上の各層の上方から塗布する（ステップＳ１７）。ステップＳ１７は、例えば、ポリイミド、アクリル等を含む感光性有機材料を、従来公知の手法により塗布することにより実行してもよい。 Next, as shown in FIG. 8B, the material of the interlayer insulating film 20 is applied from above each layer on the base material 4 (step S17). Step S17 may be performed by applying, for example, a photosensitive organic material containing polyimide, acrylic or the like by a conventionally known method.
　次いで、フォトエッチング等により、層間絶縁膜２０に、図９の（ａ）に示す、ソースコンタクトホール４６Ｓおよびドレインコンタクトホール４６Ｄを形成する（ステップＳ１８）。ソースコンタクトホール４６Ｓは、ソース領域２４の一部と重畳する位置に形成され、ドレインコンタクトホール４６Ｄは、ドレイン領域２６の一部と重畳する位置に形成される。 Next, the source contact hole 46S and the drain contact hole 46D shown in FIG. 9A are formed on the interlayer insulating film 20 by photoetching or the like (step S18). The source contact hole 46S is formed at a position where it overlaps with a part of the source region 24, and the drain contact hole 46D is formed at a position where it overlaps with a part of the drain region 26.
　次いで、図９の（ｂ）に示すように、ＴＦＴ電極層２８を形成する（ステップＳ１９）。ここで、ＴＦＴ電極層２８のソース電極２８Ｓを、ソースコンタクトホール４６Ｓと重畳する位置に形成することにより、ソース領域２４とソース電極２８Ｓとを電気的に接続する、ソースコンタクト部３０Ｓが形成される。また、ＴＦＴ電極層２８のドレイン電極２８Ｄを、ドレインコンタクトホール４６Ｄと重畳する位置に形成することにより、ドレイン領域２６とドレイン電極２８Ｄとを電気的に接続する、ドレインコンタクト部３０Ｄが形成される。 Next, as shown in FIG. 9B, the TFT electrode layer 28 is formed (step S19). Here, by forming the source electrode 28S of the TFT electrode layer 28 at a position overlapping the source contact hole 46S, a source contact portion 30S that electrically connects the source region 24 and the source electrode 28S is formed. .. Further, by forming the drain electrode 28D of the TFT electrode layer 28 at a position where it overlaps with the drain contact hole 46D, a drain contact portion 30D that electrically connects the drain region 26 and the drain electrode 28D is formed.
　以上により、図９の（ｂ）に示す、駆動トランジスタＴ１が形成される。なお、本実施形態においては、ステップＳ２において、駆動トランジスタＴ１の他、ＴＦＴ層８が備える薄膜トランジスタを、同時に形成してもよい。 From the above, the drive transistor T1 shown in FIG. 9B is formed. In this embodiment, in addition to the drive transistor T1, the thin film transistor included in the TFT layer 8 may be formed at the same time in step S2.
　ステップＳ２に次いで、発光素子層１０を形成する（ステップＳ３）。発光素子層１０の各層の形成方法は、従来公知の手法を採用できる。なお、本実施形態においては、ステップＳ３に次いで、発光素子層１０の上に、封止層を介して円偏光板を形成する工程を実施してもよい。次いで、基材、ベースコート層６、ＴＦＴ層８、発光素子層１０、円偏光板を含む積層体を分断し、複数の個片を得る（ステップＳ４）。次いで、端子部Ｔに電子回路基板（例えば、ＩＣチップ）をマウントし、表示デバイス２とする（ステップＳ５）。 Following step S2, the light emitting element layer 10 is formed (step S3). As a method for forming each layer of the light emitting element layer 10, a conventionally known method can be adopted. In this embodiment, following step S3, a step of forming a circularly polarizing plate on the light emitting element layer 10 via a sealing layer may be performed. Next, the laminate including the base material, the base coat layer 6, the TFT layer 8, the light emitting element layer 10, and the circularly polarizing plate is divided to obtain a plurality of individual pieces (step S4). Next, an electronic circuit board (for example, an IC chip) is mounted on the terminal portion T to form the display device 2 (step S5).
　なお、本実施形態においては、上述した透光性のガラス基板を、そのまま基材４としてもよい。しかし、一部工程を追加することにより、フレキシブルな表示デバイス２を製造することが可能である。 In the present embodiment, the above-mentioned translucent glass substrate may be used as the base material 4 as it is. However, it is possible to manufacture the flexible display device 2 by adding a part of the steps.
　例えば、ステップＳ５に次いで、透光性の支持基板越しにベースコート層６の下面にレーザ光を照射して、基材およびベースコート層６間の結合力を低下させ、基材をベースコート層６から剥離する。次いで、ベースコート層６の下面に、ＰＥＴフィルム等の下面フィルムを貼り付け、基材４とする。これにより、フレキシブルな表示デバイス２が得られる。 For example, following step S5, the lower surface of the base coat layer 6 is irradiated with laser light through the translucent support substrate to reduce the bonding force between the base material and the base coat layer 6, and the base material is peeled from the base coat layer 6. To do. Next, a lower surface film such as a PET film is attached to the lower surface of the base coat layer 6 to form a base material 4. As a result, a flexible display device 2 can be obtained.
　本実施形態においては、ステップＳ１３におけるゲート電極１２の形成後、ステップＳ１６において、ゲート絶縁膜１４から露出する酸化物半導体層１６への、プラズマの照射が実行される。ここで、ステップＳ１６において、ゲート電極１２の少なくとも一部、特に、チャネル長方向のゲート電極１２の端面が、無機保護絶縁膜１８によって覆われた状態において、プラズマの照射が実行される。 In the present embodiment, after the gate electrode 12 is formed in step S13, plasma irradiation is executed on the oxide semiconductor layer 16 exposed from the gate insulating film 14 in step S16. Here, in step S16, plasma irradiation is executed in a state where at least a part of the gate electrode 12, particularly the end face of the gate electrode 12 in the channel length direction is covered with the inorganic protective insulating film 18.
　このため、本実施形態においては、ゲート電極１２が低抵抗のＣｕを含んでいるものの、ゲート電極１２へのプラズマの照射量を低減でき、ゲート電極１２からの静電気放電の発生を低減できる。したがって、ゲート電極１２からの静電気放電による、酸化物半導体層１６のチャネル領域２２へのダメージが低減され、ひいては、表示デバイス２の製造工程における歩留まりが改善する。 Therefore, in the present embodiment, although the gate electrode 12 contains low-resistance Cu, the amount of plasma irradiation to the gate electrode 12 can be reduced, and the generation of electrostatic discharge from the gate electrode 12 can be reduced. Therefore, the damage to the channel region 22 of the oxide semiconductor layer 16 due to the electrostatic discharge from the gate electrode 12 is reduced, and the yield in the manufacturing process of the display device 2 is improved.
　〔実施形態２〕
　以下では、説明便宜のために、図面上の縦方向を列方向とし、図面上の横方向を行方向とし、斜め方向は行方向および列方向を基準とする。なお、例えば行方向は、表示デバイスの１つのエッジ（１辺）と平行の関係にあってもよいし、直交の関係にあってもよいし、斜めの関係にあってもよい。また、サブ画素（サブピクセル）とは、独立に駆動される最小の表示構成である。また、本実施形態において、同層とは、同一プロセスによって形成された層であることを示し、同一の材料を備えている。 [Embodiment 2]
In the following, for convenience of explanation, the vertical direction on the drawing is the column direction, the horizontal direction on the drawing is the row direction, and the diagonal direction is based on the row direction and the column direction. For example, the row direction may have a parallel relationship with one edge (one side) of the display device, an orthogonal relationship, or an oblique relationship. Further, the sub-pixel (sub-pixel) is the minimum display configuration that is driven independently. Further, in the present embodiment, the same layer indicates that the layer is formed by the same process, and includes the same material.
　本実施形態に係る表示デバイス２は、前実施形態に係る表示デバイス２と、同一の層構造を備えている。本実施形態に係る表示デバイス２は、前実施形態に係る表示デバイス２と比較して、ＴＦＴ層８が、表示デバイス２が備えるサブ画素ごとに、画素回路を備えている点においてのみ、構成が異なる。 The display device 2 according to the present embodiment has the same layer structure as the display device 2 according to the previous embodiment. The display device 2 according to the present embodiment has a configuration as compared with the display device 2 according to the previous embodiment only in that the TFT layer 8 includes a pixel circuit for each sub-pixel included in the display device 2. different.
　図１０は、本実施形態に係る表示デバイス２が備えるサブ画素ＳＰの構成例を示す回路図である。図１１は、本実施形態に係るサブ画素ＳＰが備える画素回路をより詳細に説明するための平面図であり、図１０の領域Ｂについて、当該画素回路をより詳細に示した平面図である。図１２は、本実施形態に係るサブ画素ＳＰが備える画素回路をより詳細に説明するための断面図である。図１２の（ａ）は、図１１のＣ－Ｃ線矢視断面図であり、図１２の（ｂ）は、図１１のＤ－Ｄ線矢視断面図である。 FIG. 10 is a circuit diagram showing a configuration example of a sub-pixel SP included in the display device 2 according to the present embodiment. FIG. 11 is a plan view for explaining the pixel circuit included in the sub-pixel SP according to the present embodiment in more detail, and is a plan view showing the pixel circuit in more detail with respect to the region B of FIG. FIG. 12 is a cross-sectional view for explaining the pixel circuit included in the sub-pixel SP according to the present embodiment in more detail. FIG. 12A is a cross-sectional view taken along the line CC of FIG. 11, and FIG. 12B is a cross-sectional view taken along the line DD of FIG.
　なお、図１１においては、図示の簡単のために、ＴＦＴ層８のうち、酸化物半導体層１６、ゲート電極１２、およびＴＦＴ電極層２８のそれぞれと同層の部材のみを抜き出して図示している。また、図１１においては、無機保護絶縁膜１８を、その外形のみを、２点鎖線にて示している。また、図１２は、表示デバイス２の各部材のうち、ベースコート層６とＴＦＴ層８とのみを図示している。 In FIG. 11, for the sake of simplicity of illustration, only the members of the same layer as the oxide semiconductor layer 16, the gate electrode 12, and the TFT electrode layer 28 are extracted and shown in the TFT layer 8. .. Further, in FIG. 11, only the outer shape of the inorganic protective insulating film 18 is shown by a two-dot chain line. Further, FIG. 12 illustrates only the base coat layer 6 and the TFT layer 8 among the members of the display device 2.
　本実施形態において、ＴＦＴ層８には、列方向に伸びる、複数のデータ線ＤＬと、行方向に伸びる、複数の走査信号線ＳＣが設けられ、サブ画素ＳＰはデータ線ＤＬおよび走査信号線ＳＣに接続する。なお、各サブ画素ＳＰには、有機ＥＬ素子を駆動するためのハイレベル電源ＶＤＤが、第１電源電圧線ＶＬ１を介して供給され、ローレベル電源ＶＳＳが、第２電源電圧線ＶＬ２を介して供給され、初期化電圧が、初期化電源線ＩＬを介して供給される。走査信号線ＳＣがアクティブとなる期間に、データ線ＤＬからこれに接続する各サブ画素に、表示階調データに応じた電位信号が供給される。 In the present embodiment, the TFT layer 8 is provided with a plurality of data line DLs extending in the column direction and a plurality of scanning signal lines SC extending in the row direction, and the sub-pixel SP is the data line DL and the scanning signal line SC. Connect to. A high-level power supply VDD for driving the organic EL element is supplied to each sub-pixel SP via the first power supply voltage line VL1, and a low-level power supply VSS is supplied via the second power supply voltage line VL2. It is supplied and the initialization voltage is supplied via the initialization power line IL. During the period in which the scanning signal line SC is active, a potential signal corresponding to the display gradation data is supplied from the data line DL to each sub-pixel connected to the scanning signal line SC.
　サブ画素ＳＰは、図１のＴＦＴ層８に形成される画素回路と、図１の発光素子層１０に形成された発光素子とを備える。画素回路は、駆動トランジスタＴ１と、書き込みトランジスタＴ２と、初期化トランジスタＴ３と、容量Ｃｐとを含む。なお、本実施形態においては、前実施形態において説明した第１トランジスタが、駆動トランジスタＴ１に加えて、書き込みトランジスタＴ２を含む。画素回路が備える各トランジスタは、前実施形態における駆動トランジスタＴ１と、同一の層構造を備えていてもよい。 The sub-pixel SP includes a pixel circuit formed on the TFT layer 8 of FIG. 1 and a light emitting element formed on the light emitting element layer 10 of FIG. The pixel circuit includes a drive transistor T1, a write transistor T2, an initialization transistor T3, and a capacitance Cp. In this embodiment, the first transistor described in the previous embodiment includes the writing transistor T2 in addition to the driving transistor T1. Each transistor included in the pixel circuit may have the same layer structure as the drive transistor T1 in the previous embodiment.
　また、走査信号線ＳＣ、初期化電源線ＩＬ、および第１容量電極Ｃｐ１は、ＴＦＴ層８のゲート電極１２と同層に形成される。さらに、データ信号線ＤＬ、第１電源電圧線ＶＬ１、第２容量電極Ｃｐ２は、ＴＦＴ層８のＴＦＴ電極層２８と同層に形成される。 Further, the scanning signal line SC, the initialization power supply line IL, and the first capacitance electrode Cp1 are formed in the same layer as the gate electrode 12 of the TFT layer 8. Further, the data signal line DL, the first power supply voltage line VL1, and the second capacitance electrode Cp2 are formed in the same layer as the TFT electrode layer 28 of the TFT layer 8.
　駆動トランジスタＴ１の制御端子と接続する、駆動トランジスタＴ１のゲート電極は、書き込みトランジスタＴ２のソース電極と、容量Ｃｐの一方電極である第１容量電極Ｃｐ１とに接続される。特に、図１１および図１２に示すように、第１容量電極Ｃｐ１の一部は、駆動トランジスタＴ１のゲート電極となる。 The gate electrode of the drive transistor T1 connected to the control terminal of the drive transistor T1 is connected to the source electrode of the write transistor T2 and the first capacitance electrode Cp1 which is one electrode of the capacitance Cp. In particular, as shown in FIGS. 11 and 12, a part of the first capacitance electrode Cp1 serves as a gate electrode of the drive transistor T1.
　また、駆動トランジスタＴ１のドレイン電極には、第１電源電圧線ＶＬ１からハイレベル電源ＶＤＤが供給される。さらに、駆動トランジスタＴ１のソース電極は、初期化トランジスタＴ３のソース電極と、容量Ｃｐの他方電極である第２容量電極Ｃｐ２とに接続され、発光素子層１０の第１電極３４と接続する。第２容量電極Ｃｐ２は、図１１および図１２に示すように、層間絶縁膜２０を介して、駆動トランジスタＴ１のゲート電極と対向する。 Further, a high level power supply VDD is supplied from the first power supply voltage line VL1 to the drain electrode of the drive transistor T1. Further, the source electrode of the drive transistor T1 is connected to the source electrode of the initialization transistor T3 and the second capacitance electrode Cp2 which is the other electrode of the capacitance Cp, and is connected to the first electrode 34 of the light emitting element layer 10. As shown in FIGS. 11 and 12, the second capacitance electrode Cp2 faces the gate electrode of the drive transistor T1 via the interlayer insulating film 20.
　本実施形態においては、容量Ｃｐは、図１２に示すように、層間絶縁膜２０と第１容量電極Ｃｐ１との間に、無機保護絶縁膜１８を挟持している。 In the present embodiment, as shown in FIG. 12, the capacitance Cp sandwiches the inorganic protective insulating film 18 between the interlayer insulating film 20 and the first capacitance electrode Cp1.
　書き込みトランジスタＴ２のゲート電極は、走査信号線ＳＣと、初期化トランジスタＴ３のゲート電極と接続する。特に、図１１および図１２に示すように、走査信号線ＳＣの一部は、書き込みトランジスタＴ２および初期化トランジスタＴ３のゲート電極となる。ここで、表示領域ＤＡを延伸する走査信号線ＳＣのような、制御線に含まれるゲート電極とは、ゲート絶縁膜１４を介してチャネル領域２２と重畳する制御線の領域を指す。また、書き込みトランジスタＴ２のドレイン電極は、データ信号線ＤＬと接続する。 The gate electrode of the writing transistor T2 is connected to the scanning signal line SC and the gate electrode of the initialization transistor T3. In particular, as shown in FIGS. 11 and 12, a part of the scanning signal line SC serves as a gate electrode of the writing transistor T2 and the initialization transistor T3. Here, the gate electrode included in the control line, such as the scanning signal line SC extending the display region DA, refers to a region of the control line that overlaps with the channel region 22 via the gate insulating film 14. Further, the drain electrode of the writing transistor T2 is connected to the data signal line DL.
　初期化トランジスタＴ３のドレイン電極は、初期化電源線ＩＬと接続する。 The drain electrode of the initialization transistor T3 is connected to the initialization power line IL.
　発光素子層１０の第２電極４０には、第２電源電圧線ＶＬ２からローレベル電源ＶＳＳが供給される。 A low level power supply VSS is supplied from the second power supply voltage line VL2 to the second electrode 40 of the light emitting element layer 10.
　ここで、図１１と図１２とに示すように、書き込みトランジスタＴ２のソース領域２４と、第１容量電極Ｃｐ１とは、ＴＦＴ層８のＴＦＴ電極層２８と同層の、第１接続配線４８によって接続されている。加えて、初期化トランジスタＴ３のドレイン領域２６と、初期化電源線ＩＬとは、ＴＦＴ層８のＴＦＴ電極層２８と同層の、第２接続配線５０によって接続されている。 Here, as shown in FIGS. 11 and 12, the source region 24 of the write transistor T2 and the first capacitance electrode Cp1 are connected to the first connection wiring 48 of the same layer as the TFT electrode layer 28 of the TFT layer 8. It is connected. In addition, the drain region 26 of the initialization transistor T3 and the initialization power supply line IL are connected by a second connection wiring 50, which is the same layer as the TFT electrode layer 28 of the TFT layer 8.
　また、スイッチングトランジスタである、書き込みトランジスタＴ２と初期化トランジスタＴ３は、動作によって、ソース電極、ドレイン電極が入れ替わる。 Further, in the writing transistor T2 and the initialization transistor T3, which are switching transistors, the source electrode and the drain electrode are exchanged depending on the operation.
　なお、ＴＦＴ電極層２８は、さらに、第１コンタクト部ＣＮ１と、第２コンタクト部ＣＮ２を備えている。第１コンタクト部ＣＮ１は、ＴＦＴ電極層２８と同層の部材と、酸化物半導体層１６と同層の部材とを、電気的に接続する。一方、第２コンタクト部ＣＮ２は、ＴＦＴ電極層２８と同層の部材と、ゲート電極１２と同層の部材とを、電気的に接続する。 The TFT electrode layer 28 further includes a first contact portion CN1 and a second contact portion CN2. The first contact portion CN1 electrically connects a member of the same layer as the TFT electrode layer 28 and a member of the same layer as the oxide semiconductor layer 16. On the other hand, the second contact portion CN2 electrically connects the member of the same layer as the TFT electrode layer 28 and the member of the same layer as the gate electrode 12.
　ここで、図１２に示すように、ゲート電極１２と同層の初期化電源線ＩＬは、ベースコート層６上に直接形成されたゲート絶縁膜１４上に形成されていてもよい。また、図１２に示すように、無機保護絶縁膜１８は、初期化電源線ＩＬの少なくとも端面を覆っていてもよい。初期化電源線ＩＬ上においても、無機保護絶縁膜１８が形成されていることにより、初期化電源線ＩＬと他の配線との間における寄生容量を低減できる。 Here, as shown in FIG. 12, the initialization power supply line IL in the same layer as the gate electrode 12 may be formed on the gate insulating film 14 directly formed on the base coat layer 6. Further, as shown in FIG. 12, the inorganic protective insulating film 18 may cover at least the end face of the initialization power line IL. Since the inorganic protective insulating film 18 is also formed on the initialization power supply line IL, the parasitic capacitance between the initialization power supply line IL and other wiring can be reduced.
　本実施形態に係る表示デバイス２の使用時において、データ信号線ＤＬには、サブ画素ＳＰの発光素子に係る階調値のデータを含むデータ信号が印加される。また、複数の走査信号線ＳＣが順次走査されている。ここで、当該サブ画素ＳＰに対応する走査信号線ＳＣが走査された時点において、データ信号線ＤＬに印加されているデータ信号が、書き込みトランジスタＴ２を介して容量Ｃｐに書き込まれる。これにより、駆動トランジスタＴ１によって、容量Ｃｐに書き込まれたデータ信号が含む階調値のデータに基づいて、サブ画素ＳＰの発光素子が駆動される。なお、初期化トランジスタＴ３を介して初期化電源線ＩＬから初期化電圧が容量Ｃｐに印加されることにより、容量Ｃｐに書き込まれたデータ信号が初期化される。 When the display device 2 according to the present embodiment is used, a data signal including gradation value data related to the light emitting element of the sub-pixel SP is applied to the data signal line DL. Further, a plurality of scanning signal lines SC are sequentially scanned. Here, at the time when the scanning signal line SC corresponding to the sub-pixel SP is scanned, the data signal applied to the data signal line DL is written to the capacitance Cp via the writing transistor T2. As a result, the drive transistor T1 drives the light emitting element of the sub-pixel SP based on the gradation value data included in the data signal written in the capacitance Cp. The data signal written in the capacitance Cp is initialized by applying the initialization voltage from the initialization power supply line IL to the capacitance Cp via the initialization transistor T3.
　本実施形態に係る表示デバイス２は、前実施形態に係る表示デバイス２の製造方法と同一の製造方法によって製造してもよい。 The display device 2 according to the present embodiment may be manufactured by the same manufacturing method as the manufacturing method of the display device 2 according to the previous embodiment.
　図１１および図１２に示すように、本実施形態においても、表示デバイス２は、各トランジスタの、チャネル長方向における、ゲート電極１２の端面を覆う位置に、無機保護絶縁膜１８を備える。このため、上記と同様の理由から、表示デバイス２の製造工程における歩留まりが改善する。特に、本実施形態においては、駆動トランジスタＴ１のみならず、書き込みトランジスタＴ２および初期化トランジスタＴ３を含む、内部補償用のトランジスタにおける、酸化物半導体層１６のチャネル領域２２へのダメージを低減できる。 As shown in FIGS. 11 and 12, the display device 2 also includes the inorganic protective insulating film 18 at a position of each transistor in the channel length direction so as to cover the end face of the gate electrode 12. Therefore, for the same reason as described above, the yield in the manufacturing process of the display device 2 is improved. In particular, in the present embodiment, it is possible to reduce damage to the channel region 22 of the oxide semiconductor layer 16 in the internal compensation transistor including the write transistor T2 and the initialization transistor T3 as well as the drive transistor T1.
　なお、本実施形態において、無機保護絶縁膜１８および層間絶縁膜２０は、シリコン窒化膜であることが好ましい。上記構成により、無機保護絶縁膜１８および層間絶縁膜２０がシリコン酸化膜である場合と比較して、当該２層の誘電率が高いため、容量Ｃｐの電気容量を向上させることができる。したがって、容量Ｃｐの第１容量電極Ｃｐ１および第２容量電極Ｃｐ２の面積を低減することができる。 In the present embodiment, the inorganic protective insulating film 18 and the interlayer insulating film 20 are preferably silicon nitride films. With the above configuration, the dielectric constant of the two layers is higher than that in the case where the inorganic protective insulating film 18 and the interlayer insulating film 20 are silicon oxide films, so that the electric capacity of the capacitance Cp can be improved. Therefore, the areas of the first capacitance electrode Cp1 and the second capacitance electrode Cp2 of the capacitance Cp can be reduced.
　〔変形例１〕
　図１３は、本変形例に係るサブ画素ＳＰが備える画素回路をより詳細に説明するための平面図であり、図１１と対応する平面図である。図１４は、本変形例に係るサブ画素ＳＰが備える画素回路をより詳細に説明するための断面図である。図１４の（ａ）は、図１３のＣ－Ｃ線矢視断面図であり、図１４の（ｂ）は、図１３のＤ－Ｄ線矢視断面図である。なお、図１３においては、無機保護絶縁膜１８の形成位置を明確に図示するために、無機保護絶縁膜１８のみにハッチングを施して図示している。 [Modification 1]
FIG. 13 is a plan view for explaining the pixel circuit included in the sub-pixel SP according to the present modification in more detail, and is a plan view corresponding to FIG. FIG. 14 is a cross-sectional view for explaining the pixel circuit included in the sub-pixel SP according to the present modification in more detail. 14 (a) is a cross-sectional view taken along the line CC of FIG. 13, and FIG. 14 (b) is a cross-sectional view taken along the line DD of FIG. In addition, in FIG. 13, in order to clearly show the formation position of the inorganic protective insulating film 18, only the inorganic protective insulating film 18 is hatched.
　本変形例に係る表示デバイス２は、上述した実施形態に係る表示デバイス２と比較して、無機保護絶縁膜１８の形成位置が異なる点においてのみ相違する。特に、本変形例に係る表示デバイス２において、無機保護絶縁膜１８は、図１３および図１４の（ａ）に示すように、第１容量電極Ｃｐ１を覆う位置に形成されていない。このため、第１容量電極Ｃｐ１は、図１４の（ａ）に示すように、層間絶縁膜２０と接する。 The display device 2 according to this modification is different only in that the formation position of the inorganic protective insulating film 18 is different from that of the display device 2 according to the above-described embodiment. In particular, in the display device 2 according to the present modification, the inorganic protective insulating film 18 is not formed at a position covering the first capacitance electrode Cp1 as shown in FIGS. 13 and 14 (a). Therefore, the first capacitance electrode Cp1 is in contact with the interlayer insulating film 20 as shown in FIG. 14A.
　また、本変形例においても、駆動トランジスタＴ１のゲート電極１２の、チャネル長方向における端面を覆う位置には、無機保護絶縁膜１８が形成されている。しかしながら、本変形例においては、駆動トランジスタＴ１のゲート電極１２の一部と重畳する位置に、無機保護絶縁膜１８が形成されていない。 Further, also in this modification, an inorganic protective insulating film 18 is formed at a position of the gate electrode 12 of the drive transistor T1 that covers the end face in the channel length direction. However, in this modification, the inorganic protective insulating film 18 is not formed at a position where it overlaps with a part of the gate electrode 12 of the drive transistor T1.
　このため、駆動トランジスタＴ１のチャネル領域２２と重畳するゲート電極１２の一部は、層間絶縁膜２０と接する。なお、図１３に示すように、本変形例において、無機保護絶縁膜１８は、駆動トランジスタＴ１のゲート電極１２の、ソース領域２４の側と、ドレイン領域２６の側とに、それぞれ島状に形成されている。 Therefore, a part of the gate electrode 12 that overlaps with the channel region 22 of the drive transistor T1 comes into contact with the interlayer insulating film 20. As shown in FIG. 13, in this modification, the inorganic protective insulating film 18 is formed in an island shape on the source region 24 side and the drain region 26 side of the gate electrode 12 of the drive transistor T1, respectively. Has been done.
　すなわち、本変形例に係る表示デバイス２は、第１トランジスタのうち、チャネル領域２２と重畳するゲート電極１２の一部が層間絶縁膜２０と接する第２トランジスタとして、駆動トランジスタＴ１を備えている。 That is, the display device 2 according to this modification includes a drive transistor T1 as a second transistor in which a part of the gate electrode 12 overlapping the channel region 22 of the first transistor is in contact with the interlayer insulating film 20.
　本変形例に係る表示デバイス２は、上述した各実施形態に係る表示デバイス２の製造方法と同一の製造方法によって製造してもよい。なお、本変形例においては、重畳する位置に、無機保護絶縁膜１８が形成されないゲート絶縁膜１４のパターニングを、ゲート絶縁膜をマスクパターンとしてエッチングしてもよい。 The display device 2 according to the present modification may be manufactured by the same manufacturing method as the manufacturing method of the display device 2 according to each of the above-described embodiments. In this modification, the patterning of the gate insulating film 14 in which the inorganic protective insulating film 18 is not formed may be etched using the gate insulating film as a mask pattern at the overlapping positions.
　本変形例においては、第１容量電極Ｃｐ１と第２容量電極Ｃｐ２との間に、無機保護絶縁膜１８が形成されておらず、第２容量電極Ｃｐ２と重畳する第１容量電極Ｃｐ１が、層間絶縁膜２０と接する。このために、より容量Ｃｐの電気容量を向上させることができ、容量Ｃｐの第１容量電極Ｃｐ１および第２容量電極Ｃｐ２の面積を低減することができる。 In this modification, the inorganic protective insulating film 18 is not formed between the first capacitance electrode Cp1 and the second capacitance electrode Cp2, and the first capacitance electrode Cp1 that overlaps with the second capacitance electrode Cp2 is interposed. It comes into contact with the insulating film 20. Therefore, the electric capacity of the capacitance Cp can be further improved, and the areas of the first capacitance electrode Cp1 and the second capacitance electrode Cp2 of the capacitance Cp can be reduced.
　なお、本変形例においては、駆動トランジスタＴ１のチャネル領域２２と重畳するゲート電極１２の一部と重畳する位置に、無機保護絶縁膜１８が形成されておらず、層間絶縁膜と接する。しかしながら、本変形例においても、駆動トランジスタＴ１のチャネル長方向のゲート電極１２の端面を覆う位置には、無機保護絶縁膜１８が形成されている。このため、駆動トランジスタＴ１における、ゲート電極１２からの静電気放電が、チャネル領域２２の不良を発生させない程度に低減される。 In this modification, the inorganic protective insulating film 18 is not formed at the position where it overlaps with a part of the gate electrode 12 that overlaps with the channel region 22 of the drive transistor T1, and is in contact with the interlayer insulating film. However, also in this modification, the inorganic protective insulating film 18 is formed at a position covering the end surface of the gate electrode 12 in the channel length direction of the drive transistor T1. Therefore, the electrostatic discharge from the gate electrode 12 in the drive transistor T1 is reduced to the extent that a defect in the channel region 22 does not occur.
　〔変形例２〕
　図１５は、本変形例に係るサブ画素ＳＰが備える画素回路をより詳細に説明するための平面図であり、図１１および図１３と対応する平面図である。なお、図１５においても、図１３と同様に、無機保護絶縁膜１８のみにハッチングを施して図示している。 [Modification 2]
FIG. 15 is a plan view for explaining the pixel circuit included in the sub-pixel SP according to the present modification in more detail, and is a plan view corresponding to FIGS. 11 and 13. In FIG. 15, as in FIG. 13, only the inorganic protective insulating film 18 is hatched and shown.
　本変形例に係る表示デバイス２は、前変形例に係る表示デバイス２と比較して、無機保護絶縁膜１８の形成位置が異なる点においてのみ相違する。特に、本変形例に係る表示デバイス２において、無機保護絶縁膜１８は、図１５に示すように、駆動トランジスタＴ１のゲート電極１２の、ソース領域側２４およびドレイン領域側２６に、共通して形成されている。 The display device 2 according to the present modification is different only in that the formation position of the inorganic protective insulating film 18 is different from that of the display device 2 according to the previous modification. In particular, in the display device 2 according to the present modification, the inorganic protective insulating film 18 is commonly formed on the source region side 24 and the drain region side 26 of the gate electrode 12 of the drive transistor T1 as shown in FIG. Has been done.
　〔変形例３〕
　本変形例について、図１５を用いて説明する。本変形例に係る表示デバイス２において、無機保護絶縁膜１８は、図１５に示すように、書き込みトランジスタＴ２と初期化トランジスタＴ３との、それぞれのゲート電極１２の全てを覆う位置に、島状に形成されている。換言すれば、無機保護絶縁膜１８は、走査信号線ＳＣのうち、ゲート絶縁膜１４を介してチャネル領域２２と重畳する領域の全てを覆う位置に、島状に形成されている。このため、チャネル領域２２と重畳しない走査信号線ＳＣの少なくとも一部は、層間絶縁膜２０と接する。 [Modification 3]
This modification will be described with reference to FIG. In the display device 2 according to the present modification, as shown in FIG. 15, the inorganic protective insulating film 18 is formed in an island shape at positions covering all of the gate electrodes 12 of the writing transistor T2 and the initialization transistor T3. It is formed. In other words, the inorganic protective insulating film 18 is formed in an island shape at a position covering the entire region of the scanning signal line SC that overlaps with the channel region 22 via the gate insulating film 14. Therefore, at least a part of the scanning signal line SC that does not overlap with the channel region 22 comes into contact with the interlayer insulating film 20.
　変形例２および３においても、各トランジスタのチャネル長方向のゲート電極１２の端面を覆う位置には、無機保護絶縁膜１８が形成されている。このため、各トランジスタにおける、ゲート電極１２からの静電気放電が低減される。 Also in the modified examples 2 and 3, the inorganic protective insulating film 18 is formed at a position covering the end face of the gate electrode 12 in the channel length direction of each transistor. Therefore, the electrostatic discharge from the gate electrode 12 in each transistor is reduced.
　本実施形態においては、前実施形態、および、変形例１～３の構成を、適宜組み合わせてもよい。 In the present embodiment, the configurations of the previous embodiment and the modifications 1 to 3 may be appropriately combined.
　上述した各実施形態にかかる表示デバイスが備える電気光学素子（電流によって輝度や透過率が制御される電気光学素子）は特に限定されるものではない。各実施形態にかかる表示デバイスは、例えば、電気光学素子としてＯＬＥＤ（Organic Light Emitting Diode：有機発光ダイオード）を備えていてもよい。ゆえに、各実施形態にかかる表示デバイスは、例えば、ＯＬＥＤを備えた有機ＥＬ（Electro Luminescence：エレクトロルミネッセンス）ディスプレイであってもよい。また、各実施形態にかかる表示デバイスは、電気光学素子として無機発光ダイオードを備えた無機ＥＬディスプレイであってもよい。また、各実施形態にかかる表示デバイスは、電気光学素子としてＱＬＥＤ（Quantum dot Light Emitting Diode：量子ドット発光ダイオード）を備えたＱＬＥＤディスプレイであってもよい。 The electro-optical element (electro-optical element whose brightness and transmittance are controlled by an electric current) included in the display device according to each of the above-described embodiments is not particularly limited. The display device according to each embodiment may include, for example, an OLED (Organic Light Emitting Diode) as an electro-optical element. Therefore, the display device according to each embodiment may be, for example, an organic EL (Electro Luminescence) display provided with an OLED. Further, the display device according to each embodiment may be an inorganic EL display provided with an inorganic light emitting diode as an electro-optical element. Further, the display device according to each embodiment may be a QLED display provided with a QLED (Quantum dot Light Emitting Diode) as an electro-optical element.
　本発明は上述した実施形態に限定されるものではなく、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。さらに、各実施形態にそれぞれ開示された技術的手段を組み合わせることにより、新しい技術的特徴を形成することができる。 The present invention is not limited to the above-described embodiments, and embodiments obtained by appropriately combining the technical means disclosed in the different embodiments are also included in the technical scope of the present invention. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.
　２　　　表示デバイス
　４　　　基材
　１２　　ゲート電極
　１４　　ゲート絶縁膜
　１６　　酸化物半導体層
　１８　　無機保護絶縁膜
　２０　　層間絶縁膜
　２２　　チャネル領域
　２４　　ソース領域
　２６　　ドレイン領域
　２８　　ＴＦＴ電極層
　ＤＬ　　データ信号線
　ＳＣ　　走査信号線
　ＶＬ１　第１電源電圧線
　ＶＬ２　第２電源電圧線
　ＩＬ　　初期化電源線
　Ｔ１　　駆動トランジスタ
　Ｔ２　　書き込みトランジスタ
　Ｔ３　　初期化トランジスタ
　Ｃｐ　　容量
　Ｃｐ１　第１容量電極
　Ｃｐ２　第２容量電極 2 Display device 4 Base material 12 Gate electrode 14 Gate insulating film 16 Oxide semiconductor layer 18 Inorganic protective insulating film 20 Interlayer insulating film 22 Channel area 24 Source area 26 Drain area 28 TFT electrode layer DL data signal line SC scanning signal line VL1 1 Power supply voltage line VL2 Second power supply voltage line IL Initialization power supply line T1 Drive transistor T2 Write transistor T3 Initialization transistor Cp Capacity Cp1 First capacitance electrode Cp2 Second capacitance electrode

Claims (16)

  1. 　複数の第１トランジスタを含む表示デバイスであって、
    　前記第１トランジスタのそれぞれは、
    　　Ｃｕを含むゲート電極と、
    　　前記ゲート電極と重畳するゲート絶縁膜と、
    　　前記ゲート絶縁膜を介して対向するチャネル領域と、該チャネル領域を挟むように設けられるとともに、前記ゲート絶縁膜から露出するソース領域およびドレイン領域とを含む酸化物半導体層と、
    　　前記ゲート電極の少なくとも一部を覆う無機保護絶縁膜と、
    　　前記酸化物半導体層および前記無機保護絶縁膜を覆う層間絶縁膜とを含み、
    　前記無機保護絶縁膜は、チャネル長方向の前記ゲート電極の端面を覆い、チャネル長方向において前記ゲート絶縁膜と整合する位置に設けられた表示デバイス。     A display device that includes a plurality of first transistors.
    Each of the first transistors
    A gate electrode containing Cu and
    A gate insulating film that overlaps with the gate electrode and
    An oxide semiconductor layer including a channel region facing each other via the gate insulating film, a source region and a drain region that are provided so as to sandwich the channel region and are exposed from the gate insulating film.
    An inorganic protective insulating film that covers at least a part of the gate electrode and
    The oxide semiconductor layer and the interlayer insulating film covering the inorganic protective insulating film are included.
    The inorganic protective insulating film is a display device provided at a position that covers the end surface of the gate electrode in the channel length direction and is aligned with the gate insulating film in the channel length direction.
  2. 　前記層間絶縁膜が、シリコン窒化膜である請求項１に記載の表示デバイス。 The display device according to claim 1, wherein the interlayer insulating film is a silicon nitride film.
  3. 　前記ゲート絶縁膜が、シリコン酸化膜である請求項１または２に記載の表示デバイス。 The display device according to claim 1 or 2, wherein the gate insulating film is a silicon oxide film.
  4. 　前記無機保護絶縁膜が、シリコン窒化膜である請求項１から３の何れか１項に記載の表示デバイス。 The display device according to any one of claims 1 to 3, wherein the inorganic protective insulating film is a silicon nitride film.
  5. 　前記無機保護絶縁膜が、シリコン酸化膜である請求項１から３の何れか１項に記載の表示デバイス。 The display device according to any one of claims 1 to 3, wherein the inorganic protective insulating film is a silicon oxide film.
  6. 　前記無機保護絶縁膜が、前記ゲート電極の全てを覆う位置に、島状に設けられた請求項１から５の何れか１項に記載の表示デバイス。 The display device according to any one of claims 1 to 5, which is provided in an island shape at a position where the inorganic protective insulating film covers all of the gate electrodes.
  7. 　複数の第１トランジスタは、さらに第２トランジスタを含み、
    　前記第２トランジスタにおいて、前記チャネル領域と重畳する前記ゲート電極の一部が、前記層間絶縁膜と接する請求項１から６の何れか１項に記載の表示デバイス。     The plurality of first transistors further include a second transistor.
    The display device according to any one of claims 1 to 6, wherein in the second transistor, a part of the gate electrode superimposing on the channel region is in contact with the interlayer insulating film.
  8. 　前記第２トランジスタにおいて、前記無機保護絶縁膜が、前記ソース領域の側と前記ドレイン領域の側とに、それぞれ島状に設けられた請求項７に記載の表示デバイス。 The display device according to claim 7, wherein in the second transistor, the inorganic protective insulating film is provided in an island shape on the side of the source region and the side of the drain region, respectively.
  9. 　前記第２トランジスタにおいて、前記無機保護絶縁膜が、前記ソース領域の側と前記ドレイン領域の側とに、共通して島状に設けられた請求項７に記載の表示デバイス。 The display device according to claim 7, wherein in the second transistor, the inorganic protective insulating film is provided in a common island shape on the side of the source region and the side of the drain region.
  10. 　データ信号線と、走査信号線と、第１電源電圧線と、初期化電源線とを含む画素回路をさらに備え、
    　前記画素回路は、駆動トランジスタと、該駆動トランジスタの制御端子に接続された書き込みトランジスタと、容量とを含み、
    　前記第１トランジスタが、前記駆動トランジスタと前記書き込みトランジスタとを含む請求項１から９の何れか１項に記載の表示デバイス。     A pixel circuit including a data signal line, a scanning signal line, a first power supply voltage line, and an initialization power supply line is further provided.
    The pixel circuit includes a drive transistor, a write transistor connected to a control terminal of the drive transistor, and a capacitance.
    The display device according to any one of claims 1 to 9, wherein the first transistor includes the drive transistor and the write transistor.
  11. 　前記走査信号線の一部が、前記書き込みトランジスタの前記ゲート電極である請求項１０に記載の表示デバイス。 The display device according to claim 10, wherein a part of the scanning signal line is the gate electrode of the writing transistor.
  12. 　前記無機保護絶縁膜が、前記書き込みトランジスタの前記ゲート電極の全てを覆う位置に、島状に設けられ、前記走査信号線の一部が、前記層間絶縁膜と接する請求項１１に記載の表示デバイス。 The display device according to claim 11, wherein the inorganic protective insulating film is provided in an island shape at a position covering all of the gate electrodes of the writing transistor, and a part of the scanning signal line is in contact with the interlayer insulating film. ..
  13. 　前記容量の一方の電極が、当該電極の一部が前記駆動トランジスタの前記ゲート電極となる第１容量電極であり、前記容量の他方の電極が、前記層間絶縁膜を介し、前記駆動トランジスタの前記ゲート電極と対向する第２容量電極である請求項１０から１２の何れか１項に記載の表示デバイス。 One electrode of the capacitance is a first capacitance electrode in which a part of the electrode serves as the gate electrode of the drive transistor, and the other electrode of the capacitance is the interlayer insulating film of the drive transistor. The display device according to any one of claims 10 to 12, which is a second capacitance electrode facing the gate electrode.
  14. 　前記容量が、前記層間絶縁膜と前記第１容量電極との間に、前記無機保護絶縁膜を挟持する請求項１３に記載の表示デバイス。 The display device according to claim 13, wherein the capacitance sandwiches the inorganic protective insulating film between the interlayer insulating film and the first capacitance electrode.
  15. 　前記第２容量電極と重畳する前記第１容量電極が、前記層間絶縁膜と接する請求項１３に記載の表示デバイス。 The display device according to claim 13, wherein the first capacitance electrode superimposed on the second capacitance electrode is in contact with the interlayer insulating film.
  16. 　複数のトランジスタを形成するトランジスタ形成工程を含む表示デバイスの製造方法であって、
    　前記トランジスタ形成工程は、
    　　基材上に酸化物半導体層をパターニングして形成する工程と、
    　　ゲート絶縁膜を成膜する工程と、
    　　前記ゲート絶縁膜の上層に、Ｃｕを含むゲート電極をパターニングして形成する工程と、
    　　無機保護絶縁膜を成膜する工程と、
    　　前記酸化物半導体層の一部が露出するように、前記ゲート絶縁膜と前記無機保護絶縁膜とが整合するパターンをパターニングする工程と、
    　　露出した前記酸化物半導体層にプラズマを照射する工程と、
    　　層間絶縁膜を成膜する工程と、
    　を含む表示デバイスの製造方法。     A method for manufacturing a display device including a transistor forming step of forming a plurality of transistors.
    The transistor forming step is
    The process of patterning and forming an oxide semiconductor layer on a substrate,
    The process of forming a gate insulating film and
    A step of patterning and forming a gate electrode containing Cu on the upper layer of the gate insulating film,
    The process of forming an inorganic protective insulating film and
    A step of patterning a pattern in which the gate insulating film and the inorganic protective insulating film match so that a part of the oxide semiconductor layer is exposed.
    The step of irradiating the exposed oxide semiconductor layer with plasma and
    The process of forming an interlayer insulating film and
    How to manufacture a display device, including.
PCT/JP2019/014101 2019-03-29 2019-03-29 Display device and method for manufacturing display device WO2020202286A1 (en)

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