WO2020199492A1 - Ecc memory supporting partial write, and partial data write method - Google Patents
Ecc memory supporting partial write, and partial data write method Download PDFInfo
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- WO2020199492A1 WO2020199492A1 PCT/CN2019/103951 CN2019103951W WO2020199492A1 WO 2020199492 A1 WO2020199492 A1 WO 2020199492A1 CN 2019103951 W CN2019103951 W CN 2019103951W WO 2020199492 A1 WO2020199492 A1 WO 2020199492A1
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
- G06F11/1056—Updating check bits on partial write, i.e. read/modify/write
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- the instruction processing module reads the enable signal of the data bit in the new instruction. If the enable signal is all valid, it means that the instruction is not a partial write instruction, then execute step c. If the enable signal is partially valid, it means the instruction is Part of the write instruction, execute step f (as shown in Figure 3);
Abstract
An ECC memory supporting partial write. The ECC memory comprises an instruction processing module, an instruction caching module, a storage module, a control signal module, an encoding module and a decoding module, wherein the instruction processing module receives and analyzes a new instruction, and is also internally provided with an instruction flag bit (RMW_flag) so as to flag whether the new instruction can be received; and the instruction caching module also caches an instruction to be executed. The ECC memory introduces a read flag bit (RMW_flag) so as to acquire, for a partial write instruction, a clock period for extra operation of a memory, thereby solving the problem of address conflict caused by partial write.
Description
本发明涉及存储技术，尤其涉及一种支持部分写的ECC内存及数据部分写入的方法。The present invention relates to storage technology, in particular to an ECC memory supporting partial writing and a method for partial writing of data.
由于易失性内存很广泛地应用于主控芯片中，为了确保主控芯片是长期可靠且运作稳定，适当地纠错机制是必需的。Since volatile memory is widely used in the main control chip, in order to ensure that the main control chip is reliable and stable for a long time, a proper error correction mechanism is necessary.
由于不同资料属性，内存的写入有可能是部分写(partial write)，又考虑系统运作的稳定性加上了纠错机制，部分写的操作必须分为3个步骤“读——修改——写”，部分写的操作相比常规的写和读操作来说，多出一次对存储器的访问，而这个多出来的一次访问会给之后的读或写操作造成地址冲突，从而给使用者造成困扰。Due to different data attributes, the writing of the memory may be a partial write, and considering the stability of the system operation plus an error correction mechanism, the partial writing operation must be divided into 3 steps "read-modify- "Write", compared to the conventional write and read operations, the partial write operation has one more access to the memory, and this additional access will cause address conflicts for subsequent read or write operations, which will cause the user Troubled.
发明内容Summary of the invention
本发明的目的在于克服现有技术的缺陷，提供一种支持部分写的ECC内存，引入了读标志位RMW_flag来为部分写指令获取额外操作存储器的时钟周期，解决由部分写带来的地址冲突问题。The purpose of the present invention is to overcome the shortcomings of the prior art and provide an ECC memory that supports partial writes. The read flag bit RMW_flag is introduced to obtain additional memory clock cycles for partial write instructions and resolve address conflicts caused by partial writes. problem.
为实现上述目的，本发明提出如下技术方案：一种支持部分写的ECC内存，包括：In order to achieve the above objective, the present invention proposes the following technical solution: an ECC memory supporting partial writing, including:
一指令处理模块，与外部电路进行通信，接收外部电路发送过来的新指令，并分析判断新指令是否为部分写指令，所述指令处理模块内设有指令标志位RMW_flag，所述指令标志位具有0和1两种状态，0表示可以接收新的指令，1表示不可以接受新的指令：An instruction processing module communicates with an external circuit, receives a new instruction sent by an external circuit, and analyzes and determines whether the new instruction is a partial write instruction. The instruction processing module is provided with an instruction flag RMW_flag, and the instruction flag has There are two states of 0 and 1. 0 means that new instructions can be received, and 1 means that new instructions cannot be accepted:
一指令缓存模块，与指令处理模块连接，在指令标志位为1时缓存待执行的指令；An instruction cache module, connected to the instruction processing module, and caches the instructions to be executed when the instruction flag bit is 1;
一存储模块；A storage module;
一控制信号模块，分别与指令处理模块及存储模块连接，根据指令处理模块发送的控制信号，控制存储模块进行存储或读取操作，同时反馈完成信号给指令处理模块；A control signal module, which is respectively connected to the instruction processing module and the storage module, controls the storage module to perform storage or read operations according to the control signal sent by the instruction processing module, and feeds back the completion signal to the instruction processing module at the same time;
一编码模块，分别与指令处理模块及存储模块连接，对指令处理模块输入的逻辑字编码，生成对应的奇偶校验位与逻辑字组成物理字送入存储模块；An encoding module, respectively connected with the instruction processing module and the storage module, encodes the logical word input by the instruction processing module, generates the corresponding parity bit and the logical word to form a physical word and sends it to the storage module;
一译码模块，分别与指令处理模块及存储模块连接，从存储模块中读取物理字进行解码纠错生成纠错码，将解码后的逻辑字和纠错码传送给指令处理模块。A decoding module is respectively connected with the instruction processing module and the storage module, reads the physical word from the storage module, decodes and corrects the error to generate an error correction code, and transmits the decoded logical word and error correction code to the instruction processing module.
优选的，所述部分写指令包括读、修改和写三个操作。Preferably, the partial write instruction includes three operations of read, modify and write.
优选的所述纠错码为扩展汉明码。Preferably, the error correction code is an extended Hamming code.
一种ECC内存中数据部分写入的方法，包括如下步骤：A method for partially writing data in ECC memory includes the following steps:
a、指令处理模块收到外部新指令，读取指令标志位RMW_flag的值，若为1就将新指令送入指令缓存模块内，等待下一次接收，若为0则接收新指令，并执行步骤b；a. The instruction processing module receives a new external instruction, reads the value of the instruction flag RMW_flag, if it is 1, sends the new instruction into the instruction cache module, and waits for the next reception, if it is 0, receives the new instruction and executes the steps b;
b、指令处理模块读取新指令中数据位的使能信号，若该使能信号全部有效，表示该指令不是部分写指令，则执行步骤c，若该使能信号部分有效，表示该指令为部分写指令，执行步骤f；b. The instruction processing module reads the enable signal of the data bit in the new instruction. If the enable signal is all valid, it means that the instruction is not a partial write instruction, then execute step c. If the enable signal is partially valid, it means the instruction is Part of the write instruction, execute step f;
c指令处理模块将指令中的控制信号发送给控制信号模块送入存储模块，而将指令中的逻辑字送至编码模块进行编码；c The instruction processing module sends the control signal in the instruction to the control signal module to the storage module, and sends the logic word in the instruction to the encoding module for encoding;
d、编码模块将逻辑字进行编码，并送入存储模块进行存储；d. The encoding module encodes the logical words and sends them to the storage module for storage;
e、控制信号模块反馈操作完成信号给指令处理模块，完成新指令写入，返回步骤a；e. The control signal module feeds back the operation completion signal to the instruction processing module, completes the writing of new instructions, and returns to step a;
f、指令处理模块发送读命令，根据译码模块提供的数据字为基础，根据部分写命令修改数据字内容，再发送写命令，执行步骤g，同时将指令标志位设置为1，f. The instruction processing module sends a read command, based on the data word provided by the decoding module, modifies the content of the data word according to part of the write command, and then sends the write command, execute step g, and set the instruction flag to 1.
g、指令处理模块将修改后的数据字送入编码器进行编码，并送入存储模块进行存储，同时指令处理模块将部分写指令中的控制信号发送给控制信号模块送入存储模块；g. The instruction processing module sends the modified data word to the encoder for encoding, and sends it to the storage module for storage. At the same time, the instruction processing module sends part of the control signal in the write instruction to the control signal module to the storage module;
h、控制信号模块反馈操作完成信号给指令处理模块，完成部分写指令的写入，将指令标志位设置为0，返回步骤a。h. The control signal module feeds back the operation completion signal to the instruction processing module to complete the writing of part of the write instruction, set the instruction flag bit to 0, and return to step a.
作为优选，所述步骤c中控制信号包括读信号或写信号及地址信号。Preferably, the control signal in the step c includes a read signal or a write signal and an address signal.
作为优选，所述步骤d中编码模块对逻辑字进行编码，输出逻辑字以及与之对应的奇偶校验位。Preferably, in the step d, the encoding module encodes the logical word, and outputs the logical word and the corresponding parity bit.
作为优选，所述步骤f中译码模块读取存储模块的物理字，根据编码表对逻辑字进行ECC操作，生成纠错码连同逻辑字形成数据字送入指令处理模块。Preferably, in the step f, the decoding module reads the physical word of the storage module, performs an ECC operation on the logical word according to the coding table, generates an error correction code together with the logical word to form a data word and sends it to the instruction processing module.
与现有技术相比，本发明所揭示的一种支持部分写的ECC内存，在处理模块中引入读标志位RMW_flag，为部分写指令获取额外操作存储器的时钟周期，解决由部分写带来的地址冲突问题，实现内存的部分写入操作。Compared with the prior art, the ECC memory that supports partial writes disclosed in the present invention introduces the read flag RMW_flag in the processing module to obtain additional operating memory clock cycles for partial write instructions, and solves the problems caused by partial writes. Address conflict problem, realize partial write operation of memory.
图1是本发明的内存模块图；Figure 1 is a diagram of the memory module of the present invention;
图2是本发明涉及的组织物理字的框图；；Figure 2 is a block diagram of the organization of physical words involved in the present invention;
图3是本发明中指令处理模块的判断分析流程。Figure 3 is the judgment and analysis flow of the instruction processing module of the present invention.
下面将结合本发明的附图，对本发明实施例的技术方案进行清楚、完整的描述。The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention.
如图1所示，本发明所揭示的一种支持部分写的ECC内存，包括指令处理模块，指令缓存模块，存储模块，控制信号模块，编码模块及译码模块，其中：As shown in Figure 1, an ECC memory supporting partial writing disclosed in the present invention includes an instruction processing module, an instruction cache module, a storage module, a control signal module, an encoding module, and a decoding module, wherein:
指令处理模块，与外部电路进行通信，接收外部电路发送过来的新指令(包括常规读写指令和部分写指令)，该指令处理模块中设置了指令标志位RMW_flag来判断是否可以接收新指令，该指令标志位具有0和1两个状态，0表示可以接受新指令，而1表示内部将要执行部分写指令，无法接收新指令，此外指令处理模块还可以对接收的指令进行分析，通过读取数据的位使能信号的有效程度来判断指令类别。The instruction processing module communicates with external circuits and receives new instructions (including regular read and write instructions and partial write instructions) sent by the external circuit. The instruction flag bit RMW_flag is set in the instruction processing module to determine whether new instructions can be received. The instruction flag bit has two states: 0 and 1. 0 means that new commands can be accepted, and 1 means that some write commands will be executed internally, and new commands cannot be received. In addition, the command processing module can also analyze the received commands and read data The effective degree of the bit enable signal is used to determine the instruction type.
所述指令缓存模块与指令处理模块连接，在指令标志位为1时，指令处理模块无法执行读指令，而在这个时钟周期内外部输入的指令无法被立即处理，则送入指令缓存模块中缓存，缓存的指令信息包括读/写，地址，数 据，选通信号，而当指令处理模块可以接收新指令时，优先处理缓存模块中的指令，而对于新送入指令的则依次存放至指令缓存模块内。The instruction cache module is connected to the instruction processing module. When the instruction flag bit is 1, the instruction processing module cannot execute the read instruction, and the externally input instruction cannot be processed immediately in this clock cycle, so it is sent to the instruction cache module for cache , Cached instruction information includes read/write, address, data, strobe signal, and when the instruction processing module can receive a new instruction, the instruction in the cache module is processed first, and the newly sent instruction is sequentially stored in the instruction cache Inside the module.
此外，由于部分写操作对存储模块更新的始终延迟比一般的读写操作多若干个(设为M个)，倘若在一个部分写命令后的M个时钟周期内对同一地址进行读操作，存储模块输出的是就数据，而不是更新后的新数据，则指令缓存模块发送警告信号给指令处理模块进行处理。In addition, because the partial write operation always delays the memory module update by several times more than the general read and write operation (set to M), if the same address is read in M clock cycles after a partial write command, the storage What the module outputs is just data, not the updated new data, then the instruction cache module sends a warning signal to the instruction processing module for processing.
所述存储模块用于存储电路中的相关指令信息。The storage module is used to store relevant instruction information in the circuit.
所述控制信号模块分别与指令处理模块及存储模块连接，根据指令处理模块发送的控制信号(包括读/写，地址)，控制存储模块进行存储或读取操作，同时反馈完成信号(包括读完成和地址)给指令处理模块。The control signal module is respectively connected with the instruction processing module and the storage module, and according to the control signal (including read/write, address) sent by the instruction processing module, the storage module is controlled to perform storage or read operations, and the completion signal (including read completion) And address) to the instruction processing module.
所述编码模块分别与指令处理模块及存储模块连接，对指令处理模块输入的逻辑字进行编码，生成对应的奇偶校验位与逻辑字组成物理字送入存储模块；The encoding module is respectively connected with the instruction processing module and the storage module, encodes the logical words input by the instruction processing module, generates corresponding parity bits and logical words to form physical words and sends them to the storage module;
所述译码模块分别与指令处理模块及存储模块连接，根据扩展汉明码译码原理，从存储模块中读取物理字进行译码，输出经过纠错的数据字及其检错结果(有0/1/2比特出错)，所数据字由逻辑字和纠错码组成，而纠错码是扩展汉明码。The decoding module is respectively connected with the instruction processing module and the storage module. According to the principle of extended Hamming code decoding, the physical words are read from the storage module for decoding, and the data words after error correction and the error detection results (with 0 /1/2 bit error), the data word is composed of logic words and error correction codes, and the error correction codes are extended Hamming codes.
所述部分写指令包括读、修改和写三个操作，其中读是通过译码模块读取存储模块中原先的数据字，修改是指令处理模块根据原先的数据字再结合部分写指令进行数据字修改，写是通过编码模块将修改后的数据字重新编码送入存储模块。The partial write instruction includes three operations: read, modify, and write. Reading is to read the original data word in the storage module through the decoding module, and modification is to perform the data word by the instruction processing module according to the original data word combined with the partial write instruction. Modification and writing is to recode the modified data words into the storage module through the coding module.
如图2所示，存储模块中物理字总共13位，包括8位数据位(d0～d7)，4位纠错码(h0～h3)及1位奇偶校验位(p)。As shown in Figure 2, the physical word in the storage module has a total of 13 bits, including 8 data bits (d0 ~ d7), 4 error correction codes (h0 ~ h3) and 1 parity bit (p).
本发明揭示一种ECC内存中数据部分写入的方法，包括如下步骤：The present invention discloses a method for partially writing data in ECC memory, which includes the following steps:
a、指令处理模块收到外部新指令，读取指令标志位RMW_flag的值，若为1就将新指令送入指令缓存模块内，等待下一次接收，若为0则接收新指令，并执行步骤b(如图3所示)；a. The instruction processing module receives a new external instruction, reads the value of the instruction flag RMW_flag, if it is 1, sends the new instruction into the instruction cache module, and waits for the next reception, if it is 0, receives the new instruction and executes the steps b (as shown in Figure 3);
b、指令处理模块读取新指令中数据位的使能信号，若该使能信号全部有效，表示该指令不是部分写指令，则执行步骤c，若该使能信号部分有效，表示该指令为部分写指令，执行步骤f(如图3所示)；b. The instruction processing module reads the enable signal of the data bit in the new instruction. If the enable signal is all valid, it means that the instruction is not a partial write instruction, then execute step c. If the enable signal is partially valid, it means the instruction is Part of the write instruction, execute step f (as shown in Figure 3);
c指令处理模块将指令中的控制信号发送给控制信号模块送入存储模块，而将指令中的逻辑字送至编码模块进行编码；c The instruction processing module sends the control signal in the instruction to the control signal module to the storage module, and sends the logic word in the instruction to the encoding module for encoding;
d、编码模块将逻辑字进行编码，并送入存储模块进行存储；d. The encoding module encodes the logical words and sends them to the storage module for storage;
e、控制信号模块反馈操作完成信号给指令处理模块，完成新指令写入，返回步骤a；e. The control signal module feeds back the operation completion signal to the instruction processing module, completes the writing of new instructions, and returns to step a;
f、指令处理模块发送读命令，根据译码模块提供的数据字为基础，根据部分写命令修改数据字内容，再发送写命令，执行步骤g，同时将指令标志位设置为1，f. The instruction processing module sends a read command, based on the data word provided by the decoding module, modifies the content of the data word according to part of the write command, and then sends the write command, execute step g, and set the instruction flag to 1.
g、指令处理模块将修改后的数据字送入编码器进行编码，并送入存储模块进行存储，同时指令处理模块将部分写指令中的控制信号发送给控制信号模块送入存储模块；g. The instruction processing module sends the modified data word to the encoder for encoding, and sends it to the storage module for storage. At the same time, the instruction processing module sends part of the control signal in the write instruction to the control signal module to the storage module;
h、控制信号模块反馈操作完成信号给指令处理模块，完成部分写指令的写入，将指令标志位设置为0，返回步骤a。h. The control signal module feeds back the operation completion signal to the instruction processing module to complete the writing of part of the write instruction, set the instruction flag bit to 0, and return to step a.
所述步骤c中控制信号包括读信号或写信号及地址信号；所述步骤d中编码模块对逻辑字进行编码，输出逻辑字以及与之对应的奇偶校验位；所述步骤f中译码模块读取存储模块的物理字，根据编码表对逻辑字进行ECC操作，生成纠错码连同逻辑字形成数据字送入指令处理模块。In the step c, the control signal includes a read signal or a write signal and an address signal; in the step d, the encoding module encodes the logical word, and outputs the logical word and the corresponding parity bit; in the step f, the decoding The module reads the physical words of the storage module, performs ECC operations on the logical words according to the coding table, generates an error correction code together with the logical words to form a data word and sends it to the instruction processing module.
在部分写操作下，第一个读操作也有相应的译码操作，类似地，ECC输出译码模块输出数据及检错或纠错的记录；不同地，在部分写的情况下，第三笔写操作会将译码过程的纠错结果代入，这时位选信号全部有效，即自动纠正存储模块内的单比特错误。In the partial write operation, the first read operation also has the corresponding decoding operation. Similarly, the ECC output decoding module outputs data and the record of error detection or correction; differently, in the case of partial writing, the third The write operation will substitute the error correction result of the decoding process. At this time, the bit selection signals are all valid, that is, the single-bit error in the memory module is automatically corrected.
本发明改进了ECC存储器的存储方式，增加了对部分写的支持，并解决了由部分写带来的地址冲突问题，使其在部分写的情况下不影响纠错码的纠错功能，以及后续读写操作。The present invention improves the storage mode of the ECC memory, increases the support for partial writing, and solves the address conflict problem caused by partial writing, so that it does not affect the error correction function of the error correction code in the case of partial writing, and Subsequent read and write operations.
本发明的技术内容及技术特征已揭示如上，然而熟悉本领域的技术人员仍可能基于本发明的教示及揭示而作种种不背离本发明精神的替换及修饰，因此，本发明保护范围应不限于实施例所揭示的内容，而应包括各种不背离本发明的替换及修饰，并为本专利申请权利要求所涵盖。The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the scope of protection of the present invention should not be limited The content disclosed in the embodiments should include various substitutions and modifications that do not deviate from the present invention, and are covered by the claims of this patent application.
Claims (7)
- 一种支持部分写的ECC内存，其特征在于包括：An ECC memory that supports partial writing, which is characterized by including:一指令处理模块，与外部电路进行通信，接收外部电路发送过来的新指令，并分析判断新指令是否为部分写指令，所述指令处理模块内设有指令标志位RMW_flag，所述指令标志位具有0和1两种状态，0表示可以接收新的指令，1表示不可以接受新的指令：An instruction processing module communicates with an external circuit, receives a new instruction sent by an external circuit, and analyzes and determines whether the new instruction is a partial write instruction. The instruction processing module is provided with an instruction flag RMW_flag, and the instruction flag has There are two states of 0 and 1. 0 means that new instructions can be received, and 1 means that new instructions cannot be accepted:一指令缓存模块，与指令处理模块连接，在指令标志位RMW_flag为1时缓存待执行的指令；An instruction cache module, connected to the instruction processing module, caches the instructions to be executed when the instruction flag RMW_flag is 1;一存储模块；A storage module;一控制信号模块，分别与指令处理模块及存储模块连接，根据指令处理模块发送的控制信号，控制存储模块进行存储或读取操作，同时反馈完成信号给指令处理模块；A control signal module, which is respectively connected to the instruction processing module and the storage module, controls the storage module to perform storage or read operations according to the control signal sent by the instruction processing module, and feeds back the completion signal to the instruction processing module at the same time;一编码模块，分别与指令处理模块及存储模块连接，对指令处理模块输入的逻辑字编码，生成对应的奇偶校验位与逻辑字组成物理字送入存储模块；An encoding module, respectively connected with the instruction processing module and the storage module, encodes the logical word input by the instruction processing module, generates the corresponding parity bit and the logical word to form a physical word and sends it to the storage module;一译码模块，分别与指令处理模块及存储模块连接，从存储模块中读取物理字进行解码纠错生成纠错码，将解码后的逻辑字和纠错码传送给指令处理模块。A decoding module is respectively connected with the instruction processing module and the storage module, reads the physical word from the storage module, decodes and corrects the error to generate an error correction code, and transmits the decoded logical word and error correction code to the instruction processing module.
- 根据权利要求1所述的支持部分写的ECC内存，其特征在于：所述部分写指令包括读、修改和写三个操作。The ECC memory supporting partial writing according to claim 1, wherein the partial writing instruction includes three operations of reading, modifying and writing.
- 根据权利要求1所述的支持部分写的ECC内存，其特征在于：所述纠错码为扩展汉明码。The ECC memory supporting partial writing according to claim 1, wherein the error correction code is an extended Hamming code.
- 一种ECC内存中数据部分写入的方法，基于权利要求1所述ECC内存实现，其特征在于包括如下内容：A method for partially writing data in ECC memory, implemented based on the ECC memory of claim 1, and characterized by including the following content:a、指令处理模块收到外部新指令，读取指令标志位RMW_flag的值，若为1就将新指令送入指令缓存模块内，等待下一次接收，若为0则接收新指令，并执行步骤b；a. The instruction processing module receives a new external instruction, reads the value of the instruction flag RMW_flag, if it is 1, sends the new instruction into the instruction cache module, and waits for the next reception, if it is 0, receives the new instruction and executes the steps b;b、指令处理模块读取新指令中数据位的使能信号，若该使能信号全部有效，表示该指令不是部分写指令，则执行步骤c，若该使能信号部分有效，表示该指令为部分写指令，执行步骤f；b. The instruction processing module reads the enable signal of the data bit in the new instruction. If the enable signal is all valid, it means that the instruction is not a partial write instruction, then execute step c. If the enable signal is partially valid, it means the instruction is Part of the write instruction, execute step f;c、指令处理模块将指令中的控制信号发送给控制信号模块送入存储模块，而将指令中的逻辑字送至编码模块进行编码；c. The instruction processing module sends the control signal in the instruction to the control signal module to the storage module, and sends the logic word in the instruction to the encoding module for encoding;d、编码模块将逻辑字进行编码，并送入存储模块进行存储；d. The encoding module encodes the logical words and sends them to the storage module for storage;e、控制信号模块反馈操作完成信号给指令处理模块，完成新指令写入，返回步骤a；e. The control signal module feeds back the operation completion signal to the instruction processing module, completes the writing of new instructions, and returns to step a;f、指令处理模块发送读命令，根据译码模块提供的数据字为基础，根据部分写命令修改数据字内容，再发送写命令，执行步骤g，同时将指令标志位设置为1，f. The instruction processing module sends a read command, based on the data word provided by the decoding module, modifies the content of the data word according to part of the write command, and then sends the write command, execute step g, and set the instruction flag to 1.g、指令处理模块将修改后的数据字送入编码器进行编码，并送入存储模块进行存储，同时指令处理模块将部分写指令中的控制信号发送给控制信号模块送入存储模块；g. The instruction processing module sends the modified data word to the encoder for encoding, and sends it to the storage module for storage. At the same time, the instruction processing module sends part of the control signal in the write instruction to the control signal module to the storage module;h、控制信号模块反馈操作完成信号给指令处理模块，完成部分写指令的写入，将指令标志位设置为0，返回步骤a。h. The control signal module feeds back the operation completion signal to the instruction processing module to complete the writing of part of the write instruction, set the instruction flag bit to 0, and return to step a.
- 根据权利要求4所述的ECC内存中数据部分写入的方法，其特征在于：所述步骤c中控制信号包括读信号或写信号及地址信号。The method for writing part of data in an ECC memory according to claim 4, wherein the control signal in the step c includes a read signal or a write signal and an address signal.
- 根据权利要求4所述的ECC内存中数据部分写入的方法，其特征在于：所述步骤d中编码模块对逻辑字进行编码，输出逻辑字以及与之对应的奇偶校验位。The method for writing part of the data in the ECC memory according to claim 4, wherein the encoding module in the step d encodes the logical word, and outputs the logical word and the corresponding parity bit.
- 根据权利要求4所述的ECC内存中数据部分写入的方法，其特征在于：所述步骤f中译码模块读取存储模块的物理字，根据编码表对逻辑字进行ECC操作，生成纠错码连同逻辑字形成数据字送入指令处理模块。The method for writing part of the data in the ECC memory according to claim 4, wherein the decoding module reads the physical words of the storage module in the step f, and performs ECC operations on the logical words according to the coding table to generate error correction The code together with the logic word forms a data word and is sent to the instruction processing module.
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| CN109960605A (en) * | 2019-04-01 | 2019-07-02 | 江苏华存电子科技有限公司 | A kind of ECC memory that support section is write and the method that data portion is written |
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| CN1963950A (en) * | 2005-11-11 | 2007-05-16 | 恩益禧电子股份有限公司 | Semiconductor storage device equipped with ecc function |
| US20150039968A1 (en) * | 2013-07-31 | 2015-02-05 | Arm Limited | Error code management in systems permitting partial writes |
| CN108595371A (en) * | 2016-01-20 | 2018-09-28 | 北京中科寒武纪科技有限公司 | For the digital independent of vector operation, write-in and read-write scheduler and reservation station |
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