WO2020199316A1 - 显示面板及显示模组 - Google Patents

显示面板及显示模组 Download PDF

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Publication number
WO2020199316A1
WO2020199316A1 PCT/CN2019/087132 CN2019087132W WO2020199316A1 WO 2020199316 A1 WO2020199316 A1 WO 2020199316A1 CN 2019087132 W CN2019087132 W CN 2019087132W WO 2020199316 A1 WO2020199316 A1 WO 2020199316A1
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WO
WIPO (PCT)
Prior art keywords
layer
touch
data signal
signal line
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/087132
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English (en)
French (fr)
Inventor
卢改平
崔珠峰
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Publication of WO2020199316A1 publication Critical patent/WO2020199316A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • This application relates to the display field, and in particular to a display panel and a display module.
  • LTPS Low temperature poly-silicon
  • TFT Thin Film Transistor
  • the display panel in the prior art often arranges the touch leads and the source and drain layers in the same layer. Due to the shortage of wiring space, the touch leads and the data lines are shorted, which affects the data transmission performance of the display panel.
  • the display panel displays abnormalities, which reduces the yield rate of the panel.
  • the present application provides a display panel and a display module to solve the technical problem of abnormal data transmission of the existing display panel.
  • the present application provides a display panel, which includes a substrate, a thin film transistor layer on the substrate, and a touch layer on the thin film transistor layer;
  • the thin film transistor layer includes a source/drain layer, and the source/drain layer includes a source/drain and a data signal line;
  • the display panel further includes a touch trace electrically connected to the touch layer, and the touch trace is located between the substrate and the touch layer;
  • some of the data signal lines and some of the touch wires are arranged in different layers.
  • the data signal line includes a first part and a second part
  • the first part of the data signal line and the second part of the data signal line are arranged in a different layer;
  • the first part of the data signal line and the second part of the data signal line are electrically connected through a first via;
  • the touch control trace and the second part of the data signal line are arranged in the same layer.
  • the second part of the data signal line is arranged in the same layer as the source electrode or the drain electrode;
  • the first part of the data signal line is located between the substrate and the source/drain.
  • the display panel further includes a light shielding layer between the substrate and the thin film transistor layer;
  • the first part of the data signal line and the light shielding layer are arranged in the same layer.
  • the display panel further includes a gate layer on the substrate;
  • the first part of the data signal line is arranged in the same layer as the gate layer.
  • the touch control trace includes a first part and a second part
  • the first part of the touch wire and the second part of the touch wire are arranged in a different layer;
  • the first part of the touch trace and the second part of the touch trace are electrically connected through a second via;
  • the data signal line and the second part of the touch trace are arranged in the same layer.
  • the second part of the touch control trace is arranged in the same layer as the source/drain;
  • the first part of the touch trace is located between the substrate and the source/drain.
  • the first part of the touch control trace and the light shielding layer are arranged in the same layer.
  • the first part of the touch control trace is arranged in the same layer as the gate layer.
  • the data signal line is parallel to the touch trace.
  • This application also proposes a display module, including a display panel, a polarizing layer and a cover layer on the display panel, wherein the display panel includes a substrate, a thin film transistor layer on the substrate, And a touch layer located on the thin film transistor layer;
  • the thin film transistor layer includes a source/drain layer, and the source/drain layer includes a source/drain and a data signal line;
  • the display panel further includes a touch trace electrically connected to the touch layer, and the touch trace is located between the substrate and the touch layer;
  • some of the data signal lines and some of the touch wires are arranged in different layers.
  • the data signal line includes a first part and a second part
  • the first part of the data signal line and the second part of the data signal line are arranged in a different layer;
  • the first part of the data signal line and the second part of the data signal line are electrically connected through a first via;
  • the touch control trace and the second part of the data signal line are arranged in the same layer.
  • the second part of the data signal line is arranged in the same layer as the source electrode or the drain electrode;
  • the first part of the data signal line is located between the substrate and the source/drain.
  • the display panel further includes a light shielding layer between the substrate and the thin film transistor layer;
  • the first part of the data signal line and the light shielding layer are arranged in the same layer.
  • the display panel further includes a gate layer on the substrate;
  • the first part of the data signal line is arranged in the same layer as the gate layer.
  • the touch control trace includes a first part and a second part
  • the first part of the touch wire and the second part of the touch wire are arranged in a different layer;
  • the first part of the touch trace and the second part of the touch trace are electrically connected through a second via;
  • the data signal line and the second part of the touch trace are arranged in the same layer.
  • the second part of the touch control trace is arranged in the same layer as the source/drain;
  • the first part of the touch trace is located between the substrate and the source/drain.
  • the first part of the touch control trace and the light shielding layer are arranged in the same layer.
  • the first part of the touch control trace is arranged in the same layer as the gate layer.
  • the data signal line is parallel to the touch trace.
  • This application adopts a jumper design to arrange the parts with a smaller distance between the touch trace and the data signal line on different film layers, which avoids the short connection of the touch trace and the data signal line, so that the data signal Normal transmission improves the yield of the product.
  • Figure 1 is the first structure diagram of the display panel of this application.
  • FIG. 2 is the first top view of the display panel of this application
  • Figure 3 is a second structure diagram of the display panel of this application.
  • Figure 4 is a third structural diagram of the display panel of this application.
  • FIG. 5 is a second top view of the display panel of this application.
  • FIG. 6 is a fourth structural diagram of the display panel of this application.
  • FIG. 1 is a first structure diagram of the display panel 100 of this application.
  • the display panel 100 includes a substrate 10, a thin film transistor layer 200 on the substrate 10, and a touch layer 300 on the thin film transistor layer 200.
  • the raw material of the substrate 10 may be one of a glass substrate, a quartz substrate, and a resin substrate.
  • the substrate 10 may also be a flexible substrate.
  • the material of the flexible substrate may be PI (polyimide).
  • the thin film transistor layer 200 may include a plurality of thin film transistor units.
  • the thin film transistor unit may have an etch barrier type, a back channel etch type, a bottom gate thin film transistor type or a top gate thin film transistor type structure, which is not specifically limited.
  • the thin film transistor unit may include a buffer layer 20, an active layer 30, a gate insulating layer 40, a gate layer 50, an inter insulating layer 60, a source and drain layer 70, and a passivation layer 80.
  • the buffer layer 20 is formed on the substrate 10 and is mainly used to buffer the pressure between the layered structure of the membrane, and may also have a certain function of blocking water and oxygen.
  • the material of the buffer layer 20 may include one or more combinations of silicon nitride or silicon oxide.
  • the active layer 30 is formed on the buffer layer 20.
  • the active layer 30 includes ion-doped doped regions 31 and channel regions 32 located between the doped regions 31.
  • the active layer 30 may be formed by a layer of amorphous silicon that is laser-annealed to form polysilicon, and the polysilicon is patterned to form the active layer 30.
  • the material of the active layer 30 may be indium gallium zinc oxide (IGZO), which is a conductive semiconductor, and also a transparent material.
  • IGZO indium gallium zinc oxide
  • the gate insulating layer 40 is formed on the active layer 30.
  • the gate insulating layer 40 covers the active layer 30.
  • the gate insulating layer 40 is used to isolate the active layer 30 from other metal layers.
  • the material of the gate insulating layer 40 may be silicon nitride, silicon oxide, or silicon oxynitride.
  • the gate layer 50 is formed on the gate insulating layer 40.
  • the gate layer 50 is formed by patterning a first metal layer.
  • the gate layer 50 includes a gate 51 and a scan signal line 52.
  • the first metal material may be one of molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination of the above-mentioned metal materials.
  • the metal material of the gate layer 50 may be molybdenum.
  • the inter-insulating layer 60 is formed on the gate layer 50.
  • the inter-insulating layer 60 covers the gate layer 50.
  • the inter-insulating layer 60 is mainly used to isolate the gate layer 50 and the source-drain layer 70.
  • the material of the inter-insulating layer 60 may be silicon nitride, silicon oxide, or silicon oxynitride.
  • the source and drain layer 70 is formed on the inter-insulating layer 60.
  • the source and drain layers 70 are formed by patterning a second metal layer.
  • the source-drain layer 70 includes a source 71, a drain 72 and a data signal line 73.
  • the material of the second metal layer can be one of molybdenum, aluminum, aluminum-nickel alloy, molybdenum tungsten alloy, chromium, copper, or titanium-aluminum alloy, or a combination of the foregoing metal materials.
  • the source 71/drain 72 are electrically connected to the doped region 31 on the active layer 30 through a third via 74.
  • the metal material of the source and drain layer 70 may be titanium aluminum titanium.
  • the passivation layer 80 is formed on the source and drain layer 70.
  • the passivation layer 80 covers the source/drain layer 70 to isolate the metal on the source/drain layer 70 from short-circuiting with the metal layer on the passivation layer 80.
  • the material of the passivation layer 80 may be an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.
  • the touch layer 300 is located on the passivation layer 80.
  • the touch layer 300 may be composed of transparent electrodes for receiving or outputting corresponding touch signals.
  • the material of the transparent electrode may be indium tin oxide (ITO).
  • the display panel 100 further includes a touch trace 90 electrically connected to the touch layer 300.
  • the touch trace 90 is electrically connected to the touch layer 300 through the fourth via 91.
  • the touch trace 90 is parallel to the data signal line 73.
  • the touch trace 90 is located between the substrate 10 and the touch layer 300.
  • some of the data signal lines 73 and some of the touch wires 90 are arranged in different layers.
  • the data signal line 73 includes a first part 731 and a second part 732.
  • the first part 731 of the data signal line and the second part 732 of the data signal line are arranged in a different layer.
  • the touch wiring 90 and the second part 732 of the data signal line are arranged in the same layer.
  • the second portion 732 of the data signal line and the source 71 or the drain 72 are arranged in the same layer.
  • FIG. 2 is a first top view of the display panel 100 of this application.
  • the touch wiring 90 and the second part 732 of the data signal line are arranged in the same layer.
  • the first portion 731 of the data signal line located in the first region of the display panel 100 is located between the substrate 10 and the source 71/drain 72 (not shown in FIG. 2).
  • the first part 731 of the data signal line and the second part 732 of the data signal line are electrically connected through a first via 75.
  • the first part 731 of the data signal line is disposed between the substrate 10 and the source 71/drain 72, so that the first part 731 of the data signal line in this area is connected to the
  • the touch wiring 90 is not arranged in the same layer, which avoids the short connection between the touch wiring 90 and the data signal line 73, so that the data signal is transmitted normally, and the yield of the product is improved.
  • the first part 731 of the data signal line may be provided in the same layer as the gate layer 50.
  • the first part 731 of the data signal line can be formed at the same time. Therefore, the first part 731 of the data signal line of the present application can be reached without adding a mask.
  • the first via 75 penetrates part of the inter-insulating layer 60, and the third via 74 penetrates the inter-insulating layer 60 and part of the gate insulating layer 40. Therefore, the first via 75 may also be formed in the etching process for forming the third via 74.
  • FIG. 3 is a second structure diagram of the display panel 100 of this application.
  • the display panel 100 further includes a light shielding layer 101 between the substrate 10 and the thin film transistor layer 200.
  • the light shielding layer 101 is mainly used to shield the light source for the thin film transistor unit, and affect the driving effect of the thin film transistor.
  • the first part 731 of the data signal line may be provided in the same layer as the light shielding layer 101.
  • the first part 731 of the data signal line can be formed at the same time. Therefore, the first part 731 of the data signal line of the present application can be reached without adding a mask.
  • the first via 75 penetrates the inter-insulating layer 60, the gate insulating layer 40, and a portion of the buffer layer 20, and the third via 74 penetrates the inter-insulating layer 60 and Part of the gate insulating layer 40. Therefore, the third via hole 74 may also be formed in the etching process for forming the first via hole 75.
  • FIG. 4 is a third structural diagram of the display panel 100 of this application.
  • the first part 731 of the data signal line and the second part 732 of the data signal line are arranged in the same layer, and are formed in the same photomask process as the source 71/drain 72.
  • the touch wire 90 includes a first part 901 and a second part 902.
  • the first part 901 of the touch trace and the second part 902 of the touch trace are arranged in a different layer.
  • the data signal line 73 and the second part 902 of the touch trace are arranged in the same layer.
  • the second portion 902 of the touch control trace is arranged in the same layer as the source 71 or the drain 72.
  • FIG. 5 is a second top view of the display panel 100 of this application.
  • the data signal line 73 and the second part 902 of the touch trace are arranged in the same layer.
  • the first part 901 of the touch trace located in the second area of the display panel 100 is located between the substrate 10 and the source 71/drain 72 (not shown in FIG. 5 ).
  • the first part 901 of the touch trace and the second part 902 of the touch trace are electrically connected through a second via 92.
  • the first part 901 of the touch trace is disposed between the substrate 10 and the source 71/drain 72, so that the first part 901 of the touch trace in this area is
  • the data signal lines 73 are not arranged in the same layer, which avoids the short connection between the data signal lines 73 and the touch wires 90, so that the data signals are transmitted normally, and the yield of products is improved.
  • the first portion 901 of the touch control trace may be provided in the same layer as the gate layer 50.
  • the first part 901 of the touch trace can be formed at the same time. Therefore, the first part 901 of the touch trace of the present application can be used without adding a photomask. achieve.
  • the first via 75 penetrates a portion of the inter-insulating layer 60, and the second via 92 penetrates the inter-insulating layer 60 and a portion of the gate insulating layer 40. Therefore, the first via 75 may also be formed in the etching process for forming the second via 92.
  • FIG. 6 is a fourth structural diagram of the display panel 100 of the present application.
  • the first part 901 of the touch control trace may be provided in the same layer as the light shielding layer 101.
  • the first part 901 of the touch trace can be formed at the same time. Therefore, the first part 901 of the touch trace of the present application can be achieved without adding a mask. .
  • the second via 92 penetrates the inter-insulating layer 60, the gate insulating layer 40, and a portion of the buffer layer 20, and the third via 74 penetrates the inter-insulating layer 60 and Part of the gate insulating layer 40. Therefore, the third via 74 can also be formed in the etching process for forming the second via 92.
  • the application also proposes a display module, which includes the above-mentioned display panel and a polarizing layer and a cover layer on the display panel.
  • the working principle of the display module is the same as or similar to that of the display panel, and details are not repeated here.
  • This application also proposes an electronic device, which includes the above-mentioned display module.
  • the working principle of the electronic device is the same as or the same as that of the display module, and details are not repeated here.
  • the electronic device includes, but is not limited to, mobile phones, tablet computers, computer monitors, game consoles, televisions, display screens, wearable devices, and other household appliances or household appliances with display functions.
  • the display panel includes a substrate, a thin film transistor layer on the substrate, and a touch layer on the thin film transistor layer; the thin film transistor layer It includes a source/drain layer on which source/drain electrodes and data signal lines are disposed; the display panel also includes touch traces electrically connected to the touch layer, and the touch trace
  • the wires are located between the substrate and the touch layer; wherein, some of the data signal wires and some of the touch wires are arranged in different layers.
  • This application adopts a jumper design to arrange the parts with a smaller distance between the touch trace and the data signal line on different film layers, which avoids the short connection of the touch trace and the data signal line, so that the data signal Normal transmission improves the yield of the product.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种显示面板（100）及显示模组，该显示面板（100）包括衬底（10）、位于该衬底（10）上的源漏极层（70）、及位于该源漏极层（70）上的触控层（300）；该源漏极层（70）上设置有源极（71）、漏极（72）及数据信号线（73）；该显示面板（100）还包括与该触控层（300）电连接的触控走线（90），该触控走线（90）位于该衬底（10）与该触控层（300）之间；其中，部分该数据信号线（73）与部分该触控走线（90）非同层设置。

Description

显示面板及显示模组 技术领域
本申请涉及显示领域，尤其涉及一种显示面板及显示模组。
 背景技术
低温多晶硅（Low temperature poly-silicon，LTPS），由于其具有高的电子迁移率，可以有效的减小薄膜晶体管（Thin Film Transistor，TFT）器件的面积，进而提升像素的开口率，增大面板显示亮度的同时可以降低整体的功耗，使得面板的制造成本大幅度降低，目前已成为液晶显示领域炙手可热的技术。
现有技术中的显示面板为了节省光罩，常常将触控引线与源漏极层同层设置，由于布线空间的紧缺性导致触控引线与数据线短接，影响显示面板数据传输性能，导致显示面板显示异常，降低了面板的良率。
因此，目前亟需一种显示面板以解决上述问题。
 技术问题
本申请提供一种显示面板及显示模组，以解决现有显示面板数据传输异常的技术问题。
 技术解决方案
本申请提供了一种显示面板，其包括衬底、位于所述衬底上的薄膜晶体管层、及位于所述薄膜晶体管层上的触控层；
所述薄膜晶体管层包括源漏极层，所述源漏极层包括源极/漏极及数据信号线；
所述显示面板还包括与所述触控层电连接的触控走线，所述触控走线位于所述衬底与所述触控层之间；
其中，部分所述数据信号线与部分所述触控走线非同层设置。
在本申请的显示面板中，
所述数据信号线包括第一部分和第二部分；
所述数据信号线的第一部分与所述数据信号线的第二部分非同层设置；
所述数据信号线的第一部分与所述数据信号线的第二部分通过第一过孔电连接；
所述触控走线与所述数据信号线的第二部分同层设置。
在本申请的显示面板中，
所述数据信号线的第二部分与所述源极或漏极同层设置；
所述数据信号线的第一部分位于所述衬底与所述源极/漏极之间。
在本申请的显示面板中，
所述显示面板还包括位于所述衬底与所述薄膜晶体管层之间的遮光层；
所述数据信号线的第一部分与所述遮光层同层设置。
在本申请的显示面板中，
所述显示面板还包括位于所述衬底上的栅极层；
所述数据信号线的第一部分与所述栅极层同层设置。
在本申请的显示面板中，
所述触控走线包括第一部分和第二部分；
所述触控走线的第一部分与所述触控走线的第二部分非同层设置；
所述触控走线的第一部分与所述触控走线的第二部分通过第二过孔电连接；
所述数据信号线与所述触控走线的第二部分同层设置。
在本申请的显示面板中，
所述触控走线的第二部分与所述源极/漏极同层设置；
所述触控走线的第一部分位于所述衬底与所述源极/漏极之间。
在本申请的显示面板中，
所述触控走线的第一部分与所述遮光层同层设置。
在本申请的显示面板中，
所述触控走线的第一部分与所述栅极层同层设置。
在本申请的显示面板中，
所述数据信号线与所述触控走线平行。
本申请还提出了一种显示模组，包括显示面板及位于所述显示面板上的偏光层及盖板层，其中，所述显示面板包括衬底、位于所述衬底上的薄膜晶体管层、及位于所述薄膜晶体管层上的触控层；
所述薄膜晶体管层包括源漏极层，所述源漏极层包括源极/漏极及数据信号线；
所述显示面板还包括与所述触控层电连接的触控走线，所述触控走线位于所述衬底与所述触控层之间；
其中，部分所述数据信号线与部分所述触控走线非同层设置。
在本申请的显示模组中，
所述数据信号线包括第一部分和第二部分；
所述数据信号线的第一部分与所述数据信号线的第二部分非同层设置；
所述数据信号线的第一部分与所述数据信号线的第二部分通过第一过孔电连接；
所述触控走线与所述数据信号线的第二部分同层设置。
在本申请的显示模组中，
所述数据信号线的第二部分与所述源极或漏极同层设置；
所述数据信号线的第一部分位于所述衬底与所述源极/漏极之间。
在本申请的显示模组中，
所述显示面板还包括位于所述衬底与所述薄膜晶体管层之间的遮光层；
所述数据信号线的第一部分与所述遮光层同层设置。
在本申请的显示模组中，
所述显示面板还包括位于所述衬底上的栅极层；
所述数据信号线的第一部分与所述栅极层同层设置。
在本申请的显示模组中，
所述触控走线包括第一部分和第二部分；
所述触控走线的第一部分与所述触控走线的第二部分非同层设置；
所述触控走线的第一部分与所述触控走线的第二部分通过第二过孔电连接；
所述数据信号线与所述触控走线的第二部分同层设置。
在本申请的显示模组中，
所述触控走线的第二部分与所述源极/漏极同层设置；
所述触控走线的第一部分位于所述衬底与所述源极/漏极之间。
在本申请的显示模组中，
所述触控走线的第一部分与所述遮光层同层设置。
在本申请的显示模组中，
所述触控走线的第一部分与所述栅极层同层设置。
在本申请的显示模组中，
所述数据信号线与所述触控走线平行。
 有益效果
本申请采用跳线设计将所述触控走线与所述数据信号线间距较小的部分设置在不同膜层上，避免了触控走线与所述数据信号线的短接，使得数据信号正常传输，提高了产品的良率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请显示面板的第一种结构图；
图2为本申请显示面板的第一种俯视图；
图3为本申请显示面板的第二种结构图；
图4为本申请显示面板的第三种结构图；
图5为本申请显示面板的第二种俯视图；
图6为本申请显示面板的第四种结构图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
请参阅图1，图1为本申请显示面板100的第一种结构图。
所述显示面板100包括衬底10、位于所述衬底10上的薄膜晶体管层200、及位于所述薄膜晶体管层200上的触控层300。
在本实施例中，所述衬底10的原材料可以为玻璃基板、石英基板、树脂基板等中的一种。所述衬底10还可以为柔性基板。所述柔性基板的材料可以为PI（聚酰亚胺）。
所述薄膜晶体管层200可以包括多个薄膜晶体管单元。所述薄膜晶体管单元可以蚀刻阻挡层型、背沟道蚀刻型、底栅薄膜晶体管型或顶栅薄膜晶体管型结构，具体没有限制。
本申请以顶栅薄膜晶体管型为例进行说明。所述薄膜晶体管单元可以包括缓冲层20、有源层30、栅绝缘层40、栅极层50、间绝缘层60、源漏极层70、及钝化层80。
所述缓冲层20形成于所述衬底10上，主要用于缓冲膜层质结构之间的压力，并且还可以具有一定阻水氧的功能。
在本实施例中，所述缓冲层20的材料可以包括氮化硅或氧化硅中的一种或一种以上的组合物。
所述有源层30形成于所述缓冲层20上。
所述有源层30包括经离子掺杂的掺杂区31和位于所述掺杂区31之间的沟道区32。
所述有源层30可以由一层非晶硅经镭射激光退火形成多晶硅形成，该多晶硅经图案化处理形成所述有源层30。
在本实施例中，所述有源层30的材料可以为铟镓锌氧化物（IGZO），即导电的半导体，同时也是透明材料。
所述栅绝缘层40形成于所述有源层30上。
所述栅绝缘层40将所述有源层30覆盖。所述栅绝缘层40用于将所述有源层30与其他金属层隔离。
在本实施例中，所述栅绝缘层40的材料可以为氮化硅、氧化硅或氮氧化硅等。
所述栅极层50形成于所述栅绝缘层40上。
所述栅极层50由第一金属层经图案化处理形成。所述栅极层50包括栅极51和扫描信号线52。
所述第一金属材料可以为钼、铝、铝镍合金、钼钨合金、铬、或铜等金属中的一种，也可以使用上述几种金属材料的组合物。
在本实施例中，所述栅极层50的金属材料可以为钼。
所述间绝缘层60形成于所述栅极层50上。
所述间绝缘层60将所述栅极层50覆盖。所述间绝缘层60主要用于将所述栅极层50和所述源漏极层70隔离。
在本实施例中，所述间绝缘层60的材料可以为氮化硅、氧化硅或氮氧化硅等。
所述源漏极层70形成于所述间绝缘层60上。
所述源漏极层70由第二金属层经图案化处理形成。所述源漏极层70包括源极71、漏极72、数据信号线73。
所述第二金属层的材料可以为钼、铝、铝镍合金、钼钨合金、铬、铜或钛铝合金等金属中的一种，也可以使用上述几种金属材料的组合物。
所述源极71/漏极72通过第三过孔74与所述有源层30上的掺杂区31电连接。
在本实施例中，所述源漏极层70的金属材料可以为钛铝钛。
所述钝化层80形成于所述源漏极层70上。
所述钝化层80覆盖所述源漏极层70，用于隔绝所述源漏极层70上的金属与位于所述钝化层80上的金属层短接。
在本实施例中，所述钝化层80的材料可以为氮化硅、氧化硅或氮氧化硅等无机绝缘材料。
所述触控层300位于所述钝化层80上。
所述触控层300可以由透明电极构成，用于接收或输出对应的触控信号。所述透明电极的材料可以为氧化铟锡（ITO）。
所述显示面板100还包括与所述触控层300电连接的触控走线90。
所述触控走线90通过第四过孔91与所述触控层300电连接。
在本实施例中，所述触控走线90与所述数据信号线73平行。
所述触控走线90位于所述衬底10与所述触控层300之间。
在本实施例中，部分所述数据信号线73与部分所述触控走线90非同层设置。
请参阅图1，所述数据信号线73包括第一部分731和第二部分732。
所述数据信号线的第一部分731与所述数据信号线的第二部分732非同层设置。所述触控走线90与所述数据信号线的第二部分732同层设置。所述数据信号线的第二部分732与所述源极71或漏极72同层设置。
请参阅图2，图2为本申请显示面板100的第一种俯视图。
所述触控走线90与所述数据信号线的第二部分732同层设置。而位于所述显示面板100第一区内的数据信号线的第一部分731位于所述衬底10与所述源极71/漏极72之间（图2未示出）。所述数据信号线的第一部分731与所述数据信号线的第二部分732通过第一过孔75电连接。
本实施例通过将所述数据信号线的第一部分731设置于所述衬底10与所述源极71/漏极72之间，使得该区域的所述数据信号线的第一部分731与所述触控走线90非同层设置，避免了触控走线90与所述数据信号线73的短接，使得数据信号正常传输，提高了产品的良率。
请参阅图1，所述数据信号线的第一部分731可以与所述栅极层50同层设置。在进行所述栅极层50的图案化时，可以同时形成所述数据信号线的第一部分731，因此本申请的所述数据信号线的第一部分731可以在不增加光罩的情况下达到。
在本实施例中，所述第一过孔75贯穿部分所述间绝缘层60，所述第三过孔74贯穿所述间绝缘层60及部分所述栅绝缘层40。因此所述第一过孔75也可以在形成所述第三过孔74的蚀刻工艺中形成。
请参阅图3，图3为本申请显示面板100的第二种结构图。
所述显示面板100还包括位于所述衬底10与所述薄膜晶体管层200之间的遮光层101。所述遮光层101主要用于遮挡光源进行薄膜晶体管单元，影响薄膜晶体管的驱动效果。
所述数据信号线的第一部分731可以与所述遮光层101同层设置。在进行所述遮光层101的图案化时，可以同时形成所述数据信号线的第一部分731，因此本申请的所述数据信号线的第一部分731可以在不增加光罩的情况下达到。
在本实施例中，所述第一过孔75贯穿所述间绝缘层60、所述栅绝缘层40及部分所述缓冲层20，所述第三过孔74贯穿所述间绝缘层60及部分所述栅绝缘层40。因此所述第三过孔74也可以在形成所述第一过孔75的蚀刻工艺中形成。
请参阅图4，图4为本申请显示面板100的第三种结构图。
本实施例中的所述数据信号线的第一部分731与所述数据信号线的第二部分732同层设置，与所述源极71/漏极72在同一道光罩工艺中形成。
所述触控走线90包括第一部分901和第二部分902。
所述触控走线的第一部分901与所述触控走线的第二部分902非同层设置。所述数据信号线73与所述触控走线的第二部分902同层设置。所述触控走线的第二部分902与所述源极71或漏极72同层设置。
请参阅图5，图5为本申请显示面板100的第二种俯视图。
所述数据信号线73与所述触控走线的第二部分902同层设置。而位于所述显示面板100第二区内的触控走线的第一部分901位于所述衬底10与所述源极71/漏极72之间（图5未示出）。所述触控走线的第一部分901与所述触控走线的第二部分902通过第二过孔92电连接。
本实施例通过将所述触控走线的第一部分901设置于所述衬底10与所述源极71/漏极72之间，使得该区域的所述触控走线的第一部分901与所述数据信号线73非同层设置，避免了数据信号线73与所述触控走线90的短接，使得数据信号正常传输，提高了产品的良率。
请参阅图4，所述触控走线的第一部分901可以与所述栅极层50同层设置。在进行所述栅极层50的图案化时，可以同时形成所述触控走线的第一部分901，因此本申请的所述触控走线的第一部分901可以在不增加光罩的情况下达到。
在本实施例中，所述第一过孔75贯穿部分所述间绝缘层60，所述第二过孔92贯穿所述间绝缘层60及部分所述栅绝缘层40。因此所述第一过孔75也可以在形成所述第二过孔92的蚀刻工艺中形成。
请参阅图6，图6为本申请显示面板100的第四种结构图。
所述触控走线的第一部分901可以与所述遮光层101同层设置。在进行所述遮光层101的图案化时，可以同时形成所述触控走线的第一部分901，因此本申请的所述触控走线的第一部分901可以在不增加光罩的情况下达到。
在本实施例中，所述第二过孔92贯穿所述间绝缘层60、所述栅绝缘层40及部分所述缓冲层20，所述第三过孔74贯穿所述间绝缘层60及部分所述栅绝缘层40。因此所述第三过孔74也可以在形成所述第二过孔92的蚀刻工艺中形成。
本申请还提出了一种显示模组，所述显示模组包括上述显示面板及位于所述显示面板上的偏光层及盖板层。所述显示模组的工作原理与所述显示面板相同或类似，具体不再赘述。
本申请还提出了一种电子装置，所述电子装置包括上述显示显示模组。所述电子装置的工作原理与所述显示模组的相同或相同，具体不再赘述。
在本实施例中，所述电子装置包括但不限定于手机、平板电脑、计算机显示器、游戏机、电视机、显示屏幕、可穿戴设备及其他具有显示功能的生活电器或家用电器等。
本申请提出了一种显示面板及显示模组，所述显示面板包括衬底、位于所述衬底上的薄膜晶体管层、及位于所述薄膜晶体管层上的触控层；所述薄膜晶体管层包括源漏极层，所述源漏极层上设置有源极/漏极及数据信号线；所述显示面板还包括与所述触控层电连接的触控走线，所述触控走线位于所述衬底与所述触控层之间；其中，部分所述数据信号线与部分所述触控走线非同层设置。本申请采用跳线设计将所述触控走线与所述数据信号线间距较小的部分设置在不同膜层上，避免了触控走线与所述数据信号线的短接，使得数据信号正常传输，提高了产品的良率。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其中，包括衬底、位于所述衬底上的薄膜晶体管层、及位于所述薄膜晶体管层上的触控层；
    所述薄膜晶体管层包括源漏极层，所述源漏极层包括源极/漏极及数据信号线；
    所述显示面板还包括与所述触控层电连接的触控走线，所述触控走线位于所述衬底与所述触控层之间；
    其中，部分所述数据信号线与部分所述触控走线非同层设置。
  2. 根据权利要求1所述的显示面板，其中，
    所述数据信号线包括第一部分和第二部分；
    所述数据信号线的第一部分与所述数据信号线的第二部分非同层设置；
    所述数据信号线的第一部分与所述数据信号线的第二部分通过第一过孔电连接；
    所述触控走线与所述数据信号线的第二部分同层设置。
  3. 根据权利要求2所述的显示面板，其中，
    所述数据信号线的第二部分与所述源极或漏极同层设置；
    所述数据信号线的第一部分位于所述衬底与所述源极/漏极之间。
  4. 根据权利要求3所述的显示面板，其中，
    所述显示面板还包括位于所述衬底与所述薄膜晶体管层之间的遮光层；
    所述数据信号线的第一部分与所述遮光层同层设置。
  5. 根据权利要求3所述的显示面板，其中，
    所述显示面板还包括位于所述衬底上的栅极层；
    所述数据信号线的第一部分与所述栅极层同层设置。
  6. 根据权利要求1所述的显示面板，其中，
    所述触控走线包括第一部分和第二部分；
    所述触控走线的第一部分与所述触控走线的第二部分非同层设置；
    所述触控走线的第一部分与所述触控走线的第二部分通过第二过孔电连接；
    所述数据信号线与所述触控走线的第二部分同层设置。
  7. 根据权利要求6所述的显示面板，其中，
    所述触控走线的第二部分与所述源极/漏极同层设置；
    所述触控走线的第一部分位于所述衬底与所述源极/漏极之间。
  8. 根据权利要求7所述的显示面板，其中，
    所述触控走线的第一部分与所述遮光层同层设置。
  9. 根据权利要求7所述的显示面板，其中，
    所述触控走线的第一部分与所述栅极层同层设置。
  10. 根据权利要求1所述的显示面板，其中，
    所述数据信号线与所述触控走线平行。
  11. 一种显示模组，包括显示面板及位于所述显示面板上的偏光层及盖板层，其中，所述显示面板包括衬底、位于所述衬底上的薄膜晶体管层、及位于所述薄膜晶体管层上的触控层；
    所述薄膜晶体管层包括源漏极层，所述源漏极层包括源极/漏极及数据信号线；
    所述显示面板还包括与所述触控层电连接的触控走线，所述触控走线位于所述衬底与所述触控层之间；
    其中，部分所述数据信号线与部分所述触控走线非同层设置。
  12. 根据权利要求11所述的显示模组，其中，
    所述数据信号线包括第一部分和第二部分；
    所述数据信号线的第一部分与所述数据信号线的第二部分非同层设置；
    所述数据信号线的第一部分与所述数据信号线的第二部分通过第一过孔电连接；
    所述触控走线与所述数据信号线的第二部分同层设置。
  13. 根据权利要求12所述的显示模组，其中，
    所述数据信号线的第二部分与所述源极或漏极同层设置；
    所述数据信号线的第一部分位于所述衬底与所述源极/漏极之间。
  14. 根据权利要求13所述的显示模组，其中，
    所述显示面板还包括位于所述衬底与所述薄膜晶体管层之间的遮光层；
    所述数据信号线的第一部分与所述遮光层同层设置。
  15. 根据权利要求13所述的显示模组，其中，
    所述显示面板还包括位于所述衬底上的栅极层；
    所述数据信号线的第一部分与所述栅极层同层设置。
  16. 根据权利要求11所述的显示模组，其中，
    所述触控走线包括第一部分和第二部分；
    所述触控走线的第一部分与所述触控走线的第二部分非同层设置；
    所述触控走线的第一部分与所述触控走线的第二部分通过第二过孔电连接；
    所述数据信号线与所述触控走线的第二部分同层设置。
  17. 根据权利要求16所述的显示模组，其中，
    所述触控走线的第二部分与所述源极/漏极同层设置；
    所述触控走线的第一部分位于所述衬底与所述源极/漏极之间。
  18. 根据权利要求17所述的显示模组，其中，
    所述触控走线的第一部分与所述遮光层同层设置。
  19. 根据权利要求17所述的显示模组，其中，
    所述触控走线的第一部分与所述栅极层同层设置。
  20. 根据权利要求11所述的显示模组，其中，
    所述数据信号线与所述触控走线平行。
PCT/CN2019/087132 2019-03-29 2019-05-16 显示面板及显示模组 Ceased WO2020199316A1 (zh)

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CN110416270B (zh) 2019-07-30 2022-01-07 京东方科技集团股份有限公司 Oled显示面板及其检测方法、显示装置
CN111755464B (zh) * 2020-06-28 2022-07-12 合肥维信诺科技有限公司 一种阵列基板以及显示面板
CN113655919B (zh) * 2021-08-18 2023-06-30 深圳市华星光电半导体显示技术有限公司 内嵌式的oled触控显示面板
CN113805393A (zh) 2021-08-25 2021-12-17 武汉华星光电技术有限公司 显示面板及电子终端
CN115411055A (zh) * 2022-08-24 2022-11-29 合肥鑫晟光电科技有限公司 一种显示基板、显示面板、显示装置和制作方法
CN118870911A (zh) * 2023-04-28 2024-10-29 京东方科技集团股份有限公司 显示面板及显示装置
CN116719190B (zh) * 2023-05-31 2026-04-10 厦门天马微电子有限公司 显示面板和显示装置

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