WO2020194905A1 - Solid-state imaging element, imaging device, and method for controlling solid-state imaging element - Google Patents

Abstract

This solid-state imaging element for amplifying a difference between signals of each pair of pixels enables improvement in quality of image data. A load current source supplies a prescribed load current to a vertical reset input line connected to a node of a prescribed reset voltage. A pair of reset transistors initialize a pair of floating diffusion layers by means of a reference voltage obtained by dropping the reset voltage through wiring resistance of the vertical reset input line. A transfer transistor transfers charges from one of a pair of photoelectric conversion elements to one of the floating diffusion layers, and generates a voltage according to the amount of the charges as a signal voltage. A pair of amplification transistors generate an output current according to a difference between the reference voltage and the signal voltage. A current mirror circuit outputs, from a vertical signal line, a pixel signal of a voltage according to the output current.

Description

Solid-state image sensor, image sensor, and control method for solid-state image sensor

The present technology relates to a solid-state image sensor, an image sensor, and a control method for the solid-state image sensor. More specifically, the present invention relates to a solid-state image sensor, an image pickup device, and a method for controlling a solid-state image sensor that differentially amplify a signal and output it from a vertical signal line.

Conventionally, in an image pickup device or the like, a differential amplification type solid-state image sensor that amplifies the difference between the signals of a pair of pixels has been used. For example, a solid-state image sensor has been proposed in which pixels are arranged in a two-dimensional lattice, the difference between the signals of two adjacent pixels in the row direction is amplified, and the difference is output from a vertical signal line (for example, Patent Document). See 1.).

Japanese Unexamined Patent Publication No. 2018-182496

In the above-mentioned conventional technology, the sensitivity is increased by differential amplification to improve the image quality of image data captured in a dark place. However, in the above-mentioned solid-state image sensor, the amount of voltage drop due to the wiring resistance of the vertical signal line increases as the line is farther from the power supply, and the conversion efficiency of converting electric charge into voltage decreases due to the increase in the amount of voltage drop. There is a risk. Due to this difference in conversion efficiency for each row, there is a problem that a density gradient called shading appears in the image data and the image quality deteriorates.

This technology was created in view of such a situation, and aims to improve the image quality of image data in a solid-state image sensor that amplifies the difference between the signals of a pair of pixels.

The present technology has been made to solve the above-mentioned problems, and the first aspect thereof is a load current that supplies a predetermined load current to a vertical reset input line connected to a node having a predetermined reset voltage. A pair of reset transistors that initialize a pair of stray diffusion layers with a source and a reference voltage according to the amount of voltage drop due to the wiring resistance of the vertical reset input line, and a pair of stray diffusion layers from one of the pair of photoelectric conversion elements. A transfer transistor that transfers a charge to one side to generate a voltage corresponding to the amount of the charge as a signal voltage, and a pair of amplification transistors that generate an output current according to the difference between the reference voltage and the signal voltage. A solid-state imaging device including a current mirror circuit that outputs a pixel signal having a voltage corresponding to the output current from a vertical signal line, and a control method thereof. This has the effect of increasing the charge-voltage conversion efficiency according to the amount of voltage drop due to the wiring resistance of the vertical reset input line.

Further, in the first aspect, one of the pair of photoelectric conversion elements, one of the pair of floating diffusion layers, one of the pair of reset transistors, the transfer transistor, and one of the pair of amplification transistors are predetermined. The other of the pair of photoelectric conversion elements, the other of the pair of stray diffusion layers, the other of the pair of reset transistors, and the other of the pair of amplification transistors are arranged on one of the pair of pixels arranged in the direction. It may be arranged on the other side of the pair of pixels. This has the effect of differentially amplifying the signals of each of the pair of pixels.

Further, in the first aspect, a reset voltage supply transistor that lowers a predetermined power supply voltage and supplies it as a reset voltage to the vertical reset input line may be further provided. This has the effect of supplying a reset voltage lower than the power supply voltage.

Further, in the first aspect, the wiring resistance per unit length of the vertical reset input line may be larger than the wiring resistance per unit length of the vertical signal line. This has the effect of reducing power consumption.

Further, in this first aspect, a buffer that amplifies the voltage of the vertical reset input line and supplies it to each of the pair of reset transistors may be further provided. This has the effect of increasing the driving force of the pixels.

Further, in the first aspect, the voltage drop measuring unit that measures the voltage drop amount due to the wiring resistance of the vertical signal line and supplies the measured value, and the reset voltage that generates the bias voltage corresponding to the measured value. It may further include a bias voltage generator that supplies the gate of the supply transistor. This has the effect of supplying an appropriate reset voltage according to the amount of voltage drop.

Further, in the first aspect, when the differential mode is set, after initializing the pair of floating diffusion layers, one of the pair of photoelectric conversion elements is transferred to one of the pair of floating diffusion layers. Further, a vertical drive unit that controls the transfer of electric charges and controls the transfer of electric charges from the other of the pair of photoelectric conversion elements to the other of the pair of floating diffusion layers after initializing the pair of floating diffusion layers. It may be provided. As a result, in the differential mode, the pixel signal obtained by differentially amplifying each signal of the pair of pixels is read out.

Further, in the first aspect, the vertical drive unit initializes the pair of floating diffusion layers when the source follower mode is set, and then receives the pair of floating diffusion elements from each of the pair of photoelectric conversion elements. Control may be performed to transfer the charge to the diffusion layer. As a result, in the source follower mode, the pixel signal is read out without differential amplification.

Further, the second aspect of the present technology is a load current source that supplies a predetermined load current to a vertical reset input line connected to a node having a predetermined reset voltage, and a voltage drop due to the wiring resistance of the vertical reset input line. A pair of reset transistors that initialize the pair of floating diffusion layers with a reference voltage according to the voltage, and a charge transferred from one of the pair of photoelectric conversion elements to one of the pair of floating diffusion layers according to the amount of the charge. A transfer transistor that generates a voltage as a signal voltage, a pair of amplification transistors that generate an output current corresponding to the difference between the reference voltage and the signal voltage, and a pixel signal having a voltage corresponding to the output current are generated from a vertical signal line. It is an image pickup apparatus including a current mirror circuit for output and a signal processing unit for processing the pixel signal. This has the effect of processing the pixel signal of the voltage converted by the charge-voltage conversion efficiency that has increased according to the amount of voltage drop due to the wiring resistance of the vertical reset input line.

It is a block diagram which shows one configuration example of the image pickup apparatus in the 1st Embodiment of this technique. It is a block diagram which shows one structural example of the solid-state image sensor in 1st Embodiment of this technique. It is a block diagram which shows one structural example of the column reading circuit in 1st Embodiment of this technique. It is a circuit diagram which shows one structural example of the unit reading circuit in 1st Embodiment of this technique. It is a circuit diagram which shows one structural example of a pixel in 1st Embodiment of this technique. It is a block diagram which shows one structural example of the column signal processing part in 1st Embodiment of this technique. It is a timing chart which shows an example of the operation at the start of exposure of the solid-state image sensor of the differential mode in 1st Embodiment of this technique. It is a timing chart which shows an example of the operation at the end of exposure of the solid-state image sensor of the differential mode in the 1st Embodiment of this technique. It is a timing chart which shows an example of the operation at the start of the exposure of the solid-state image sensor in SF (Source Follower) mode in the modification of the 1st Embodiment of this technique. It is a timing chart which shows an example of the operation at the end of exposure of the solid-state image sensor of SF mode in the modification of the 1st Embodiment of this technique. This is an example of an equivalent circuit of a pixel and unit readout circuit in a differential mode according to the first embodiment of the present technology. It is a graph which shows an example of the charge-voltage conversion efficiency for each row in the 1st Embodiment of this technique and the comparative example. It is a figure for demonstrating the saturation margin in the comparative example. It is a figure for demonstrating the saturation margin in the 1st Embodiment of this technique. It is a flowchart which shows an example of the operation of the solid-state image sensor in 1st Embodiment of this technique. This is an example of an equivalent circuit of a pixel and unit reading circuit in the second embodiment of the present technology. This is an example of an equivalent circuit of a pixel and unit reading circuit according to a third embodiment of the present technology. This is an example of an equivalent circuit of a pixel and unit reading circuit according to a fourth embodiment of the present technology. It is a circuit diagram which shows one structural example of the unit reading circuit in 5th Embodiment of this technique. It is a block diagram which shows an example of the schematic structure of a vehicle control system. It is explanatory drawing which shows an example of the installation position of the vehicle exterior information detection unit and the image pickup unit.

Hereinafter, embodiments for carrying out the present technology (hereinafter referred to as embodiments) will be described. The explanation will be given in the following order.
1. 1. First Embodiment (Example of voltage drop due to wiring resistance of vertical reset input line)
2. 2. Second embodiment (example of voltage drop due to wiring resistance of a vertical reset input line having a wiring resistance larger than that of a vertical signal line)
3. 3. Third embodiment (example of reducing the number of transistors and lowering the voltage by the wiring resistance of the vertical reset input line)
4. Fourth Embodiment (Example of providing a buffer and lowering the voltage by the wiring resistance of the vertical reset input line)
5. Fifth Embodiment (Example of measuring the voltage drop amount of the vertical signal line and dropping the voltage by the wiring resistance of the vertical reset input line)
6. Application example to moving body

<1. First Embodiment>
[Configuration example of imaging device]
FIG. 1 is a block diagram showing a configuration example of the image pickup apparatus 100 according to the first embodiment of the present technology. The image pickup device 100 is a device for capturing image data, and includes an optical unit 110, a solid-state image sensor 200, and a digital signal processor 120. Further, the image pickup apparatus 100 includes a display unit 130, an operation unit 140, a bus 150, a power supply unit 160, a storage unit 170, and a frame memory 180. As the image pickup device 100, for example, in addition to a digital camera such as a digital still camera, a smartphone having an image pickup function, a personal computer, an in-vehicle camera, or the like is assumed.

The optical unit 110 collects the light from the subject and guides it to the solid-state image sensor 200. The solid-state image sensor 200 generates image data in synchronization with the vertical synchronization signal VSYNC. Here, the vertical synchronization signal VSYNC is a periodic signal having a predetermined frequency (for example, 30 hertz) indicating the timing of imaging. The solid-state image sensor 200 supplies the generated image data to the digital signal processor 120 via the signal line 209.

The digital signal processor 120 executes predetermined signal processing such as demosaic processing and noise reduction processing on the image data from the solid-state image sensor 200. The digital signal processor 120 outputs the processed image data to the frame memory 180 or the like via the bus 150. Further, the digital signal processor 120 generates a mode signal indicating either the differential mode or the SF mode and the vertical synchronization signal VSYNC and supplies them to the solid-state image sensor 200.

Here, the differential mode is a mode in which the solid-state image sensor 200 generates a signal obtained by amplifying (differential amplification) the difference between the signals of each pair of pixels. On the other hand, the SF mode is a mode in which a source follower circuit is formed to output a pixel signal without differential amplification. In the differential mode, the gain for the image signal can be increased to greatly increase the conversion efficiency, but the operating point is narrow and it is difficult to expand the dynamic range. Therefore, the differential mode is suitable for imaging in a dark place, and the SF mode is suitable for imaging in a bright place. Therefore, for example, the digital signal processor 120 measures the amount of ambient light and instructs the differential mode when the metering amount is smaller than a predetermined threshold value, and instructs the SF mode when the metering amount is equal to or more than the threshold value.

The display unit 130 displays image data. As the display unit 130, for example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed. The operation unit 140 generates an operation signal according to the operation of the user.

The bus 150 is a common route for the optical unit 110, the solid-state image sensor 200, the digital signal processor 120, the display unit 130, the operation unit 140, the power supply unit 160, the storage unit 170, and the frame memory 180 to exchange data with each other. ..

The power supply unit 160 supplies power to the solid-state image sensor 200, the digital signal processor 120, the display unit 130, and the like. The storage unit 170 stores various data such as image data. The frame memory 180 holds image data.

[Structure example of solid-state image sensor]
FIG. 2 is a block diagram showing a configuration example of the solid-state image sensor 200 according to the first embodiment of the present technology. The solid-state image sensor 200 includes a vertical drive unit 210, a pixel array unit 220, a system control unit 291 and a column readout circuit 300, a column signal processing unit 270, a horizontal drive unit 292, a data storage unit 293, and an image processing unit 294.

The system control unit 291 controls the vertical drive unit 210, the column readout circuit 300, the column signal processing unit 270, and the horizontal drive unit 292. The system control unit 291 is configured by a timing generator or the like. The system control unit 291 generates a timing signal instructing each operation timing of the vertical drive unit 210, the column signal processing unit 270, and the horizontal drive unit 292 in synchronization with the vertical synchronization signal VSYNC, and supplies the timing signal to the corresponding circuit. Further, the system control unit 291 generates a control signal for controlling the switch in the column read circuit 300 and supplies the control signal to the column read circuit 300.

A plurality of pixels are arranged in a two-dimensional grid pattern in the pixel array unit 220. Hereinafter, a set of pixels arranged in a predetermined direction (horizontal direction, etc.) is referred to as a "row", and a set of pixels arranged in a direction perpendicular to the row is referred to as a "column". Further, the number of rows in the pixel array unit 220 is M (M is an integer), and the number of columns is N (N is an integer).

Here, it is assumed that all the pixels in the pixel array unit 220 are effective pixels that perform photoelectric conversion. In addition to the effective pixels, dummy pixels that are not photoelectrically converted and light-shielding pixels that block incident light can be further arranged in the pixel array unit 220.

The vertical drive unit 210 drives by selecting rows in order. The vertical drive unit 210 is composed of a shift register, an address decoder, and the like. In the differential mode, the vertical drive unit 210 selects rows one by one, and each time a row is selected, the vertical drive unit 210 drives the odd columns and even columns in the row in order. On the other hand, in the SF mode, the vertical drive unit 210 selects rows in order and simultaneously drives all the pixels in the selected rows. Therefore, in the SF mode, one image data is generated by reading M times, and in the differential mode, one image data is generated by reading 2 × M times. The control method that drives in units of rows in this way is called a rolling shutter method. Although the vertical drive unit 210 uses a rolling shutter method, a global shutter method that drives all pixels at the same time can also be used.

The column reading circuit 300 reads out the pixel signal of each pixel in the row and supplies it to the column signal processing unit 270.

The column signal processing unit 270 executes signal processing such as AD (Analog to Digital) conversion processing for the pixel signals from the column for each column. The column signal processing unit 270 outputs each of the pixel data after signal processing to the image processing unit 294 in order according to the control of the horizontal drive unit 292. The column signal processing unit 270 is an example of the signal processing unit described in the claims.

The horizontal drive unit 292 controls the column signal processing unit 270 to output pixel data in order. The horizontal drive unit 292 is composed of a shift register and an address decoder.

The image processing unit 294 executes various image processing such as pixel addition processing on image data composed of pixel data arranged in a two-dimensional grid pattern. The image processing unit 294 causes the data storage unit 293 to temporarily hold the image data as needed in the image processing. Further, the image processing unit 294 supplies the processed image data to the digital signal processor 120.

The image processing unit 294 may be arranged outside the solid-state image sensor 200 (inside the digital signal processor 120, etc.).

[Configuration example of column readout circuit]
FIG. 3 is a block diagram showing a configuration example of the column readout circuit 300 according to the first embodiment of the present technology. The column reading circuit 300 includes a unit reading circuit 310 for every two columns. When the number of columns is N, N / 2 unit reading circuits 310 are arranged.

Each of the unit reading circuits 310 is connected to the pixel array unit 220 via six signal lines. Further, the unit reading circuit 310 supplies the corresponding two rows of pixel signals Vout1 and Vout2 to the column signal processing unit 270, respectively.

[Unit read circuit configuration example]
FIG. 4 is a circuit diagram showing a configuration example of the unit reading circuit 310 according to the first embodiment of the present technology. The unit readout circuit 310 includes pMOS (p-channel Metal Oxide Semiconductor) 311 to 314, tail current sources 321 and 322, load current sources 323 and 324, and switches 331 to 347.

Further, the unit read circuit 310 is connected to the corresponding two rows via the vertical signal lines 22S and 22R, the vertical reset input lines 61S and 61R, and the vertical current supply lines 62S and 62R.

The pMOS transistors 311 to 314 are connected in parallel to the node of the power supply voltage VDD. The gate of the pMOS transistor 311 is connected to the gate of the pMOS transistor 312. Further, the pixel signal Vout1 is output from the drain of the pMOS transistor 311 and the pixel signal Vout2 is output from the drain of the pMOS transistor 312.

Also, in each of the pMOS transistors 313 and 314, the gate and drain are short-circuited. By this diode connection, a voltage obtained by lowering the power supply voltage VDD by a predetermined voltage is supplied as the reset voltage Vrst from the drains of the pMOS transistors 313 and 314. The pMOS transistors 313 and 314 are examples of the reset voltage supply transistors described in the claims.

The tail current sources 321 and 322 supply a constant tail current to the unit read circuit 310 via the vertical current supply lines 62S and 62R. The load current source 323 supplies a predetermined load current to the vertical reset input line 61S via the switch 346. The load current source 324 supplies a predetermined load current to the vertical reset input line 61R via the switch 347.

The switch 331 opens and closes the path between the gate and the drain of the pMOS transistor 311 according to the control signal SW11 from the system control unit 291. The switch 332 opens and closes the path between the gate and the drain of the pMOS transistor 312 according to the control signal SW21 from the system control unit 291.

The switch 333 opens and closes the path between the vertical current supply line 62S and the tail current source 321 according to the control signal SW13 from the system control unit 291. The switch 334 opens and closes the path between the vertical current supply line 62R and the tail current source 321 according to the control signal SW0 from the system control unit 291. The switch 335 opens and closes the path between the vertical current supply line 62R and the tail current source 322 according to the control signal SW23 from the system control unit 291.

The switch 336 opens and closes the path between the vertical current supply line 62S and the node of the power supply voltage VDD according to the control signal SW12 from the system control unit 291. The switch 337 opens and closes the path between the vertical signal line 22S and the tail current source 321 according to the control signal SW14 from the system control unit 291.

The switch 338 opens and closes the path between the vertical current supply line 62R and the node of the power supply voltage VDD according to the control signal SW22 from the system control unit 291. The switch 339 opens and closes the path between the vertical signal line 22R and the tail current source 322 according to the control signal SW24 from the system control unit 291.

The switch 340 opens and closes the path between the drain of the pMOS transistor 313 (that is, the node of the reset voltage Vrst) and the vertical reset input line 61S according to the control signal SW16 from the system control unit 291. The switch 341 opens and closes the path between the node of the power supply voltage VDD and the vertical reset input line 61S according to the control signal SW17 from the system control unit 291.

The switch 342 opens and closes the path between the drain of the pMOS transistor 314 (that is, the node of the reset voltage Vrst) and the vertical reset input line 61R according to the control signal SW26 from the system control unit 291. The switch 343 opens and closes the path between the node of the power supply voltage VDD and the vertical reset input line 61R according to the control signal SW27 from the system control unit 291.

The switch 344 opens and closes the path between the vertical signal line 22S and the vertical reset input line 61S according to the control signal SW15 from the system control unit 291. The switch 346 opens and closes the path between the vertical signal line 22R and the vertical reset input line 61R according to the control signal SW25 from the system control unit 291.

The switch 346 opens and closes the path between the vertical reset input line 61S and the load current source 323 according to the control signal SW18 from the system control unit 291. The switch 347 opens and closes the path between the vertical reset input line 61R and the load current source 324 according to the control signal SW28 from the system control unit 291.

The control timing of each of the above switches 331 to 347 will be described later.

Although the load current sources 323 and 324 are arranged in each of the two rows (in other words, the load current sources are arranged in each row), one load current source is shared by a plurality of rows (two rows or all rows). You can also do it. As a result, the number of load current sources and the power consumption can be reduced as compared with the case where the load current sources are arranged for each row.

[Pixel configuration example]
FIG. 5 is a circuit diagram showing a configuration example of pixels 230 and 240 according to the first embodiment of the present technology. Pixels 230 are arranged in odd rows and pixels 240 are arranged in even rows.

The pixel 230 includes a photoelectric conversion element 231, a transfer transistor 232, a reset transistor 233, a floating diffusion layer 234, a selection transistor 235, and an amplification transistor 236. The pixel 240 includes a photoelectric conversion element 241, a transfer transistor 242, a reset transistor 243, a floating diffusion layer 244, a selection transistor 245, and an amplification transistor 246.

The photoelectric conversion element 231 generates an electric charge by photoelectric conversion. The transfer transistor 232 transfers an electric charge from the photoelectric conversion element 231 to the floating diffusion layer 234 according to the transfer signal TRG1 from the vertical drive unit 210.

The reset transistor 233 connects the floating diffusion layer 234 to the vertical reset input line 61S according to the reset signal RST1 from the vertical drive unit 210, extracts the electric charge from the floating diffusion layer 234, and initializes the voltage. The connection nodes of the vertical reset input line 61S and the reset transistor 233 in each row are arranged at regular intervals in the vertical direction.

The floating diffusion layer 234 accumulates the transferred electric charge and generates a voltage according to the amount of the electric charge. The amplification transistor 236 generates an output current corresponding to the voltage of the floating diffusion layer 234. Further, the source of the amplification transistor 236 is connected to the vertical current supply line 62S. The selection transistor 235 outputs the output current of the amplification transistor 236 to the vertical signal line 22S according to the selection signal SEL1. The connection nodes between the vertical current supply line 62S and the selection transistor 235 in each row are arranged at regular intervals in the vertical direction.

The connection configuration of the photoelectric conversion element 241 in the pixel 240, the transfer transistor 242, the reset transistor 243, the floating diffusion layer 244, the selection transistor 245, and the amplification transistor 246 is the same as that of the pixel 230. However, the transfer transistor 242 transfers the electric charge according to the transfer signal TRS2, and the reset transistor 243 connects the floating diffusion layer 244 to the vertical reset input line 61R according to the reset signal RST2. Further, the source of the amplification transistor 246 is connected to the vertical current supply line 62R, and the selection transistor 245 outputs a current to the vertical signal line 22R according to the selection signal SEL2.

In the differential mode, the column read circuit 300 reads the pixel signal of the read pixel with one of the pixels 230 and 240 in the row as the reference pixel and the other as the read pixel. Here, the read pixel is a pixel that generates a signal voltage according to the exposure amount, and the reference pixel is a pixel that generates a predetermined reference voltage.

Further, in the differential mode, the column readout circuit 300 in the solid-state image sensor 200 and the pixels 230 and 240 form a differential amplifier circuit that amplifies the difference between the reference voltage and the signal voltage. The column reading circuit 300 reads the differentially amplified signal as a pixel signal of the read pixel and supplies it to the column signal processing unit 270. Subsequently, the column reading circuit 300 replaces the reference pixel and the read pixel, reads the differentially amplified signal as the pixel signal of the read pixel, and supplies the signal to the column signal processing unit 270.

The solid-state image sensor 200 changes the row to be read, and repeats the above process until the reading of all rows is completed. In this way, reading is performed twice for each line. Assuming that the number of lines is M (M is an integer), reading is performed 2 × M times.

[Configuration example of column signal processing unit]
FIG. 6 is a block diagram showing a configuration example of the column signal processing unit 270 according to the first embodiment of the present technology. The column signal processing unit 270 includes a plurality of ADCs (Analog to Digital Converters) 271 and an output unit 280. ADC271 is arranged in each row.

ADC271 converts an analog pixel signal into digital pixel data. The ADC 271 includes a comparator 272 and a counter 273. The pixel signal Vout1 is input to the ADC271 in the odd-numbered column, and the pixel signal Vout2 is input to the ADC271 in the even-numbered column.

The comparator 272 compares the pixel signal of the corresponding row with the saw-wavy lamp signal REF. The comparator 272 supplies the comparison result to the counter 273. The counter 273 counts the count value over a period until the comparison result is reversed. The counter 273 supplies data indicating the count value to the output unit 280 as digital pixel data.

Here, the level of the pixel signal generated by supplying the reset signals RST1 and RST2 immediately before the end of exposure is referred to as "reset level". Further, the level of the pixel signal generated by the supply of the transfer signal TRG1 or TRG2 at the end of exposure is referred to as "signal level".

The counter 273, for example, performs one of up-counting and down-counting of the count value when converting the reset level, and performs the other of up-counting and down-counting when converting the signal level. As a result, along with AD (Analog to Digital) conversion, CDS (Correlated Double Sampling) processing for obtaining the difference between the reset level and the signal level is executed.

It should be noted that the counter 273 may perform only one of up-counting and down-counting, and the CDS processing may be executed by the circuit in the subsequent stage.

The output unit 280 outputs pixel data for each column to the image processing unit 294 in order under the control of the horizontal drive unit 292.

In the differential mode, the odd-numbered row pixel signal Vout1 and the even-numbered row pixel signal Vout2 are generated in order. Therefore, the odd-numbered row ADC271 and the even-numbered row ADC271 perform AD conversion of corresponding pixel signals in order. On the other hand, in the SF mode, since the odd-numbered pixel signal Vout1 and the even-numbered pixel signal Vout2 are generated at the same time, the ADC271 in all rows simultaneously AD-converts the corresponding pixel signals.

[Operation example of solid-state image sensor]
FIG. 7 is a timing chart showing an example of the operation of the solid-state image sensor 200 in the differential mode at the start of exposure according to the first embodiment of the present technology. When the differential mode is set at timing T0, the system control unit 291 sets the control signals SW13 and 23 to a high level and closes the corresponding switches 333 and 335.

Then, at the start timing T1 of the exposure accumulation period of the pixels 230 in the odd-numbered rows, the vertical drive unit 210 supplies the high-level reset signal RST1 and the transfer signal TRG1 over a predetermined pulse period. Further, the system control unit 291 supplies a high-level control signal SW17 over a pulse period at the timing T1 and closes the corresponding switch 341. By these controls, the electric charge of the floating diffusion layer 234 of the pixel 230 is discharged.

Further, at the start timing T2 of the exposure accumulation period of the even-numbered pixels 240, the vertical drive unit 210 supplies the high-level reset signal RST2 and the transfer signal TRG2 over a predetermined pulse period. Further, the system control unit 291 supplies a high-level control signal SW27 over a pulse period at the timing T2, and closes the corresponding switch 343. By these controls, the electric charge of the floating diffusion layer 244 of the pixel 240 is discharged.

FIG. 8 is a timing chart showing an example of the operation of the solid-state image sensor 200 in the differential mode at the end of exposure according to the first embodiment of the present technology.

At the timing T3 at which the reading is started, the vertical drive unit 210 sets the selection signals SEL1 and SEL2 to a high level. Further, at the timing T3, the system control unit 291 sets the control signals SW0, SW15, SW21, SW26 and SW28 to a high level and closes the corresponding switches 334, 344, 332, 342 and 347. As a result, the pixels 230 and 240 and the column readout circuit 300 form a differential amplifier circuit in which the pixel 230 is the read pixel and the pixel 240 is the reference pixel. Further, in the differential amplifier circuit, the load current from the load current source 324 is supplied to the vertical reset input line 61R.

Then, the vertical drive unit 210 supplies high-level reset signals RST1 and RST2 over the pulse period at the timing T4 immediately before the end of the exposure accumulation period of the odd-numbered rows. As a result, electric charges are discharged from the floating diffusion layers of the read pixel (pixel 230) and the reference pixel (pixel 240), and their voltages are initialized to a predetermined reference voltage. The level of the pixel signal Vout1 that amplifies the difference between these voltages is read out as a reset level.

The vertical drive unit 210 supplies a high-level transfer signal TRG1 over the pulse period at the end timing T5 of the exposure accumulation period of the odd-numbered rows. As a result, the electric charge is transferred from the photoelectric conversion element 231 of the pixel 230, which is a read pixel, to the floating diffusion layer 234, and the floating diffusion layer 234 generates a voltage corresponding to the amount of the electric charge as a signal voltage. The level of the pixel signal Vout1 obtained by amplifying the difference between the reference voltage of the reference pixel and the signal voltage of the read pixel is read as a signal level.

At the timing T6 when the reading of the pixel signal Vout1 is completed, the system control unit 291 lowers the control signals SW15, SW21, SW26 and SW28. Then, at the timing T7 immediately after that, the system control unit 291 sets the control signals SW11, SW16, SW18 and SW25 to a high level and closes the corresponding switches 331, 340, 346 and 345. As a result, the pixels 230 and 240 and the column readout circuit 300 form a differential amplifier circuit in which the pixel 240 is the read pixel and the pixel 230 is the reference pixel. In other words, the read pixel and the reference pixel are replaced. Further, in the differential amplifier circuit, the load current from the load current source 323 is supplied to the vertical reset input line 61S.

Then, the vertical drive unit 210 supplies high-level reset signals RST1 and RST2 over the pulse period at the timing T8 immediately before the end of the exposure accumulation period of the even-numbered rows. As a result, electric charges are discharged from the floating diffusion layers of the read pixel (pixel 240) and the reference pixel (pixel 230), and their voltages are initialized to a predetermined reference voltage. The level of the pixel signal Vout2 that amplifies the difference between these voltages is read out as a reset level.

The vertical drive unit 210 supplies a high-level transfer signal TRG2 over the pulse period at the end timing T9 of the even-numbered row of exposure accumulation periods. As a result, the charge is transferred from the photoelectric conversion element 241 of the pixel 240, which is a read pixel, to the floating diffusion layer 244, and the floating diffusion layer 244 generates a voltage corresponding to the amount of the charge as a signal voltage. The level of the pixel signal Vout2 obtained by amplifying the difference between the reference voltage of the reference pixel and the signal voltage of the read pixel is read as a signal level.

The controls illustrated in FIGS. 7 and 8 are performed row by row in differential mode.

FIG. 9 is a timing chart showing an example of the operation of the SF mode solid-state image sensor 200 at the start of exposure in the modified example of the first embodiment of the present technology. At the start timing T1 of the exposure accumulation period, the vertical drive unit 210 supplies the high-level reset signals RST1 and RST2 and the high-level transfer signals TRG1 and TRG2 over a predetermined pulse period. Further, the system control unit 291 supplies high-level control signals SW17 and SW27 over a pulse period. As a result, the electric charges of the floating diffusion layers of the pixels 230 and 240 are discharged. In the figure, the driving during the period of timings T2 to T3 does not contribute to the reading of pixels 230 and 240.

FIG. 10 is a timing chart showing an example of the operation of the SF mode solid-state image sensor 200 at the end of exposure according to the first embodiment of the present technology.

At the timing T3 at which the reading is started, the vertical drive unit 210 sets the selection signals SEL1 and SEL2 to a high level. Further, at the timing T3, the system control unit 291 sets the control signals SW12, SW14, SW17, SW22, SW24 and SW27 to a high level and closes the corresponding switches 336, 337, 341, 338, 339 and 343. As a result, the pixels 230 and 240 and the column readout circuit 300 form a source follower circuit for each column. Further, in the source follower circuit, the load current is not supplied to the vertical reset input lines 61R and 61S.

Then, the vertical drive unit 210 supplies high-level reset signals RST1 and RST2 over the pulse period at the timing T4 immediately before the end of the exposure accumulation period. As a result, charges are discharged from the floating diffusion layers of the pixels 230 and 240, and their voltages are initialized to a predetermined reference voltage. The respective levels of the pixel signals Vout1 and Vout2 at this time are read out as reset levels.

The vertical drive unit 210 supplies high-level transfer signals TRG1 and TRG2 over the pulse period at the end timing T5 of the exposure accumulation period. As a result, electric charges are transferred from the photoelectric conversion element to the floating diffusion layer in the pixels 230 and 240, and a voltage corresponding to the amount of electric charges is generated. The levels of the pixel signals Vout1 and Vout2 at this time are read out as signal levels.

Further, at the timing T6, the vertical drive unit 210 lowers the selection signals SEL1 and SEL2, and the system control unit 291 lowers the control signals SW12, SW14, SW17, SW22, SW24 and SW27. In the figure, driving during the period of timings T7 to T8 does not contribute to the reading of pixels 230 and 240.

The controls illustrated in FIGS. 9 and 10 are executed line by line in the SF mode. Although the solid-state image sensor 200 switches the mode to either the differential mode or the SF mode, the SF mode may not be set. In this case, the switch required for mode switching in the unit reading circuit 310 becomes unnecessary. In this case, the unit reading circuit 310 has, for example, a configuration in which load current sources 323 and 324 and switches 346 and 347 are added to the circuit shown in FIG. 16 of JP-A-2018-182496.

FIG. 11 is an example of an equivalent circuit of the pixel and unit reading circuit 310 in the differential mode according to the first embodiment of the present technology. The figure shows an equivalent circuit in the case where the pixel 230 is a read pixel and the pixel 240 is a reference pixel. In the figure, switches 331 to 347, tail current source 322, and load current source 323 are omitted. Further, the vertical current supply lines 62R and 62S are represented by a single vertical current supply line 62.

The reset transistors 233 and 243 on the read side and the reference side initialize the voltages of the floating diffusion layers 234 and 244 with a reference voltage corresponding to the reset voltage Vrst immediately before the end of exposure. _Let this reference voltage be V _fdr . Since the load current is supplied to the vertical reset input line 61R, a voltage drop occurs due to the wiring resistance in the vertical reset input line 61R, and the reference voltage V _fdr becomes a value corresponding to the voltage drop amount.

Then, the transfer transistor 232 on the reading side transfers an electric charge from the photoelectric conversion element 231 on the reading side to the floating diffusion layer 234 at the end of exposure, and generates a voltage corresponding to the amount of the electric charge as a signal voltage. _Let this signal voltage be V _fds .

The pair of amplification transistors 236 and 246 generate an output current I _out according to the difference between the reference voltage V _fdr and the signal voltage V _fds . The current mirror circuit including the pMOS transistors 311 and 312 outputs a pixel signal Vout having a voltage corresponding to the output current I _out from the vertical signal line 22S on the reading side.

In the above configuration, the charge-voltage conversion efficiency η of the differential amplifier circuit including the pixels 230 and 240 and the unit readout circuit 310 is expressed by, for example, the following equation.
η = e ⁻ / (−C _fd / Av + C _gd ) ・ ・ ・ Equation 1
In the above equation, e ⁻ indicates a signal charge. Av indicates the open loop gain of the differential amplifier circuit. C _gd is the overlap capacitance between the gate and drain of the amplification transistor 236. C _fd indicates the capacity of the floating diffusion layer. The unit of these volumes is, for example, microfarad (μF).

The open loop gain Av of Equation 1 is expressed by the following equation.
Av = gm ・ Rout _amp・ Rout _pMOS
/ (Rout _amp + Rout _pMOS ) ・ ・ ・ Equation 2
In the above equation, gm represents the transconductance of the amplification transistors 236, and the unit is, for example, Siemens (S). Rout _amp indicates the output resistance of the amplification transistor 236, and the unit is, for example, ohm (Ω). Rout _pMOS indicates the output resistance of the pMOS transistor 311 and the unit is, for example, ohm (Ω).

The overlap capacitance C _gd is smaller than the FD diffusion capacitance and the FD wiring capacitance, and C _fd , which is the sum of the gate capacitances of the amplification transistor 236, the transfer transistor 232, and the reset transistor 233. Further, from Equation 1, since C _fd is rebated by the open loop gain Av, the effective capacitance becomes small, and a high charge-voltage conversion efficiency η can be realized.

The pixels 230 and 240 for each row form a differential pair, and at the time of reading, the first row to the Mth row are read in order in the vertical direction. At this time, the distance from the current mirror circuit differs from line to line, and the wiring resistance of the vertical signal line 22S is small in the line close to the current mirror circuit, and large in the line far from the current mirror circuit. Therefore, the operating point of the amplification transistor 236 on the reading side is not uniformly determined in the vertical direction, and is set while maintaining the in-plane difference.

The transconductance gm, output resistance Rout _amp , and overlap capacitance C _{gd, which} are important in determining the conversion efficiency of the differential amplifier circuit, are bias-dependent, and the vertical signal line 22S determines the output current I _out . It's flowing. Therefore, a voltage drop always occurs due to the metal wiring resistance. Due to this voltage drop, the voltage of the drain of the amplification transistor 236 drops, and the drain-source voltage Vds _amp decreases.

Here, a comparative example in which the load current sources 323 and 324 are not arranged is assumed. In this comparative example, the output resistance Rout _amp becomes smaller due to the decrease in the drain-source voltage Vds _amp . When the output resistance Rout _amp becomes smaller, the open loop gain Av decreases as compared with Equation 2.

Further, since the signal voltage V _fds becomes lower as the exposure amount increases, the gate-drain voltage _Vgd of the amplification transistor 236 increases. This increase in the gate-drain voltage Vgd increases the overlap capacitance C _gd .

Due to the decrease in the open loop gain Av and the increase in the overlap capacitance C _gd described above, from Equation 1, in the comparative example, the charge-voltage conversion efficiency η decreases as the line is farther from the current mirror circuit. Therefore, in the comparative example, an in-plane difference in the charge-voltage conversion efficiency η occurs depending on the distance from the current mirror circuit, and in a bright imaging place, the difference is a pixel signal, which is observed as shading.

On the other hand, in the configuration in which the load current sources 323 and 324 are arranged, those current sources supply the load current I _load to the vertical reset input lines 61R and 61S. The farther from the current mirror circuit than the supply of this load current I _load, the greater the amount of voltage drop due to the wiring resistance of the vertical reset input lines 61R and 61S. Due to this voltage drop, the farther the line is from the current mirror circuit, the lower the voltage at the time of initialization of the floating diffusion layer (reference voltage V _fdr ). Due to this decrease in the reference voltage V _fdr , the difference from the signal voltage V _fds increases, and the output current I _out increases. Due to this increase in the output current I _out , the drain voltage of the pMOS transistor 311 decreases, and the drain-source voltage Vds _pMOS increases. The increase in the drain-source voltage Vds _pMOS increases the output resistance Rout _pMOS . When the output resistance Rout _pMOS becomes large, the open loop gain Av increases by that amount and the charge-voltage conversion efficiency η increases according to the equation 2.

In summary, the farther the line is from the current mirror circuit, the larger the amount of voltage drop due to the wiring resistance of the vertical signal line 22S, and the output resistance Rout _amp of the amplification transistor 236 decreases due to the voltage drop. On the other hand, due to the supply of the load current I _load, the farther the line is from the current mirror circuit, the larger the amount of voltage drop due to the wiring resistance of the vertical reset input line 61R, and the output resistance Rout _pMOS of the pMOS transistor 311 increases due to the voltage drop. Increase. As illustrated in Equations 1 and 2, the charge-voltage conversion efficiency η decreases as the output resistance Rout _amp decreases, and the charge-voltage conversion efficiency η increases as the output resistance Rout _pMOS increases. Further, as the overlap capacitance C _gd increases, the charge-voltage conversion efficiency η decreases.

Therefore, the decrease in the charge-voltage conversion efficiency η due to the decrease in the output resistance Rout _amp and the increase in the overlap capacitance C _gd can be offset by the increase in the charge-voltage conversion efficiency η due to the increase in the output resistance Rout _pMOS . As a result, it is possible to suppress the in-plane difference in the charge-voltage conversion efficiency η by adjusting the balance between the transconductance gm, the output resistance Rout _amp, and the overlap capacitance C _gd . As a result, shading can be suppressed and the image quality of the image data can be improved.

The wiring resistance per unit length of the vertical reset input line 61R is R _vpx , the wiring resistance per unit length of the vertical signal line 22S is R _vsl, and the wiring resistances are set to substantially the same value, for example. To. Here, "substantially the same" means that the two values are exactly the same, or that the difference between them is within a predetermined allowable value. Further, the unit length corresponds to the length between the node to which one of the two adjacent lines is connected and the node to which the other is connected on the vertical reset input line 61R.

If the open loop gain Av is increased by increasing the output resistance Route _pMOS by the amount that the overlap capacitance C _gd is increased, the in-plane difference in the charge-voltage conversion efficiency η can be improved. Therefore, it is not always necessary to adjust the voltage drop due to the wiring resistance of the vertical reset input line 61R and the voltage drop due to the wiring resistance of the vertical signal line 22S equally.

Further, the solid-state image sensor 200 amplifies the difference between the signals of the pair of adjacent pixels in the horizontal direction, but is not limited to this configuration, and the difference between the signals of the pair of adjacent pixels in the vertical direction. Can also be amplified. In this case, for example, a unit reading circuit 300 is arranged for each column, and differential amplification is performed with one of the odd-numbered row pixels and the even-numbered row of pixels as reference pixels and the other as read pixels.

FIG. 12 is a graph showing an example of the charge-voltage conversion efficiency for each row in the first embodiment of the present technology and the comparative example. In the figure, a is a graph showing an example of charge-voltage conversion efficiency for each row in a comparative example in which the load current sources 323 and 324 are not provided. In the figure, b is a graph showing an example of the charge-voltage conversion efficiency for each row in the first embodiment in which the load current sources 323 and 324 are provided. In the figure, the vertical axis shows the charge-voltage conversion efficiency, and the horizontal axis shows the number of pixels in the vertical direction. It is assumed that the larger the number of pixels in the vertical direction, the longer the distance from the current mirror circuit.

As illustrated in a in the figure, in the comparative example in which the load current sources 323 and 324 are not provided, the charge-voltage conversion efficiency decreases as the number of pixels in the vertical direction increases (that is, the line farther from the current mirror circuit). .. This is because the farther the line is from the current mirror circuit, the larger the amount of voltage drop due to the wiring resistance of the vertical signal line 22S, and the lower the output resistance Rout _amp of the amplification transistor 236 due to the voltage drop.

On the other hand, when the load current sources 323 and 324 are provided as illustrated in b in the figure, the charge-voltage conversion efficiency decreases as the number of pixels in the vertical direction increases (that is, the line farther from the current mirror circuit). However, the amount of decrease is smaller than that of the comparative example. This is because the farther the line is from the current mirror circuit, the larger the amount of voltage drop due to the wiring resistance of the vertical reset input line 61R, and the output resistance Rout _pMOS of the pMOS transistor 311 in the current mirror circuit increases due to the voltage drop. Because.

FIG. 13 is a diagram for explaining the saturation margin in the comparative example. In the comparative example in which the load current sources 323 and 324 are not provided, the drain-source voltage Vds _pMOS of the pMOS transistor 311 increases as the read line is farther from the current mirror circuit, and saturates at the farthest line. Let Vdsat1 be the drain-source voltage Vds _pMOS when reading a certain line. Further, the drain-source voltage Vds _amp of the amplification transistor 236 increases as the distance from the current mirror circuit increases, and saturates at the farthest row. Let the drain-source voltage Vds _amp in a row be Vdsat2.

Further, assuming that the threshold voltage of the amplification transistor 236 is Vth, the difference between the threshold voltage Vth and the gate-drain voltage Vgd of the amplification transistor 236 is set as the saturation margin. On the other hand, in the voltage range between the power supply voltage VDD and the common voltage _{V COM,} the drain - remaining voltage excluding the saturation margin source voltage Vdsat1 and Vdsat2 and amplifier transistor 236, is set as the saturation margin of the pMOS transistor 311 To.

FIG. 14 is a diagram for explaining a saturation margin in the first embodiment of the present technology. By providing the load current sources 323 and 324, the amount of voltage drop due to the wiring resistance of the vertical reset input line 61R increases as the line is farther from the current mirror circuit. Due to this voltage drop, the drain-source voltage Vds _pMOS of the pMOS transistor 311 increases. By increasing the drain-source voltage Vds _pMOS , the saturation margin of the pMOS transistor 311 can be increased as compared with the comparative example.

FIG. 15 is a flowchart showing an example of the operation of the solid-state image sensor 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing image data is executed.

The solid-state image sensor 200 selects a row, starts exposure of that row (step S901), and ends the exposure at the end of the exposure accumulation period (step S902). The solid-state image sensor 200 performs signal processing such as CDS processing on the pixel signal read from the row (step S903).

The solid-state image sensor 200 determines whether or not the differential mode is set (step S904). When the differential mode is set (step S904: Yes), the solid-state image sensor 200 determines whether or not the reading of all rows is completed (step S905). When the reading of all rows is not completed (step S905: No), the solid-state image sensor 200 replaces the read pixels with the reference pixels (step S906).

When the SF mode is set (step S904: No) and the reading of all columns is completed (step S905: Yes), the solid-state image sensor 200 determines whether or not the reading of all rows is completed (step S904: No). Step S907). When the reading of all lines is not completed (step S907: No), or after step S906, the solid-state image sensor 200 repeatedly executes the processes after step S901. On the other hand, when the reading of all the rows is completed (step S907: Yes), the solid-state image sensor 200 ends the operation for capturing the image data.

When a plurality of image data are captured in synchronization with the vertical synchronization signal, steps S901 to S907 are repeatedly executed in synchronization with the vertical synchronization signal.

As described above, according to the first embodiment of the present technology, since the load current source 324 supplies the load current to the vertical reset input line 61R, the reference voltage according to the amount of voltage drop due to the wiring resistance of the signal line. The floating diffusion layer can be initialized by. The voltage drop of the vertical reset input line 61R increases the charge-voltage conversion efficiency η, and the increase offsets the decrease in the charge-voltage conversion efficiency η due to the voltage drop of the vertical signal line 22S. As a result, it is possible to reduce the difference in charge-voltage conversion efficiency for each row, suppress shading, and improve the image quality of image data.

<2. Second Embodiment>
In the first embodiment described above, the wiring resistance per unit length of the vertical reset input line 61R wiring resistance per unit length of the R _vpx and vertical signal lines 22S sets the R _vsl to the same value Was there. However, in this configuration, the larger the voltage drop amount of the vertical signal line 22S, the larger the load current I _load required for suppressing shading, and the larger the power consumption. The second solid-state imaging device 200 according to the embodiment of the wiring resistance R _vpx the vertical reset input line 61R made larger than the wiring resistance R _vsl vertical signal line 22S, the first embodiment in that a power consumption is reduced It is different from the form of.

FIG. 16 is an example of an equivalent circuit of the pixel and unit reading circuit 310 in the second embodiment of the present technology. The wiring resistance R _vpx per unit length of the vertical reset input line 61R of the second embodiment is larger than the wiring resistance R _vsl per unit length of the vertical signal line 22S. For example, the wiring resistance R _vpx is set to about S (S is a real number larger than 1) times the wiring resistance R _vsl .

Further, _assuming that the load current required when the wiring resistance R _vpx is substantially the same as the wiring resistance R _vsl is I _load , the load current source 324 of the second embodiment has a _load of 1 / S times that of the I load. Supply current. The same applies to the load current source 323. As described above, in the second embodiment, the required load current can be smaller than that in the first embodiment, so that the power consumption can be reduced.

Thus, according to the second embodiment of the present technology, since the wiring resistance R _vpx the vertical reset input line 61R larger than the wiring resistance R _vsl vertical signal line 22S, required for that amount, suppressing shading The load current can be reduced. As a result, power consumption can be reduced.

<3. Third Embodiment>
In the first embodiment described above, the pMOS transistors 313 and 314 arranged in every two rows generate the reset voltage Vrst. However, in this configuration, as the number of columns increases, the number of pMOS transistors 313 and 314 to be arranged increases, and the circuit scale of the column readout circuit 300 increases. The solid-state image sensor 200 of the third embodiment is different from the first embodiment in that the number of pMOS transistors is reduced.

FIG. 17 is an example of an equivalent circuit of the pixel and unit reading circuit 310 in the differential mode according to the third embodiment of the present technology. The unit readout circuit 310 of the third embodiment is different from the first embodiment in that the pMOS transistors 313 and 314 are not provided. The vertical reset input line 61R is directly connected to the node to which the fixed bias voltage is applied as the reset voltage Vrst without passing through the pMOS transistor 314. The same applies to the vertical reset input line 61S. The reset voltage Vrst is supplied by, for example, an external circuit of the column reading circuit 300.

It should be noted that the second embodiment can also be applied to the solid-state image sensor 200 of the third embodiment.

As described above, in the third embodiment of the present technology, since the vertical reset input line 61R is directly connected to the node of the reset voltage Vrst, the pMOS transistor 314 becomes unnecessary. As a result, the number of pMOS transistors can be reduced and the circuit scale of the column readout circuit 300 can be reduced.

<4. Fourth Embodiment>
In the first embodiment described above, the load current sources 323 and 324 supply the load current to the vertical reset input lines 61R and 61S to cause a voltage drop, but in this configuration, the farther the line is from the current mirror circuit, the more the line becomes. The amount of voltage drop increases, and the reference voltage V _fdr decreases. Therefore, if the reference voltage V _fdr is too low, the driving force of the pixels 230 and 240 may be insufficient. The solid-state image sensor 200 of the fourth embodiment is different from the first embodiment in that the shortage of the driving force is compensated by the buffer.

FIG. 18 is an example of an equivalent circuit of the pixel and unit reading circuit 310 in the differential mode according to the fourth embodiment of the present technology. The pixel array unit 220 of the fourth embodiment is different from the first embodiment in that buffers 251 and 252 are further arranged for each row.

The buffer 251 is inserted between the node corresponding to the line on the vertical reset input line 61S and the reset transistor 233. The buffer 252 is inserted between the node corresponding to the line on the vertical reset input line 61R and the reset transistor 243. The buffers 251 and 252 amplify the voltage of the connected nodes on the vertical reset input lines 61R and 61S and supply them to the reset transistors 233 and 243, respectively. By amplifying the buffers 251 and 252, the reference voltage V _fdr can be increased and the driving force of the pixels 230 and 240 can be improved.

It should be noted that each of the second and third embodiments can be applied to the solid-state image sensor 200 of the fourth embodiment.

As described above, according to the fourth embodiment of the present technology, the buffers 251 and 252 amplify the voltage of the node on the vertical reset input lines 61R and 61S, so that the driving force of the pixel can be improved. ..

<5. Fifth Embodiment>
In the first embodiment described above, the diode-connected pMOS transistors 313 and 314 supplied the reset voltage Vrst. However, in this configuration, an appropriate reset voltage Vrst corresponding to the amount of voltage drop of the vertical signal line may not be supplied. The solid-state image sensor 200 of the fifth embodiment is different from the first embodiment in that the voltage drop amount is measured and the reset voltage Vrst corresponding to the measured value is supplied.

FIG. 19 is a circuit diagram showing a configuration example of the unit reading circuit 310 according to the fifth embodiment of the present technology. The unit reading circuit 310 of the fifth embodiment is different from the first embodiment in that the voltage drop measuring unit 351 and the bias voltage generating unit 352 are further arranged.

The voltage drop measuring unit 351 measures the voltage drop amount of each of the vertical signal lines 22R and 22S. For example, the voltage drop measuring unit 351 measures each of the voltage between the upper end and the lower end of the vertical signal line 22R and the voltage between the upper end and the lower end of the vertical signal line 22S as a voltage drop amount, and measures the measured values. Statistics (total or average) are supplied to the bias voltage generation unit 352.

Although the voltage drop measuring unit 351 measures the voltage drop amount of both the vertical signal lines 22R and 22S, it is also possible to measure only the voltage drop amount of one of the vertical signal lines 22R and 22S.

The bias voltage generation unit 352 generates a bias voltage according to the statistic of the measured value and supplies it to the gates of the pMOS transistors 313 and 314. As a result, an appropriate reset voltage Vrst according to the amount of voltage drop is supplied.

The bias voltage generation unit 352 supplies a bias voltage corresponding to the statistics of the measured values of both the vertical signal lines 22R and 22S to both the pMOS transistors 313 and 314, but the configuration is not limited to this. The bias voltage generation unit 352 can also supply the bias voltage corresponding to the measured value of the vertical signal line 22S to the pMOS transistor 313 and supply the bias voltage corresponding to the measured value of the vertical signal line 22R to the pMOS transistor 314.

It should be noted that each of the second to fourth embodiments can be applied to the solid-state image sensor 200 of the fifth embodiment.

As described above, according to the fifth embodiment of the present technology, since the bias voltage generation unit 352 generates the bias voltage according to the measured value of the voltage drop amount, the bias voltage is appropriate according to the voltage drop amount. Reset voltage Vrst can be generated.

<6. Application example to moving body>
The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure is realized as a device mounted on a moving body of any kind such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. You may.

FIG. 20 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving body control system to which the technique according to the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via the communication network 12001. In the example shown in FIG. 20, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

The drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 provides a driving force generator for generating the driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism for adjusting and a braking device for generating braking force of the vehicle.

The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, blinkers or fog lamps. In this case, the body system control unit 12020 may be input with radio waves transmitted from a portable device that substitutes for the key or signals of various switches. The body system control unit 12020 receives inputs of these radio waves or signals and controls a vehicle door lock device, a power window device, a lamp, and the like.

The vehicle outside information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle outside information detection unit 12030 causes the image pickup unit 12031 to capture an image of the outside of the vehicle and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as a person, a vehicle, an obstacle, a sign, or characters on the road surface based on the received image.

The imaging unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of the light received. The image pickup unit 12031 can output an electric signal as an image or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects the in-vehicle information. For example, a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing.

The microcomputer 12051 calculates the control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit. A control command can be output to 12010. For example, the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, and the like. It is possible to perform cooperative control for the purpose of.

Further, the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform coordinated control for the purpose of automatic driving that runs autonomously without depending on the operation.

Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the external information detection unit 12030, and performs cooperative control for the purpose of antiglare such as switching the high beam to the low beam. It can be carried out.

The audio image output unit 12052 transmits the output signal of at least one of the audio and the image to the output device capable of visually or audibly notifying the passenger of the vehicle or the outside of the vehicle. In the example of FIG. 20, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an onboard display and a heads-up display.

FIG. 21 is a diagram showing an example of the installation position of the imaging unit 12031.

In FIG. 21, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, 12105.

The imaging units 12101, 12102, 12103, 12104, 12105 are provided at positions such as, for example, the front nose, side mirrors, rear bumpers, back doors, and the upper part of the windshield in the vehicle interior of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100. The imaging units 12102 and 12103 provided in the side mirrors mainly acquire images of the side of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100. The imaging unit 12105 provided on the upper part of the windshield in the vehicle interior is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

Note that FIG. 21 shows an example of the photographing range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and the imaging range 12114 indicates the imaging range of the imaging units 12102 and 12103. The imaging range of the imaging unit 12104 provided on the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 as viewed from above can be obtained.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image pickup units 12101 to 12104 may be a stereo camera composed of a plurality of image pickup elements, or may be an image pickup element having pixels for phase difference detection.

For example, the microcomputer 12051 has a distance to each three-dimensional object within the imaging range 12111 to 12114 based on the distance information obtained from the imaging units 12101 to 12104, and a temporal change of this distance (relative velocity with respect to the vehicle 12100). By obtaining, it is possible to extract as the preceding vehicle a three-dimensional object that is the closest three-dimensional object on the traveling path of the vehicle 12100 and that travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or more). it can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in front of the preceding vehicle in advance, and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform coordinated control for the purpose of automatic driving or the like in which the vehicle travels autonomously without depending on the operation of the driver.

For example, the microcomputer 12051 converts three-dimensional object data related to a three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that can be seen by the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.

At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. Such pedestrian recognition includes, for example, a procedure for extracting feature points in an image captured by an imaging unit 12101 to 12104 as an infrared camera, and pattern matching processing for a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. It is done by the procedure to determine. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 outputs a square contour line for emphasizing the recognized pedestrian. The display unit 12062 is controlled so as to superimpose and display. Further, the audio image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.

The above is an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technique according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. Specifically, the imaging device 100 of FIG. 1 can be applied to the imaging unit 12031. By applying the technique according to the present disclosure to the imaging unit 12031, shading can be suppressed and a photographed image that is easier to see can be obtained, so that driver fatigue can be reduced.

It should be noted that the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention within the scope of claims have a corresponding relationship with each other. Similarly, the matters specifying the invention within the scope of claims and the matters in the embodiment of the present technology having the same name have a corresponding relationship with each other. However, the present technology is not limited to the embodiment, and can be embodied by applying various modifications to the embodiment without departing from the gist thereof.

Further, the processing procedure described in the above-described embodiment may be regarded as a method having these series of procedures, and as a program for causing a computer to execute these series of procedures or as a recording medium for storing the program. You may catch it. As the recording medium, for example, a CD (Compact Disc), MD (MiniDisc), DVD (Digital Versatile Disc), memory card, Blu-ray Disc (Blu-ray (registered trademark) Disc) and the like can be used.

It should be noted that the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.

The present technology can have the following configurations.
(1) A load current source that supplies a predetermined load current to a vertical reset input line connected to a node having a predetermined reset voltage, and
A pair of reset transistors that initialize a pair of stray diffusion layers with a reference voltage according to the amount of voltage drop due to the wiring resistance of the vertical reset input line.
A transfer transistor that transfers an electric charge from one of a pair of photoelectric conversion elements to one of the pair of floating diffusion layers and generates a voltage corresponding to the amount of the electric charge as a signal voltage.
A pair of amplification transistors that generate an output current according to the difference between the reference voltage and the signal voltage,
A solid-state image sensor including a current mirror circuit that outputs a pixel signal having a voltage corresponding to the output current from a vertical signal line.
(2) One of the pair of photoelectric conversion elements, one of the pair of floating diffusion layers, one of the pair of reset transistors, the transfer transistor, and one of the pair of amplification transistors are arranged in a predetermined direction. Placed on one of the pixels of
The other of the pair of photoelectric conversion elements, the other of the pair of floating diffusion layers, the other of the pair of reset transistors, and the other of the pair of amplification transistors are arranged on the other of the pair of pixels (1). The solid-state imaging device described.
(3) The solid-state image pickup device according to (1) or (2), further comprising a reset voltage supply transistor that lowers a predetermined power supply voltage and supplies the reset voltage to the vertical reset input line.
(4) The solid according to any one of (1) to (3), wherein the wiring resistance per unit length of the vertical reset input line is larger than the wiring resistance per unit length of the vertical signal line. Image sensor.
(5) The solid-state image sensor according to any one of (1) to (4), further comprising a buffer that amplifies the voltage of the vertical reset input line and supplies the voltage to each of the pair of reset transistors.
(6) A voltage drop measuring unit that measures the amount of voltage drop due to the wiring resistance of the vertical signal line and supplies the measured value, and
The solid-state image sensor according to any one of (1) to (5) above, further comprising a bias voltage generating unit that generates a bias voltage according to the measured value and supplies the bias voltage to the gate of the reset voltage supply transistor.
(7) When the differential mode is set, the control is such that after initializing the pair of floating diffusion layers, the electric charge is transferred from one of the pair of photoelectric conversion elements to one of the pair of floating diffusion layers. (1) The above (1) further includes a vertical drive unit that sequentially controls the transfer of electric charges from the other of the pair of photoelectric conversion elements to the other of the pair of floating diffusion layers after initializing the pair of floating diffusion layers. The solid-state imaging device according to any one of (6) to (6).
(8) The vertical drive unit initializes the pair of floating diffusion layers when the source follower mode is set, and then transfers the electric charge from each of the pair of photoelectric conversion elements to the pair of floating diffusion layers. The solid-state imaging device according to (7) above, which controls transfer.
(9) A load current source that supplies a predetermined load current to a vertical reset input line connected to a node having a predetermined reset voltage.
A pair of reset transistors that initialize a pair of stray diffusion layers with a reference voltage according to the amount of voltage drop due to the wiring resistance of the vertical reset input line.
A transfer transistor that transfers an electric charge from one of a pair of photoelectric conversion elements to one of the pair of floating diffusion layers and generates a voltage corresponding to the amount of the electric charge as a signal voltage.
A pair of amplification transistors that generate an output current according to the difference between the reference voltage and the signal voltage,
A current mirror circuit that outputs a pixel signal with a voltage corresponding to the output current from a vertical signal line, and
An image pickup apparatus including a signal processing unit that processes the pixel signal.
(10) A pair of reset transistors are connected to a node having a predetermined reset voltage, and a pair of stray diffusion layers are formed by a reference voltage according to the amount of voltage drop due to the wiring resistance of the vertical reset input line to which a predetermined load current is supplied. Initialization procedure to initialize and
A transfer procedure in which a transfer transistor transfers an electric charge from one of a pair of photoelectric conversion elements to one of the pair of floating diffusion layers to generate a voltage corresponding to the amount of the electric charge as a signal voltage.
An amplification procedure in which a pair of amplification transistors generate an output current according to the difference between the reference voltage and the signal voltage.
A method for controlling a solid-state image sensor, comprising an output procedure in which a current mirror circuit outputs a pixel signal having a voltage corresponding to the output current from a vertical signal line.

100 Image sensor 110 Optical unit 120 Digital signal processor 130 Display unit 140 Operation unit 150 Bus 160 Power supply unit 170 Recording unit 180 Frame memory 200 Solid-state image sensor 210 Vertical drive unit 220 Pixel array unit 230, 240 pixels 231, 241 Transistor conversion element 232 242 Transfer transistor 233, 243 Reset transistor 234, 244 Floating diffusion layer 235, 245 Selective transistor 236, 246 Amplification transistor 251, 252 Buffer 270 Column signal processor 271 ADC
272 Comparator 273 Counter 280 Output unit 291 System control unit 292 Horizontal drive unit 293 Data storage unit 294 Image processing unit 300 Column readout circuit 310 Unit readout circuit 311 to 314 pMOS transistor 321 to 322 Tail current source 323, 324 Load current source 331 ~ 347 Switch 351 Voltage drop measurement unit 352 Bias voltage generator 12031 Imaging unit

Claims (10)

1. A load current source that supplies a given load current to a vertical reset input line connected to a node with a given reset voltage,
   A pair of reset transistors that initialize a pair of stray diffusion layers with a reference voltage according to the amount of voltage drop due to the wiring resistance of the vertical reset input line.
   A transfer transistor that transfers an electric charge from one of a pair of photoelectric conversion elements to one of the pair of floating diffusion layers and generates a voltage corresponding to the amount of the electric charge as a signal voltage.
   A pair of amplification transistors that generate an output current according to the difference between the reference voltage and the signal voltage,
   A solid-state image sensor including a current mirror circuit that outputs a pixel signal having a voltage corresponding to the output current from a vertical signal line.
2. One of the pair of photoelectric conversion elements, one of the pair of floating diffusion layers, one of the pair of reset transistors, the transfer transistor, and one of the pair of amplification transistors are a pair of pixels arranged in a predetermined direction. Placed on one side,
   The first aspect of claim 1, wherein the other of the pair of photoelectric conversion elements, the other of the pair of floating diffusion layers, the other of the pair of reset transistors, and the other of the pair of amplification transistors are arranged on the other of the pair of pixels. Solid-state image sensor.
3. The solid-state image sensor according to claim 1, further comprising a reset voltage supply transistor that lowers a predetermined power supply voltage and supplies the reset voltage to the vertical reset input line.
4. The solid-state image sensor according to claim 1, wherein the wiring resistance per unit length of the vertical reset input line is larger than the wiring resistance per unit length of the vertical signal line.
5. The solid-state image sensor according to claim 1, further comprising a buffer that amplifies the voltage of the vertical reset input line and supplies the voltage to each of the pair of reset transistors.
6. A voltage drop measuring unit that measures the amount of voltage drop due to the wiring resistance of the vertical signal line and supplies the measured value,
   The solid-state image sensor according to claim 1, further comprising a bias voltage generating unit that generates a bias voltage according to the measured value and supplies the bias voltage to the gate of the reset voltage supply transistor.
7. When the differential mode is set, the control of initializing the pair of floating diffusion layers and then transferring the charge from one of the pair of photoelectric conversion elements to one of the pair of floating diffusion layers and the pair of The solid-state imaging according to claim 1, further comprising a vertical drive unit that sequentially controls the transfer of electric charges from the other of the pair of photoelectric conversion elements to the other of the pair of floating diffusion layers after initializing the floating diffusion layer. element.
8. When the source follower mode is set, the vertical drive unit initializes the pair of floating diffusion layers and then transfers the electric charge from each of the pair of photoelectric conversion elements to the pair of floating diffusion layers. 7. The solid-state image sensor according to claim 7.
9. A load current source that supplies a given load current to a vertical reset input line connected to a node with a given reset voltage,
   A pair of reset transistors that initialize a pair of stray diffusion layers with a reference voltage according to the amount of voltage drop due to the wiring resistance of the vertical reset input line.
   A transfer transistor that transfers an electric charge from one of a pair of photoelectric conversion elements to one of the pair of floating diffusion layers and generates a voltage corresponding to the amount of the electric charge as a signal voltage.
   A pair of amplification transistors that generate an output current according to the difference between the reference voltage and the signal voltage,
   A current mirror circuit that outputs a pixel signal with a voltage corresponding to the output current from a vertical signal line, and
   An image pickup apparatus including a signal processing unit that processes the pixel signal.
10. A pair of reset transistors are connected to a node with a predetermined reset voltage, and a pair of stray diffusion layers are initialized by a reference voltage according to the amount of voltage drop due to the wiring resistance of the vertical reset input line to which a predetermined load current is supplied. Initialization procedure and
    A transfer procedure in which a transfer transistor transfers an electric charge from one of a pair of photoelectric conversion elements to one of the pair of floating diffusion layers to generate a voltage corresponding to the amount of the electric charge as a signal voltage.
    An amplification procedure in which a pair of amplification transistors generate an output current according to the difference between the reference voltage and the signal voltage.
    A method for controlling a solid-state image sensor, comprising an output procedure in which a current mirror circuit outputs a pixel signal having a voltage corresponding to the output current from a vertical signal line.

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