WO2020235146A1

WO2020235146A1 - Solid-state imaging element, imaging device, and method for controlling solid-state imaging element

Info

Publication number: WO2020235146A1
Application number: PCT/JP2020/003958
Authority: WO
Inventors: 秀徳田畑
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2019-05-22
Filing date: 2020-02-03
Publication date: 2020-11-26
Also published as: JP2020191543A

Abstract

The purpose of the present invention is to improve image quality of image data in a solid-state imaging element that performs signal processing for each column.　Each of a plurality of analog output units increases or decreases a difference between a pair of analog input signals by a prescribed gain and outputs the resulting signal as an analog output signal. An analog/digital conversion unit converts the analog output signal of each of the plurality of analog output units to a digital signal. A correction processing unit corrects noise of the digital signal due to variation in the gain of each of the plurality of analog output units.

Description

Solid-state image sensor, image sensor, and control method for solid-state image sensor

This technology relates to a solid-state image sensor. More specifically, the present invention relates to a solid-state image sensor that converts an analog signal into a digital signal for each column, an image pickup device, and a control method for the solid-state image sensor.

Conventionally, for the purpose of reducing fixed pattern noise, CDS (Correlated Double Sampling) processing for obtaining the difference between the signal voltage according to the amount of received light and the reset voltage when the pixel is initialized has been performed on the solid-state image sensor. There is. For example, a solid-state imaging device is proposed that samples and holds an analog signal voltage and an analog reset voltage, converts the difference voltage into a current, and inputs it to an analog-to-digital converter (ADC). (See, for example, Patent Document 1). In this solid-state image sensor, in order to perform ADC for each column, a sample hold circuit, a resistance element that converts a voltage into a current with a constant gain, and an ADC are arranged for each column.

U.S. Pat. No. 9525837

In the above-mentioned conventional technique, fixed pattern noise is reduced by executing CDS processing. However, if the resistance element varies from column to column, the gain when converting voltage to current varies from column to column. Then, there is a problem that noise is generated in the digital signal after AD (Analog-to-Digital) conversion due to the variation in the gain, and the image quality of the image data is deteriorated.

This technology was created in view of such a situation, and aims to improve the image quality of image data in a solid-state image sensor that performs signal processing for each column.

The present technology has been made to solve the above-mentioned problems, and the first aspect thereof is a plurality of analogs that increase or decrease the difference between a pair of analog input signals by a predetermined gain and output them as analog output signals. The output unit, the analog digital conversion unit that converts the analog output signal of each of the plurality of analog output units into a digital signal, and the digital signal due to the variation in the gain of each of the plurality of analog output units. It is a solid-state image sensor including a correction processing unit for correcting noise, and a control method thereof. This has the effect of capturing image data consisting of digital signals with reduced noise.

Further, in the first aspect, a signal voltage corresponding to the amount of received light and a predetermined reset voltage are sampled and held in order, and the signal voltage and the reset voltage are used as the pair of analog input signals and a pair of output signal lines. A plurality of sample hold circuits that output via the above may be further provided. This has the effect that the difference between the signal voltage and the reset voltage is increased or decreased by the gain.

Further, in the first aspect, a sample hold horizontal connection circuit for opening and closing a path between the pair of output signal lines of each of the plurality of sample hold circuits may be further provided. This has the effect of suppressing noise due to variations in the offset of the sample hold circuit.

Further, in the first aspect, the correction processing unit is a gain correction value calculation circuit that calculates a correction value for correcting noise due to the variation in gain as a gain correction value when the path is in the closed state. An offset correction value calculation circuit that calculates the correction value as an offset correction value for correcting noise due to variations in the offsets of the plurality of sample hold circuits when the path is open, and the above calculation. A correction calculation circuit for correcting the noise by using the obtained gain correction value and the calculated offset correction value may be provided. This has the effect of capturing image data in which noise due to offset variation and noise due to gain variation are reduced.

Further, in the first aspect, the analog output signal may be a current signal in which the difference between the signal voltage and the reset voltage is increased or decreased by the gain. This has the effect of converting the current signal into a digital signal.

Further, in the first aspect, each of the plurality of sample hold circuits includes a pair of reset voltage sample hold circuits and a pair of signal voltage sample hold circuits, and one of the pair of reset voltage sample hold circuits is provided. The other may hold when the reset voltage is sampled, and the other may hold when one of the pair of signal voltage sample hold circuits samples the signal voltage. This brings about the effect that one of the pair of sample hold circuits samples the signal while the other holds the signal.

Further, in the first aspect, a pixel array unit in which a plurality of rows are arranged is further provided, and each of the plurality of rows is composed of a plurality of pixels arranged in a predetermined direction, which is half of the plurality of sample hold circuits. Is connected to an even number of the plurality of rows, and the rest of the plurality of sample hold circuits is connected to an odd number of the plurality of rows and is connected to the even number of rows, and the odd number of the sample hold circuits. The sample hold circuits connected to the row may be arranged alternately along the predetermined direction. This has the effect that two lines are AD-converted at the same time.

Further, in the first aspect thereof, a pixel array unit in which a plurality of rows are arranged is further provided, half of the plurality of sample hold circuits are arranged in the upper column signal processing circuit, and the rest are arranged in the lower column signal processing circuit. Arranged in a circuit, the upper column signal processing circuit is connected to one of the odd and even rows in the plurality of rows, and the lower column signal processing circuit is connected to the other of the odd and even rows. May be done. This has the effect that two lines are AD-converted at the same time.

Further, in the first aspect thereof, a pixel array unit in which a plurality of pixels are arranged is further provided, and the pixel array unit is arranged on a predetermined light receiving chip, and the plurality of sample hold circuits and the sample hold horizontal connection circuit are provided. And at least a part of the plurality of analog output units, the analog-digital conversion unit, and the correction processing unit may be arranged on a predetermined circuit chip. This has the effect of reducing the circuit scale per chip.

Further, in the first aspect, the pixel array portion in which a plurality of vertical signal lines connected to the sample hold circuits different from each other are wired, and the adjacent odd-numbered signal lines of the plurality of vertical signal lines are connected to each other. In addition to being connected, a vertical signal line addition circuit for connecting adjacent even-numbered signal lines among the plurality of vertical signal lines may be further provided. This has the effect of adding pixels in the horizontal direction.

Further, in the first aspect, a signal voltage corresponding to the amount of light received by the pixels and a predetermined reset voltage are sampled and held in order, and the signal voltage and the reset voltage are output via the pair of output signal lines. Select one of the pair of output signal lines of each of the plurality of sample hold circuits and the plurality of sample hold circuits, and set the voltage of the selected signal line as one of the pair of analog input signals. The other of the pair of analog input signals may further include a selection circuit that outputs to, and may have a predetermined reference voltage. This has the effect of reducing noise in the single-slope ADC.

Further, the second aspect of the present technology is a plurality of analog output units that increase or decrease the difference between a pair of analog input signals by a predetermined gain and output them as analog output signals, and the plurality of analog output units, respectively. The analog digital conversion unit that converts the analog output signal into a digital signal, the correction processing unit that corrects the noise of the digital signal due to the variation in the gain of each of the plurality of analog output units, and each of the digital signals. It is an image pickup apparatus including a digital signal processing circuit that performs predetermined image processing on the included image data. As a result, image data composed of digital signals with reduced noise is generated, and image processing is performed.

It is a block diagram which shows one configuration example of the image pickup apparatus in the 1st Embodiment of this technique. It is a block diagram which shows one structural example of the solid-state image sensor in 1st Embodiment of this technique. It is a circuit diagram which shows one configuration example of a pixel in 1st Embodiment of this technique. It is a block diagram which shows one structural example of the column signal processing circuit in 1st Embodiment of this technique. It is a circuit diagram which shows one configuration example of the switch in the 1st Embodiment of this technique. It is a block diagram which shows one structural example of the sample hold circuit and the voltage-current conversion part in the 1st Embodiment of this technique. It is a block diagram which shows one structural example of the correction processing part in 1st Embodiment of this technique. It is a graph which shows an example of the relationship between a test voltage and a digital signal in the 1st Embodiment of this technique. It is a figure which shows an example of the offset correction value and the gain correction value in the 1st Embodiment of this technique. It is a timing chart which shows an example of the operation of the solid-state image sensor in the 1st Embodiment of this technique. It is a graph for demonstrating the effect of the correction in the 1st Embodiment of this technique. It is a flowchart which shows an example of the operation of the solid-state image sensor in 1st Embodiment of this technique. It is a flowchart which shows an example of the gain correction value calculation processing in 1st Embodiment of this technique. It is a flowchart which shows an example of the offset correction value calculation process in 1st Embodiment of this technique. It is a block diagram which shows one structural example of the sample hold circuit and the voltage-current conversion part in the modification of 1st Embodiment of this technique. It is a block diagram which shows one configuration example of the reset voltage sample hold circuit in the modification of the 1st Embodiment of this technique. It is a block diagram which shows one configuration example of the signal voltage sample hold circuit in the modification of the 1st Embodiment of this technique. It is a block diagram which shows one structural example of the solid-state image pickup device in the 2nd Embodiment of this technique. It is a block diagram which shows one configuration example of the column signal processing circuit in the 2nd Embodiment of this technique. It is a block diagram which shows one structural example of the solid-state image sensor in the 3rd Embodiment of this technique. It is a figure which shows an example of the laminated structure of the solid-state image sensor in 4th Embodiment of this technique. It is a block diagram which shows one structural example of the solid-state image sensor in 4th Embodiment of this technique. It is a block diagram which shows one structural example of the column signal processing circuit in 5th Embodiment of this technique. FIG. 5 is a circuit diagram showing a configuration example of a VSL (Vertical Signal Line) adder circuit and an SH (Sample Hold) horizontal connection circuit according to a fifth embodiment of the present technology. It is a circuit diagram which shows the state of the VSL addition circuit and SH horizontal connection circuit at the time of connecting a vertical signal line in 5th Embodiment of this technique. It is a circuit diagram which shows the state of the VSL addition circuit and SH horizontal connection circuit when the vertical signal line is not connected in the 5th Embodiment of this technique. It is a block diagram which shows one configuration example of the column signal processing circuit in the 6th Embodiment of this technique. It is a block diagram which shows one structural example of the analog-digital conversion part in the 6th Embodiment of this technique. It is a block diagram which shows the schematic configuration example of a vehicle control system. It is explanatory drawing which shows an example of the installation position of the imaging unit.

Hereinafter, embodiments for carrying out the present technology (hereinafter referred to as embodiments) will be described. The explanation will be given in the following order.
1. 1. First Embodiment (Example of correcting noise due to gain variation)
2. 2. Second embodiment (example of correcting noise due to gain variation and reading two lines at the same time)
3. 3. Third embodiment (example of correcting noise due to gain variation and reading from the upper and lower column signal processing circuits)
4. Fourth Embodiment (Example of correcting noise due to gain variation in a laminated structure)
5. Fifth Embodiment (Example of adding pixels and correcting noise due to gain variation)
6. Sixth Embodiment (Example of correcting noise due to gain variation of a single slope type ADC)
7. Application example to mobile

<1. First Embodiment>
[Configuration example of imaging device]
FIG. 1 is a block diagram showing a configuration example of the image pickup apparatus 100 according to the first embodiment of the present technology. The image pickup device 100 is a device for capturing image data, and includes an optical unit 110, a solid-state image sensor 200, and a DSP (Digital Signal Processing) circuit 120. Further, the image pickup apparatus 100 includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. As the image pickup device 100, for example, in addition to a digital camera such as a digital still camera, a smartphone having an image pickup function, a personal computer, an in-vehicle camera, or the like is assumed.

The optical unit 110 collects the light from the subject and guides it to the solid-state image sensor 200. The solid-state image sensor 200 generates image data by photoelectric conversion in synchronization with the vertical synchronization signal XVS. Here, the vertical synchronization signal XVS is a periodic signal having a predetermined frequency indicating the timing of imaging. The solid-state image sensor 200 supplies the generated image data to the DSP circuit 120 via the signal line 209.

The DSP circuit 120 executes predetermined image processing on the image data from the solid-state image sensor 200. The DSP circuit 120 outputs the processed image data to the frame memory 160 or the like via the bus 150. The DSP circuit 120 is an example of the digital signal processing circuit described in the claims.

The display unit 130 displays image data. As the display unit 130, for example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed. The operation unit 140 generates an operation signal according to the operation of the user.

The bus 150 is a common route for the optical unit 110, the solid-state image sensor 200, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170, and the power supply unit 180 to exchange data with each other.

The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the solid-state image sensor 200, the DSP circuit 120, the display unit 130, and the like.

[Structure example of solid-state image sensor]
FIG. 2 is a block diagram showing a configuration example of the solid-state image sensor 200 according to the first embodiment of the present technology. The solid-state image sensor 200 includes a vertical scanning circuit 210, a timing control circuit 220, a pixel array unit 230, a column signal processing circuit 300, a horizontal scanning circuit 250, a test voltage generating unit 260, and a correction processing unit 270. Also, these circuits are arranged, for example, on a single semiconductor chip.

Further, in the pixel array unit 230, a plurality of pixels 240 are arranged in a two-dimensional grid pattern. Hereinafter, a set of pixels 240 arranged in a predetermined horizontal direction is referred to as a "row", and a set of pixels 240 arranged in a direction perpendicular to the horizontal direction is referred to as a "column".

The timing control circuit 220 controls the operation timing of the vertical scanning circuit 210, the column signal processing circuit 300, the correction processing unit 270, and the like in synchronization with the vertical synchronization signal XVS.

The vertical scanning circuit 210 selects and drives rows in order to output an analog pixel signal. The pixel 240 generates a pixel signal by photoelectric conversion under the control of the vertical scanning circuit 210. Each of the pixels 240 outputs a pixel signal to the column signal processing circuit 300.

The test voltage generation unit 260 generates a predetermined test voltage according to the mode signal MODE from the DSP circuit 120, and supplies the signal of that voltage to the column signal processing circuit 300 as a test signal.

Here, the mode signal MODE is a signal instructing the solid-state image sensor 200 to use one of a plurality of modes. These modes include a calibration mode and a normal imaging mode. The calibration mode is a mode in which the column signal processing circuit 300 calculates a correction value for correcting noise. The cause of noise generation and the calculation method of the correction value will be described later. On the other hand, the normal imaging mode is a mode for capturing image data while correcting noise using the calculated correction value.

When the calibration mode is set, the test voltage generator 260 generates a test signal by DA (Digital to Analog) conversion or the like. A DAC (Digital to Analog Converter) or the like is used as the test voltage generating unit 260. Further, the timing control circuit 220 stops the vertical scanning circuit 210, and the correction processing unit 270 calculates the correction value.

On the other hand, when the normal imaging mode is set, the test voltage generating unit 260 does not generate a test signal, and the timing control circuit 220 drives the line to the vertical scanning circuit 210. Further, the correction processing unit 270 corrects the noise by using the correction value.

The column signal processing circuit 300 performs signal processing such as CDS processing and AD conversion processing on the pixel signal for each column. The column signal processing circuit 300 supplies the digital signal after signal processing to the correction processing unit 270.

The correction processing unit 270 calculates a correction value when the calibration mode is set, and corrects the digital signal using the correction value when the normal imaging mode is set. The correction processing unit 270 outputs the image data in which the corrected digital signals are arranged to the DSP circuit 120 via the signal line 209.

[Pixel configuration example]
FIG. 3 is a circuit diagram showing a configuration example of the pixel 240 according to the first embodiment of the present technology. The pixel 240 includes a photoelectric conversion element 241 and a transfer switch 242 and an amplifier circuit 243.

The photoelectric conversion element 241 converts the incident light into an electric charge.

The transfer switch 242 transfers the electric charge from the photoelectric conversion element 241 to the floating diffusion layer (not shown) under the control of the vertical scanning circuit 210.

The amplifier circuit 243 amplifies the voltage according to the amount of electric charge of the floating diffusion layer. The amplifier circuit 243 outputs the amplified signal as a pixel signal to the column signal processing circuit 300 via the vertical signal line 249.

The vertical signal line 249 is wired in the pixel array unit 230 in the vertical direction for each row. When the number of columns is N (N is an integer of 2 or more), N vertical signal lines 249 are wired. Also, each of the pixels 240 in the row is commonly connected to the corresponding vertical signal line 249.

[Configuration example of column signal processing circuit]
FIG. 4 is a block diagram showing a configuration example of the column signal processing circuit 300 according to the first embodiment of the present technology. The column signal processing circuit 300 includes a plurality of multiplexers 310, a plurality of current sources 320, and a VSL horizontal connection circuit 330. Further, the column signal processing circuit 300 further includes a plurality of sample hold circuits 400, an SH horizontal connection circuit 350, a plurality of voltage / current conversion units 365, an analog-digital conversion unit 370, and an output unit 375. Each of the multiplexer 310, the current source 320, the sample hold circuit 400, and the voltage-current converter 365 is arranged in a row. When the number of columns is N, the multiplexer 310, the current source 320, the sample hold circuit 400, and the voltage-current converter 365 are arranged by N each.

Further, the VSL horizontal connection circuit 330 includes a plurality of switches 331. The SH horizontal connection circuit 350 includes a plurality of switches 351 and a plurality of switches 352. The analog-to-digital conversion unit 370 includes a plurality of current modes ADC 371. Each of the

switches

331, 351 and 352 is arranged in each row except the last row. When the number of columns is N, N-1

switches

331, 351 and 352 are arranged. The current mode ADC 371 is arranged for each row, and when the number of rows is N, N is arranged at a time.

The multiplexer 310 selects one of the pixel signal V _vsl from the vertical signal line 249 of the corresponding row and the test signal V _test from the test voltage generator 260 according to the control signal SWt from the timing control circuit 220. is there. The timing control circuit 220 causes the multiplexer 310 to select the test signal V _test by the control signal SWt in the calibration mode. On the other hand, in the normal imaging mode, the timing control circuit 220 causes the multiplexer 310 to select the pixel signal V _vsl by the control signal SWt. The multiplexer 310 feeds the selected signal through the current source 320 to the corresponding sample hold circuit 400. The signal line connected to the output of the multiplexer 310 is also a vertical signal line 249.

The current source 320 supplies a constant constant current. As the current source 320, for example, a MOS (Metal Oxide Semiconductor) transistor is used.

The VSL horizontal connection circuit 330 connects N vertical signal lines 249 to each other according to the control signal SWvc from the timing control circuit 220. The nth switch 331 (n is an integer of 1 to N-1) opens and closes the path between the nth vertical signal line 249 and the n + 1th vertical signal line 249. The timing control circuit 220 controls the switches 331 in all rows to the closed state by the control signal SWvc in the calibration mode. As a result, N vertical signal lines 249 are connected horizontally, and noise due to variations in the MOS transistors of the current source 320 can be suppressed. By suppressing this noise, the correction accuracy can be improved. On the other hand, in the normal imaging mode, the timing control circuit 220 controls the switches 331 in all rows to the open state by the control signal SWvc.

The sample hold circuit 400 holds the reset voltage and the signal voltage of the pixel signal V _vsl of the corresponding column in order, and outputs those voltages to the corresponding voltage-current converter 365 via the

output signal lines

408 and 409. It is a thing. N lines of each of the

output signal lines

408 and 409 are wired. Here, the reset voltage is the voltage of the pixel signal V _vsl when the floating diffusion layer in the pixel 240 is initialized. The signal voltage is the voltage of the pixel signal V _vsl according to the amount of light received by the pixel 240.

The SH horizontal connection circuit 350 connects N pairs of

output signal lines

408 and 409 to each other according to the control signals SWs. The nth switch 351 opens and closes the path between the nth output signal line 408 and the n + 1th output signal line 408. The nth switch 352 opens and closes the path between the nth output signal line 409 and the n + 1th output signal line 409. The timing control circuit 220 controls the

switches

351 and 352 in all rows in the closed state by the control signals SWs in the calibration mode. As a result, N pairs of

output signal lines

408 and 409 are horizontally connected. On the other hand, in the normal imaging mode, the timing control circuit 220 controls the

switches

351 and 352 in all rows to the open state by the control signals SWs.

The voltage-current conversion unit 365 amplifies the difference between the pair of analog input signals with a predetermined gain and outputs the difference as an analog output signal. The reset voltage and signal voltage from the corresponding sample hold circuit 400 are input to the voltage-current conversion unit 365 as a pair of analog input signals. The voltage-current converter 365 converts these analog input signals (that is, voltage) into current signals whose difference is increased or decreased. The voltage-current converter 365 supplies the generated current signal as an analog output signal to the corresponding current mode ADC.

The voltage-current conversion unit 365 is an example of the analog output unit described in the claims.

The current mode ADC 371 converts the analog output signal (that is, the current signal) from the voltage-current converter 365 into the digital signal Dout. As the current mode ADC 371, for example, a delta sigma ADC is used. The current mode ADC 371 supplies a digital signal to the output unit 375 under the control of the horizontal scanning circuit 250.

The output unit 375 supplies each of the digital signal Douts to the correction processing unit 270.

FIG. 5 is a circuit diagram showing a configuration example of the switch 351 according to the first embodiment of the present technology. In the figure, a is a circuit diagram of a switch 351 when an nMOS (n-channel MOS) transistor and a pMOS (p-channel MOS) transistor are used. Reference numeral b in the figure is a circuit diagram of the switch 351 when an nMOS transistor is used. Reference numeral c in the figure is a circuit diagram of the switch 351 when a pMOS transistor is used.

As illustrated in a in the figure, when the nMOS transistor 362 and the pMOS transistor 363 are used, the inverter 361 is further arranged. The nMOS transistor 362 and the pMOS transistor 363 are inserted in parallel in the path to be opened and closed. The inverter 361 inverts the control signals SWs and supplies them to the gate of the pMOS transistor 363. Further, control signals SWs are input to the gate of the nMOS transistor 362.

Further, as illustrated in b in the figure, only the nMOS transistor 362 can be used. As illustrated in c in the figure, only the pMOS transistor 363 can be used.

Switches other than switch 351 (switches 331 and 352) can also be realized by using nMOS transistors and pMOS transistors in the same manner as switch 351.

[Configuration example of sample hold circuit and voltage / current converter]
FIG. 6 is a block diagram showing a configuration example of the sample hold circuit 400 and the voltage / current conversion unit 365 according to the first embodiment of the present technology. The sample hold circuit 400 includes a reset voltage sample hold circuit 410 and a signal voltage sample hold circuit 420. Further, the voltage-current conversion unit 365 includes a current source 366, a resistor 367, and

nMOS transistors

368 and 369.

The reset voltage sample hold circuit 410 samples and holds the reset voltage. The reset voltage sample hold circuit 410 includes

switches

411, 413 and 414, a capacitor 412, and an amplifier 415.

The switch 411 opens and closes the path between the vertical signal line 249 and the capacitor 412 according to the control signal SW11 from the timing control circuit 220.

The capacitor 412 is inserted between the switch 411 and the inverting input terminal (-) of the amplifier 415.

The switch 413 opens and closes the connection point of the switch 411 and the capacitor 412 and the connection point of the current source 366 and the resistor 367 according to the control signal SW12 from the timing control circuit 220.

The switch 414 opens and closes the path between the inverting input terminal (-) of the amplifier 415 and its output terminal according to the control signal SW13 from the timing control circuit 220.

The amplifier 415 amplifies the difference between one end of the capacitor 412 and the ground voltage. The output terminal of this amplifier 415 is connected to the gate of the nMOS transistor 369. The signal line between the switch 413 and the voltage-current conversion unit 365 corresponds to the output signal line 409, and this signal line is horizontally connected.

The signal voltage sample hold circuit 420 samples and holds the signal voltage. The signal voltage sample hold circuit 420 includes

switches

421, 423 and 424, a capacitor 422 and an amplifier 425.

The connection configuration of the elements in the signal voltage sample hold circuit 420 is the same as that of the reset voltage sample hold circuit 410. However, one end of the switch 423 is connected to the connection point of the resistor 367 and the nMOS transistor 368. Further, the output terminal of the amplifier 425 is connected to the gate of the nMOS transistor 368. Further, the signal line between the switch 423 and the voltage-current conversion unit 365 corresponds to the output signal line 408, and this signal line is horizontally connected.

In the voltage-current conversion unit 365, the current source 366, the resistor 367, and the nMOS transistor 368 are connected in series between the power supply and the analog-to-digital conversion unit 370. Also, the drain of the nMOS transistor 369 is connected to the connection point of the current source 366 and the resistor 367, and the source is grounded.

The timing control circuit 220 controls the

switches

414 and 424 to be in the closed state and puts the

amplifiers

415 and 425 in the auto-zero state before sampling the reset voltage.

Then, the timing control circuit 220 closes only the switch 411 and opens the remaining switches when the pixels are initialized. This samples the reset voltage.

Next, the timing control circuit 220 closes only the switch 421 and opens the remaining switches at the end of the exposure. This samples the signal voltage.

Then, the timing control circuit 220 closes the

switches

413 and 423 and opens the remaining switches within the AD period. As a result, the reset voltage and the signal voltage are maintained, and the

amplifiers

415 and 425 output these voltages as a pair of analog input signals.

The voltage-current conversion unit 365 converts a pair of analog input signals (reset voltage and signal voltage) into a current signal I _out whose difference is increased or decreased, and outputs the analog output signal to the analog-digital conversion unit 370. That is, CDS processing and voltage-current conversion processing are performed.

_Assuming that the reset voltage is V _vslp and the signal voltage is V _vsls , the current signal (that is, analog output signal) I _out is expressed by the following equation.

I _out = G × (V _vslp- V _vsls ) + Ofs = G × V _in + Ofs
In the above equation, G is a gain proportional to the reciprocal of the resistance value of the resistor 367, and the unit is, for example, volt (A / V) per ampere. Ofs is the offset generated by the sample and hold of the sample hold circuit 400, and the unit is, for example, amperes (A). The gain G and offset Ofs for each column may vary. V _in is the pixel signal after CDS processing unit is, for example, bolts (V).

[Configuration example of correction processing unit]
FIG. 7 is a block diagram showing a configuration example of the correction processing unit 270 according to the first embodiment of the present technology. The correction processing unit 270 includes a demultiplexer 271, a correction value calculation circuit 280, and a correction calculation circuit 290.

The demultiplexer 271 outputs a digital signal from the column signal processing circuit 300 to either the correction value calculation circuit 280 or the correction calculation circuit 290 according to the mode signal MODE. When the calibration mode is set, the demultiplexer 271 outputs the digital signal to the correction value calculation circuit 280, and outputs the digital signal to the correction calculation circuit 290 when the normal imaging mode is set.

The correction value calculation circuit 280 calculates a correction value for correcting noise due to variations in gain G and offset Ofs for each column. The correction value calculation circuit 280 includes a demultiplexer 281, an offset correction value calculation circuit 282, a gain correction value calculation circuit 283, and a correction value holding unit 284.

The demultiplexer 281 outputs a digital signal from the demultiplexer 271 to either the offset correction value calculation circuit 282 or the gain correction value calculation circuit 283 according to the control signals SWs from the timing control circuit 220.

The offset correction value calculation circuit 282 calculates for each of the columns using a correction value for correcting noise due to variation in offset Ofs for each column as an offset correction value when the SH horizontal connection circuit 350 is not horizontally connected. It is a thing. The noise due to the offset Ofs appears as vertical stripe-shaped random noise in the image data when AD conversion is performed for each column. The offset correction value calculation circuit 282 causes the correction value holding unit 284 to hold each of the calculated offset correction values.

The gain correction value calculation circuit 283 calculates for each of the columns using a correction value for correcting noise due to variation in gain G for each column as a gain correction value when the SH horizontal connection circuit 350 is horizontally connected. Is. The noise due to this gain appears as vertical stripe-shaped random noise in the image data when AD conversion is performed for each column. The gain correction value calculation circuit 283 causes the correction value holding unit 284 to hold each of the calculated gain correction values.

The correction value holding unit 284 holds the offset correction value and the gain correction value for each column. When the number of columns is N, N offset correction values and N gain correction values are held.

The correction calculation circuit 290 uses the offset correction value and the gain correction value to correct the noise of the digital signal due to the variation in the offset and the gain. The correction calculation circuit 290 includes a line buffer 291 and a subtractor 292 and a multiplier 293.

The line buffer 291 holds a digital signal for at least one line. The line buffer 291 supplies a plurality of held digital signals to the subtractor 292 in order.

The subtractor 292 subtracts the offset correction value of the corresponding column from the digital signal. The subtractor 292 supplies the subtracted digital signal to the multiplier 293. The multiplier 293 multiplies the digital signal by the gain correction value of the corresponding column. The multiplier 293 supplies the multiplied digital signal to the DSP circuit 120.

The operation of the solid-state image sensor 200 in the calibration mode will be described. When the calibration mode is set, the timing control circuit 220 controls the column signal processing circuit 300 to horizontally connect the vertical signal line 249 and the

output signal lines

408 and 409, respectively. Further, the test voltage generation unit 260 supplies the black level VL, which is the level when the light is shielded, as the test voltage. Then, the column signal processing circuit 300 performs AD conversion of the current signal I _out for M (M is an integer) line in order. Further, the timing control circuit 220 controls the demultiplexer 281 to output a digital signal to the gain correction value calculation circuit 283.

When the AD conversion of all lines for the black level VL is completed, the test voltage generation unit 260 supplies the white level VH, which is a predetermined level different from the black level (for example, the level at the highest brightness), as the test voltage. Then, the column signal processing circuit 300 performs AD conversion of M rows in order. The gain correction value calculation circuit 283 calculates the gain correction value for each column from the digital signal at the black level VL and the digital signal at the white level VH.

The calculation method of this gain correction value will be explained. The horizontal connection of the

output signal lines

408 and 409 suppresses random noise caused by offset variation. Therefore, the gain correction value calculation circuit 283 can calculate the gain correction value from those digital signals.

When the black level VL is applied, M digital signals are acquired for each of the N rows. The average value of the nth column at this time is defined as the column average value bl _{gain -n} . Further, when the white level VH is applied, M digital signals are acquired for each of the N rows. The average value of the nth column at this time is defined as the column average value vh _{gain -n} . Further, the average value of the column mean values vl _{gain-1 to} vl _gain-N is defined as the line mean value vl _gain-AV , and the average value of the column mean values vh _{gain-1 to} vh _gain-N is the line mean value vh _gain-AV. And. At this time, the gain correction value c _gain-n in the nth column is calculated by the following equation.
c _gain-n = (vh _gain-AV -vl _gain-AV ) / (vh _gain-n -vl _gain-n ) ... Equation 1

Next, the timing control circuit 220 controls the column signal processing circuit 300 to release the horizontal connection with the

output signal lines

408 and 409, respectively. Further, the test voltage generation unit 260 supplies the black level VL as a test voltage. Then, the column signal processing circuit 300 performs AD conversion of M rows in order. Further, the timing control circuit 220 controls the demultiplexer 281 to output a digital signal to the offset correction value calculation circuit 282. The offset correction value calculation circuit 282 calculates the offset correction value for each column.

When the horizontal connection of the

output signal lines

408 and 409 is released, random noise is generated due to the variation in gain and the variation in offset. Since the gain correction value has already been calculated, the gain correction value calculation circuit 283 can calculate the offset correction value by eliminating the influence of random noise due to the variation in gain by the gain correction value.

Let the average value of the samples in the nth column be the column average value _{bl of s-n} . Further, the average value of vl of s _{-1 to} vl of s _-N is defined as the line average value vl of s _-AV . At this time, the offset correction value c of s _-n in the nth column is calculated by the following formula.
c ofs _-n = vl ofs _-AV -vl ofs _-n × c _gain-n・・・ Equation 2

FIG. 8 is a graph showing an example of the relationship between the test voltage and the digital signal in the first embodiment of the present technology. The horizontal axis in the figure is a test voltage, and the vertical axis in the figure is a digital signal obtained by AD-converting the current signal I _out corresponding to the test voltage. The solid line in the figure is a straight line showing the relationship between the test voltage and the column average value of the nth column, and the dotted line is a straight line showing the relationship between the test voltage and the line average value.

As illustrated in the figure, the straight line (solid line) in a certain column may not match the straight line (dotted line) of the average value. Let lv _gain-n be the column mean value of the nth column when the black level VL is applied, and vh _gain-n be the column mean value of the nth column when the white level VH is applied. Further, the line average value vr _gain-AV when the black level VL is applied and the line average value vh _gain-AV when the white level VH is applied are used. In this case, the ratio of the difference between the column mean values vh _gain-n and vl _{gain-n and} the difference between the line mean values vh _gain-AV and vl _gain-AV is used as a gain correction value for correcting the gain variation. Calculated by Equation 1.

Here, if the correction value is calculated and the SH horizontal connection circuit 350 is not used for horizontal connection, the random noise due to the gain and the random noise due to the offset cannot be separated, and the correction accuracy due to the correction value is lowered. There is a risk of On the other hand, in the configuration in which the SH horizontal connection circuit 350 is used for horizontal connection, random noise due to offset can be suppressed, so that an accurate gain correction value can be calculated. Further, since the horizontal connection by the SH horizontal connection circuit 350 is released and the offset correction value is also calculated, the correction accuracy by the gain correction value can be improved without lowering the correction accuracy by the offset correction value.

FIG. 9 is a diagram showing an example of an offset correction value and a gain correction value according to the first embodiment of the present technology. As illustrated in the figure, the correction value holding unit 284 holds the offset correction value and the gain correction value of the column for each column address which is the address assigned to the column. For example, the offset correction value c of s _-1 and the gain correction value c _gain-1 are held in association with the column address Y1. Further, the offset correction value c of s _-2 and the gain correction value c _gain-2 are held in association with the column address Y2.

FIG. 10 is a timing chart showing an example of the operation of the solid-state image sensor 200 according to the first embodiment of the present technology. It is assumed that the solid-state image sensor 200 shifts to the calibration mode at timing T0.

The timing control circuit 220 controls the corresponding switches in the ON state by the control signals SWvc and SWs, and connects the vertical signal line 249 and the

output signal lines

408 and 409 of the sample hold circuit 400 horizontally, respectively.

Further, the test voltage generation unit 260 supplies the black level VL as the test voltage. Then, the column signal processing circuit 300 performs AD conversion of M rows in order in synchronization with the vertical synchronization signal XVS.

Then, at the timing T1, the test voltage generation unit 260 supplies the white level VH as the test voltage. The column signal processing circuit 300 performs AD conversion of M rows in order in synchronization with the vertical synchronization signal XVS. The correction processing unit 270 calculates the gain correction value for each column from the digital signal at the black level VL and the digital signal at the white level VH by Equation 1.

Next, at the timing T2, the timing control circuit 220 controls the corresponding switch to the off state by the control signals SWs, and releases the horizontal connection of the 400

output signal lines

408 and 409 of the sample hold circuit. The test voltage generation unit 260 supplies the black level VL as a test voltage. The column signal processing circuit 300 performs AD conversion of M rows in order in synchronization with the vertical synchronization signal XVS. The correction processing unit 270 calculates an offset correction value for each column from the digital signal and the gain correction value according to Equation 2.

At timing T3, the solid-state image sensor 200 shifts to the normal image pickup mode. The timing control circuit 220 controls the corresponding switches to the off state by the control signals SWvc and SWs, and releases the horizontal connection between the vertical signal line 249 and the

output signal lines

408 and 409 of the sample hold circuit 400, respectively. The correction processing unit 270 performs a digital signal correction calculation using the offset correction value and the gain correction value.

FIG. 11 is a graph for explaining the effect of correction in the first embodiment of the present technology. In the figure, a is a graph showing an example of the relationship between analog gain and random noise. In the figure, b is a graph showing an example of the relationship between the dynamic range and the analog gain. In the figure, c is a graph showing an example of the relationship between random noise and analog gain per unit dynamic range.

The vertical axis of a in the figure is input-converted random noise. The horizontal axis is an analog gain, which corresponds to the gain G when converting a voltage into a current. In the figure, the vertical axis of b is the dynamic range, and the horizontal axis is the analog gain. In the figure, the vertical axis of c is random noise per unit dynamic range, and the horizontal axis is analog gain. Further, the solid lines a and c in the figure show the locus when the gain correction value and the offset correction value are corrected, and the alternate long and short dash line shows the locus when the correction is not performed.

As illustrated in a in the figure, the effect of reducing random noise becomes greater as the analog gain becomes larger by performing the correction. Further, as illustrated in b in the figure, generally, the larger the analog gain, the narrower the dynamic range. Therefore, as illustrated in c in the figure, the effect of reducing random noise per unit dynamic range becomes large, especially when the analog gain is large.

[Operation example of solid-state image sensor]
FIG. 12 is a flowchart showing an example of the operation of the solid-state image sensor 200 according to the first embodiment of the present technology. This operation is started, for example, when the solid-state image sensor 200 is turned on.

The solid-state image sensor 200 determines whether or not the calibration mode has been set (step S901). When the calibration mode is set (step S901: Yes), the timing control circuit 220 in the solid-state image sensor 200 switches the input destination of the column signal processing circuit 300 from the pixel 240 to the test voltage generation unit 260 (step S902). ). Further, the timing control circuit 220 horizontally connects the vertical signal lines 249 (step S903), and executes a gain correction value calculation process for calculating the gain correction value (step S910). Then, the timing control circuit 220 executes the offset correction value calculation process for calculating the offset correction value (step S920).

On the other hand, when the calibration mode is not set (step S901: No), or after step S920, the solid-state image sensor 200 determines whether or not the normal image pickup mode is set (step S904). When the normal imaging mode is not set (step S904: No), the timing control circuit 220 repeats steps S904 and subsequent steps.

On the other hand, when the normal imaging mode is set (step S904: Yes), the timing control circuit 220 switches the input destination of the column signal processing circuit 300 to the pixel 240 (step S905). Further, the timing control circuit 220 releases the horizontal connection of the vertical signal lines 249 (step S906), and the column signal processing circuit 300 generates image data composed of digital signals (step S907). The correction processing unit 270 corrects noise due to variations in gain and offset (step S908). After step S908, the solid-state image sensor 200 repeatedly executes step S904 and subsequent steps.

FIG. 13 is a flowchart showing an example of the gain correction value calculation process according to the first embodiment of the present technology. The timing control circuit 220 horizontally connects the outputs of the sample hold circuit 400 (that is, the output signal lines 408 and 409) (step S911). Further, the test voltage generation unit 260 applies a black level VL (step S912). The correction processing unit 270 calculates the column mean value bl _gain-n for each column and the line mean value lv _gain-AV (step S913).

Next, the test voltage generation unit 260 applies a white level VH (step S914). The correction processing unit 270 calculates a column mean value vh _gain-n for each column and a line mean value vh _gain-AV (step S915). The correction processing unit 270 calculates the gain correction value for each column according to the equation 1 (step S916), and holds them (step S917). The timing control circuit 220 releases the horizontal connection of the outputs of the sample hold circuit 400 (step S918), and ends the gain correction value calculation process.

FIG. 14 is a flowchart showing an example of the offset correction value calculation process according to the first embodiment of the present technology. The test voltage generation unit 260 applies the black level VL (step S921), and the correction processing unit 270 calculates the column mean value vh of s _-n for each column (step S922). The correction processing unit 270 calculates the offset correction value for each column according to the equation 2 (step S923), and holds them (step S924). After step S924, the solid-state image sensor 200 ends the offset correction value calculation process.

As described above, according to the first embodiment of the present technology, since the correction processing unit 270 corrects the noise due to the variation in the gain of the voltage / current conversion unit 365 for each column, the image is compared with the case where the correction is not performed. The image quality of the data can be improved.

[Modification example]
In the first embodiment described above, one reset voltage sample hold circuit and one signal voltage sample hold circuit are arranged for each row. However, in this configuration, AD conversion cannot be performed in parallel in the sample. The solid-state image sensor in the modification of the first embodiment is the first in that two reset voltage sample hold circuits and two signal voltage sample hold circuits are arranged in each row, and samples and AD conversion are performed in parallel. Different from the embodiment.

FIG. 15 is a circuit diagram showing a configuration example of the sample hold circuit 400 in the modified example of the first embodiment of the present technology. The sample hold circuit 400 of the modified example of the first embodiment is different from the first embodiment in that a reset voltage sample hold circuit 430 and a signal voltage sample hold circuit 440 are further arranged.

FIG. 16 is a circuit diagram showing a configuration example of the reset voltage sample hold

circuits

410 and 430 in the modified example of the first embodiment of the present technology.

The reset voltage sample hold circuit 410 of the modified example of the first embodiment further includes a switch 416. The switch 416 opens and closes the path between the output terminal of the amplifier 415 and the gate of the nMOS transistor 369 according to the control signal SW14 from the timing control circuit 220.

The reset voltage sample hold circuit 430 includes

switches

431, 433, 434 and 436, a capacitor 432, and an amplifier 435. The connection configuration of these elements is the same as that of the reset voltage sample hold circuit 410.

The timing control circuit 220 opens the switch 416 and closes the switch 436 during the sample of the reset voltage sample hold circuit 410. On the other hand, the timing control circuit 220 closes the switch 416 and opens the switch 436 while the reset voltage sample hold circuit 410 is being held.

FIG. 17 is a circuit diagram showing a configuration example of the signal voltage sample hold

circuits

420 and 440 in the modified example of the first embodiment of the present technology.

The signal voltage sample hold circuit 420 of the modified example of the first embodiment further includes a switch 426. The switch 426 opens and closes the path between the output terminal of the amplifier 425 and the gate of the nMOS transistor 368 according to the control signal SW24 from the timing control circuit 220.

The signal voltage sample hold circuit 440 includes

switches

441, 443, 444 and 446, a capacitor 442, and an amplifier 445. The connection configuration of these elements is the same as that of the signal voltage sample hold circuit 420.

The timing control circuit 220 opens the switch 426 and closes the switch 446 during the sample of the signal voltage sample hold circuit 420. On the other hand, the timing control circuit 220 closes the switch 426 and opens the switch 446 while the signal voltage sample hold circuit 420 is being held.

As described above, since the reset voltage sample hold

circuits

410 and 430 are provided, the timing control circuit 220 can hold the other in one of the samples. The same applies to the signal voltage. As a result, the sample and AD conversion are executed in parallel.

For example, when reading an odd number of lines, the reset voltage sample hold circuit 410 and the signal voltage sample hold circuit 420 sample the reset voltage and the signal voltage in order. On the other hand, the reset voltage sample hold circuit 430 and the signal voltage sample hold circuit 440 hold the sampled voltage, and the current corresponding to the difference between them is AD-converted.

Further, when reading even rows, the reset voltage sample hold circuit 430 and the signal voltage sample hold circuit 440 sample the reset voltage and the signal voltage in order. On the other hand, the reset voltage sample hold circuit 410 and the signal voltage sample hold circuit 420 hold the sampled voltage, and the current corresponding to the difference between them is AD-converted.

As described above, according to the modification of the first embodiment of the present technology, one of the reset voltage sample hold

circuits

410 and 430 can sample while the other can hold. The same applies to the set of the signal voltage sample hold

circuits

420 and 440. As a result, the reading speed can be doubled as compared with the first embodiment.

<2. Second Embodiment>
In the above-described first embodiment, one sample hold circuit 400 is arranged for each column, but in this configuration, AD conversion can be performed only for each row. The solid-state image sensor 200 of the second embodiment is different from the first embodiment in that two sample hold circuits 400 are arranged for each column and AD conversion is performed simultaneously in two rows.

FIG. 18 is a block diagram showing a configuration example of the solid-state image sensor 200 according to the second embodiment of the present technology. In this second embodiment,

vertical signal lines

248 and 249 are wired in the pixel array unit 230 for each row. The vertical signal line 248 is connected to even lines. On the other hand, the vertical signal line 249 is connected to odd lines.

FIG. 19 is a block diagram showing a configuration example of the column signal processing circuit 300 according to the second embodiment of the present technology. In the column signal processing circuit 300 of the second embodiment, two sample hold circuits 400 are arranged for each column. When the number of columns is N, 2N sample hold circuits 400 are arranged. Similarly, two multiplexer 310s, a current source 320, a switch 331, a switch 351, a switch 352, a voltage-current converter 365, and a current mode ADC 371 are also arranged in each row.

One of the pair of sample hold circuits 400 corresponding to the columns is connected to even rows via the vertical signal line 248, and the other is connected to odd rows via the vertical signal line 249. In other words, half of the 2N sample hold circuits 400 are connected to even rows and the rest are connected to odd rows. Further, the sample hold circuit 400 connected to the even-numbered rows and the sample hold circuit 400 connected to the odd-numbered rows are alternately arranged along the horizontal direction.

With the above configuration, the column signal processing circuit 300 can simultaneously hold the odd-numbered row pixel signal and the even-numbered row pixel signal and perform AD conversion. As a result, the reading speed can be doubled as compared with the first embodiment.

It should be noted that a modified example of the first embodiment can be applied to the second embodiment.

As described above, according to the second embodiment of the present technology, since the two sample hold circuits 400 are arranged for each column, the pixel signals for two rows can be held at the same time and read out.

<3. Third Embodiment>
In the above-described first embodiment, only the column signal processing circuit 300 is arranged, but in this configuration, AD conversion can be performed only one line at a time. The solid-state image sensor 200 of the third embodiment has a first embodiment in that an upper column signal processing circuit and a lower column signal processing circuit are arranged for each column to perform AD conversion in two rows at the same time. Different from.

FIG. 20 is a block diagram showing a configuration example of the solid-state image sensor 200 according to the third embodiment of the present technology. The solid-state image sensor 200 of the third embodiment is different from the first embodiment in that an upper column signal processing circuit 301 and a lower column signal processing circuit 302 are provided instead of the column signal processing circuit 300. .. Further, instead of the horizontal scanning circuit 250, an upper horizontal scanning circuit 251 and a lower horizontal scanning circuit 252 are provided.

The upper column signal processing circuit 301 is connected to one of an odd-numbered row and an even-numbered row (odd-numbered row, etc.), and performs signal processing on those rows. The lower column signal processing circuit 302 is connected to the other of the odd-numbered rows and the even-numbered rows (even-numbered rows and the like), and performs signal processing on those rows. The configurations of the upper column signal processing circuit 301 and the lower column signal processing circuit 302 are the same as those of the column signal processing circuit 300.

The upper column signal processing circuit 301 and the lower column signal processing circuit 302 simultaneously perform AD conversion of odd-numbered rows and even-numbered rows, so that two rows can be read out at the same time.

The upper horizontal scanning circuit 251 controls the upper column signal processing circuit 301, and the lower horizontal scanning circuit 252 controls the lower column signal processing circuit 302.

It should be noted that a modified example of the first embodiment can be applied to the third embodiment.

As described above, according to the second embodiment of the present technology, since the upper column signal processing circuit 301 and the lower column signal processing circuit 302 are arranged, two rows can be read out at the same time.

<4. Fourth Embodiment>
In the third embodiment described above, the circuits and elements in the solid-state image sensor 200 are arranged on a single chip, but in this configuration, the circuit scale of the light receiving chip 201 increases as the number of pixels increases. To do. The solid-state image sensor 200 of the fourth embodiment is different from the third embodiment in that circuits and the like are dispersedly arranged on two stacked chips.

FIG. 21 is a diagram showing an example of a laminated structure of the solid-state image sensor 200 according to the fourth embodiment of the present technology. The solid-state image sensor 200 includes a circuit chip 202 and a light receiving chip 201 laminated on the circuit chip 202. These chips are electrically connected via a connection such as a via. In addition to vias, it can also be connected by Cu-Cu bonding or bumps.

FIG. 22 is a block diagram showing a configuration example of the solid-state image sensor 200 according to the fourth embodiment of the present technology. A pixel array unit 230 is arranged on the light receiving chip 201. Circuits and elements other than the pixel array unit 230 are arranged on the circuit chip 202.

The circuits and elements arranged in the light receiving chip 201 and the circuit chip 202 are not limited to the configurations illustrated at the same time. For example, a part of each of the upper column signal processing circuit 301 and the lower column signal processing circuit 302 may be arranged on the light receiving chip 201, and the rest may be arranged on the circuit chip 202.

Further, the solid-state image pickup devices 200 of the first, second, and third embodiments may have a laminated structure. The solid-state image sensor 200 of the modified example of the first embodiment may have a laminated structure.

As described above, according to the fourth embodiment of the present technology, since the circuits and the like are distributed and arranged on the stacked light receiving chips 201 and the circuit chips 202, the circuit scale per chip can be reduced.

<5. Fifth Embodiment>
In the first embodiment described above, all the columns have been read out, but as the number of columns increases, the number of AD conversions increases. The solid-state image sensor 200 of the fifth embodiment is different from the first embodiment in that the number of AD conversions is reduced by performing pixel addition in the horizontal direction.

FIG. 23 is a block diagram showing a configuration example of the column signal processing circuit 300 according to the fifth embodiment of the present technology. The column signal processing circuit 300 of the fifth embodiment is different from the first embodiment in that the VSL adder circuit 340 is arranged between the VSL horizontal connection circuit 330 and the sample hold circuit 400.

The VSL adder circuit 340 connects adjacent odd-numbered vertical signal lines to each other and also connects adjacent even-numbered vertical signal lines to each other. The VSL adder circuit 340 is an example of the vertical signal line adder circuit described in the claims.

FIG. 24 is a circuit diagram showing a configuration example of the VSL adder circuit 340 and the SH horizontal connection circuit 350 according to the fifth embodiment of the present technology. In the VSL adder circuit 340, an inverter 341, a plurality of switches 342, a plurality of switches 343, a plurality of switches 344, and a plurality of switches 345 are arranged. Each of the switches 342 to 345 is arranged in every four rows except the last four rows. When the number of columns is N, the switches 342 to 345 are arranged by (N-4) / 4.

The inverter 341 inverts the control signal SWadd from the timing control circuit 220 and outputs it as a control signal xSWadd to the SH horizontal connection circuit 350.

The switch 342 opens and closes a path between the vertical signal line of the first row and the vertical signal line of the third row among the corresponding four rows according to the control signal SWadd. The switch 343 opens and closes the path between the vertical signal line in the second row and the vertical signal line in the fourth row according to the control signal SW _vsl . The switch 344 opens and closes the path between the vertical signal line in the third row and the sample hold circuit 400 according to the control signal xSWadd. The switch 345 opens and closes the path between the vertical signal line in the fourth row and the sample hold circuit 400 according to the control signal xSWadd.

Further, in the SH horizontal connection circuit 350, switches 351 to 360 are arranged in every four rows except the last four rows. When the number of columns is N, the switches 351 to 360 are arranged (N-4) / 4 each.

The switch 351 is a path between the output signal line 408 that transmits the signal voltage of the first row of the corresponding four rows and the output signal line 408 that transmits the signal voltage of the second row according to the control signals SWs. Is to open and close. The switch 352 opens and closes a path between the output signal line 409 that transmits the reset voltage of the first row and the output signal line 409 that transmits the reset voltage of the second row according to the control signals SWs. ..

The switch 353 opens and closes the path between the output signal line 408 in the second row and the output signal line 408 in the third row according to the control signal xSWadd. The switch 354 opens and closes the path between the output signal line 409 in the second row and the output signal line 409 in the third row according to the control signal xSWadd.

The switch 355 opens and closes the path between the output signal line 408 in the third row and the output signal line 408 in the fourth row according to the control signals SWs. The switch 356 opens and closes the path between the output signal line 409 in the third row and the output signal line 409 in the fourth row according to the control signals SWs.

The switch 357 opens and closes the path between the output signal line 408 in the fourth row and the output signal line 408 in the first row of the next four rows according to the control signal xSWadd. The switch 358 opens and closes the path between the output signal line 408 in the second row and the output signal line 408 in the first row of the next four rows according to the control signal SWadd.

The switch 359 opens and closes the path between the output signal line 409 in the fourth row and the output signal line 409 in the first row of the next four rows according to the control signal xSWadd. The switch 360 opens and closes the path between the output signal line 409 in the second row and the output signal line 409 in the first row of the next four rows according to the control signal SWadd.

The timing control circuit 220 closes the switches 342 to 345 by the control signal SWadd when performing pixel addition in the horizontal direction. As a result, the vertical signal line in the first row and the vertical signal line in the third row are connected, and the vertical signal line in the second row and the vertical signal line in the fourth row are connected. In other words, the adjacent odd-numbered (first and third columns) vertical signal lines are connected, and the adjacent even-numbered (second and fourth columns) vertical signal lines are connected. As a result, the pixel signals of the first and third columns are added, and the pixel signals of the second and fourth columns are added.

On the other hand, when pixel addition is not performed, the timing control circuit 220 opens switches 342 to 345.

FIG. 25 is a circuit diagram showing the states of the VSL addition circuit 340 and the SH horizontal connection circuit 350 when the vertical signal lines are connected (that is, pixel addition) in the fifth embodiment of the present technology.

When calculating the gain correction value, the

switches

351, 352, 355 and 356 are controlled in the closed state by the control signals SWs as in the first embodiment, and the output of the sample hold circuit 400 is horizontally connected.

The

switch

342, 343, 358 and 360 are controlled to the closed state by the control signal SWadd. Further, the

switch

344, 345, 353, 354, 357 and 359 are controlled to be in the open state by the control signal xSWadd. As a result, vertical signal lines such as the first row and the third row are horizontally connected. The number of pixels is thinned out in half by connecting the vertical signal lines horizontally (pixel addition). As a result, the reading speed is improved and the power consumption is reduced.

When calculating the offset correction value, the control signal SWadd is left as it is, and the control signal SWs releases the horizontal connection of the output of the sample hold circuit 400.

FIG. 26 is a circuit diagram showing the states of the VSL addition circuit 340 and the SH horizontal connection circuit 350 when the vertical signal lines are not connected (that is, pixel addition) in the fifth embodiment of the present technology.

When calculating the gain correction value, the

switches

The

switches

342, 343, 358 and 360 are controlled to the open state by the control signal SWadd. Further, the

switch

344, 345, 353, 354, 357 and 359 are controlled to the closed state by the control signal xSWadd. As a result, the horizontal connection of the vertical signal lines such as the first row and the third row is released. In this case, the pixels are not thinned out, and the same number of pixel signals as in the first embodiment are read out.

It should be noted that the second, third and fourth embodiments and modified examples of the first embodiment can be applied to the fifth embodiment.

As described above, according to the fifth embodiment of the present technology, since the VSL addition circuit 340 connects adjacent vertical signal lines, pixel addition can be performed in the horizontal direction. As a result, the number of pixels can be thinned out to improve the reading speed and reduce the power consumption.

<6. 6th Embodiment>
In the above-described first embodiment, AD conversion is performed by the current mode ADC 371 that targets the current signal, but in this configuration, the voltage-current conversion unit 365 is required before the current mode ADC 371. The solid-state image sensor 200 of the sixth embodiment is different from the first embodiment in that AD conversion is performed by an ADC whose voltage is a conversion target and the voltage-current conversion unit 365 is not required.

FIG. 27 is a block diagram showing a configuration example of the column signal processing circuit 300 according to the sixth embodiment of the present technology. The column signal processing circuit 300 of the sixth embodiment differs from the first embodiment in that it includes a selection circuit 380 and a signal processing block 385 instead of the voltage-current conversion unit 365 and the analog-digital conversion unit 370. ..

The selection circuit 380 selects either the

output signal line

408 or 409, and supplies the voltage of the selected signal line to the signal processing block 385 as an analog input signal Ain. In this selection circuit 380,

switches

381 and 382 are arranged for each row. When the number of columns is N, N switches 381 and 382 are arranged.

The switch 381 opens and closes the path between the output signal line 408 that transmits the signal voltage and the signal processing block 385 according to the control signal SWd from the timing control circuit 220. The switch 382 opens and closes the path between the output signal line 409 that transmits the reset voltage and the signal processing block 385 according to the control signal SWp from the timing control circuit 220.

When the reset voltage is AD-converted, the timing control circuit 220 controls the switch 381 to the open state and the switch 382 to the closed state by the control signals SWd and SWp. As a result, the reset voltage is input to the signal processing block 385 as an analog input signal Ain.

On the other hand, when the signal voltage is AD-converted, the timing control circuit 220 controls the switch 381 to the closed state and the switch 382 to the open state by the control signals SWd and SWp. As a result, the signal voltage is input to the signal processing block 385 as an analog input signal Ain.

FIG. 28 is a block diagram showing a configuration example of the signal processing block 385 according to the sixth embodiment of the present technology. A comparator 386, a latch circuit 387, and a switch 388 are arranged in each row in the signal processing block 385. When the number of columns is N, the comparator 386, the latch circuit 387, and the switch 388 are arranged N by N.

The comparator 386 increases or decreases the difference between the pair of analog input signals by a predetermined gain and outputs the analog output signal VCO. One of these pair of analog input signals is the analog input signal Vin (ie, either the reset voltage or the signal voltage) from the selection circuit 380, and the other is the ramp signal RMP from the DAC (not shown). .. This lamp signal RMP is a slope-shaped signal indicating a reference voltage. The analog output signal VCO shows a comparison result of the analog input signal Vin and the lamp signal RMP.

Here, the level of the analog output signal VCO is expressed by the following equation.
VCO = Av × (Ain-RMP) + Ofs = Av × V _in + Ofs
In the above equation, Av is the gain for the difference between the analog input signal Ain and the lamp signal RMP.

The latch circuit 387 converts the analog output signal VCO into the digital signal Dout. A time code indicating a relative time within the period in which the lamp signal RMP changes and an analog output signal VCO of the corresponding column are input to the latch circuit 387. The latch circuit 387 holds the time code when the analog output signal VCO is inverted, and outputs the digital signal Dout to the switch 388.

Note that instead of the latch circuit 387, a counter that counts over the period until the analog output signal VCO is inverted can be arranged.

The analog input signal Ain is converted into a digital signal Dout by the comparator 386 and the latch circuit 387. That is, the comparator 386 and the latch circuit 387 function as ADCs. Further, an ADC (comparator 386, latch circuit 387, etc.) that uses a slope-shaped signal such as the lamp signal RMP is generally called a single slope type ADC. The circuit composed of the latch circuits 387 in each row is an example of the analog-to-digital conversion unit described in the claims.

The switch 388 outputs the digital signal Dout of the corresponding column to the output unit 375 under the control of the horizontal scanning circuit 250.

Similar to the first embodiment, the timing control circuit 220 connects the outputs of the sample hold circuit 400 horizontally to calculate a gain correction value for correcting noise due to variation in gain Av. Further, the timing control circuit 220 releases the horizontal connection of the outputs of the sample hold circuit 400 to calculate the offset correction value.

It should be noted that each of the second, third and fourth embodiments can be applied to the sixth embodiment.

As described above, according to the sixth embodiment of the present technology, since the signal processing block 385 converts either the reset voltage or the signal voltage into a digital signal, the AD is not used in the voltage-current converter 365. The conversion can be done. As a result, the circuit scale can be reduced as compared with the case where the voltage-current conversion unit 365 is provided.

<7. Application example to mobile>
The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure is realized as a device mounted on a moving body of any kind such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. You may.

FIG. 29 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via the communication network 12001. In the example shown in FIG. 29, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

The drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 provides a driving force generator for generating the driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism for adjusting and a braking device for generating a braking force of a vehicle.

The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, blinkers or fog lamps. In this case, the body system control unit 12020 may be input with radio waves transmitted from a portable device that substitutes for the key or signals of various switches. The body system control unit 12020 receives inputs of these radio waves or signals and controls a vehicle door lock device, a power window device, a lamp, and the like.

The vehicle outside information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image pickup unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle outside information detection unit 12030 causes the image pickup unit 12031 to capture an image of the outside of the vehicle and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as a person, a vehicle, an obstacle, a sign, or characters on the road surface based on the received image.

The image pickup unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of the light received. The imaging unit 12031 can output an electric signal as an image or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects the in-vehicle information. For example, a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing.

The microcomputer 12051 calculates the control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit. A control command can be output to 12010. For example, the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, and the like. It is possible to perform cooperative control for the purpose of.

Further, the microcomputer 12051 controls the driving force generating device, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the outside information detection unit 12030 or the inside information detection unit 12040, so that the driver can control the driver. It is possible to perform coordinated control for the purpose of automatic driving that runs autonomously without depending on the operation.

Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the external information detection unit 12030, and performs coordinated control for the purpose of antiglare such as switching the high beam to the low beam. It can be carried out.

The audio image output unit 12052 transmits the output signal of at least one of the audio and the image to the output device capable of visually or audibly notifying the passenger or the outside of the vehicle of the information. In the example of FIG. 29, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an onboard display and a heads-up display.

FIG. 30 is a diagram showing an example of the installation position of the imaging unit 12031.

In FIG. 30, the image pickup unit 12031 has

image pickup units

12101, 12102, 12103, 12104, 12105.

The

imaging units

12101, 12102, 12103, 12104, 12105 are provided at positions such as the front nose, side mirrors, rear bumpers, back doors, and the upper part of the windshield in the vehicle interior of the vehicle 12100, for example. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100. The

imaging units

12102 and 12103 provided in the side mirrors mainly acquire images of the side of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100. The imaging unit 12105 provided on the upper part of the windshield in the vehicle interior is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

Note that FIG. 30 shows an example of the photographing range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the

imaging units

12102 and 12103 provided on the side mirrors, respectively, and the imaging range 12114 indicates the imaging range of the

imaging units

12102 and 12103. The imaging range of the imaging unit 12104 provided on the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 as viewed from above can be obtained.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image pickup units 12101 to 12104 may be a stereo camera composed of a plurality of image pickup elements, or may be an image pickup element having pixels for phase difference detection.

For example, the microcomputer 12051 has a distance to each three-dimensional object within the imaging range 12111 to 12114 based on the distance information obtained from the imaging units 12101 to 12104, and a temporal change of this distance (relative velocity with respect to the vehicle 12100). By obtaining, it is possible to extract as the preceding vehicle a three-dimensional object that is the closest three-dimensional object on the traveling path of the vehicle 12100 and that travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or more). it can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in front of the preceding vehicle in advance, and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform cooperative control for the purpose of automatic driving or the like in which the vehicle travels autonomously without depending on the operation of the driver.

For example, the microcomputer 12051 converts three-dimensional object data related to a three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, electric poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that can be seen by the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.

At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. Such pedestrian recognition includes, for example, a procedure for extracting feature points in an image captured by an imaging unit 12101 to 12104 as an infrared camera, and pattern matching processing for a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. It is done by the procedure to determine. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 outputs a square contour line for emphasizing the recognized pedestrian. The display unit 12062 is controlled so as to superimpose and display. Further, the audio image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.

The above is an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technique according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. Specifically, the image pickup apparatus 100 of FIG. 1 can be applied to the image pickup unit 12031. By applying the technique according to the present disclosure to the imaging unit 12031, it is possible to reduce random noise due to gain variation and obtain a photographed image that is easier to see, so that driver fatigue can be reduced.

Note that the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the claims have a corresponding relationship with each other. Similarly, the matters specifying the invention within the scope of claims and the matters in the embodiment of the present technology having the same name have a corresponding relationship with each other. However, the present technology is not limited to the embodiment, and can be embodied by applying various modifications to the embodiment without departing from the gist thereof.

It should be noted that the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.

The present technology can have the following configurations.
(1) A plurality of analog output units that increase or decrease the difference between a pair of analog input signals by a predetermined gain and output them as analog output signals.
An analog-to-digital conversion unit that converts the analog output signal of each of the plurality of analog output units into a digital signal,
A solid-state image sensor including a correction processing unit that corrects noise of the digital signal due to a variation in the gain of each of the plurality of analog output units.
(2) A plurality of signal voltages corresponding to the amount of received light and a predetermined reset voltage are sampled and held in order, and the signal voltage and the reset voltage are output as the pair of analog input signals via the pair of output signal lines. The solid-state imaging device according to (1) above, further comprising the sample hold circuit of.
(3) The solid-state imaging device according to claim 2, further comprising a sample hold horizontal connection circuit that opens and closes a path between the pair of output signal lines of each of the plurality of sample hold circuits.
(4) The correction processing unit is
When the path is in the closed state, a gain correction value calculation circuit that calculates a correction value for correcting noise due to the variation in gain as a gain correction value, and a gain correction value calculation circuit.
When the path is in the open state, an offset correction value calculation circuit that calculates the correction value as an offset correction value for correcting noise due to variations in the offsets of the plurality of sample hold circuits, and an offset correction value calculation circuit.
The solid-state image sensor according to (3), further comprising a correction calculation circuit that corrects the noise by using the calculated gain correction value and the calculated offset correction value.
(5) The solid-state image sensor according to (3) or (4), wherein the analog output signal is a current signal in which the difference between the signal voltage and the reset voltage is increased or decreased by the gain.
(6) Each of the plurality of sample hold circuits
A pair of reset voltage sample hold circuits and
Equipped with a pair of signal voltage sample hold circuits
When one of the pair of reset voltage sample hold circuits samples the reset voltage, the other holds it.
The solid-state imaging device according to any one of (3) to (5), wherein one of the pair of signal voltage sample hold circuits holds the other when the signal voltage is sampled.
(7) A pixel array unit in which a plurality of rows are arranged is further provided.
Each of the plurality of rows consists of a plurality of pixels arranged in a predetermined direction.
Half of the plurality of sample hold circuits are connected to even rows of the plurality of rows, and the rest of the plurality of sample hold circuits are connected to odd rows of the plurality of rows.
The sample hold circuit connected to the even-numbered rows and the sample-hold circuit connected to the odd-numbered rows are described in any one of (3) to (6), which are arranged alternately along the predetermined direction. Solid-state image sensor.
(8) A pixel array unit in which a plurality of rows are arranged is further provided.
Half of the plurality of sample hold circuits are arranged in the upper column signal processing circuit, and the rest are arranged in the lower column signal processing circuit.
The upper column signal processing circuit is connected to one of the odd-numbered rows and the even-numbered rows in the plurality of rows, and the lower column signal processing circuit is connected to the other of the odd-numbered rows and the even-numbered rows (3). ) To (5).
(9) A pixel array unit in which a plurality of pixels are arranged is further provided.
The pixel array unit is arranged on a predetermined light receiving chip, and is arranged.
At least a part of the plurality of sample hold circuits, the sample hold horizontal connection circuit, the plurality of analog output units, the analog-digital conversion unit, and the correction processing unit is arranged on a predetermined circuit chip (3). The solid-state image sensor according to any one of (8) to (8).
(10) A pixel array unit in which a plurality of vertical signal lines connected to the sample hold circuits different from each other are wired, and
The vertical signal line addition circuit for connecting the adjacent odd-numbered signal lines of the plurality of vertical signal lines and connecting the adjacent even-numbered signal lines of the plurality of vertical signal lines is further provided. The solid-state imaging device according to any one of (3) to (9).
(11) A plurality of sample hold circuits that sample and hold a signal voltage corresponding to the amount of light received by a pixel and a predetermined reset voltage in order, and output the signal voltage and the reset voltage via a pair of output signal lines. ,
A selection circuit that selects one of the pair of output signal lines of each of the plurality of sample hold circuits and outputs the voltage of the selected signal line as one of the pair of analog input signals to the analog-to-digital converter. Further equipped
The solid-state image sensor according to (1) above, wherein the other of the pair of analog input signals has a predetermined reference voltage.
(12) A plurality of analog output units that increase or decrease the difference between a pair of analog input signals by a predetermined gain and output them as analog output signals.
An analog-to-digital conversion unit that converts the analog output signal of each of the plurality of analog output units into a digital signal,
A correction processing unit that corrects noise of the digital signal due to a variation in the gain of each of the plurality of analog output units, and a correction processing unit.
An imaging device including a digital signal processing circuit that performs predetermined image processing on image data including each of the digital signals.
(13) An analog output procedure in which each of the plurality of analog output units increases or decreases the difference between the pair of analog input signals by a predetermined gain and outputs the analog output signal.
An analog-to-digital conversion procedure for converting the analog output signal of each of the plurality of analog output units into a digital signal, and
A method for controlling a solid-state image sensor, comprising a correction processing procedure for correcting noise of the digital signal due to a variation in the gain of each of the plurality of analog output units.

100 Imaging device 110 Optical unit 120 DSP circuit 130 Display unit 140 Operation unit 150 Bus 160 Frame memory 170 Storage unit 180 Power supply unit 200 Solid-state imaging element 201 Light receiving chip 202 Circuit chip 210 Vertical scanning circuit 220 Timing control circuit 230 Pixer array unit 240 pixels 241 Photoelectric conversion element 242 Transfer switch 243 Amplifier circuit 250 Horizontal scanning circuit 251 Upper horizontal scanning circuit 252 Lower horizontal scanning circuit 260 Test voltage generator 270

Correction processing unit

271, 281 Demultiplexer 280 Correction value calculation circuit 282 Offset correction value calculation circuit 283 Gain correction value calculation circuit 284 Correction value holder 290 Correction calculation circuit 291 Line buffer 292 Subtractor 293 Multiplier 300 Column signal processing circuit 301 Upper column signal processing circuit 302 Lower column signal processing circuit 310

multiplexer

320, 366 Current source 330 VSL

horizontal connection circuit

331, 342 to 345, 351 to 360, 381, 382, 388, 411, 413, 414, 416, 421, 423, 424, 426, 431, 433, 434, 436, 441, 443, 444, 446 Switch 340

VSL Amplifier Circuit

341, 361 Inverter 350 SH

Horizontal Connection Circuit

362, 368, 369 nMOS Transistor 363 pMOS Transistor 365 Voltage / Current Converter 367 Resistance 370 Analog Digital Converter 371 Current Mode ADC
375 Output unit 380 Selection circuit 385 Signal processing block 386 Comparator 387 Latch circuit 400

Sample hold circuit

410, 430 Reset voltage

Sample hold circuit

420, 440 Signal voltage

sample hold circuit

412, 422, 432, 442

Capacitor

415, 425, 435, 445 Amplifier 12031 Imaging unit

Claims

A plurality of analog output units that increase or decrease the difference between a pair of analog input signals by a predetermined gain and output them as analog output signals.
An analog-to-digital conversion unit that converts the analog output signal of each of the plurality of analog output units into a digital signal,
A solid-state image sensor including a correction processing unit that corrects noise of the digital signal due to a variation in the gain of each of the plurality of analog output units.
A plurality of sample holds in which a signal voltage corresponding to the amount of received light and a predetermined reset voltage are sampled and held in order, and the signal voltage and the reset voltage are output as the pair of analog input signals via a pair of output signal lines. The solid-state imaging device according to claim 1, further comprising a circuit.
The solid-state image sensor according to claim 2, further comprising a sample hold horizontal connection circuit for opening and closing a path between the pair of output signal lines of each of the plurality of sample hold circuits.
The correction processing unit
When the path is in the closed state, a gain correction value calculation circuit that calculates a correction value for correcting noise due to the variation in gain as a gain correction value, and a gain correction value calculation circuit.
When the path is in the open state, an offset correction value calculation circuit that calculates the correction value as an offset correction value for correcting noise due to variations in the offsets of the plurality of sample hold circuits, and an offset correction value calculation circuit.
The solid-state image sensor according to claim 3, further comprising a correction calculation circuit that corrects the noise by using the calculated gain correction value and the calculated offset correction value.
The solid-state image sensor according to claim 3, wherein the analog output signal is a current signal in which the difference between the signal voltage and the reset voltage is increased or decreased by the gain.
Each of the plurality of sample hold circuits
A pair of reset voltage sample hold circuits and
Equipped with a pair of signal voltage sample hold circuits
When one of the pair of reset voltage sample hold circuits samples the reset voltage, the other holds it.
The solid-state imaging device according to claim 3, wherein one of the pair of signal voltage sample hold circuits holds the other when the signal voltage is sampled.
A pixel array unit in which a plurality of rows are arranged is further provided.
Each of the plurality of rows consists of a plurality of pixels arranged in a predetermined direction.
Half of the plurality of sample hold circuits are connected to even rows of the plurality of rows, and the rest of the plurality of sample hold circuits are connected to odd rows of the plurality of rows.
The solid-state image sensor according to claim 3, wherein the sample hold circuit connected to the even-numbered rows and the sample hold circuit connected to the odd-numbered rows are alternately arranged along the predetermined direction.
A pixel array unit in which a plurality of rows are arranged is further provided.
Half of the plurality of sample hold circuits are arranged in the upper column signal processing circuit, and the rest are arranged in the lower column signal processing circuit.
3. The upper column signal processing circuit is connected to one of the odd-numbered rows and the even-numbered rows in the plurality of rows, and the lower column signal processing circuit is connected to the other of the odd-numbered rows and the even-numbered rows. The solid-state imaging device described.
Further provided with a pixel array unit in which a plurality of pixels are arranged,
The pixel array unit is arranged on a predetermined light receiving chip, and is arranged.
3. The third aspect of claim 3, wherein at least a part of the plurality of sample hold circuits, the sample hold horizontal connection circuit, the plurality of analog output units, the analog-digital conversion unit, and the correction processing unit is arranged on a predetermined circuit chip. Solid-state image sensor.
A pixel array unit in which a plurality of vertical signal lines connected to the sample hold circuits different from each other are wired, and
A claim further comprising a vertical signal line addition circuit that connects adjacent odd-numbered signal lines among the plurality of vertical signal lines and connects adjacent even-numbered signal lines among the plurality of vertical signal lines. Item 3. The solid-state image sensor according to Item 3.
A plurality of sample hold circuits that sample and hold a signal voltage corresponding to the amount of light received by a pixel and a predetermined reset voltage in order, and output the signal voltage and the reset voltage via a pair of output signal lines.
A selection circuit that selects one of the pair of output signal lines of each of the plurality of sample hold circuits and outputs the voltage of the selected signal line as one of the pair of analog input signals to the analog-to-digital converter. Further equipped
The solid-state image sensor according to claim 1, wherein the other of the pair of analog input signals has a predetermined reference voltage.
A plurality of analog output units that increase or decrease the difference between a pair of analog input signals by a predetermined gain and output them as analog output signals.
An analog-to-digital conversion unit that converts the analog output signal of each of the plurality of analog output units into a digital signal,
A correction processing unit that corrects noise of the digital signal due to a variation in the gain of each of the plurality of analog output units, and a correction processing unit.
An imaging device including a digital signal processing circuit that performs predetermined image processing on image data including each of the digital signals.
An analog output procedure in which each of a plurality of analog output units increases or decreases the difference between a pair of analog input signals by a predetermined gain and outputs the analog output signal.
An analog-to-digital conversion procedure for converting the analog output signal of each of the plurality of analog output units into a digital signal, and
A method for controlling a solid-state image sensor, comprising a correction processing procedure for correcting noise of the digital signal due to a variation in the gain of each of the plurality of analog output units.