WO2020187072A1 - 阵列基板及其制备方法、显示装置及其成像方法 - Google Patents

阵列基板及其制备方法、显示装置及其成像方法 Download PDF

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Publication number
WO2020187072A1
WO2020187072A1 PCT/CN2020/078370 CN2020078370W WO2020187072A1 WO 2020187072 A1 WO2020187072 A1 WO 2020187072A1 CN 2020078370 W CN2020078370 W CN 2020078370W WO 2020187072 A1 WO2020187072 A1 WO 2020187072A1
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Prior art keywords
imaging
layer
array substrate
metal layer
sensor units
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English (en)
French (fr)
Inventor
邱海军
何月娣
唐国强
张振华
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to US15/733,811 priority Critical patent/US12089475B2/en
Publication of WO2020187072A1 publication Critical patent/WO2020187072A1/zh
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Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/45—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/57—Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure generally relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display device and an imaging method thereof.
  • the front camera device is usually set at the frame position of the display device, and this structure is not conducive to the development of narrow frame and full screen.
  • an array substrate including:
  • the sensor units have a one-to-one correspondence.
  • the plurality of sensor units are arranged to have different thicknesses, so that the distances between the plurality of sensor units and the plurality of imaging apertures corresponding thereto are different.
  • the array substrate further includes: a light-shielding metal layer disposed above the base substrate, wherein the plurality of imaging apertures are located in the light-shielding metal layer.
  • the array substrate further includes: a first source drain metal layer and a second source drain metal layer disposed above the base substrate, wherein the plurality of imaging apertures are located The second source and drain metal layer.
  • the array substrate further includes: a pixel defining layer disposed above the base substrate, and a plurality of openings for disposing light-emitting devices are disposed in the pixel defining layer; wherein, the plurality of openings The orthographic projection on the base substrate and the orthographic projection of the plurality of imaging apertures on the base substrate do not overlap.
  • the array substrate further includes: a flat layer disposed above the base substrate and below the pixel defining layer; wherein the plurality of imaging apertures penetrate the pixel defining layer and the flat layer. Layer, or, the plurality of imaging apertures penetrate the flat layer.
  • each of the imaging apertures is about 3 to 4 microns; and/or, each of the imaging apertures is a circular hole with a diameter of about 5 to 10 microns.
  • embodiments of the present disclosure provide a method for manufacturing an array substrate, including:
  • a metal layer is formed above the plurality of sensor units through a patterning process, and a plurality of imaging apertures are formed in the metal layer, wherein the plurality of imaging apertures are respectively located above the plurality of sensor units, So that each imaging aperture corresponds to each sensor unit one-to-one.
  • the plurality of sensor units are respectively formed to have different thicknesses through an evaporation process, so that the distances between the plurality of sensor units and the plurality of corresponding imaging apertures are different. of.
  • the metal layer includes a light-shielding metal layer formed by a patterning process above the sensor unit, and the imaging aperture is located in the light-shielding metal layer.
  • the metal layer includes a first source-drain metal layer and a second source-drain metal layer formed by a patterning process over the plurality of sensor units, wherein the plurality of imaging The small hole is located in the second source and drain metal layer.
  • the preparation method further includes: forming a pixel defining layer above the base substrate through a patterning process; forming a plurality of openings on the pixel defining layer, and the plurality of openings are formed on the base substrate.
  • the orthographic projection on the upper surface does not overlap with the orthographic projection of the plurality of imaging apertures on the base substrate.
  • the preparation method further includes: forming a flat layer under the pixel defining layer through a patterning process; making the plurality of imaging apertures penetrate through the pixel defining layer and the flat layer through an etching process, Or an etching process is used to make the plurality of imaging small holes penetrate the flat layer.
  • an embodiment of the present disclosure provides a display device including: the array substrate as described in any of the foregoing embodiments.
  • an embodiment of the present disclosure provides an imaging method, which is applied to the display device according to any of the foregoing embodiments, and the method includes:
  • an imaging area is determined according to the acquired image information, the imaging area includes at least one sensor unit corresponding to the image information, and the image information includes the object distance of the object to be photographed or the at least one sensor The focal length of the unit;
  • FIG. 1 shows a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure
  • FIG. 2 shows a schematic structural diagram of an array substrate provided by another embodiment of the present disclosure
  • Fig. 3 shows a schematic structural diagram of an array substrate provided by another embodiment of the present disclosure
  • FIG. 4 shows a schematic diagram of the distribution position of the imaging apertures in the display area provided by an embodiment of the present disclosure
  • FIG. 5 shows a schematic diagram of the distribution positions of imaging apertures in a display area provided by another embodiment of the present disclosure
  • FIG. 6 shows a schematic diagram of the principle of imaging of light in the image forming layer through the imaging aperture in the array substrate provided by the embodiment of the present disclosure
  • FIG. 7 shows a schematic diagram of imaging area division in an array substrate provided by an embodiment of the present disclosure
  • FIG. 8 shows a schematic flowchart of an imaging method of a display device according to an embodiment of the present disclosure.
  • the front camera device may usually be set at the frame position of the display device. Due to the structural requirements of the camera device itself, it needs to occupy a certain position space, so that the expansion of the display screen is limited. The existence of the front camera device, It is not conducive to the development of narrow bezels and full screens.
  • FIG. 1 shows a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • the array substrate 10 includes: a base substrate 101; and a plurality of imaging apertures 102 and a plurality of sensor units 103 arranged above the base substrate 101.
  • the plurality of imaging apertures 102 are respectively located above the plurality of sensor units 103, so that each imaging aperture 102 corresponds to each optical sensing unit 103 one-to-one.
  • the technical idea of the present disclosure is to integrate the camera function into the display screen.
  • the imaging function is integrated in the display area according to the imaging aperture principle, thereby solving the problem that the related art camera device occupies the display area.
  • the layer where the imaging pinhole 102 is located is defined as the imaging pinhole layer 200
  • the layer where the sensor unit 103 is located is defined as the image forming layer 300 herein.
  • the imaging aperture can be formed as an independent imaging aperture layer (for example, a light-shielding metal layer or a second source/drain metal layer), or can be formed in the original array substrate.
  • Functional layer for example, flat layer or pixel defining layer.
  • the imaging pinhole layer and the original functional layer (such as a flat layer or a pixel defining layer) formed on the array substrate are the same layer, for example, the imaging pinhole is formed in the flat layer or the pixel defining layer.
  • the base substrate 101 may be a flexible substrate.
  • the flexible substrate refers to a bendable, foldable or rollable substrate.
  • the material of the flexible substrate can be ultra-thin glass, metal or plastic. For example, polymer resin, polyimide, etc.
  • the imaging pinhole layer (that is, the layer where the imaging pinhole 102 is located) 200 may be a metal layer.
  • the metal layer may be, for example, a light-shielding metal layer, or may be, for example, a second layer of source and drain metal layers.
  • the process is simple and the cost is low, but there is a problem of stray light.
  • stray light can be resolved, and greater light transmittance can be obtained, but the cost is higher.
  • the array substrate may include: a light-shielding metal layer disposed on the base substrate 101, and the imaging aperture is located in the metal layer.
  • the imaging pinhole layer that is, the layer where the imaging pinhole 102 is located
  • 200 in FIG. 1 is a light-shielding metal layer.
  • the array substrate may include: a first source drain metal layer and a second source drain metal layer disposed above the base substrate 101, and the imaging aperture is located in the second source drain metal layer.
  • the imaging pinhole layer ie, the layer where the imaging pinhole 102 is located
  • 200 in FIG. 1 is the second source/drain metal layer.
  • the shooting mode When the shooting mode is activated, incident light passes through the imaging aperture 102.
  • the aperture imaging principle when the light from different parts of the object to be photographed reaches the sensor unit 103, an image that is upside down to the object to be photographed is formed in the sensor unit 103 .
  • the size of the imaging aperture 102 and the distance between the sensor unit 103 and the imaging aperture 102 (the distance is the image distance) determine the definition of imaging.
  • the sensor unit 103 may also be referred to as an image sensor, for example, it may be a charge-coupled device (CCD), a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS), etc.
  • CCD charge-coupled device
  • CMOS complementary metal oxide semiconductor
  • the specific location of the sensor unit is not particularly limited, as long as it can be ensured that the sensor unit is located between the corresponding imaging aperture and the base substrate, and the distance between the imaging aperture and the corresponding sensor unit can meet the imaging requirements.
  • the sensor unit is directly arranged on the base substrate. In another embodiment, the sensor unit is arranged in other functional layers.
  • a plurality of sensor units 103 can be set to have different thicknesses, so that the plurality of sensor units 103 and corresponding ones
  • the distances between the multiple imaging apertures 102 are different. That is, the distances from different sensor units 103 to their corresponding imaging apertures 102 can be set to different values. For example, as shown in FIG. 1, the thickness of the sensor unit 103 corresponding to different imaging apertures 102 is different. In this way, the distance from the surface of the sensor unit 103 away from the base substrate 101 (ie, the imaging plane) to the imaging aperture 102 corresponding to the sensor unit 103 may be different.
  • the display area may be divided into different imaging areas, and the sensor units 103 included in the different imaging areas may be set to have different thicknesses. It can be understood that at least one sensor unit 103 included in the imaging area A11 is set to a first thickness value, at least one sensor unit 103 included in the imaging area A12 is set to a second thickness value, and so on, the sensor units in different imaging areas 103 has different thickness values. Whether different imaging areas need to be divided can be determined according to the proportion of the imaging area occupying the screen. In an embodiment, the depth of field of one imaging area meets the requirements of the imaging range, and only one imaging area may be used in full screen for the entire display area. If the depth of field of an imaging area cannot meet the requirements of the imaging range, the entire display area can be divided into multiple imaging areas according to the proportion of the screen covered.
  • the imaging range is expanded.
  • the array substrate 10 provided by the embodiment of the present disclosure may also form a buffer layer 107 between the imaging pinhole layer 200 where the multiple imaging pinholes 102 are located and the image forming layer 300 where the multiple sensor units 103 are located, as shown in FIG. 6 .
  • FIG. 2 shows a schematic structural diagram of an array substrate 10 provided by another embodiment of the present disclosure.
  • the array substrate 10 includes: a base substrate 101, a plurality of imaging apertures 102 and a plurality of sensor units 103 arranged above the base substrate 101, and a pixel defining layer arranged above the base substrate 101 105, wherein a plurality of imaging apertures 102 are respectively located above the plurality of sensor units 103, so that each imaging aperture 102 corresponds to each light sensing unit 103 one-to-one; the pixel defining layer 105 is provided for setting The multiple openings 104 of the light emitting device; the orthographic projection of the opening 104 on the base substrate 101 and the orthographic projection of the imaging aperture 102 on the base substrate 101 do not overlap.
  • the layer where the multiple imaging apertures 102 are located is defined as the imaging aperture layer 200, and the layer where the sensor unit 103 is located is defined as the image forming layer 300.
  • the imaging aperture 102, the sensor unit 103, and the opening 104 are all located in the display area of the array substrate 10.
  • the array substrate provided by the embodiment of the present disclosure realizes the integrated camera function of the display screen based on the principle of small hole imaging by adding the imaging pinhole layer 200 where the multiple imaging pinholes 102 are located and the image forming layer 300 where the multiple sensor units 103 are located.
  • the multiple sensor units 103 can be set to have different thickness values, so that the distances between the multiple sensor units 103 and the multiple imaging apertures 102 corresponding thereto are different.
  • FIG. 6 shows a schematic diagram of the principle that light passes through the imaging aperture 102 and is imaged in the image forming layer 300 where the sensor unit 103 is located.
  • h1 to h5 represent the distance from the object to be photographed to the imaging aperture 102, which can generally be referred to as the object distance.
  • the position of the sensor unit 103 needs to be adjusted so that the distance from its imaging plane to the imaging aperture 102 can capture clear images at different object distances. image.
  • the distance from the imaging plane to the imaging aperture is the image distance, also known as the focal length.
  • the multiple sensor units 102 of the image forming layer 300 can be designed to have different thicknesses, so that the distance between the multiple sensor units 103 and the corresponding multiple imaging apertures 102 is Different, so that the distance from the imaging aperture meets the focal length setting requirements.
  • FIG. 7 shows a schematic diagram of imaging area division provided by an embodiment of the present disclosure.
  • a plurality of sensor units 103 can be divided into different regions according to different focal lengths.
  • multiple sensor units 103 with a first focal length are deployed in the A11 area to form a clear image of the object to be photographed corresponding to the first focal length.
  • the imaging result can correspond to the shooting range of the object distance h1 in FIG. 6,
  • the first focal length is the distance between the sensor unit 103 and the imaging aperture 102 below the mark h1 in FIG. 6.
  • multiple sensor units 103 with a second focal length can be deployed in the A12 area to form a clear image of the object to be photographed corresponding to the second focal length.
  • the imaging result can correspond to the object distance h2 in Figure 6
  • the second focal length is the distance between the sensor unit 103 and the imaging aperture 102 below the mark h2 in FIG. 6.
  • the entire display area can be divided into multiple sub-areas according to the proportion of the screen occupied by the divided area, and each sub-area corresponds to an imaging area with a different shooting focal length.
  • the position of the opening 104 for arranging the light emitting device and the position of the imaging aperture 102 are set so that the orthographic projection on the base substrate does not coincide, thereby solving the problem of poor imaging effect caused by backlight.
  • the layer where the imaging pinhole 102 is located can be made of light-shielding material to block visible light.
  • the material of the layer where the imaging aperture 102 is located can be selected to include polyimide and a black light-absorbing substance doped in polyimide to block visible light, thereby improving imaging quality.
  • the display device as a whole is developing towards ultra-thin.
  • the thickness of the imaging aperture 102 can also be set to be about 3-4 ⁇ m, and this value range can have both imaging effects and ultra-thin performance.
  • a plurality of imaging apertures 102 may be evenly distributed in the entire display area.
  • the shape of the imaging aperture 102 can be set in various shapes. According to its light transmission effect, it can be set in the shape of a circular hole, for example, the diameter is set to be about 5-10 ⁇ m.
  • FIG. 3 shows a schematic structural diagram of an array substrate 10 according to another embodiment of the present disclosure. The following mainly describes the difference between the embodiment shown in FIG. 3 and the foregoing embodiment.
  • the pixel defining layer 105 where the multiple openings 104 for arranging the light emitting device are located and the flat layer (not shown in the figure) located between the base substrate 101 and the pixel defining layer 105 are used in common
  • An imaging aperture layer 200 in which a plurality of imaging apertures 102 are located is formed.
  • the pixel defining layer 105, the flat layer and the imaging pinhole layer 200 share the same layer, that is, the same layer.
  • the imaging aperture 102 penetrates the pixel defining layer 105, the flat layer and the imaging aperture layer 200.
  • the flat layer located between the base substrate and the pixel defining layer where the plurality of openings for arranging the light emitting device are located can be used as the imaging aperture in which the plurality of imaging apertures are located.
  • the flat layer and the imaging pinhole layer share the same layer. At this time, it can be understood that the imaging aperture penetrates the flat layer and the imaging aperture layer at the same time.
  • the thickness space of the display device can be effectively saved, and a better imaging effect can be obtained.
  • the embodiment of the present disclosure also provides a method for preparing the array substrate, the method including:
  • a plurality of sensor units 103 are formed on the base substrate 101 through an evaporation process
  • a metal layer is formed through a patterning process, and a plurality of imaging apertures are formed in the metal layer, wherein the plurality of imaging apertures 103 are respectively located above the plurality of sensor units 103, so that each imaging
  • the small hole 102 corresponds to each sensor unit 103 one to one, and its structure is shown in FIG. 1.
  • the sensor unit 103 may form photosensitive layers of different thicknesses through an evaporation process.
  • a certain sensor unit 103 or a group (a plurality of) of sensor units 103 may form a photosensitive layer with the same thickness through an evaporation process, or form multiple photosensitive layers through multiple evaporation processes to form the same thickness.
  • a metal layer may be formed on the base substrate 101 through a patterning process.
  • the metal layer may be a light-shielding metal layer, or a first source drain metal layer and a second source drain metal layer are formed.
  • the patterning process includes: photoresist coating, masking, exposure, development, etching, photoresist stripping and other partial or all processes.
  • FIG. 4 shows a schematic diagram of the distribution positions of the imaging apertures 102 in the display area provided by an embodiment of the present disclosure.
  • FIG. 4 illustrates the basic structure of the array substrate, only the functional layers related to the technical solutions of the embodiments of the present disclosure in the array substrate are marked with numbers.
  • the image forming layer 300 is formed by an evaporation process.
  • the image forming layer 300 may include a plurality of sensor units 103 (only one is shown in the figure) having different thicknesses.
  • a light-shielding metal layer (may be simply referred to as light-shielding layer 106) is formed on the image forming layer 300 through a patterning process, which may be one layer or multiple layers.
  • a photoresist is formed on the light-shielding layer 106, and a patterned mask is used to expose and develop the photoresist to form a photoresist mask; then, the light-shielding layer 106 is dry-etched using the photoresist mask Etched to form an imaging hole 102.
  • the layer where the imaging pinhole 102 is located (the imaging pinhole layer 200) is the light-shielding layer 106.
  • the light-shielding layer 106 is disposed on the base substrate 101, and the original functional layer of the array substrate (including but not limited to pixel definition The layer 105, etc.) is provided above the light shielding layer 106.
  • FIG. 5 shows another schematic diagram of the distribution position of the imaging apertures 102 in the display area provided by another embodiment of the present disclosure.
  • FIG. 5 illustrates the basic structure of the array substrate, only the functional layers in the array substrate related to the technical solutions of the embodiments of the present disclosure are marked with numbers.
  • the image forming layer 300 is formed by an evaporation process.
  • the image forming layer 300 may include a plurality of sensor units 103 (only one is shown in the figure) having different thicknesses.
  • a light-shielding metal layer is formed on the image forming layer 300 through a patterning process, which may be one layer or multiple layers.
  • an active layer a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer dielectric layer, and a first source are sequentially formed through a patterning process
  • the passivation layer is formed by methods such as plasma enhanced chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), etc. Graphics.
  • PECVD plasma enhanced chemical vapor deposition
  • the second source and drain metal layer 109 is formed by a film forming method such as magnetron sputtering and thermal evaporation.
  • a photoresist is formed on the second source and drain metal layer 109, and a patterned mask is used to expose and develop the photoresist to form a photoresist mask; then, the photoresist mask is used to
  • the two source and drain metal layers 109 are dry-etched to form small holes 102 for imaging.
  • a flat layer may be formed after the second source and drain metal layer is formed, a photoresist is formed on the flat layer, and a patterned mask is used to expose and expose the photoresist.
  • a photoresist mask is used to dry or wet etch the flat layer to form a small hole for imaging, which penetrates the flat layer and the second source drain ⁇ metal layer.
  • the anode layer may also be formed after the flat layer is formed, and after the anode layer is formed, the pixel defining layer is formed, and a photoresist is formed on the pixel defining layer, and a patterned mask is used The plate exposes and develops the photoresist to form a photoresist mask; then, the photoresist mask is used to dry or wet etch the pixel defining layer to form small holes for imaging. Through the pixel defining layer and the flat layer.
  • the pixel defining layer 105 above the base substrate 101 is wet-etched with an opening 104, which is used to place a light emitting device.
  • the opening 104 and the orthographic projection of the imaging aperture 102 on the base substrate do not overlap.
  • the imaging function structure composed of the imaging aperture 102 and the sensor unit 103 can be arranged at the peripheral position of the original functional layer of the array substrate, and therefore is not Affect the work of the original functional layer.
  • the layer where the imaging aperture 102 is located can be made of a light-shielding material to block visible light.
  • the thickness of the imaging aperture can also be set to 3 to 4 ⁇ m. This thickness value can meet the development needs of ultra-thin performance while obtaining better imaging results.
  • the light-shielding material of the layer where the imaging apertures are located can be selected from polyimide and black light-absorbing materials doped in polyimide.
  • the black light-absorbing material can be similar to the material used in the black matrix in the liquid crystal display technology or carbon black.
  • the imaging aperture may be a circular hole with a diameter of 5-10 ⁇ m. And the imaging apertures are evenly distributed in the entire display area according to the area of the display area.
  • An embodiment of the present disclosure also provides a display device, which includes the array substrate 10 described in any of the foregoing embodiments.
  • the display device provided by the embodiment of the present disclosure integrates the camera function on the display screen, which prevents the front camera device from occupying the frame position of the display device, and facilitates the realization of a narrow-side screen and a full screen.
  • FIG. 8 shows a schematic flowchart of the imaging method of the display device provided by the embodiment of the present disclosure.
  • the imaging method of the display device provided by the embodiment of the present disclosure includes at least the following two steps:
  • Step 801 in response to the photographing mode activation signal, determine an imaging area according to the acquired image information, the imaging area including at least one sensor unit corresponding to the image information;
  • Step 802 Notifying the at least one sensor unit corresponding to the acquired image information to perform imaging work.
  • the image processor determines the imaging area used for imaging according to the light signal sent by the sensor unit 103.
  • the imaging area may include one or more sensor units 103 located in the display area and corresponding to a certain focal length. And after determining one or more sensor units 103 for imaging, the image processor notifies the one or more sensor units 103 to start forming an image of the object to be photographed.
  • the image information may be that the image processor determines the object distance between the object to be photographed and the imaging aperture according to the light signal sent by the sensor unit 103, or determines the focal length between the imaging plane of the sensor unit and the imaging aperture.
  • the imaging aperture and the corresponding sensor unit are arranged on the base substrate, that is, the imaging function is integrated in the display screen based on the imaging aperture principle, thereby overcoming the need for the front camera device in the related art to occupy the display.
  • the problem of the position of the device frame is conducive to the development of narrow-edge screens and full screens.
  • the distances between the multiple sensor units and the multiple imaging apertures corresponding to the multiple sensor units are different to meet the imaging requirements of different depths of field.
  • the shape and size of the imaging aperture and the material of the layer where the imaging aperture is located can also be designed to improve shooting clarity.
  • the vertical space of the display device can be compressed through the settings shared on the same layer.

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Abstract

本公开提供了阵列基板及其制备方法、显示装置及其成像方法。在一个实施例中，一种阵列基板，包括：衬底基板；和设置在衬底基板上方的多个成像小孔和多个传感器单元，其中，所述多个成像小孔分别位于所述多个传感器单元的上方，以使得每个所述成像小孔与每个所述传感器单元一一对应。

Description

阵列基板及其制备方法、显示装置及其成像方法
相关申请的交叉引用
本公开要求于2019年3月21日向中国国家知识产权局递交的中国专利申请201910219792.4的权益，该申请的公开内容通过引用整体并入本公开中。
技术领域
本公开一般涉及显示技术领域，尤其涉及阵列基板及其制备方法、显示装置及其成像方法。
背景技术
随着智能终端的快速发展，用户对终端设备的显示界面，提出了窄边框、全面屏等需求。但是，由于前置摄像装置的存在，屏占比问题一直找不到更好的解决方案。在一个实施例中有些厂商提出了升降式、弹出式摄像头，但这些方案难以避免的存在机械结构成本高、及镜头防尘等诸多问题。
相关技术中，前置摄像装置通常设置在显示装置的边框位置，这种结构设置不利于窄边框和全面屏的发展。
发明内容
一方面，本公开实施例提供了一种阵列基板，包括：
衬底基板；和
设置在衬底基板上方的多个成像小孔和多个传感器单元，其中，所述多个成像小孔分别位于所述多个传感器单元的上方，以使得每个所述成像小孔与每个所述传感器单元一一对应。
在一些实施例中，所述多个传感器单元设置成具有不同的厚度，以使得所述多个传感器单元和与之对应的所述多个成像小孔之间的距离是不同的。
在一些实施例中，该阵列基板还包括：设置在所述衬底基板上方的遮光金属层，其中，所述多个成像小孔位于所述遮光金属层中。
在一些实施例中，该阵列基板还包括：设置在所述衬底基板上方的第一源极漏极金属层和第二源极漏极金属层，其中，所述多个成像小孔位于所述第二源极漏极金属层中。
在一些实施例中，该阵列基板还包括：设置在所述衬底基板上方的像素界定层，在所述像素界定层中设置用于设置发光器件的多个开口；其中，所述多个开口在所述衬底基板上的正投影与所述多个成像小孔在所述衬底基板上的正投影不重叠。
在一些实施例中，该阵列基板还包括：设置在所述衬底基板上方且所述像素界定层下方的平坦层；其中，所述多个成像小孔贯穿所述像素界定层和所述平坦层，或者，所述多个成像小孔贯穿所述平坦层。
在一些实施例中，每个所述成像小孔的厚度约为3～4微米；和/或，每个所述成像小孔为直径约为5～10微米的圆孔。
又一方面，本公开实施例提供了一种阵列基板的制备方法，包括：
在衬底基板上通过蒸镀工艺形成多个传感器单元；以及
在所述多个传感器单元的上方，通过构图工艺形成金属层，在所述金属层中形成多个成像小孔，其中，所述多个成像小孔分别位于所述多个传感器单元的上方，以使得每个所述成像小孔与每个所述传感器单元一一对应。
在一些实施例中，所述多个传感器单元通过蒸镀工艺分别形成为具有不同的厚度，以使得所述多个传感器单元和与之对应的所述多个成像小孔之间的距离是不同的。
在一些实施例中，所述金属层包括在所述传感器单元的上方通过构图工艺形成的遮光金属层，所述成像小孔位于该遮光金属层中。
在一些实施例中，所述金属层包括在所述多个传感器单元的上方通过构图工艺形成的第一源极漏极金属层和第二源极漏极金属层，其中，所述多个成像小孔位于所述第二源极漏极金属层中。
在一些实施例中，该制备方法还包括：通过构图工艺在所述衬底基板上方形成像素界定层；在所述像素界定层上形成多个开口，所述多个开口在所述衬底基板上的正投影与所述多个成像小孔的在所述衬底基板上的正投影不重叠。
在一些实施例中，该制备方法还包括：通过构图工艺在所述像素界定层下方形成平坦层；通过刻蚀工艺使得所述多个成像小孔贯穿所述像素界定层和所述平坦层，或者通过刻蚀工艺使得所述多个成像小孔贯通所述平坦层。
另一方面，本公开实施例提供了一种显示装置，包括：如前述任一实施例所述的阵列基板。
还一方面，本公开实施例提供了一种成像方法，应用于如前述任一实施例所述的显示装置，该方法包括：
响应于拍照模式启动信号，根据获取的图像信息确定成像区域，所述成像区域包括与所述图像信息对应的至少一个传感器单元，所述图像信息包括待拍摄对象的物距或者所述至少一个传感器单元的焦距；和
通知与所述图像信息对应的所述至少一个传感器单元进行成像工作。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本公开的其它特征、目的和优点将会变得更明显：
图1示出了本公开一个实施例提供的阵列基板的结构示意图；
图2示出了本公开另一个实施例提供的阵列基板的结构示意图；
图3示出了本公开又一个实施例提供的阵列基板的结构示意图；
图4示出了本公开一个实施例提供的成像小孔在显示区域中的分布位置示意图；
图5示出了本公开另一个实施例提供的成像小孔在显示区域中的分布位置示意图；
图6示出了本公开实施例提供的阵列基板中光线通过成像小孔在图像形成层中成像的原理示意图；
图7示出了本公开实施例提供的阵列基板中成像区域划分示意图；
图8示出了本公开实施例提供的显示装置的成像方法的流程示意图。
具体实施方式
下面结合附图和实施例对本公开作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关公开，而非对该公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与公开相关的部分。
需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本公开。
相关技术中，前置摄像装置通常可能设置在显示装置的边框位置，由于摄像装置自身的结构需求，需要占据一定的位置空间，使得显示屏幕的扩大受到了局限性，前置摄像装置的存在，不利于窄边框和全面屏的发展。
本公开提出了一种阵列基板。请参考图1，图1示出了本公开一个实施例提供的阵列基板的结构示意图。
如图1所示，该阵列基板10包括：衬底基板101；和设置在衬底基板101上方的多个成像小孔102和多个传感器单元103。其中，多个成像小孔102分别位于多个传感器单元103的上方，以使得每个成像小孔102与每个光传感单元103一一对应。
为了解决相关技术中前置摄像装置占用显示装置的边框的问题，本公开的技术构思是将摄像功能集成到显示屏中。本公开实施例中，通过在阵列基板的显示区域中设置成像小孔102和与之对应的传感器单元103，根据成像小孔原理将成像功能集成在显示区域，从而解决了相关技术摄像装置占用显示装置的边框位置的问题。为了便于解释和说明，本文中将成像小孔102所在的层定义为成像小孔层200，而传感器单元103所在的层定义为图像形成层300。需要说明的是，根据本公开不同实施例，成像小孔既可以形成为独立的成像小孔层(例如遮光金属层或第二源极漏极金属层)，也可以形成在阵列基板的原有功能层(例如平坦层或像素界定层)中。在后一情况下，成像小孔层与形成在阵列基板的原有功能层(例如平坦层或像素界定层)为同一层，例如成像小孔形成在平坦层或像素界定层中。还需要说明的是，为了清楚阐述本公开的技术方案，在本说明书中仅说明和解释与本案技术方案相关的结构和/或功能，与此同时附图中也仅展示与本案技术方案相关的结构。本领域技术人员应该了解，虽然未在本说明书和附图中展示，本公开实施例提供的阵列基板和显示装置还应该包括必要的结构和部件。
本公开实施例提出的阵列基板中，衬底基板101可以是柔性基板。柔性基板是指可弯曲的、可折叠的或者可卷曲的基板。柔性基板的材料可以是超薄玻璃、金属或者塑料。例如聚合树脂、聚酰亚胺等。
本公开实施例提出的阵列基板中，成像小孔层(即成像小孔102所在的层)200可以为金属层。金属层例如可以是遮光金属层，或者例如可以是第二层源极漏极金属层。在前一情况下工艺简单，成本低，但存在杂散光问题。在后一情况下可以解决杂散光，获得较大透光率，但成本较高。
在一个实施例中，阵列基板可以包括：设置在衬底基板101上方的遮光金属层，则成像小孔位于该金属层中。此时，图1中成像小孔层(即成像小孔102所在的层)200为遮光金属层。
在另一个实施例中，阵列基板可以包括：设置在衬底基板101上方的第一源极漏极金属层和第二源极漏极金属层，则成像小孔位于第二源极漏极金属层中。此时，图1中成像小孔层(即成像小孔102所在的层)200为第二源极漏极金属层。
在启动拍摄模式时，入射光线透过成像小孔102，根据小孔成像原理，来自待拍摄对象的不同部分的光线在到达传感器单元103时，在传感器单元103中形成与待拍摄对象倒立的图像。成像小孔102的大小和传感器单元103与成像小孔102之间的距离(该距离即像距)决定着成像的清晰度。
传感器单元103也可以称为图像传感器，例如可以是电荷耦合元件(Charge-coupled Device，CCD)，互补型金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)等。对传感器单元的具体位置没有特别限定，只要能够确保传感器单元位于与之对应的成像小孔和衬底基板之间，并且成像小孔和与之对应的传感器单元的距离能够满足成像要求即可。在一个实施例中，传感器单元直接设置在衬底基板上。在另一个实施例中，传感器单元设置在其它功能层中。
本公开实施例提供的阵列基板10，考虑到不同焦距的成像需求，在上述阵列基板中，可以将多个传感器单元103设置成具有不同的厚度，以使得多个传感器单元103和与之对应的多个成像小孔102之间的距离是不同的。也就是说，不同传感器单元103到其对应的成像小孔102的距离可以设置成不同值。例如可以如图1所示，与不同成像小孔102对应的传感器单元103的厚度不同。这样，传感器单元103的远离衬底基板101的表面(即成像平面)到与该传感器单元103对应的成像小孔102的距离可以是不同的。例如也可以如图7所示，将显示区域划分成不同成像区域，并将不同成像区域内包含的传感器单元103设置成具有不同的厚度。可以理解为将成像区域A11包含的至少一个传感器单元103设置成第一厚度值，将成像区域A12包含的至少一个传感器单元103设置成第二厚度值，依此类 推，不同成像区域中的传感器单元103具有不同的厚度值。不同成像区域是否需要划分可以根据成像区域占用屏幕的比例来确定。在一个实施例中，一个成像区域的景深满足成像范围的需求，可以仅整个显示区域全屏采用一个成像区域。如果一个成像区域的景深不能满足成像范围的需求，可以根据其覆盖屏幕的比例，将整个显示区域屏幕划分成多个成像区域。
通过设置具有不同厚度的传感器单元103以满足不同成像焦距的需求，扩大成像范围。
本公开实施例提供的阵列基板10，还可以在多个成像小孔102所在的成像小孔层200与多个传感器单元103所在的图像形成层300之间形成缓冲层107，如图6所示。
进一步地，考虑到背光光源的工作会对成像效果造成影响，本公开实施例还提出了阵列基板的另一种结构。请参考图2，图2示出了本公开另一实施例提供的阵列基板10的结构示意图。
如图2所示，该阵列基板10包括：衬底基板101，设置在衬底基板101上方的多个成像小孔102和多个传感器单元103，和设置在衬底基板101上方的像素界定层105，其中，多个成像小孔102分别位于多个传感器单元103的上方，以使得每个成像小孔102与每个光传感单元103一一对应；在像素界定层105上设置用于设置发光器件的多个开口104；开口104在衬底基板101上的正投影与成像小孔102在衬底基板101上的正投影不重叠。多个成像小孔102所在的层定义为成像小孔层200，而传感器单元103所在的层定义为图像形成层300。
在本公开上述实施例中，成像小孔102、传感器单元103和开口104均位于阵列基板10的显示区域中。
本公开实施例提供的阵列基板，通过增设多个成像小孔102所在的成像小孔层200和多个传感器单元103所在的图像形成层300，基于小孔成像原理实现显示屏集成摄像功能。
为了满足摄像功能的不同焦距成像需求，可以将多个传感器单元103设置成具有不同的厚度值，以使得多个传感器单元103和与之对应的多个成像小孔102之间的距离是不同的。在一个实施例中，可以参考图6，其示出了光线通过成像小孔102在传感器单元103所在的图像形成层300中成像的原理示意图。如图6所示，其中h1～h5表示待拍摄对象到成像小孔102的距离，通常可以称为物距。在不同物距的情况下，为了形成与不同物距对应的清晰的成像结果，需要调整传感器单元103的位置，使得其成像平面到成像小孔102的距离能够在不同物距下拍摄出清晰的图像。成像平面到成像小孔的距离即像距，也称为焦距。在本公开实施例中，例如可以将图像形成层300的多个传感器单元102设计成具有不同的厚度，以使得多个传感器单元103和与之对应的多个成像小孔102之间的距离是不同的，从而使其距离成像小孔的距离符合焦距的设置需求。
本公开实施例中，可以根据具有不同焦距的多个传感器单元在显示屏幕部署时占用屏幕的比例，来决定是否将传感器单元进行区域划分。图7示出了本公开实施例提供的成像区域划分示意图。如图7所示，可以将多个传感器单元103根据不同的焦距划分到不同的区域中。例如，在A11区域内部署具有第一焦距的多个传感器单元103，用于形成与第一焦距对应的待拍摄对象的清晰图像，其成像结果可以对应图6中物距为h1的拍摄范围，第一焦距即图6中标识h1下方的传感器单元103与成像小孔102之间的距离。为了满足变焦功能，可以在A12区域内部署具有第二焦距的多个传感器单元103，用于形成与第二焦距对应的待拍摄对象的清晰图像，其成像结果可以对应图6中物距为h2的拍摄范围，第二焦距即图6中标识h2下方的传感器单元103与成像小孔102之间的距离。以此类推，可以根据划分区域占用屏幕的比例，将整个显示区域划分为多个子区域，每个子区域分别对应不同拍摄焦距的成像区域。
在拍照时，如果背光光源工作，则其发射的光可能对处于拍摄模式的 成像小孔造成影响，导致通过成像小孔形成的图像效果不佳。本公开实施例，通过将用于设置发光器件的开口104的位置与成像小孔102的位置设置为在衬底基板上的正投影不重合，从而解决因背光导致成像效果不佳的问题。
进一步地，为了避免杂散光对成像结果造成影响，导致成像效果不好，成像小孔102所在的层(即成像小孔层200)可以采用遮光材料，用于遮挡可见光。在一个实施例中，成像小孔102所在的层的材料可以选择包括聚酰亚胺以及掺杂在聚酰亚胺中的黑色吸光物质以便实现遮挡可见光，从而提升成像质量。
进一步地，显示装置整体向超薄方向发展，为了获取更好的成像效果，还可以将成像小孔102的厚度设置约为3～4μm，该取值范围可以兼具成像效果和超薄性能。
本公开实施例中，还可以将多个成像小孔102均匀地分布在整个显示区域。成像小孔102的形状可以设置多种形状，根据其透光效果，可以设置成圆孔形状，例如直径设置约为5～10μm。
本公开实施例中，在设置成像小孔102时，可以考虑进一步节省显示器件的垂直空间，压缩显示器件。请参考图3，图3示出了本公开又一实施例提供的阵列基板10的结构示意图。以下主要描述图3所示的实施例与前述实施例的不同之处。
如图3所示，将用于设置发光器件的多个开口104所在的像素界定层105以及位于衬底基板101和像素界定层105之间的平坦层(图中未示出)两者共同用作多个成像小孔102位于其中的成像小孔层200。也就是说，像素界定层105、平坦层和成像小孔层200共用同一层，即为同一层。此时，可以理解为成像小孔102贯穿像素界定层105、平坦层和成像小孔层200。
在未图示的可替换实施例中，可将位于衬底基板和用于设置发光器件 的多个开口所在的像素界定层之间的平坦层用作多个成像小孔位于其中的成像小孔层。也就是说，平坦层和成像小孔层共用同一层。此时，可以理解为成像小孔同时贯穿平坦层和成像小孔层。
本公开实施例中通过将平坦层、或平坦层和像素界定层两者设计为与成像小孔层共用同一层，能够有效地节省显示器件的厚度空间，并获得较好的成像效果。
为了更进一步清楚地描述制备本公开实施例提供的阵列基板的过程，本公开实施例还提供一种阵列基板的制备方法，该方法包括：
在衬底基板101上通过蒸镀工艺形成多个传感器单元103；
在多个传感器单元103的上方，通过构图工艺形成金属层，在金属层中形成多个成像小孔，其中，多个成像小孔103分别位于多个传感器单元103的上方，以使得每个成像小孔102与每个传感器单元103一一对应，其结构如图1所示。
进一步地，传感器单元103可以通过蒸镀工艺形成不同的厚度的感光层。例如，某个传感器单元103或者某组(多个)传感器单元103通过蒸镀工艺形成同一厚度值的感光层，或者通过多次蒸镀工艺形成多层感光层，以形成同一厚度值。
本公开实施例中可以在衬底基板101上，通过构图工艺形成金属层。该金属层可以是遮光金属层，或者，形成第一源极漏极金属层和第二源极漏极金属层。构图工艺包括：光刻胶涂布、掩膜、曝光、显影、刻蚀、光刻胶剥离等部分或者全部工艺。
本公开实施例中，在上述金属层中形成成像小孔，可以采用干刻蚀的工艺。在一个实施例中，如图4所示，图4示出了本公开实施例提供的成像小孔102在显示区域中的分布位置示意图。为了清晰的目的，图4虽然示意了阵列基板的基本结构，但是仅对阵列基板中与本公开实施例的技术方案相关的功能层用数字标号进行标注。
在制备衬底基板101之后，通过蒸镀工艺形成图像形成层300，在图像形成层300可以包括具有不同厚度的多个传感器单元103(图中仅示出一个)。
然后，通过构图工艺在图像形成层300上方形成遮光金属层(可以简称为遮光层106)，可以一层或者多层。在遮光层106上形成光刻胶，采用刻有图案的掩膜版对光刻胶进行曝光和显影，形成光刻胶掩膜；然后，采用光刻胶掩膜对遮光层106进行干法刻蚀，形成成像小孔102。
在图4中，成像小孔102所在的层(成像小孔层200)为遮光层106，遮光层106设置在衬底基板101上，而阵列基板的原有功能层(包括但不限于像素限定层105等)设置在遮光层106的上方。也可以如图5所示，图5示出了本公开另一实施例提供的成像小孔102在显示区域中的又一分布位置示意图。为了清晰的目的，图5虽然示意了阵列基板的基本结构，但是仅对阵列基板中与本公开实施例的技术方案相关的功能层用数字标号进行标注。
在制备衬底基板101之后，通过蒸镀工艺形成图像形成层300，在图像形成层300可以包括具有不同厚度的多个传感器单元103(图中仅示出一个)。
也可以理解为采用蒸镀工艺在不同材质的缓冲层中形成传感器单元。
然后，通过构图工艺在图像形成层300上方形成遮光金属层，可以一层或者多层。
在遮光层上方，通过构图工艺依次形成有源层、第一栅极绝缘层、第一栅极金属层、第二栅极绝缘层、第二栅极金属层、层间介质层、第一源极漏极金属层108、钝化层、第二源极漏极金属层109、平坦层110、阳极层、像素界定层105。
在通过磁控溅射、热蒸发等成膜方法形成第一源极漏极金属层108之后，再通过等离子体增强化学的气相沉积法(PECVD，Plasma Enhanced  Chemical Vapor Deposition)等方法形成钝化层的图形。然后，通过磁控溅射、热蒸发等成膜方法形成第二源极漏极金属层109。
在第二源极漏极金属层109上形成光刻胶，采用刻有图案的掩膜版对光刻胶进行曝光和显影，形成光刻胶掩膜；然后，采用光刻胶掩膜对第二源极漏极金属层109进行干法刻蚀，形成用于成像的小孔102。
在未图示的实施例中，还可以在形成第二源极漏极金属层之后形成平坦层，在平坦层上形成光刻胶，采用刻有图案的掩膜版对光刻胶进行曝光和显影，形成光刻胶掩膜；然后，采用光刻胶掩膜对平坦层进行干法或湿法刻蚀，形成用于成像的小孔，该成像小孔贯穿平坦层和第二源极漏极金属层。
在未图示的实施例中，还可以在形成平坦层之后形成阳极层，在形成阳极层成之后，再形成像素界定层，在像素界定层上形成光刻胶，采用刻有图案的掩膜版对光刻胶进行曝光和显影，形成光刻胶掩膜；然后，采用光刻胶掩膜对像素界定层进行干法或湿法刻蚀，形成用于成像的小孔，该成像小孔贯穿像素界定层和平坦层。
在图5所示的实施例中，在形成成像小孔102之后，在衬底基板101上方的像素界定层105上采用湿法刻蚀开孔104，该开孔用于放置发光器件。开孔104与成像小孔102的在衬底基板上的正投影不重叠。
从图4和图5中可知，根据本公开实施例提供的阵列基板中，由成像小孔102和传感器单元103构成的摄像功能结构可以设置在阵列基板的原有功能层的周边位置，因而不影响原有功能层的工作。
在制备成像小孔时，考虑到成像效果可以将成像小孔102所在的层采用遮光材料制成，用于遮挡可见光。还可以将成像小孔的厚度设置为3～4μm。该厚度值可以兼备超薄性能发展需求的同时获得较好的成像效果。
成像小孔所在的层的遮光材料可以选择聚酰亚胺以及掺杂在聚酰亚胺中的黑色吸光物质。其中，黑色吸光物质例如可以类似液晶显示技术中 黑色矩阵所采用的材料或者炭黑等。
在一个实施例中，成像小孔可以设置为圆孔，其直径设置5～10μm。并将成像小孔根据显示区域的面积均匀分布在整个显示区域中。
本公开实施例还提供了一种显示装置，包括上述任一实施例所述的阵列基板10。本公开实施例提供的显示装置将摄像功能集成在显示屏上，避免了前置摄像装置占用显示装置的边框位置，有利于实现窄边屏和全面屏。
为了更清楚地描述本公开实施例提供的显示装置的成像原理，请参考图8，图8示出了本公开实施例提供的显示装置的成像方法的流程示意图。本公开实施例提供的显示装置的成像方法至少包括如下两个步骤：
步骤801，响应于拍照模式启动信号，根据获取的图像信息确定成像区域，该成像区域包括与图像信息对应的至少一个传感器单元；以及
步骤802，通知与所获取的图像信息对应的所述至少一个传感器单元进行成像工作。
在拍照模式启动时，来自待拍摄对象的各个部位的光透过均匀分布在显示区域中的成像小孔102，直接透射到传感器单元103，传感器单元103将光信号记录并发送至图像处理器。图像处理器根据传感器单元103发送的光信号确定用于成像的成像区域。其中，成像区域可以包括位于显示区域内与某焦距对应的一个或多个传感器单元103。并在确定用于成像的一个或多个传感器单元103之后，图像处理器通知所述一个或多个传感器单元103开始形成待拍摄对象的图像。
图像信息，例如可以是图像处理器根据传感器单元103发送的光信号，确定待拍摄对象和成像小孔之间的物距，或者确定传感器单元的成像平面和成像小孔之间的焦距。
本公开实施例通过在衬底基板上设置成像小孔和与之对应的传感器单元，即基于成像小孔原理将摄像功能集成在显示屏中，从而克服了相关技术中前置摄像装置需要占用显示装置边框位置的问题，有利于窄边屏和 全面屏的发展。此外，通过设置传感器单元的不同厚度，以使得多个传感器单元和与之对应的多个成像小孔之间的距离是不同的，来满足不同景深的摄像需求。此外，还可以设计成像小孔的形状大小以及成像小孔所在层的材料，来提高拍摄清晰度。此外，还可以通过同层共享的设置压缩显示装置的垂直空间。
以上描述仅为本公开的示例性实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本公开中所涉及的公开范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离前述公开构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本公开中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (15)

  1. 一种阵列基板，包括：
    衬底基板；和
    设置在衬底基板上方的多个成像小孔和多个传感器单元，其中，所述多个成像小孔分别位于所述多个传感器单元的上方，以使得每个所述成像小孔与每个所述传感器单元一一对应。
  2. 根据权利要求1所述的阵列基板，其中，所述多个传感器单元设置成具有不同的厚度，以使得所述多个传感器单元和与之对应的所述多个成像小孔之间的距离是不同的。
  3. 根据权利要求1或2所述的阵列基板，还包括：设置在所述衬底基板上方的遮光金属层，其中，所述多个成像小孔位于所述遮光金属层中。
  4. 根据权利要求1或2所述的阵列基板，还包括：设置在所述衬底基板上方的第一源极漏极金属层和第二源极漏极金属层，其中，所述多个成像小孔位于所述第二源极漏极金属层中。
  5. 根据权利要求1或2所述的阵列基板，还包括：设置在所述衬底基板上方的像素界定层，在所述像素界定层中设置用于设置发光器件的多个开口；
    其中，所述多个开口在所述衬底基板上的正投影与所述多个成像小孔在所述衬底基板上的正投影不重叠。
  6. 根据权利要求5所述的阵列基板，还包括：
    设置在所述衬底基板上方且所述像素界定层下方的平坦层；
    其中，所述多个成像小孔贯穿所述像素界定层和所述平坦层，或者，所述多个成像小孔贯穿所述平坦层。
  7. 根据权利要求1或2所述的阵列基板，其中，每个所述成像小孔的厚度约为3～4微米；和/或，每个所述成像小孔为直径约为5～10微米的圆孔。
  8. 一种阵列基板的制备方法，包括：
    在衬底基板上通过蒸镀工艺形成多个传感器单元；以及
    在所述多个传感器单元的上方，通过构图工艺形成金属层，在所述金属层中形成多个成像小孔，其中，所述多个成像小孔分别位于所述多个传感器单元的上方，以使得每个所述成像小孔与每个所述传感器单元一一对应。
  9. 根据权利要求8所述的阵列基板的制备方法，其中，所述多个传感器单元通过蒸镀工艺分别形成为具有不同的厚度，以使得所述多个传感器单元和与之对应的所述多个成像小孔之间的距离是不同的。
  10. 根据权利要求8或9所述的阵列基板的制备方法，其中，所述金属层包括在所述传感器单元的上方通过构图工艺形成的遮光金属层，所述成像小孔位于该遮光金属层中。
  11. 根据权利要求8或9所述的阵列基板的制备方法，其中，所述金属层包括在所述多个传感器单元的上方通过构图工艺形成的第一源极漏极金属层和第二源极漏极金属层，其中，所述多个成像小孔位于所述第二源极漏极金属层中。
  12. 根据权利要求8或9所述的阵列基板的制备方法，还包括：通过构图工艺在所述衬底基板上方形成像素界定层；
    在所述像素界定层上形成多个开口，所述多个开口在所述衬底基板上的正投影与所述多个成像小孔的在所述衬底基板上的正投影不重叠。
  13. 根据权利要求8或9所述的阵列基板的制备方法，还包括：
    通过构图工艺在所述像素界定层下方形成平坦层；
    通过刻蚀工艺使得所述多个成像小孔贯穿所述像素界定层和所述平坦层，或者通过刻蚀工艺使得所述多个成像小孔贯通所述平坦层。
  14. 一种显示装置，包括：如权利要求1-7中任一项所述的阵列基板。
  15. 一种成像方法，应用于如权利要求14所述的显示装置，该方法包括：
    响应于拍照模式启动信号，根据获取的图像信息确定成像区域，所述成像区域包括与所述图像信息对应的至少一个传感器单元，所述图像信息包括待拍摄对象的物距或者所述至少一个传感器单元的焦距；和
    通知与所述图像信息对应的所述至少一个传感器单元进行成像工作。
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Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA3002752A1 (en) 2015-10-26 2017-05-04 Oti Lumionics Inc. Method for patterning a coating on a surface and device including a patterned coating
KR20260049653A (ko) 2016-12-02 2026-04-14 오티아이 루미오닉스 인크. 방출 영역 위에 배치된 전도성 코팅을 포함하는 디바이스 및 이를 위한 방법
KR20250036969A (ko) 2017-04-26 2025-03-14 오티아이 루미오닉스 인크. 표면의 코팅을 패턴화하는 방법 및 패턴화된 코팅을 포함하는 장치
KR20260023089A (ko) 2017-05-17 2026-02-20 오티아이 루미오닉스 인크. 패턴화 코팅 위에 전도성 코팅을 선택적으로 증착시키는 방법 및 전도성 코팅을 포함하는 디바이스
US11751415B2 (en) 2018-02-02 2023-09-05 Oti Lumionics Inc. Materials for forming a nucleation-inhibiting coating and devices incorporating same
US11489136B2 (en) 2018-05-07 2022-11-01 Oti Lumionics Inc. Method for providing an auxiliary electrode and device including an auxiliary electrode
JP2022508040A (ja) 2018-11-23 2022-01-19 オーティーアイ ルミオニクス インコーポレーテッド 光透過領域を含むオプトエレクトロニクスデバイス
CN116456753A (zh) 2019-03-07 2023-07-18 Oti照明公司 一种光电子器件
CN109830495B (zh) 2019-03-21 2021-10-08 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置及其成像方法
KR20250110358A (ko) 2019-04-18 2025-07-18 오티아이 루미오닉스 인크. 핵 생성 억제 코팅 형성용 물질 및 이를 포함하는 디바이스
WO2020225778A1 (en) 2019-05-08 2020-11-12 Oti Lumionics Inc. Materials for forming a nucleation-inhibiting coating and devices incorporating same
CN114097102B (zh) 2019-06-26 2023-11-03 Oti照明公司 包括具有光衍射特征的光透射区域的光电设备
US11832473B2 (en) 2019-06-26 2023-11-28 Oti Lumionics Inc. Optoelectronic device including light transmissive regions, with light diffraction characteristics
WO2021028800A1 (en) 2019-08-09 2021-02-18 Oti Lumionics Inc. Opto-electronic device including an auxiliary electrode and a partition
WO2021092887A1 (en) * 2019-11-15 2021-05-20 Qualcomm Incorporated Display shade compensation for cameras
JP7403883B2 (ja) 2019-12-24 2023-12-25 オーティーアイ ルミオニクス インコーポレーテッド キャッピング層を含む発光デバイスおよびそれを製造するための方法
CN112071205B (zh) * 2020-09-11 2022-03-08 武汉华星光电半导体显示技术有限公司 一种粘结结构及其制备方法、盖板及其制备方法
US12113279B2 (en) 2020-09-22 2024-10-08 Oti Lumionics Inc. Device incorporating an IR signal transmissive region
US12672476B2 (en) 2020-10-29 2026-06-30 Oti Lumionics Inc. Opto-electronic device with nanoparticle deposited layers
WO2022097043A1 (en) 2020-11-03 2022-05-12 Oti Lumionics Inc. Silicon-containing compounds for forming a patterning coating and devices incorporating same
KR20250139404A (ko) 2020-12-07 2025-09-23 오티아이 루미오닉스 인크. 핵 생성 억제 코팅 및 하부 금속 코팅을 사용한 전도성 증착 층의 패턴화
US12689817B2 (en) * 2024-02-05 2026-07-21 Dell Products L.P. Display device having an integrated camera aperture system

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106847092A (zh) * 2017-03-10 2017-06-13 京东方科技集团股份有限公司 一种显示面板、显示装置及其获取图像的方法
CN107832749A (zh) * 2017-12-14 2018-03-23 京东方科技集团股份有限公司 一种阵列基板、其制备方法、指纹识别方法及显示装置
CN107977632A (zh) * 2017-12-05 2018-05-01 京东方科技集团股份有限公司 一种阵列基板、显示装置及其纹路识别方法
CN108242453A (zh) * 2016-12-23 2018-07-03 京东方科技集团股份有限公司 一种oled显示面板及显示装置
CN108878501A (zh) * 2018-07-16 2018-11-23 成都京东方光电科技有限公司 一种显示基板及其制作方法、显示装置
CN108922905A (zh) * 2018-07-17 2018-11-30 京东方科技集团股份有限公司 一种显示基板及制备方法、显示面板
CN208271897U (zh) * 2018-03-16 2018-12-21 华为技术有限公司 一种显示屏及显示终端
CN109449181A (zh) * 2018-10-29 2019-03-08 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN109830495A (zh) * 2019-03-21 2019-05-31 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置及其成像方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030007089A1 (en) * 2001-01-12 2003-01-09 Anteon Corporation Opto-electronic video compression system
JP4886162B2 (ja) * 2003-06-18 2012-02-29 キヤノン株式会社 撮像装置付き表示装置
CN100449764C (zh) * 2003-11-18 2009-01-07 松下电器产业株式会社 光电探测器
US9450005B2 (en) * 2013-03-29 2016-09-20 Sony Corporation Image pickup device and image pickup apparatus

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108242453A (zh) * 2016-12-23 2018-07-03 京东方科技集团股份有限公司 一种oled显示面板及显示装置
CN106847092A (zh) * 2017-03-10 2017-06-13 京东方科技集团股份有限公司 一种显示面板、显示装置及其获取图像的方法
CN107977632A (zh) * 2017-12-05 2018-05-01 京东方科技集团股份有限公司 一种阵列基板、显示装置及其纹路识别方法
CN107832749A (zh) * 2017-12-14 2018-03-23 京东方科技集团股份有限公司 一种阵列基板、其制备方法、指纹识别方法及显示装置
CN208271897U (zh) * 2018-03-16 2018-12-21 华为技术有限公司 一种显示屏及显示终端
CN108878501A (zh) * 2018-07-16 2018-11-23 成都京东方光电科技有限公司 一种显示基板及其制作方法、显示装置
CN108922905A (zh) * 2018-07-17 2018-11-30 京东方科技集团股份有限公司 一种显示基板及制备方法、显示面板
CN109449181A (zh) * 2018-10-29 2019-03-08 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN109830495A (zh) * 2019-03-21 2019-05-31 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置及其成像方法

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