WO2020186736A1 - 功率器件及电器 - Google Patents

功率器件及电器 Download PDF

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Publication number
WO2020186736A1
WO2020186736A1 PCT/CN2019/110971 CN2019110971W WO2020186736A1 WO 2020186736 A1 WO2020186736 A1 WO 2020186736A1 CN 2019110971 W CN2019110971 W CN 2019110971W WO 2020186736 A1 WO2020186736 A1 WO 2020186736A1
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WIPO (PCT)
Prior art keywords
circuit
output
switch tube
terminal
sub
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PCT/CN2019/110971
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English (en)
French (fr)
Inventor
冯宇翔
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广东美的制冷设备有限公司
美的集团股份有限公司
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Publication of WO2020186736A1 publication Critical patent/WO2020186736A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • This application relates to the technical field of electrical appliances, and more specifically, to a power device and an electrical appliance.
  • IPM Intelligent Power Module
  • the threshold voltage (3V) of GaN devices, the threshold voltage (20V) of SiC devices and the threshold voltage (15V) of Si devices are different.
  • the threshold voltage of GaN devices is lower than that of Si devices. If the same high-voltage integrated circuit (HVIC) is used for driving, it is easy to cause the gate of GaN devices to be broken down; the threshold voltage of SiC devices is higher than If the threshold voltage of Si devices is driven by the same high-voltage integrated circuit tube, the turn-on process of SiC devices is likely to be incomplete, and the low power consumption advantages of SiC devices cannot be used.
  • HVIC high-voltage integrated circuit
  • the high-voltage integrated circuit tube driving the Si device uses a lower voltage for power supply, which will easily increase the power consumption of the entire Si device smart power module, and even cause the Si device to fail to work normally.
  • This application provides a power device and an electrical appliance.
  • the power device of the present application includes a control input terminal, an upper bridge arm switch tube, and a lower bridge arm switch tube, a first drive circuit connected to the control input terminal and used to drive the upper bridge arm switch tube, and the control The input terminal is connected and used to drive the second driving circuit of the lower-arm switch tube.
  • the control input terminal can be connected to the first level, the second level or the third level.
  • the first driving circuit and the second driving circuit output high and low level signals in the first voltage range.
  • the control input terminal is connected to the second level
  • the first driving circuit and the second driving circuit output high and low level signals in the second voltage range.
  • the control input terminal is connected to the third level
  • the first driving circuit and the second driving circuit output high and low level signals in the third voltage range.
  • the first voltage range, the second voltage range, and the third voltage range are different.
  • the electrical appliance in the embodiment of the present application includes the above-mentioned power device and a processor, and the processor is connected to the power device.
  • the power devices and electrical appliances in the embodiments of the present application can output multiple high and low level signals with different voltage ranges to adapt to different types of devices (such as GaN devices, SiC devices, and Si devices) without changing the external input voltage.
  • devices such as GaN devices, SiC devices, and Si devices
  • the use requirements, the conduction process of different types of devices are in a fully conductive state, and their performance is fully utilized.
  • first driving circuit and second driving circuit can be used to output high and low level signals in different voltage ranges, there is no risk of mixing materials in the production process of power devices, which facilitates material organization and reduces material costs.
  • FIG. 1 is a circuit structure diagram of a power device according to some embodiments of the application.
  • FIG. 2 is a schematic diagram of connecting a control input terminal to a power supply or ground through a bonding wire of a power device according to some embodiments of the application;
  • FIG. 3 is a schematic diagram of a module of a power device according to an embodiment of the application.
  • FIGS. 4 to 11 are schematic diagrams of the structure of the upper bridge arm switch tube and the lower bridge arm switch tube of some embodiments of this application;
  • FIG. 12 is a schematic diagram of a UH driving circuit according to some embodiments of the application.
  • FIG. 13 is a schematic diagram of a VH driving circuit according to some embodiments of this application.
  • FIG. 14 is a schematic diagram of a WH driving circuit according to some embodiments of the application.
  • FIG. 15 is a schematic diagram of a UL/VL/WL driving circuit according to some embodiments of the application.
  • FIG. 16 is a schematic diagram of modules of an electrical appliance according to some embodiments of this application.
  • the “on” or “under” of the first feature on the second feature may be in direct contact with the first and second features, or indirectly through an intermediary. contact.
  • the "above”, “above” and “above” of the first feature on the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the level of the first feature is higher than the second feature.
  • the “below”, “below” and “below” of the second feature of the first feature may mean that the first feature is directly below or obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • an embodiment of the present application provides a power device 100.
  • the power device 100 of the present application includes a control input terminal SS, an upper bridge arm switch tube 127, and a lower bridge arm switch tube 128, which are connected to the control input terminal SS and used
  • the first driving circuit 129 for driving the high-side switch tube 127 is connected to the control input terminal SS and is used for driving the second driving circuit 120 of the low-side switch tube 128.
  • the control input terminal SS can be connected to the first level, the second level or the third level. When the control input terminal SS is connected to the first level, the first driving circuit 129 and the second driving circuit 120 output high and low level signals in the first voltage range.
  • the first driving circuit 129 and the second driving circuit 120 When the control input terminal SS is connected to the second level, the first driving circuit 129 and the second driving circuit 120 output high and low level signals in the second voltage range.
  • the control input terminal SS When the control input terminal SS is connected to the third level, the first driving circuit 129 and the second driving circuit 120 output high and low level signals in the third voltage range.
  • the first voltage range, the second voltage range, and the third voltage range are different.
  • the power device 100 of the present application can output high and low level signals in different voltage ranges without changing the external input voltage to meet the requirements of different types of devices (such as GaN devices, SiC devices, and Si devices).
  • the conduction process of the device of this type is in a fully conduction state, and its performance is fully exerted.
  • the same first driving circuit and second driving circuit can be used to output high and low level signals in different voltage ranges, there is no risk of mixing materials in the production process of power devices, which facilitates material organization and reduces material costs.
  • the first driving circuit 129 includes a UH driving circuit 101, a VH driving circuit 102, and a WH driving circuit 103;
  • the second driving circuit 120 includes a UL/VL/WL driving circuit 104;
  • the arm switch tube 127 includes a first upper bridge arm switch tube 121, a second upper bridge arm switch tube 122, and a third upper bridge arm switch tube 123;
  • the lower bridge arm switch tube 128 includes a first lower bridge arm switch tube 124, a second The lower bridge arm switch tube 125 and the third lower bridge arm switch tube 126; wherein the control input terminal SS is connected to the UH drive circuit 101, the VH drive circuit 102, and the WH drive circuit 103, and the UH drive circuit 101 and the VH drive circuit 102 And WH drive circuit 103 to drive the first upper switch tube 121, the second upper switch tube 122, and the third upper switch tube 123 respectively; the UH drive circuit 101 is connected to the first upper switch tube 121, VH The driving circuit 102 is connected
  • the UL/VL/WL driving circuit 104 and the first low-side switch tube 124, the first The second lower bridge arm switch tube 125 is connected to the third lower bridge arm switch tube 126.
  • the UH drive circuit 101, the VH drive circuit 102, the WH drive circuit 103, and the UL/VL/WL drive circuit 104 may be an electrical appliance 1000, such as a three-phase drive circuit for a compressor of an air conditioner, where the UH drive circuit 101 It is connected to the UL drive circuit 104, the VH drive circuit 102 is connected to the VL drive circuit 104, and the WH drive circuit 103 is connected to the WL drive circuit 104.
  • the first level is 0, the second level is the power level VCC, and the third level is half the power level VCC; the first voltage range is 0-20V, and the second voltage range is 0-3V , The third voltage range is 0-15V.
  • the power device 100 further includes a GND terminal, a VCC terminal, and a reference voltage source Vreg.
  • the control input terminal SS When the control input terminal SS is connected to the GND terminal through a bonding wire 115 (bonding wire), the control input terminal SS is connected to the first level ;
  • the control input terminal SS When the control input terminal SS is connected to the VCC terminal through the bonding line 115, the control input terminal SS is connected to the second level; when the control input terminal SS is connected to the reference voltage source Vreg through the bonding line 115, the control input terminal SS Access the third level.
  • the UH drive circuit 101, the VH drive circuit 102, the WH drive circuit 103 and the UL/VL/WL drive circuit 104 are integrated in the high-voltage integrated circuit tube 111, and the VCC terminal of the high-voltage integrated circuit tube 111 is used as
  • the positive terminal VDD of the low-voltage area power supply of the power device 100, VDD is generally 15V; inside the high-voltage integrated circuit tube 111, the VCC terminal is connected with the UH drive circuit 101, VH drive circuit 102, WH drive circuit 103, UL/VL/WL drive circuit
  • the positive terminal of the power supply of 104 is connected to the positive terminal of the power supply of the reference voltage source Vreg; here, the reference voltage source Vreg is a voltage source with a voltage value of VCC/2 generated inside the high-voltage integrated circuit tube 111.
  • the HIN1 terminal of the high-voltage integrated circuit tube 111 is used as the U-phase upper arm input terminal UHIN of the power device 100, and is connected to the input terminal of the UH driving circuit 101 inside the high-voltage integrated circuit tube 111; the HIN2 terminal of the high-voltage integrated circuit tube 111 is used as a power device
  • the V-phase upper bridge arm input terminal VHIN of 100 is connected to the input terminal of the VH drive circuit 102 inside the high-voltage integrated circuit tube 111;
  • the HIN3 terminal of the high-voltage integrated circuit tube 111 serves as the W-phase upper bridge arm input terminal WHIN of the power device 100,
  • the high-voltage integrated circuit tube 111 is connected to the input terminal of the WH drive circuit 103; the LIN1 terminal of the high-voltage integrated circuit tube 111 is used as the U-phase lower arm input terminal ULIN of the power device 100, and is connected to the UL/VL inside the high-voltage integrated circuit tube 111.
  • the /WL driving circuit 104 is connected to the first input terminal; the LIN2 terminal of the high voltage integrated circuit tube 111 is used as the V-phase lower arm input terminal VLIN of the power device 100, and is connected to the UL/VL/WL driving circuit 104 inside the high voltage integrated circuit tube 111
  • the LIN3 terminal of the high-voltage integrated circuit tube 111 is used as the W-phase lower arm input terminal WLIN of the power device 100, and is connected to the third input terminal of the UL/VL/WL driving circuit 104 within the high-voltage integrated circuit tube 111 Connected.
  • the six inputs of three phases U, V, and W of the power device 100 receive 0V or 5V input signals.
  • the GND terminal of the high-voltage integrated circuit tube 111 is used as the negative terminal COM of the power supply in the low-voltage area of the power device 100, and is connected with the UH drive circuit 101, VH drive circuit 102, WH drive circuit 103, and UL/VL/WL drive circuit 104.
  • the VB1 terminal of the high-voltage integrated circuit tube 111 is connected to the positive terminal of the high-voltage area power supply of the UH drive circuit 101 inside the high-voltage integrated circuit tube 111; one end of the capacitor 131 is connected outside the high-voltage integrated circuit tube 111 and used as the power device 100
  • the HO1 terminal of the high voltage integrated circuit tube 111 is connected to the output terminal of the UH drive circuit 101 inside the high voltage integrated circuit tube 111, and is connected to the first upper arm switch tube outside the high voltage integrated circuit tube 111 121 is connected to the control pole;
  • the VS1 terminal of the high-voltage integrated circuit tube 111 is connected to the negative terminal of the high-voltage area power supply of the UH drive circuit 101 inside the high-voltage integrated circuit tube 111, and is connected to the first upper arm switch tube outside the high-voltage integrated circuit tube 111
  • the VB2 terminal of the high-voltage integrated circuit tube 111 is connected to the positive terminal of the high-voltage area power supply of the VH drive circuit 102 inside the high-voltage integrated circuit tube 111, and one end of the capacitor 132 is connected outside the high-voltage integrated circuit tube 111 as the U-phase high voltage of the power device 100 Area power supply positive terminal VVB;
  • the HO2 terminal of the high-voltage integrated circuit tube 111 is connected to the output terminal of the VH drive circuit 102 inside the high-voltage integrated circuit tube 111, and is controlled by the second upper arm switch tube 122 outside the high-voltage integrated circuit tube 111
  • the VS2 terminal of the high-voltage integrated circuit tube 111 is connected to the negative terminal of the high-voltage area power supply of the VH drive circuit 102 inside the high-voltage integrated circuit tube 111, and is connected to the output negative terminal of the upper arm power tube 122 outside the high-voltage integrated circuit tube 111.
  • the VB3 terminal of the high-voltage integrated circuit tube 111 is connected to the positive terminal of the high-voltage area power supply of the WH drive circuit 103 inside the high-voltage integrated circuit tube 111, and one end of the capacitor 133 is connected outside the high-voltage integrated circuit tube 111 as the W phase high voltage of the power device 100 District power supply positive terminal WVB;
  • HO3 terminal of the high-voltage integrated circuit tube 111 is connected to the output terminal of the WH drive circuit 101 inside the high-voltage integrated circuit tube 111, and is controlled by the third upper arm switch tube 123 outside the high-voltage integrated circuit tube 111
  • the VS3 terminal of the high-voltage integrated circuit tube 111 is connected to the negative terminal of the power supply in the high-voltage area of the WH drive circuit 103 inside the high-voltage integrated circuit tube 111, and is connected to the output negative terminal of the power tube 123 outside the high-voltage integrated circuit tube 111 and the third bottom
  • the output anode of the bridge switch tube 126
  • the LO1 terminal of the high-voltage integrated circuit tube 111 is connected to the control pole of the first low-side switch tube 124; the LO2 terminal of the high-voltage integrated circuit tube 111 is connected to the control pole of the second low-side switch tube 125; The LO3 terminal is connected to the control pole of the third low-side switch tube 126; the output negative electrode of the first low-side switch tube 124 serves as the U-phase low-voltage reference terminal UN of the power device 100; the output of the second low-side switch tube 125 The negative electrode is used as the V-phase low voltage reference terminal VN of the power device 100; the output negative electrode of the third lower-arm switch tube 126 is used as the W-phase low voltage reference terminal WN of the power device 100; The output anode of the second upper-arm switch tube 122 and the output anode of the third upper-arm switch tube 123 are connected, and serve as the high-voltage input terminal P of the power device 100, which is generally connected to 300V.
  • the lower-side switch tube 126 can be a combination of Si IGBT tube (ie Si device) and FRD tube in parallel, or a combination of IGBT tube and GaN SBD (Schottky Barrier Diode, Schottky diode) tube, or GaN MOS Tube (Metal Oxide Semiconductor) (ie, GaN device), it can also be a combination of GaN MOS tube and FRD tube, or a combination of GaN MOS tube and GaN SBD tube; it can also be IGBT tube and
  • the combination of SiC SBD tubes can also be SiC MOS tubes (ie SiC devices), or a combination of SiC MOS tubes and FRD tubes, or a combination of SiC MOS tubes and SiC SBD tubes.
  • the function of the high voltage integrated circuit tube 111 is: when the control input terminal SS is at 0 level, HO1 ⁇ HO3, LO1 ⁇ LO3 output high and low level signals of 0 ⁇ 20V, that is, when the control input When the terminal SS is at the first level, the UH drive circuit 101, the VH drive circuit 102, the WH drive circuit 103, and the UL/VL/WL drive circuit 104 output high and low level signals in the first voltage range; when the control input terminal SS is the VCC voltage Normally, HO1 ⁇ HO3, LO1 ⁇ LO3 output 0 ⁇ 3V high and low level signals, that is to say, when the control input SS is at the second level, the UH drive circuit 101, VH drive circuit 102, WH drive circuit 103 and The UL/VL/WL driving circuit 104 outputs the high and low level signals of the second voltage range; when the control input terminal SS is at the VCC/2 level, HO1 ⁇ HO3, LO1
  • the power device 100 includes a first connection portion 116, a second connection portion 117, and an SSS terminal.
  • the first connection portion 116 is used to connect the VCC terminal and the VDD terminal, and the second connection
  • the part 117 is used to connect the GND terminal and the COM terminal, and the SSS terminal is used to connect the SS terminal and the reference voltage source Vreg.
  • the first connecting portion 116 and the second connecting portion 117 may be wires, electrodes, etc., with conductive transmission functions.
  • the three lower-arm switch tubes 126 all include SiC devices (the SiC device is the SiC MOS tube 1211 shown in Figs. 9-11.
  • the first upper-side switch tube 121, the second upper-side switch tube 122, and the The three upper-side switching tubes 123, the first lower-side switching tubes 124, the second lower-side switching tubes 125, and the third lower-side switching tubes 126 are all in the form of the SiC MOS tube 1211 shown in FIG.
  • the switch tubes 126 are all combinations of the SiC MOS tube 1211 and the Si FRD tube 1212 shown in FIG. 10; or, the first upper bridge arm switch tube 121, the second upper bridge arm switch tube 122, and the third upper bridge arm switch tube 123.
  • the first low-side switching tube 124, the second low-side switching tube 125, and the third low-side switching tube 126 are all of the SiC MOS tube 1211 and SiC SBD tube 1212 or GaN SBD tube 1212 shown in FIG. 11 Combination).
  • control input terminal SS is connected to the GND terminal through a bonding wire 115, the control input terminal SS is connected to the first level, and the first driving circuit 129 and the second driving circuit 120 output the first voltage Range of high and low level signals;
  • the arm switch tubes 126 all include GaN devices (the GaN device is the GaN MOS tube 1211 shown in FIGS. 6 to 8.
  • the first upper bridge arm switch tube 121, the second upper bridge arm switch tube 122, and the third upper bridge The arm switch tube 123, the first lower bridge arm switch tube 124, the second lower bridge arm switch tube 125, and the third lower arm switch tube 126 are all in the manner of the GaN MOS tube 1211 shown in FIG.
  • the first upper Bridge arm switch tube 121, second upper bridge arm switch tube 122, third upper bridge arm switch tube 123, first lower bridge arm switch tube 124, second lower bridge arm switch tube 125, and third lower bridge arm switch tube 126 They are all combinations of the GaN MOS tube 1211 and the Si FRD tube 1212 shown in FIG. 7; or, the first upper bridge arm switch tube 121, the second upper bridge arm switch tube 122, the third upper bridge arm switch tube 123, and the (The lower-side switch tube 124, the second lower-side switch tube 125, and the third lower-side switch tube 126 are all the combination of GaN MOS tube 1211 and GaN SBD tube 1212 or SiC SBD tube 1212 shown in FIG.
  • the SSS terminal is connected to the VCC terminal through a bonding line 115, the control input terminal SS is connected to the second level, and the first driving circuit 129 and the second driving circuit 120 output the high and low levels of the second voltage range signal;
  • the arm switch tubes 126 all include Si devices (Si devices are the Si IGBT tubes 1211 shown in FIGS. 4 to 5).
  • the first upper bridge arm switch tube 121, the second upper bridge arm switch tube 122, and the third upper bridge The arm switch tube 123, the first lower bridge arm switch tube 124, the second lower bridge arm switch tube 125, and the third lower bridge arm switch tube 126 are all the combination of the Si IGBT tube 1211 and the Si FRD tube 1212 shown in Figure 4 ;
  • the lower-arm switch tube 126 is a combination of Si IGBT tube 1211 and GaN SBD tube 1212 or SiC SBD tube 1212 shown in FIG. 5).
  • the SSS terminal passes through the bonding line 115 and the reference voltage source Vreg Connected, the control input terminal SS is connected to the third level, and the first driving circuit 129 and the second driving circuit 120 output high and low level signals in the third voltage range.
  • the power supply voltage of the power device 100 in the embodiment of the present application remains unchanged at 20V, and the power consumption of the high-voltage integrated circuit tube 111 has not substantially increased; driving GaN devices, SiC devices, and driving Si devices are the same high-voltage integrated circuit tube 111 There is no risk of mixing in the production process, which facilitates material organization and reduces material costs; drive GaN devices with 3V voltage, drive SiC devices with 20V voltage, and drive Si devices with 15V voltage, making GaN devices, SiC devices and Si devices The conduction process of each is in a fully conductive state, and at the same time it will not cause breakdown, so that their respective performance can be exerted.
  • the power device 100 includes a controller 130, the control input terminal SS is connected to the controller 130, and the controller 130 is used to control the control input terminal SS to connect to the first level, The second level or the third level.
  • the controller 130 may include a digital circuit for outputting the first level, the second level, or the third level, and may also include a flip-flop, but is not limited thereto.
  • the controller 130 may be installed inside the high voltage integrated circuit tube 111, for example, installed between the control input terminal SS and the SSS terminal or other places.
  • the controller 130 may also be installed outside the high-voltage integrated circuit tube 111, for example, near the control input terminal SS or other places. Or the controller 130 is installed on the microprocessor of the electrical appliance.
  • Figures 4 to 11 are combinations of the upper bridge arm switch tube 127 and the lower bridge arm switch tube 128.
  • the structures of the first low-side switching tube 124, the second low-side switching tube 125, and the third low-side switching tube 126 are the same. Take the first upper-side switching tube 121 as an example for description:
  • Figure 4 shows the combination of Si IGBT tube 1211 and Si FRD tube 1212: (1) The collector of the Si IGBT tube 1211 is connected to the cathode of the Si FRD tube 1212 and serves as the output of the first upper arm switch tube 121 Positive; (2) The emitter of the Si IGBT tube 1211 is connected to the anode of the Si FRD tube 1212, and serves as the output negative electrode of the first upper-side switch tube 121; (3) The gate of the Si IGBT tube 1211 serves as the first upper bridge The control pole of the arm switch tube 121;
  • Figure 5 shows the combination of Si IGBT tube 1211 and GaN SBD tube 1212 or SiC SBD tube 1212: (1) The combination of Si IGBT tube 1211 and GaN SBD tube 1212, where the collector of Si IGBT tube 1211 and The cathode of the GaN SBD tube 1212 is connected and serves as the output anode of the first upper switch tube 121; the emitter of the Si IGBT tube 1211 is connected to the anode of the GaN SBD tube 1212 and serves as the output of the first upper switch tube 121 Negative pole; (2) Combination of Si IGBT tube 1211 and SiC SBD tube 1212, in which the cathode of Si IGBT tube 1211 and SiC SBD tube 1212 are connected and used as the output anode of the first upper arm switch tube 121; Si IGBT tube The emitter of 1211 is connected to the anode of the Si SBD tube, and serves as the output negative electrode of the first upper-side switch tube 121; (3) The gate of the Si IGB
  • Figure 6 shows the way of the GaN MOS tube 1211: (1) The drain of the GaN MOS tube 1211 is used as the output anode of the first upper arm switch tube 121; (2) The source of the GaN MOS tube 1211 is used as the first upper The output negative pole of the bridge arm switch tube 121; (3) The gate of the GaN MOS tube 1211 serves as the control electrode of the first upper bridge arm switch tube 121;
  • Figure 7 shows the combination of GaN MOS tube 1211 and Si FRD tube 1212: (1) The drain of GaN MOS tube 1211 is connected to the cathode of Si FRD tube 1212 and serves as the output of the first upper arm switch tube 121 Anode; (2) The source of the GaN MOS tube 1211 is connected to the anode of the Si FRD tube 1212 and serves as the output negative electrode of the first upper-side switch tube 121; (3) The gate of the GaN MOS tube 1211 serves as the first upper-bridge The control pole of the arm switch tube 121;
  • Figure 8 shows the combination of GaN MOS tube 1211 and GaN SBD tube 1212 or SiC SBD tube 1212: (1) The combination of GaN MOS tube 1211 and GaN SBD tube 1212, where the drain of GaN MOS tube 1211 is connected to The cathode of the GaN SBD tube 1212 is connected and serves as the output anode of the first upper switch tube 121; the source of the GaN MOS tube 1211 is connected to the anode of the GaN SBD tube 1212 and serves as the output of the first upper switch tube 121 Negative; (2) a combination of GaN MOS tube 1211 and SiC SBD tube 1212, wherein the drain of GaN MOS tube 1211 is connected to the cathode of SiC SBD tube 1212, and serves as the output anode of first upper arm switch tube 121; The source of the GaN MOS tube 1211 is connected to the anode of the SiC SBD tube 1212, and serves as the output negative electrode of the first upper-arm switch tube 121; (3)
  • Figure 9 shows the way of the SiC MOS tube 1211: (1) The drain of the SiC MOS tube 1211 is used as the output anode of the first upper arm switch tube 121; (2) the source of the SiC MOS tube 1211 is used as the first upper The output negative electrode of the bridge arm switch tube 121; (3) The gate of the SiC MOS tube 1211 serves as the control electrode of the first upper bridge arm switch tube 121;
  • Figure 10 shows the combination of SiC MOS tube 1211 and Si FRD tube 1212: (1) The drain of SiC MOS tube 1211 is connected to the cathode of Si FRD tube 1212 and serves as the output of the first upper arm switch tube 121 Positive; (2) The source of the SiC MOS tube 1211 is connected to the anode of the Si FRD tube 1212, and serves as the output negative electrode of the first upper-side switch tube 121; (3) The gate of the SiC MOS tube 1211 serves as the first upper-bridge The control pole of the arm switch tube 121;
  • Figure 11 shows the combination of SiC MOS tube 1211 and SiC SBD tube 1212 or GaN SBD tube 1212: (1) The combination of SiC MOS tube 1211 and SiC SBD tube 1212, where the drain of SiC MOS tube 1211 is The cathode of the SiC SBD tube 1212 is connected and serves as the output anode of the first upper switch tube 121; the source of the SiC MOS tube 1211 is connected to the anode of the SiC SBD tube 1212 and serves as the output of the first upper switch tube 121 Negative; (2) a combination of SiC MOS tube 1211 and GaN SBD tube 1212, where the drain of SiC MOS tube 1211 is connected to the cathode of GaN SBD tube 1212, and serves as the output anode of first upper arm switch tube 121; The source of the SiC MOS tube 1211 is connected to the anode of the GaN SBD tube 1212, and serves as the output negative electrode of the first upper-side switch tube 121; (3) The gate of
  • the second upper switching tube 122 can be any combination of switching tubes shown in FIGS. 4 to 11; the third upper switching tube 123 may be any combination shown in FIGS. 4 to 11 A combination of switching tubes; the first lower-arm switching tube 124 can be any combination of switching tubes shown in Figures 4 to 11; the second lower-side switching tube 125 can be the one shown in Figures 4 to 11 The switch tube in any combination shown; the third lower-arm switch tube 126 can be the switch tube in any combination shown in FIGS. 4 to 11.
  • the same structure of the three lower arm switch tubes 126 means that in the actual power device 100, the first upper arm switch tube 121, the second upper arm switch tube 122, the third upper arm switch tube 123, and the first
  • the lower bridge arm switch tube 124, the second lower bridge arm switch tube 125, and the third lower bridge arm switch tube 126 are all switch tubes of the combination of Si IGBT and Si FRD shown in FIG.
  • the first upper bridge arm The switch tube 121, the second upper bridge arm switch tube 122, the third upper bridge arm switch tube 123, the first lower bridge arm switch tube 124, the second lower bridge arm switch tube 125, and the third lower bridge arm switch tube 126 are all The switch tube of the combination of Si IGBT and GaN SBD tube or SiC SBD tube shown in FIG. 5; or, the first upper bridge arm switch tube 121, the second upper bridge arm switch tube 122, and the third upper bridge arm switch tube 123 , The first low-side switch tube 124, the second low-side switch tube 125, and the third low-side switch tube 126 are all GaN MOS switch tubes shown in FIG.
  • the tube 121, the second upper bridge arm switch tube 122, the third upper bridge arm switch tube 123, the first lower bridge arm switch tube 124, the second lower bridge arm switch tube 125, and the third lower arm switch tube 126 are all shown in the figure 7 shows the combination of GaN MOS and Si FRD switch tube; or, the first upper bridge arm switch tube 121, the second upper bridge arm switch tube 122, the third upper bridge arm switch tube 123, the first lower bridge arm
  • the switching tube 124, the second lower-side switching tube 125, and the third lower-side switching tube 126 are all switching tubes of a combination of GaN MOS and GaN SBD tubes or SiC SBD tubes shown in FIG.
  • the first upper Bridge arm switch tube 121, second upper bridge arm switch tube 122, third upper bridge arm switch tube 123, first lower bridge arm switch tube 124, second lower bridge arm switch tube 125, and third lower bridge arm switch tube 126 All are the switching tubes of the SiC MOS mode shown in FIG. 9; or, the first upper-side switching tube 121, the second upper-side switching tube 122, the third upper-side switching tube 123, and the first lower-side switching tube
  • the tube 124, the second low-side switch tube 125, and the third low-side switch tube 126 are all switch tubes of the combination of SiC MOS and Si FRD shown in FIG.
  • the first upper-side switch tube 121, The second upper bridge arm switch tube 122, the third upper bridge arm switch tube 123, the first lower bridge arm switch tube 124, the second lower bridge arm switch tube 125, and the third lower bridge arm switch tube 126 are all shown in FIG. 11 SiC MOS and SiC SBD tube or GaN SBD tube combination switch tube.
  • UH drive circuit 101, VH drive circuit 102, WH drive circuit 103 have the same structure
  • Figure 12 Figure 13 and Figure 14 are UH drive circuit 101, VH drive circuit 102 and WH drive circuit 103, respectively ⁇ Example.
  • the following description will respectively introduce the structure of the UH driving circuit 101, the VH circuit 102, and the WH circuit 103.
  • the UH drive circuit 101 includes: a first input sub-circuit 1011, a first switch tube 1012, a second switch tube 1013, a third switch tube 1014, a fourth switch tube 1021, an output The sub-circuit 1017, the first voltage output sub-circuit 1023, and the second voltage output sub-circuit 1024.
  • the first input sub-circuit 1011 is connected to the control input terminal SS.
  • the first input sub-circuit 1011 includes a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal.
  • the first output terminal and the second output terminal output trigger pulses, and the third output terminal outputs the trigger pulse of the first time length; when the control input terminal SS is at the second level, The first output terminal and the second output terminal output trigger pulses, and the third output terminal outputs trigger pulses of the second time length.
  • the first time length is less than the second time length; when the control input terminal SS is at the third level, the first output The second output terminal and the second output terminal output the trigger pulse, and the fourth output terminal outputs the trigger pulse of the first time length.
  • the first switch tube 1012 is connected to the first output terminal.
  • the first switch tube 1012 When the first output terminal outputs a trigger pulse, the first switch tube 1012 is turned on; the second switch tube 1013 is connected to the second output terminal and outputs a trigger pulse at the second output terminal.
  • the third switch tube 1014 When the second switch tube 1013 is turned on; the third switch tube 1014 is connected to the third output terminal, when the third output terminal outputs a trigger pulse, the third switch 1014 is turned on; the fourth switch tube 1021 is connected to the fourth output terminal , When the trigger pulse is output at the fourth output terminal, the fourth switch tube 1021 is turned on.
  • the first voltage output sub-circuit 1023 is connected to the first switch tube 1012, the second switch tube 1013, and the third switch tube 1014 respectively; the second voltage output sub-circuit 1024 is connected to the fourth switch tube 1021; the output sub-circuit 1017 is connected to the A voltage output sub-circuit 1023 and a second voltage output sub-circuit 1024 are connected.
  • the first voltage output sub-circuit 1023 includes a latch and step-down circuit 1016 connected to the first switch tube 1012 and the second switch tube 1013, a first switching module 1018, and a The first latch circuit 1015 to which the three switch tubes 1014 are connected.
  • the first switching module 1018 is respectively connected to the latch and step-down circuit 1016 and the power supply; when the third switch tube 1014 is turned on for a first period of time, the first latch circuit 1015 is used to control the action of the first switching module 1018 to turn the power supply off.
  • the first latch circuit 1015 is used to control the action of the first switching module 1018 to latch and step down
  • the output voltage of the circuit 1016 is used as the output voltage of the first voltage output sub-circuit 1023.
  • the second voltage output sub-circuit 1024 includes a first step-down circuit 1022, a second switching module 1019, and a second latch circuit 1020 connected to the fourth switch tube 1021.
  • the second switching module 1019 is respectively connected to the first voltage output sub-circuit 1023 and the first step-down circuit 1022.
  • the second latch circuit 1020 controls the second switching module 1019.
  • the output sub-circuit 1017 is connected to the first voltage output sub-circuit 1023, and when the fourth switch tube 1021 is turned on for a first period of time, the output sub-circuit 1017 is connected to the first step-down circuit 1022.
  • the VCC terminal is connected to the positive terminal of the power supply of the first input sub-circuit 1011
  • HIN1 is connected to the input terminal of the first input sub-circuit 1011
  • the control input terminal SS is connected to the first input sub-circuit 1011.
  • the control terminal of an input sub-circuit 1011 is connected.
  • the first output terminal of the first input sub-circuit 1011 is connected to the gate of the first switching tube 1012
  • the second output terminal of the first input sub-circuit 1011 is connected to the gate of the second switching tube 1013
  • the first input sub-circuit 1011 The third output terminal of is connected to the gate of the high-voltage third switch tube 1014
  • the fourth output terminal of the first input sub-circuit 1011 is connected to the gate of the fourth switch tube 1021.
  • the substrate of the fourth switch tube 1021 is connected to the source.
  • the drain of the first switch tube 1012 enters the high voltage region and is connected to the first input terminal of the latch and buck circuit 1016; the drain of the second switch tube 1013 enters the high voltage region and is connected to the second input terminal of the latch and buck circuit 1016
  • the drain of the third switch tube 1014 enters the high voltage region and is connected to the enable terminal of the first latch circuit 1015; the drain of the fourth switch tube 1021 enters the high voltage region and is connected to the enable terminal of the latch circuit 1020.
  • the first output terminal of the latch and step-down circuit 1016 is connected to the 1 selection terminal of the analog switch 1018; the second output terminal of the latch and step-down circuit 1016 is connected to the input terminal of the output circuit 1017; the output terminal of the latch circuit 1015 Connected to the control terminal of the analog switch 1018; the fixed terminal of the analog switch 1018 is connected to the positive terminal of the power supply of the output circuit 1017; the output terminal of the step-down circuit 1022 is connected to the movable terminal of the second switching module 1019; the second latch circuit 1020 The output terminal of is connected to the control terminal of the second switching module 1019.
  • the 0 selection terminal of the analog switch 1018 is connected.
  • the negative terminal of the power supply of the output sub-circuit 1017 is connected.
  • HO1 is connected to the output terminal of the output sub-circuit 1017.
  • the function of the first input sub-circuit 1011 is to output a pulse signal with a pulse width of about 300 ns at the first output end of the first input sub-circuit 1011 on the rising edge of the signal at the input end of the first input sub-circuit 1011; Input the falling edge of the signal at the input end of the sub-circuit 1011, and output a pulse signal with a pulse width of about 300 ns at the second output end of the first input sub-circuit 1011; when the control input end of the first input sub-circuit 1011 is at the VCC level, A pulse signal with a pulse width of about 600 ns is output at the third output end of the first input sub-circuit 1011; when the control input end of the first input sub-circuit 1011 is at 0 level, the third output of the first input sub-circuit 1011 Output a pulse signal with a pulse width of about 300ns; when the control input terminal of the first input sub-circuit 1011 is at the VCC/2 level, a pulse width of
  • the function of the first latch circuit 1015 is: when the signal at the input terminal of the first latch circuit 1015 appears at a low level of 600 ns, the output terminal of the first latch circuit 1015 outputs a high level, and when the input terminal of the first latch circuit 1015 When the signal appears at a low level of 300 ns, the output terminal of the first latch circuit 1015 outputs a low level. When the signal at the input terminal of the first latch circuit 1015 never appears at a low level, the output terminal of the first latch circuit 1015 outputs VCC /2 voltage.
  • the function of the latch and step-down circuit 1016 is to output a continuous high level at the second output end of the latch and step-down circuit 1016 when a low level of 300 ns appears at the first input end of the latch and step-down circuit 1016;
  • the second input terminal of the latch and step-down circuit 1016 has a low level of 300 ns
  • the second output terminal of the latch and step-down circuit 1016 outputs a continuous low level, that is, the HIN1 signal is two in the first input sub-circuit 1011
  • the two pulse signals decomposed at the output are reintegrated into a complete signal.
  • the latch and step-down circuit 1016 has a step-down circuit inside, and the second output terminal of the latch and step-down circuit 1016 outputs a voltage of 3V to VS1.
  • the function of the second latch circuit 1020 is: when a low level appears at the first input end of the latch and step-down circuit 1016 for 300 ns, the second output end of the latch and step-down circuit 1016 outputs a continuous high level, otherwise the output Low level.
  • the function of the output sub-circuit 1017 is to output a signal whose phase is consistent with HIN1 when the voltage value is consistent with the positive terminal of the power supply at high level and the voltage value is consistent with the negative terminal of the power supply at low level.
  • the narrow pulse signal of 300ns or 600ns is used to control the first switching tube 1012, the second switching tube 1013, the third switching tube 1014, and the fourth switching tube 1021 in order to shorten the first switching tube 1012, the second switching tube 1013.
  • the conduction time of the third switching tube 1014 and the fourth switching tube 1021 reduces their power consumption.
  • the working principle of reducing the power consumption of the first switching tube 1012, the second switching tube 1013, the third switching tube 1014, and the fourth switching tube 1021 by shortening the conduction time is:
  • a 300ns narrow pulse is output at the first output terminal and the second output terminal of the first input sub-circuit 1011 at the rising edge and the falling edge of the signal.
  • the first switch tube 1012 and the second switch tube 1013 are turned on for 300 ns, so that the first input terminal and the second input terminal of the latch and step-down circuit 1016 respectively generate a low level of 300 ns.
  • the latch and step-down circuit 1016 has RS flip-flops and other devices, so that two low-level signals are recombined into a complete signal in phase with HIN1;
  • both the upper-side switch tube 127 and the lower-side switch tube 128 include SiC MOS transistors
  • the control input terminal SS is at 0 level, so that the fourth output terminal of the first input sub-circuit 1011 will not appear high level ,
  • the fourth switch tube 1021 will not be turned on, and the input terminal of the second latch circuit 1020 will not appear low level, the output terminal of the second latch circuit 1020 remains low level, and the analog switch 1019 is in the off state.
  • the third output terminal of the first input sub-circuit 1011 appears a 300ns (first time length) high-level pulse
  • the third switch tube 1014 appears to be turned on for 300ns
  • the input terminal of the first latch circuit 1015 appears a 300ns low level.
  • the output terminal of the first latch circuit 1015 outputs from high to low, and the positive terminal of the power supply of the output sub-circuit 1017 is connected to VB1, that is, the output sub-circuit 1017 outputs a high and low level of 0-20V.
  • both the upper-side switch tube 127 and the lower-side switch tube 128 include GaN MOS transistors
  • the control input terminal SS is at the VCC level, so that the fourth output terminal of the first input sub-circuit 1011 will not appear high level,
  • the fourth switch tube 1021 will not be turned on, and the input terminal of the second latch circuit 1020 will not appear at a low level, the output terminal of the second latch circuit 1020 will remain at a low level, and the second switching module 1019 will be in an off state.
  • the third output terminal of the first input sub-circuit 1011 appears a 600ns (second time length) high level pulse
  • the third switch tube 1014 appears 600ns conduction
  • the input terminal of the first latch circuit 1015 appears 600ns low level.
  • the output terminal of the first latch circuit 1015 outputs from low to high level, and the positive terminal of the power supply of the output sub-circuit 1017 is connected to the output terminal of the latch and step-down circuit 1016, that is, the output sub-circuit 1017 outputs 0 ⁇ 3V The high and low levels.
  • the control input terminal SS is at the VCC/2 level, so that the third output terminal of the first input sub-circuit 1011 will not have high voltage If the third switch tube 1014 will not be turned on, and the input terminal of the first latch circuit 1015 will not appear at a low level, the output terminal of the first latch circuit 1015 will always be at a low level, and the first switching module 1018 will be floating status.
  • the fourth output terminal of the first input sub-circuit 1011 appears a 300ns (first time length) high-level pulse
  • the fourth switch tube 1021 appears 300ns conduction
  • the input terminal of the second latch circuit 1020 appears a 300ns low level
  • the output terminal of the second latch circuit 1020 outputs a high level
  • the positive terminal of the power supply of the output sub-circuit 1017 is connected to the output terminal of the second step-down circuit 1022, that is, the output sub-circuit 1017 outputs a high and low level of 0-15V .
  • the VH driving circuit 102 includes: a first input sub-circuit 1211, an output sub-circuit 1217, a first switching tube 1212, a second switching tube 1213, a third switching tube 1214, a fourth The switch tube 1221, the first voltage output sub-circuit 1223, and the second voltage output sub-circuit 1224.
  • the first input sub-circuit 1211 is connected to the control input terminal SS.
  • the first input sub-circuit 1211 includes a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal.
  • the control input terminal SS When the control input terminal SS is the first output terminal, At the level, the first output terminal and the second output terminal output trigger pulses, and the third output terminal outputs the trigger pulse for the first time length; when the control input terminal SS is at the second level, the first output terminal and the second output terminal output Trigger pulse, the third output terminal outputs a trigger pulse of the second time length, the first time length is less than the second time length; when the control input terminal SS is at the third level, the first output terminal and the second output terminal output trigger pulses, The fourth output terminal outputs a trigger pulse of the first time length.
  • the first switch tube 1212 is connected to the first output terminal.
  • the first switch tube 1212 When the first output terminal outputs a trigger pulse, the first switch tube 1212 is turned on; the second switch tube 1213 is connected to the second output terminal and outputs a trigger pulse at the second output terminal.
  • the third switch tube 1214 When the second switch tube 1213 is turned on; the third switch tube 1214 is connected to the third output terminal, when the third output terminal outputs a trigger pulse, the third switch 1214 is turned on; the fourth switch tube 1221 is connected to the fourth output terminal When the trigger pulse is output at the fourth output terminal, the fourth switch tube 1221 is turned on.
  • the first voltage output sub-circuit 1223 is connected to the first switch tube 1212, the second switch tube 1213, and the third switch tube 1214, respectively.
  • the second voltage output sub-circuit 1224 is connected to the fourth switch tube 1221.
  • the output sub-circuit 1217 is respectively connected to the first voltage output sub-circuit 1223 and the second voltage output sub-circuit 1224.
  • the first voltage output sub-circuit 1223 includes a latch and step-down circuit 1216 connected to a first switch tube 1212 and a second switch tube 1213, a first switching module 1218, and a The first latch circuit 1215 to which the three switch tubes 1214 are connected.
  • the first switching module 1218 is respectively connected to the latch and step-down circuit 1216 and the power supply; when the third switch tube 1214 is turned on for a first period of time, the first latch circuit 1215 is used to control the action of the first switching module 1218 to turn the power supply off.
  • the first latch circuit 1215 is used to control the action of the first switching module 1218 to latch and step down
  • the output voltage of the circuit 1216 is used as the output voltage of the first voltage output sub-circuit 1223.
  • the second voltage output sub-circuit 1224 includes a first step-down circuit 1222, a second switching module 1219, and a second latch circuit 1220 connected to the fourth switch tube 1221.
  • the second switching module 1219 is respectively connected to the first voltage output sub-circuit 1223 and the first step-down circuit 1222.
  • the second latch circuit 1220 controls the second switching module 1219.
  • the output sub-circuit 1217 is connected to the first voltage output sub-circuit 1223, and when the fourth switch tube 1221 is turned on for the first time period, the output sub-circuit 1217 is connected to the first step-down circuit 1222.
  • the VCC terminal is connected to the positive terminal of the power supply of the first input sub-circuit 1211
  • HIN1 is connected to the input terminal of the first input sub-circuit 1211
  • the control input terminal SS is connected to the first input sub-circuit 1211.
  • the control terminal of an input sub-circuit 1211 is connected.
  • the first output terminal of the first input sub-circuit 1211 is connected to the gate of the first switch tube 1212
  • the second output terminal of the first input sub-circuit 1211 is connected to the gate of the second switch tube 1213
  • the first input sub-circuit 1211 The third output terminal of the first input sub-circuit 1211 is connected to the gate of the third switch tube 1214
  • the fourth output terminal of the first input sub-circuit 1211 is connected to the gate of the fourth switch tube 1221.
  • the GND terminal and the negative terminal of the power supply of the first input sub-circuit 1211, the substrate and source of the first switch tube 1212, the substrate and source of the second switch tube 1213, and the substrate and source of the third switch tube 1214 The substrate of the fourth switch tube 1221 is connected to the source.
  • the drain of the first switch tube 1212 enters the high voltage region and is connected to the first input terminal of the latch and step-down circuit 1216; the drain of the second switch tube 1213 enters the high voltage region and is connected to the second input terminal of the latch and step-down circuit 1216 Connected; the drain of the third switch tube 1214 enters the high voltage region and is connected to the enable terminal of the first latch circuit 1215; the drain of the fourth switch tube 1221 enters the high voltage region and is connected to the enable terminal of the latch circuit 1220.
  • the first output terminal of the latch and step-down circuit 1216 is connected to the 1 selection terminal of the analog switch 1218; the second output terminal of the latch and step-down circuit 1216 is connected to the input terminal of the output circuit 1217; the output terminal of the latch circuit 1215 Connected to the control terminal of the analog switch 1218; the fixed terminal of the analog switch 1218 is connected to the positive terminal of the power supply of the output circuit 1217; the output terminal of the step-down circuit 1222 is connected to the movable terminal of the second switching module 1219; the second latch circuit 1220 The output terminal of is connected to the control terminal of the second switching module 1219.
  • the 0 selection terminal of the analog switch 1218 is connected.
  • the negative terminal of the power supply of the output sub-circuit 1217 is connected.
  • HO1 is connected to the output terminal of the output sub-circuit 1217.
  • the function of the first input sub-circuit 1211 is to output a pulse signal with a pulse width of about 300 ns at the first output end of the first input sub-circuit 1211 on the rising edge of the signal at the input end of the first input sub-circuit 1211; Input the falling edge of the signal at the input end of the sub-circuit 1211, and output a pulse signal with a pulse width of about 300 ns at the second output end of the first input sub-circuit 1211; when the control input end of the first input sub-circuit 1211 is at the VCC level, A pulse signal with a pulse width of about 600 ns is output at the third output end of the first input sub-circuit 1211; when the control input end of the first input sub-circuit 1211 is at 0 level, the third output of the first input sub-circuit 1211 When the control input terminal of the first input sub-circuit 1211 is at VCC/2 level, the fourth output terminal of the first input sub-circuit 1211 outputs a pulse width of about 300
  • the function of the first latch circuit 1215 is: when the signal at the input terminal of the first latch circuit 1215 appears at a low level of 600 ns, the output terminal of the first latch circuit 1215 outputs a high level, and when the input terminal of the first latch circuit 1215 When the signal appears at a low level of 300 ns, the output terminal of the first latch circuit 1215 outputs a low level. When the signal at the input terminal of the first latch circuit 1215 never appears at a low level, the output terminal of the first latch circuit 1215 outputs VCC /2 voltage.
  • the function of the latch and step-down circuit 1216 is to output a continuous high level at the second output end of the latch and step-down circuit 1216 when a low level of 300 ns appears at the first input end of the latch and step-down circuit 1216;
  • the second output terminal of the latch and step-down circuit 1216 outputs a continuous low level, that is, the signal of HIN1 is two in the first input sub-circuit 1211
  • the two pulse signals decomposed at the output are reintegrated into a complete signal.
  • the latch and step-down circuit 1216 has a step-down circuit inside, and the second output terminal of the latch and step-down circuit 1216 outputs a voltage of 3V to VS1.
  • the function of the second latch circuit 1220 is: when a low level appears at the first input end of the latch and step-down circuit 1216 for 300 ns, the second output end of the latch and step-down circuit 1216 outputs a continuous high level, otherwise the output Low level.
  • the function of the output sub-circuit 1217 is to output a signal whose phase is consistent with HIN1 when the voltage value is consistent with the positive terminal of the power supply at high level and the voltage value is consistent with the negative terminal of the power supply at low level.
  • using a narrow pulse signal of 300ns or 600ns to control the first switching tube 1212, the second switching tube 1213, the third switching tube 1214, and the fourth switching tube 1221 is to shorten the first switching tube 1212, the second switching tube 1213.
  • the conduction time of the third switch tube 1214 and the fourth switch tube 1221 reduces its power consumption.
  • the working principle of reducing the power consumption of the first switching tube 1212, the second switching tube 1213, the third switching tube 1214, and the fourth switching tube 1221 by shortening the conduction time is:
  • a 300ns narrow pulse is output at the first output end and the second output end of the first input sub-circuit 1211 at the rising edge and the falling edge of the signal respectively.
  • the first switch tube 1212 and the second switch tube 1213 are turned on for 300 ns, so that the first input terminal and the second input terminal of the latch and step-down circuit 1216 respectively generate a low level of 300 ns.
  • the latch and step-down circuit 1216 has RS flip-flops and other devices, so that two low-level signals are recombined into a complete signal in phase with HIN1;
  • both the upper-side switch tube 127 and the lower-side switch tube 128 contain SiC MOS transistors, the control input terminal SS is at 0 level, so that the fourth output terminal of the first input sub-circuit 1211 will not appear high level , The fourth switch tube 1221 will not be turned on, and the input terminal of the second latch circuit 1220 will not appear low level, the output terminal of the second latch circuit 1220 will remain low level, and the analog switch 1219 will be in the off state.
  • the third output terminal of the first input sub-circuit 1211 appears a 300ns (first time length) high-level pulse, the third switch tube 1214 appears to be turned on for 300ns, and the input terminal of the first latch circuit 1215 appears a 300ns low level.
  • the output terminal of the first latch circuit 1215 outputs from high to low, and the positive terminal of the power supply of the output sub-circuit 1217 is connected to VB1, that is, the output sub-circuit 1217 outputs a high and low level of 0-20V.
  • both the upper-side switch tube 127 and the lower-side switch tube 128 include GaN MOS transistors
  • the control input terminal SS is at the VCC level, so that the fourth output terminal of the first input sub-circuit 1211 will not appear high level,
  • the fourth switch tube 1221 will not be turned on, and the input terminal of the second latch circuit 1220 will not appear at a low level, the output terminal of the second latch circuit 1220 will remain at a low level, and the second switching module 1219 will be in an off state.
  • the third output terminal of the first input sub-circuit 1211 appears 600ns (second time length) high-level pulse
  • the third switch tube 1214 appears 600ns conduction
  • the input terminal of the first latch circuit 1215 appears 600ns low level
  • the output terminal of the first latch circuit 1215 outputs from low to high level
  • the positive terminal of the power supply of the output sub-circuit 1217 is connected to the output terminal of the latch and step-down circuit 1216, that is, the output sub-circuit 1217 outputs 0 ⁇ 3V The high and low levels.
  • the control input terminal SS is at the VCC/2 level, so that the third output terminal of the first input sub-circuit 1211 will not have high voltage If the third switch tube 1214 will not be turned on, and the input terminal of the first latch circuit 1215 will not appear at a low level, the output terminal of the first latch circuit 1215 will always be at a low level, and the first switching module 1218 will be floating status.
  • the fourth output terminal of the first input sub-circuit 1211 appears a 300ns (first time length) high-level pulse
  • the fourth switch tube 1221 appears 300ns conduction
  • the input terminal of the second latch circuit 1220 appears a 300ns low level
  • the output terminal of the second latch circuit 1220 outputs a high level
  • the positive terminal of the power supply of the output sub-circuit 1217 is connected to the output terminal of the second step-down circuit 1222, that is, the output sub-circuit 1217 outputs a high and low level of 0-15V .
  • the WH driving circuit 103 includes: a first input sub-circuit 1311, an output sub-circuit 1317, a first switching tube 1312, a second switching tube 1313, a third switching tube 1314, and a fourth The switch tube 1321, the first voltage output sub-circuit 1323, and the second voltage output sub-circuit 1324.
  • the first input sub-circuit 1311 is connected to the control input terminal SS.
  • the first input sub-circuit 1311 includes a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal.
  • the control input terminal SS When the control input terminal SS is the first output terminal, At the level, the first output terminal and the second output terminal output trigger pulses, and the third output terminal outputs the trigger pulse for the first time length; when the control input terminal SS is at the second level, the first output terminal and the second output terminal output Trigger pulse, the third output terminal outputs a trigger pulse of the second time length, the first time length is less than the second time length; when the control input terminal SS is at the third level, the first output terminal and the second output terminal output trigger pulses, The fourth output terminal outputs a trigger pulse of the first time length.
  • the first switch tube 1312 is connected to the first output terminal. When the first output terminal outputs a trigger pulse, the first switch tube 1312 is turned on; the second switch tube 1313 is connected to the second output terminal and outputs a trigger pulse at the second output terminal When the second switching tube 1313 is turned on; the third switching tube 1314 is connected to the third output terminal, when the third output terminal outputs a trigger pulse, the third switch 1314 is turned on; the fourth switching tube 1321 is connected to the fourth output terminal When the trigger pulse is output at the fourth output terminal, the fourth switch tube 1321 is turned on.
  • the first voltage output sub-circuit 1323 is respectively connected to the first switch tube 1312, the second switch tube 1313, and the third switch tube 1314; the second voltage output sub-circuit 1324 is connected to the fourth switch tube 1321; the output sub-circuit 1317 is connected to the A voltage output sub-circuit 1323 and a second voltage output sub-circuit 1324 are connected.
  • the first voltage output sub-circuit 1323 includes a latch and step-down circuit 1316 connected to the first switch tube 1312 and the second switch tube 1313, a first switching module 1318, and The first latch circuit 1315 connected to the third switch tube 1314.
  • the first switching module 1318 is respectively connected to the latch and step-down circuit 1316 and the power supply; when the third switch tube 1314 is turned on for a first period of time, the first latch circuit 1315 is used to control the action of the first switching module 1318 to turn the power supply off.
  • the first latch circuit 1315 is used to control the action of the first switching module 1318 to latch and step down
  • the output voltage of the circuit 1316 is used as the output voltage of the first voltage output sub-circuit 1323.
  • the second voltage output sub-circuit 1324 includes a first step-down circuit 1322, a second switching module 1319, and a second latch circuit 1320 connected to the fourth switch tube 1321.
  • the second switching module 1319 is respectively connected to the first voltage output sub-circuit 1323 and the first step-down circuit 1322.
  • the second latch circuit 1320 controls the second switching module 1319.
  • the VCC terminal is connected to the positive terminal of the power supply of the first input sub-circuit 1311
  • HIN1 is connected to the input terminal of the first input sub-circuit 1311
  • the control input terminal SS is connected to the first input sub-circuit 1311.
  • the control terminal of an input sub-circuit 1311 is connected.
  • the first output terminal of the first input sub-circuit 1311 is connected to the gate of the first switch tube 1312
  • the second output terminal of the first input sub-circuit 1311 is connected to the gate of the second switch tube 1313
  • the first input sub-circuit 1311 The third output terminal of is connected to the gate of the high-voltage third switch tube 1314
  • the fourth output terminal of the first input sub-circuit 1311 is connected to the gate of the fourth switch tube 1321.
  • the GND terminal and the negative terminal of the power supply of the first input sub-circuit 1311, the substrate and source of the first switch tube 1312, the substrate and source of the second switch tube 1313, and the substrate and source of the third switch tube 1314 The substrate of the fourth switch tube 1321 is connected to the source.
  • the drain of the first switch tube 1312 enters the high voltage region and is connected to the first input terminal of the latch and step-down circuit 1316; the drain of the second switch tube 1313 enters the high voltage region and is connected to the second input terminal of the latch and step-down circuit 1316
  • the drain of the third switch tube 1314 enters the high voltage region and is connected to the enable terminal of the first latch circuit 1315; the drain of the fourth switch tube 1321 enters the high voltage region and is connected to the enable terminal of the latch circuit 1320.
  • the first output terminal of the latch and step-down circuit 1316 is connected to the 1 selection terminal of the analog switch 1318; the second output terminal of the latch and step-down circuit 1316 is connected to the input terminal of the output circuit 1317; the output terminal of the latch circuit 1315 Connected to the control terminal of the analog switch 1318; the fixed terminal of the analog switch 1318 is connected to the positive terminal of the power supply of the output circuit 1317; the output terminal of the step-down circuit 1322 is connected to the movable terminal of the second switching module 1319; the second latch circuit 1320 The output terminal of is connected to the control terminal of the second switching module 1319.
  • the 0 selection terminal of the analog switch 1318 is connected.
  • the negative terminal of the power supply of the output sub-circuit 1317 is connected.
  • HO1 is connected to the output terminal of the output sub-circuit 1317.
  • the function of the first input sub-circuit 1311 is to output a pulse signal with a pulse width of about 300 ns at the first output end of the first input sub-circuit 1311 on the rising edge of the signal at the input end of the first input sub-circuit 1311; Input the falling edge of the signal at the input end of the sub-circuit 1311, and output a pulse signal with a pulse width of about 300 ns at the second output end of the first input sub-circuit 1311; when the control input end of the first input sub-circuit 1311 is at the VCC level, A pulse signal with a pulse width of about 600 ns is output at the third output end of the first input sub-circuit 1311; when the control input end of the first input sub-circuit 1311 is at 0 level, the third output of the first input sub-circuit 1311 Output a pulse signal with a pulse width of about 300ns; when the control input terminal of the first input sub-circuit 1311 is at VCC/2 level, a pulse width of about
  • the function of the first latch circuit 1315 is: when the signal at the input end of the first latch circuit 1315 appears at a low level of 600 ns, the output end of the first latch circuit 1315 outputs a high level, when the input end of the first latch circuit 1315 When the signal appears at a low level of 300 ns, the output terminal of the first latch circuit 1315 outputs a low level. When the signal at the input terminal of the first latch circuit 1315 never appears at a low level, the output terminal of the first latch circuit 1315 outputs VCC /2 voltage.
  • the function of the latch and step-down circuit 1316 is to output a continuous high level at the second output end of the latch and step-down circuit 1316 when a low level of 300 ns appears at the first input end of the latch and step-down circuit 1316;
  • the second output terminal of the latch and step-down circuit 1316 outputs a continuous low level, that is, the signal of HIN1 is two in the first input sub-circuit 1311
  • the two pulse signals decomposed at the output are reintegrated into a complete signal.
  • the latch and step-down circuit 1316 has a step-down circuit inside, and the second output terminal of the latch and step-down circuit 1316 outputs a voltage of 3V to VS1.
  • the function of the second latch circuit 1320 is: when a low level appears at the first input end of the latch and step-down circuit 1316 for 300 ns, the second output end of the latch and step-down circuit 1316 outputs a continuous high level, otherwise the output Low level.
  • the function of the output sub-circuit 1317 is to output a signal whose phase is consistent with HIN1 when the voltage value is consistent with the positive terminal of the power supply at high level, and the voltage value is consistent with the negative terminal of the power supply at low level.
  • the narrow pulse signal of 300ns or 600ns is used to control the first switching tube 1312, the second switching tube 1313, the third switching tube 1314, and the fourth switching tube 1321 in order to shorten the first switching tube 1312, the second switching tube 1313.
  • the conduction time of the third switch tube 1314 and the fourth switch tube 1321 reduces its power consumption.
  • the working principle of reducing the power consumption of the first switching tube 1312, the second switching tube 1313, the third switching tube 1314, and the fourth switching tube 1321 by shortening the conduction time is:
  • a 300ns narrow pulse is output at the first output end and the second output end of the first input sub-circuit 1311 at the rising edge and the falling edge of the signal, respectively.
  • the first switch tube 1312 and the second switch tube 1313 are turned on for 300ns, so that the first input terminal and the second input terminal of the latch and step-down circuit 1316 respectively generate a low level of 300ns.
  • the latch and step-down circuit 1316 has RS flip-flops and other devices, so that two low-level signals are recombined into a complete signal in phase with HIN1;
  • both the upper-side switch tube 127 and the lower-side switch tube 128 contain SiC MOS transistors, the control input terminal SS is 0 level, so that the fourth output terminal of the first input sub-circuit 1311 will not appear high level , The fourth switch tube 1321 will not be turned on, and the input terminal of the second latch circuit 1320 will not appear low level, the output terminal of the second latch circuit 1320 will remain low level, and the analog switch 1319 will be in the off state.
  • the third output terminal of the first input sub-circuit 1311 appears a 300ns (first time length) high-level pulse, the third switch tube 1314 appears to be turned on for 300ns, and the input terminal of the first latch circuit 1315 appears a 300ns low level.
  • the output terminal of the first latch circuit 1315 outputs from high to low, and the positive terminal of the power supply of the output sub-circuit 1317 is connected to VB1, that is, the output sub-circuit 1317 outputs a high and low level of 0-20V.
  • both the upper-side switch tube 127 and the lower-side switch tube 128 include GaN MOS transistors
  • the control input terminal SS is at the VCC level, so that the fourth output terminal of the first input sub-circuit 1311 will not appear high level,
  • the fourth switch tube 1321 will not be turned on, and the input terminal of the second latch circuit 1320 will not appear at a low level, the output terminal of the second latch circuit 1320 will remain at a low level, and the second switching module 1319 will be in an off state.
  • the third output terminal of the first input sub-circuit 1311 appears 600ns (second time length) high level pulse
  • the third switch tube 1314 appears 600ns conduction
  • the input terminal of the first latch circuit 1315 appears 600ns low level
  • the output terminal of the first latch circuit 1315 outputs from low to high level
  • the positive terminal of the power supply of the output sub-circuit 1317 is connected to the output terminal of the latch and step-down circuit 1316, that is, the output sub-circuit 1317 outputs 0 ⁇ 3V The high and low levels.
  • the control input terminal SS is at the VCC/2 level, so that the third output terminal of the first input sub-circuit 1311 will not appear high voltage If the third switch tube 1314 will not be turned on, and the input terminal of the first latch circuit 1315 will not appear at a low level, the output terminal of the first latch circuit 1315 will always be at a low level, and the first switching module 1318 will be floating status. And the fourth output terminal of the first input sub-circuit 1311 appears a 300ns (first time length) high level pulse, the fourth switch tube 1321 appears to be turned on for 300ns, and the input terminal of the second latch circuit 1320 appears a 300ns low level.
  • the output terminal of the second latch circuit 1320 outputs a high level
  • the positive terminal of the power supply of the output sub-circuit 1317 is connected to the output terminal of the second step-down circuit 1322, that is, the output sub-circuit 1317 outputs a high and low level of 0-15V .
  • the UL/VL/WL driving circuit 104 includes a second input sub-circuit 1041, a first step-down sub-circuit 1048, a second step-down sub-circuit 1050, a switch circuit 1049, and a second input sub-circuit 1041.
  • the switching circuit 1049, the first step-down sub-circuit 1048, and the second step-down sub-circuit 1050 are connected to a third voltage output sub-circuit 1051.
  • the second input sub-circuit 1041 includes a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, and a fifth output terminal.
  • the fourth output terminal When the control input terminal SS inputs the first level, the fourth output terminal outputs The first trigger pulse; when the control input terminal SS inputs the second level, the fourth output terminal outputs the second trigger pulse, the first trigger pulse and the second trigger pulse are reversed; when the control input terminal SS outputs the third level, the first trigger pulse Five output terminals output trigger pulses; the first step-down sub-circuit 1048 steps down the power supply voltage to the second voltage range; the second step-down sub-circuit 1050 steps down the power supply voltage to the third voltage range; the switch circuit 1049 and the first step down The voltage sub-circuit 1048 is connected, and the switch circuit 1049 is controlled by the fifth output terminal; wherein, when the fourth output terminal outputs the first trigger pulse, the third voltage output sub-circuit 1051 outputs the high and low level signals in the first voltage range; When the output terminal outputs the second trigger pulse, the third voltage output sub-circuit 1051 outputs the high and low level signals of the second voltage range; when the fifth output terminal outputs the
  • the third voltage output sub-circuit 1051 includes a UL output module 1042 connected to the first output end, the second output end, and the third output end of the second input sub-circuit 1041, respectively.
  • the third switching module 1045, the fourth switching module 1046, and the fifth switching module 1047 select the power supply voltage or the output voltage of the second step-down sub-circuit 1050 as the third voltage according to the fourth output terminal of the second input sub-circuit 1041
  • the output voltage of the sub-circuit 1051 is output.
  • the VCC terminal and the positive terminal of the power supply of the second input sub-circuit 1041, the positive terminal of the power supply of the second step-down sub-circuit 1050, and the first step-down sub-circuit The positive terminal of the power supply of the circuit 1048, the 0 selection terminal of the third switching module 1045, the 0 selection terminal of the fourth switching module 1046, and the 0 selection terminal of the fifth switching module 1047 are connected.
  • LIN1 is connected to the first input terminal of the second input sub-circuit 1041.
  • LIN2 is connected to the second input terminal of the second input sub-circuit 1041.
  • LIN3 is connected to the third input terminal of the second input sub-circuit 1041.
  • the control input terminal SS is connected to the control terminal of the second input sub-circuit 1041, the first output terminal of the second input sub-circuit 1041 is connected to the input terminal of the UL output circuit 1042; the second output terminal of the second input sub-circuit 1041 is connected to the VL The input terminal of the output circuit 1042 is connected; the third output terminal of the second input sub-circuit 1041 is connected to the input terminal of the VL output circuit 1043; the third output terminal of the first input sub-circuit 1011 is connected to the control terminal of the third switching module 1045, respectively The control terminal of the fourth switching module 1046 and the control terminal of the fifth switching module 1047 are connected.
  • the GND terminal and the power supply negative terminal of the second input sub-circuit 1041, the power supply negative terminal of the second step-down sub-circuit 1048, the power supply negative terminal of the UL output circuit 1042, the power supply negative terminal of the VL output circuit 1043, and WL output The negative terminal of the power supply of the circuit 1044 is connected; the output terminal of the second step-down sub-circuit 1048 is connected to the 1 selection terminal of the third switching module 1045, the 1 selection terminal of the fourth switching module 1046, and the 1 selection terminal of the fifth switching module 1047.
  • LO1 is connected to the output terminal of the UL output circuit 1042, LO2 is connected to the output terminal of the VL output circuit 1043, and LO3 is connected to the output terminal of the WL output circuit 1043.
  • the function of the second input sub-circuit 1041 is to output a signal in phase with the first input terminal of the second input sub-circuit 1041 at the first output terminal of the second input sub-circuit 1041;
  • the second input sub-circuit 1041 has the same phase signal at the second input end; the second input sub-circuit 1041 outputs the same phase signal at the third output end of the second input sub-circuit 1041.
  • the fifth output terminal of the second input sub-circuit 1041 When the control input terminal SS of the second input sub-circuit 1041 is at the VCC level, the fifth output terminal of the second input sub-circuit 1041 outputs a high level, and when the control input terminal SS of the second input sub-circuit 1041 is at 0 level , Output low level at the fourth output terminal of the second input sub-circuit 1041, when the control input terminal SS of the second input sub-circuit 1041 is at the VCC/2 level, output at the fourth output terminal of the second input sub-circuit 1041 High level.
  • the function of the first step-down sub-circuit 1048 is to output a voltage of 3V to the GND terminal at the output end of the first step-down sub-circuit 1048.
  • the function of the second step-down sub-circuit 1050 is to output a voltage of 15V to the GND terminal at the output end of the second step-down sub-circuit 1050.
  • the function of the UL output circuit 1042 is to output a signal whose voltage value is consistent with the positive terminal of the power supply at high level and the voltage value is consistent with the negative terminal of the power supply at low level.
  • the phase of the VL output circuit 1043 is consistent with that of LIN1.
  • the voltage value at level is consistent with the positive terminal of the power supply, and at low level the voltage value is consistent with the negative terminal of the power supply.
  • the phase is consistent with the signal of LIN2;
  • the function of the WL output circuit 1044 is to output a high level voltage value consistent with the positive terminal of the power supply ,
  • the signal whose voltage value is consistent with the negative terminal of the power supply at low level is consistent with the signal of LIN3.
  • the working principle of obtaining a signal consistent with LIN1, a signal consistent with LIN2, and a signal consistent with LIN3 are: LIN1, LIN2, and LIN3 pass through the second input sub-circuit 1041, respectively, in the first input sub-circuit 1041
  • the output phases of the second and third output terminals are the same as LIN1, LIN2, and LIN3 respectively, and the signal is a square wave after shaping;
  • the control input terminal SS is at 0 level, so that the fourth output terminal of the UL/VL/WL driving circuit 104 outputs a voltage from high to low.
  • the fixed end of the third switching module 1045 is connected to the 0 selection end of the third switching module 1045
  • the fixed end of the fourth switching module 1046 is connected to the 0 selection end of the fourth switching module 1046
  • the fifth switch The fixed end of the module 1047 is connected to the 0 selection end of the fifth switching module 1047, so that LO1 outputs a signal of 0-20V in phase with the input of UL output circuit 1042, and makes LO2 output a signal of 0-20V in phase with the input of VL output circuit 1043
  • the signal that makes LO3 output 0 ⁇ 20V is in phase with the input terminal of WL output circuit 1044;
  • the control input terminal SS is at the VCC level, so that the fourth output terminal of the UL/VL/WL driving circuit 104 outputs low to high voltage.
  • the fixed end of the third switching module 1045 is connected to the 1 selection end of the third switching module 1045
  • the fixed end of the fourth switching module 1046 is connected to the 1 selection end of the fourth switching module 1046
  • the fifth switch The fixed end of the module 1047 is connected to the 1 selection end of the fifth switching module 1047, so that LO1 outputs a signal of 0 ⁇ 3V in phase with the input terminal of UL output circuit 1042, and makes LO2 output 0 ⁇ 3V in phase with the input terminal of VL output circuit 1043
  • the control input terminal SS is at the VCC/2 level, so that the output of the fourth output terminal of the UL/VL/WL driving circuit 104 remains low ,
  • the third switching module 1045 is in the floating state, the fourth switching module 1046 is in the floating state, and the fifth switching module 1047 is in the floating state.
  • the fifth output terminal of the UL/VL/WL driving circuit 104 outputs a high level, and the fixed terminal of the switching circuit 1049 is connected to
  • the output terminal of the first step-down sub-circuit 1050 is connected to make LO1 output a signal of 0-15V in phase with the input terminal of the UL output circuit 1042, make LO2 output a signal of 0-15V in phase with the input terminal of the VL output circuit 1043, and make LO3 Output 0-15V signal in phase with the input terminal of WL output circuit 1044.
  • an electrical appliance 1000 includes a power device 100 and a processor 200 according to any one of the foregoing embodiments, and the processor 200 is connected to the power device 100.
  • the above-mentioned power device 100 can improve the adaptability of the Si IGBT tube, GaN MOS tube, and SiC MOS tube, so that the Si IGBT tube, GaN MOS tube, and SiC MOS tube All of the technical advantages can be brought into play.
  • the processor 200 is connected to the controller 10 of the power device 100. When the user operates the electrical appliance 1000, the processor 200 sends a signal to the controller 130 of the power device 100, and the controller 130 controls the control input terminal SS to connect to the first level and the second level. Level or the third level, the electrical appliance 1000 switches the desired function.
  • the above-mentioned electrical appliance 1000 may be an air conditioner, a washing machine, a refrigerator, or an induction cooker, etc., and the power device 100 therein can realize the functions of the power device 100 described in the foregoing section.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include at least one of the features. In the description of the present application, “plurality” means at least two, such as two or three, unless otherwise specifically defined.

Abstract

一种功率器件(100)，功率器件(100)包括控制输入端(SS)、上桥臂开关管(127)和下桥臂开关管(128)、与控制输入端(SS)相连且用于驱动上桥臂开关管(127)的第一驱动电路(129)、与控制输入端(SS)相连且用于驱动下桥臂开关管(128)的第二驱动电路(120)。控制输入端(SS)能够接入第一电平、第二电平或第三电平。当控制输入端(SS)接入第一电平时，第一驱动电路(129)及第二驱动电路(120)输出第一电压范围的高低电平信号。当控制输入端(SS)接入第二电平时，第一驱动电路(129)及第二驱动电路(120)输出第二电压范围的高低电平信号。当控制输入端(SS)接入第三电平时，第一驱动电路(129)及第二驱动电路(120)输出第三电压范围的高低电平信号。第一电压范围、第二电压范围及第三电压范围不同。

Description

功率器件及电器
优先权信息
本申请请求2019年03月19日向中国国家知识产权局提交的、专利申请号为201910208194.7的专利申请的优先权和权益，并且通过参照将其全文并入此处。
技术领域
本申请涉及电器技术领域，更具体而言，涉及一种功率器件及电器。
背景技术
现有技术中，随着对系统能耗要求的不断提高，智能功率模块(Intelligent Power Module，IPM)的功耗成为变频空调的变频电控功耗主要来源，如何降低智能功率模块功耗成为了影响智能功率模块乃至变频空调进一步推广应用的重要课题。通过GaN器件或SiC器件替代Si器件是降低智能功率模块功耗的有效途径，但是随之也带来了新的问题。
GaN器件的阈值电压(3V)、SiC器件的阈值电压(20V)和Si器件的阈值电压(15V)不同。GaN器件的阈值电压低于Si器件的阈值电压，如果采用同一款高压集成电路管(High Voltage Integrated Circuit，HVIC)进行驱动，容易造成GaN器件的栅极被击穿；SiC器件的阈值电压高于Si器件的阈值电压，如果采用同一款高压集成电路管进行驱动，容易造成SiC器件的开通过程不彻底，SiC器件的低功耗优势得不到发挥。但如果使用不同的高压集成电路管进行驱动，由造成生产过程中的物料组织的困难，有混料风险，也推高了智能功率模块的成本。并且，如果为了保证GaN器件不被击穿，驱动Si器件的高压集成电路管使用更低的电压进行供电，也容易造成整个Si器件智能功率模块的功耗提高，甚至造成Si器件不能正常工作。
发明内容
本申请提供了一种功率器件及电器。
本申请的功率器件包括控制输入端、上桥臂开关管和下桥臂开关管、与所述控制输入端相连且用于驱动所述上桥臂开关管的第一驱动电路、与所述控制输入端相连且用于驱动所述下桥臂开关管的第二驱动电路。所述控制输入端能够接入第一电平、第二电平或第三电平。当所述控制输入端接入第一电平时，所述第一驱动电路及所述第二驱动电路输出第一电压范围的高低电平信号。当所述控制输入端接入第二电平时，所述第一驱动电路及所述第二驱动电路输出第二电压范围的高低电平信号。当所述控制输入端接入第三电平时，所述第一驱动电路及所述第二驱动电路输出第三电压范围的高低电平信号。所述第一电压范围、所述第二电压范围及所述第三电压范围不同。
本申请实施方式的电器包括上述所述的功率器件和处理器，所述处理器连接所述功率器件。
本申请实施方式的功率器件及电器在不需要改变外部输入电压的前提下，能够输出多个不同电压范围的高低电平信号以适应不同类型的器件(如GaN器件、SiC器件及Si器件)的使用需求，不同类型的器件的导通过程都处于完全导通状态，且其性能得到充分的发挥。另外，由于采用同一个第一驱动电路及第二驱动电路就能实现输出不同电压范围的高低电平信号，在功率器件的生产过程中没有混料风险，便于物料组织，降低物料成本。
本申请的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请的上述和/或附加的方面和优点从结合下面附图对实施方式的描述中将变得明显和容易理解，其中：
图1为本申请某些实施方式的功率器件的电路结构图；
图2为本申请某些实施方式的功率器件的通过邦定线将控制输入端与电源或地相连的示意图；
图3为本申请实施方式的功率器件的模块示意图；
图4至图11为本申请某些实施方式的上桥臂开关管、下桥臂开关管的结构示意图；
图12为本申请某些实施方式的UH驱动电路的示意图；
图13为本申请某些实施方式的VH驱动电路的示意图；
图14为本申请某些实施方式的WH驱动电路的示意图；
图15为本申请某些实施方式的UL/VL/WL驱动电路的示意图；
图16为本申请某些实施方式的电器的模块示意图。
具体实施方式
以下结合附图对本申请的实施方式作进一步说明。附图中相同或类似的标号自始至终表示相同或类似的元件或具有相同或类似功能的元件。
另外，下面结合附图描述的本申请的实施方式是示例性的，仅用于解释本申请的实施方式，而不能理解为对本申请的限制。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。而且，第一特征在第二特征“之上”、“上方”和“上面”可是第一特征在第二特征正上方或斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”可以是第一特征在第二特征正下方或斜下方，或仅仅表示第一特征水平高度小于第二特征。
请参阅图1，本申请实施方式提供一种功率器件100，本申请的功率器件100包括控制输入端SS、上桥臂开关管127和下桥臂开关管128、与控制输入端SS相连且用于驱动上桥臂开关管127的第一驱动电路129、与控制输入端SS相连且用于驱动下桥臂开关管128的第二驱动电路120。控制输入端SS能够接入第一电平、第二电平或第三电平。当控制输入端SS接入第一电平时，第一驱动电路129及第二驱动电路120输出第一电压范围的高低电平信号。当控制输入端SS接入第二电平时，第一驱动电路129及第二驱动电路120输出第二电压范围的高低电平信号。当控制输入端SS接入第三电平时，第一驱动电路129及第二驱动电路120输出第三电压范围的高低电平信号。第一电压范围、第二电压范围及第三电压范围不同。
本申请的功率器件100的在不需要改变外部输入电压的前提下，能够输出不同电压范围的高低电平信号以适应不同类型的器件(如GaN器件、SiC器件及Si器件)的使用需求，不同类型的器件的导通过程都处于完全导通状态，且其性能得到充分的发挥。另外，由于采用同一个第一驱动电路及第二驱动电路就能实现输出不同电压范围的高低电平信号，在功率器件的生产过程中没有混料风险，便于物料组织，降低物料成本。
请参阅图1，在某些实施方式中，第一驱动电路129包括UH驱动电路101、VH驱动电路102与WH驱动电路103；第二驱动电路120包括UL/VL/WL驱动电路104；上桥臂开关管127包括第一上桥臂开关管121、第二上桥臂开关管122与第三上桥臂开关管123；下桥臂开关管128包括第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126；其中，控制输入端SS与UH驱动电路101、VH驱动电路102和WH驱动电路103均相连，且UH驱动电路101、VH驱动电路102与WH驱动电路103分别驱动第一上桥臂开关管121、第二上桥臂开关管122与第三上桥臂开关管123；UH驱动电路101与第一上桥臂开关管121相连，VH驱动电路102与第二上桥臂开关管122相连，WH驱动电路103与第三上桥臂开关123相连；控制输入端SS与UL/VL/WL驱动电路104相连，且UL/VL/WL驱动电路104驱动第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126，UL/VL/WL驱动电路104分别与第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126连接。本实施方式中，UH驱动电路101、VH驱动电路102、WH驱动电路103和UL/VL/WL驱动电路104可为电器1000，例如空调的压缩机的三相驱动电路，其中，UH驱动电路101与UL驱动电路104连接，VH驱动电路102与VL驱动电路104连接，WH驱动电路103与WL 驱动电路104连接。
其中，第一电平为0，第二电平为电源电平VCC，第三电平为二分之一电源电平VCC；第一电压范围为0～20V，第二电压范围为0～3V，第三电压范围为0～15V。
更多地，功率器件100还包括GND端、VCC端与参考电压源Vreg，当控制输入端SS通过邦定线115(bonding wire)与GND端连接时，控制输入端SS接入第一电平；当控制输入端SS通过邦定线115与VCC端连接时，控制输入端SS接入第二电平；当控制输入端SS通过邦定线115与参考电压源Vreg连接时，控制输入端SS接入第三电平。
具体地，请参阅图1，将UH驱动电路101、VH驱动电路102、WH驱动电路103和UL/VL/WL驱动电路104集成在高压集成电路管111内部，高压集成电路管111的VCC端作为功率器件100的低压区供电电源正端VDD，VDD一般为15V；在高压集成电路管111内部，VCC端与UH驱动电路101、VH驱动电路102、WH驱动电路103、UL/VL/WL驱动电路104的供电电源正端相连、参考电压源Vreg的供电电源正端相连；在此，参考电压源Vreg是在高压集成电路管111内部生成的一个电压值为VCC/2的电压源。
高压集成电路管111的HIN1端作为功率器件100的U相上桥臂输入端UHIN，在高压集成电路管111内部与UH驱动电路101的输入端相连；高压集成电路管111的HIN2端作为功率器件100的V相上桥臂输入端VHIN，在高压集成电路管111内部与VH驱动电路102的输入端相连；高压集成电路管111的HIN3端作为功率器件100的W相上桥臂输入端WHIN，在高压集成电路管111内部与WH驱动电路103的输入端相连；高压集成电路管111的LIN1端作为功率器件100的U相下桥臂输入端ULIN，在高压集成电路管111内部与UL/VL/WL驱动电路104的第一输入端相连；高压集成电路管111的LIN2端作为功率器件100的V相下桥臂输入端VLIN，在高压集成电路管111内部与UL/VL/WL驱动电路104的第二输入端相连；高压集成电路管111的LIN3端作为功率器件100的W相下桥臂输入端WLIN，在高压集成电路管111内部与UL/VL/WL驱动电路104的第三输入端相连。在此，功率器件100的U、V、W三相的六路输入接收0V或5V的输入信号。
高压集成电路管111的GND端作为功率器件100的低压区供电电源负端COM，并与UH驱动电路101、VH驱动电路102、WH驱动电路103、UL/VL/WL驱动电路104供电电源负端相连；高压集成电路管111的VB1端在高压集成电路管111内部与UH驱动电路101的高压区供电电源正端相连；在高压集成电路管111外部连接电容131的一端，并作为功率器件100的U相高压区供电电源正端UVB；高压集成电路管111的HO1端在高压集成电路管111内部与UH驱动电路101的输出端相连，在高压集成电路管111外部与第一上桥臂开关管121的控制极相连；高压集成电路管111的VS1端在高压集成电路管111内部与UH驱动电路101的高压区供电电源负端相连，在高压集成电路管111外部与第一上桥臂开关管121的输出负极、第一下桥臂开关管124的输出输出正极、电容131的另一端相连，并作为功率器件100的U相高压区供电电源负端UVS。
高压集成电路管111的VB2端在高压集成电路管111内部与VH驱动电路102的高压区供电电源正端相连，在高压集成电路管111外部连接电容132的一端，作为功率器件100的U相高压区供电电源正端VVB；高压集成电路管111的HO2端在高压集成电路管111内部与VH驱动电路102的输出端相连，在高压集成电路管111外部与第二上桥臂开关管122的控制极相连；高压集成电路管111的VS2端在高压集成电路管111内部与VH驱动电路102的高压区供电电源负端相连，在高压集成电路管111外部与上桥臂功率管122的输出负极、第二下桥臂开关管125的输出正极、电容132的另一端相连，并作为功率器件100的W相高压区供电电源负端VVS。
高压集成电路管111的VB3端在高压集成电路管111内部与WH驱动电路103的高压区供电电源正端相连，在高压集成电路管111外部连接电容133的一端，作为功率器件100的W相高压区供电电源正端WVB；高压集成电路管111的HO3端在高压集成电路管111内部与WH驱动电路101的输出端相连，在高压集成电路管111外部与第三上桥臂开关管123的控制极相连；高压集成电路管111的VS3端在高压集成电路管111内部与WH驱动电路103的高压区供电电源负端相连，在高压集成电路管111外部与功率管123的输出负极、第三下桥臂开关管126的输出正极、电容133的另一端相连，并作为功率器件100的W相高压区供电电源负端WVS。
高压集成电路管111的LO1端与第一下桥臂开关管124的控制极相连；高压集成电路管111的LO2端与第二下 桥臂开关管125的控制极相连；高压集成电路管111的LO3端与第三下桥臂开关管126的控制极相连；第一下桥臂开关管124的输出负极作为功率器件100的U相低电压参考端UN；第二下桥臂开关管125的输出负极作为功率器件100的V相低电压参考端VN；第三下桥臂开关管126的输出负极作为功率器件100的W相低电压参考端WN；第一上桥臂开关管121的输出正极、第二上桥臂开关管122的输出正极、第三上桥臂开关管123的输出正极相连，并作为功率器件100的高电压输入端P，P一般接300V。在此，VDD的供电电压为20V。
在此，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125和第三下桥臂开关管126可以是Si IGBT管(即Si器件)和FRD管并联的组合，也可以是IGBT管和GaN SBD(Schottky Barrier Diode，肖特基二极管)管的组合，也可以是GaN MOS管(Metal Oxide Semiconductor，金属-氧化物-半导体)(即GaN器件)，也可以是GaN MOS管和FRD管的组合，也可以是GaN MOS管和GaN SBD管的组合；也可以是IGBT管和SiC SBD管的组合，也可以是SiC MOS管(即SiC器件)，也可以是SiC MOS管和FRD管的组合，也可以是SiC MOS管和SiC SBD管的组合。
在功率器件100中，高压集成电路管111的作用是：当控制输入端SS为0电平时，HO1～HO3、LO1～LO3输出0～20V的高低电平信号，也即是说，当控制输入端SS为第一电平时，UH驱动电路101、VH驱动电路102、WH驱动电路103和UL/VL/WL驱动电路104输出第一电压范围的高低电平信号；当控制输入端SS为VCC电平时，HO1～HO3、LO1～LO3输出0～3V的高低电平信号，也即是说，当控制输入端SS为第二电平时，UH驱动电路101、VH驱动电路102、WH驱动电路103和UL/VL/WL驱动电路104输出第二电压范围的高低电平信号；当控制输入端SS为VCC/2电平时，HO1～HO3、LO1～LO3输出0～15V的高低电平信号，也即是说，当控制输入端SS为第三电平时，UH驱动电路101、VH驱动电路102、WH驱动电路103和UL/VL/WL驱动电路104输出第三电压范围的高低电平信号。
而在实际应用中，请结合图1与图2，功率器件100包括第一连接部116、第二连接部117与SSS端，第一连接部116用于连接VCC端与VDD端，第二连接部117用于连接GND端与COM端，SSS端用于连接SS端与参考电压源Vreg。第一连接部116与第二连接部117可以为具备导电传输功能的导线、电极等。
具体地，当第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126均包括SiC器件时(SiC器件为图9至图11所示的SiC MOS管1211。例如，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126均为图9所示的SiC MOS管1211的方式；或，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126均为图10所示的SiC MOS管1211和Si FRD管1212的组合方式；或，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126均为图11所示的SiC MOS管1211和SiC SBD管1212或GaN SBD管1212的组合方式)，在功率器件100内部，控制输入端SS通过邦定线115与GND端相连，控制输入端SS接入第一电平，第一驱动电路129及第二驱动电路120输出第一电压范围的高低电平信号；
当第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126均包括GaN器件时(GaN器件为图6至图8所示的GaN MOS管1211。例如，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126均为图6所示的GaN MOS管1211的方式；或，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126均为图7所示的GaN MOS管1211和Si FRD管1212的组合方式；或，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126均为图8所示的GaN MOS管1211和GaN SBD管1212或SiC SBD管1212的组合方式)，在功率器件100内部，SSS端通过邦定线115与VCC端相连，控制输入端SS接入第二电平，第一驱动电路129及第二驱动电路120输出第二电压范围的高低电平信号；
当第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126均包括Si器件时(Si器件为图4至图5所示的Si IGBT管1211。例如，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126均为图4所示的Si IGBT管1211和Si FRD管1212的组合方式；或，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126均为图5所示的Si IGBT管1211和GaN SBD管1212或SiC SBD管1212的组合方式)，在功率器件100内部，SSS端通过邦定线115与参考电压源Vreg相连，控制输入端SS接入第三电平，第一驱动电路129及第二驱动电路120输出第三电压范围的高低电平信号。
综上可知，本申请实施方式的功率器件100的供电电压为20V不变，高压集成电路管111的功耗没有发生本质增加；驱动GaN器件、SiC器件和驱动Si器件为同一高压集成电路管111，生产过程中没有混料风险，便于物料组织，降低物料成本；驱动GaN器件使用3V的电压，驱动SiC器件使用20V的电压，驱动Si器件使用15V的电压，使GaN器件、SiC器件和Si器件的导通过程都处于完全导通状态的同时也不会对其造成击穿，使各自性能得到发挥。
请参阅图1与图3，在某些实施方式中，功率器件100包括控制器130，控制输入端SS与控制器130连接，控制器130用于控制控制输入端SS接入第一电平、第二电平或第三电平。
控制器130可以是包括用于输出第一电平、第二电平或第三电平的数字电路，也可以包括触发器等，但不限于此。控制器130可安装在高压集成电路管111的内部，例如安装在控制输入端SS与SSS端之间或其它地方。控制器130还可安装在高压集成电路管111的外部，例如安装在靠近控制输入端SS的地方或其它地方。或者控制器130安装在电器的微处理器上。
图4至图11是上桥臂开关管127与下桥臂开关管128的组合方式，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126的结构一致，以第一上桥臂开关管121为例进行说明：
图4所示的是Si IGBT管1211和Si FRD管1212的组合方式：(1)Si IGBT管1211的集电极与Si FRD管1212的阴极相连，并作为第一上桥臂开关管121的输出正极；(2)Si IGBT管1211的发射极与Si FRD管1212的阳极相连，并作为第一上桥臂开关管121的输出负极；(3)Si IGBT管1211的栅极作为第一上桥臂开关管121的控制极；
图5所示的是Si IGBT管1211和GaN SBD管1212或SiC SBD管1212的组合方式：(1)Si IGBT管1211和GaN SBD管1212的组合方式，其中，Si IGBT管1211的集电极与GaN SBD管1212的阴极相连，并作为第一上桥臂开关管121的输出正极；Si IGBT管1211的发射极与GaN SBD管1212的阳极相连，并作为第一上桥臂开关管121的输出负极；(2)Si IGBT管1211和SiC SBD管1212的组合方式，其中，Si IGBT管1211和SiC SBD管1212的阴极相连，并作为第一上桥臂开关管121的输出正极；Si IGBT管1211的发射极与Si SBD管的阳极相连，并作为第一上桥臂开关管121的输出负极；(3)Si IGBT管1211的栅极作为第一上桥臂开关管121的控制极；
图6所示的是GaN MOS管1211的方式：(1)GaN MOS管1211的漏极作为第一上桥臂开关管121的输出正极；(2)GaN MOS管1211的源极作为第一上桥臂开关管121的输出负极；(3)GaN MOS管1211的栅极作为第一上桥臂开关管121的控制极；
图7所示的是GaN MOS管1211和Si FRD管1212的组合方式：(1)GaN MOS管1211的漏极与Si FRD管1212的阴极相连，并作为第一上桥臂开关管121的输出正极；(2)GaN MOS管1211的源极与Si FRD管1212的阳极相连，并作为第一上桥臂开关管121的输出负极；(3)GaN MOS管1211的栅极作为第一上桥臂开关管121的控制极；
图8所示的是GaN MOS管1211和GaN SBD管1212或SiC SBD管1212的组合方式：(1)GaN MOS管1211和GaN SBD管1212的组合方式，其中，GaN MOS管1211的漏极与GaN SBD管1212的阴极相连，并作为第一上桥臂开关管121的输出正极；GaN MOS管1211的源极与GaN SBD管1212的阳极相连，并作为第一上桥臂开关管121的输 出负极；(2)GaN MOS管1211和SiC SBD管1212的组合方式，其中，GaN MOS管1211的漏极与SiC SBD管1212的阴极相连，并作为第一上桥臂开关管121的输出正极；GaN MOS管1211的源极与SiC SBD管1212的阳极相连，并作为第一上桥臂开关管121的输出负极；(3)Si IGBT管1211的栅极作为第一上桥臂开关管121的控制极；
图9所示的是SiC MOS管1211的方式：(1)SiC MOS管1211的漏极作为第一上桥臂开关管121的输出正极；(2)SiC MOS管1211的源极作为第一上桥臂开关管121的输出负极；(3)SiC MOS管1211的栅极作为第一上桥臂开关管121的控制极；
图10所示的是SiC MOS管1211和Si FRD管1212的组合方式：(1)SiC MOS管1211的漏极与Si FRD管1212的阴极相连，并作为第一上桥臂开关管121的输出正极；(2)SiC MOS管1211的源极与Si FRD管1212的阳极相连，并作为第一上桥臂开关管121的输出负极；(3)SiC MOS管1211的栅极作为第一上桥臂开关管121的控制极；
图11所示的是SiC MOS管1211和SiC SBD管1212或GaN SBD管1212的组合方式：(1)SiC MOS管1211和SiC SBD管1212的组合方式，其中，SiC MOS管1211的漏极与SiC SBD管1212的阴极相连，并作为第一上桥臂开关管121的输出正极；SiC MOS管1211的源极与SiC SBD管1212的阳极相连，并作为第一上桥臂开关管121的输出负极；(2)SiC MOS管1211和GaN SBD管1212的组合方式，其中，SiC MOS管1211的漏极与GaN SBD管1212的阴极相连，并作为第一上桥臂开关管121的输出正极；SiC MOS管1211的源极与GaN SBD管1212的阳极相连，并作为第一上桥臂开关管121的输出负极；(3)Si IGBT管1211的栅极作为第一上桥臂开关管121的控制极。
可以理解，第二上桥臂开关管122可以为图4至图11所示的任意一种组合方式的开关管；第三上桥臂开关管123可以为图4至图11所示的任意一种组合方式的开关管；第一下桥臂开关管124可以为图4至图11所示的任意一种组合方式的开关管；第二下桥臂开关管125可以为图4至图11所示的任意一种组合方式的开关管；第三下桥臂开关管126可以为图4至图11所示的任意一种组合方式的开关管。
另外，上述的第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126的结构一致是指：在实际的功率器件100中，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126全部为图4所示的Si IGBT和Si FRD的组合方式的开关管；或者，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126全部为图5所示的Si IGBT和GaN SBD管或SiC SBD管的组合方式的开关管；或者，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126全部为图6所示的GaN MOS的方式的开关管；或者，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126全部为图7所示的GaN MOS和Si FRD的组合方式的开关管；或者，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126全部为图8所示的GaN MOS和GaN SBD管或SiC SBD管的组合方式的开关管；或者，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126全部为图9所示的SiC MOS的方式的开关管；或者，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126全部为图10所示的SiC MOS和Si FRD的组合方式的开关管；或者，第一上桥臂开关管121、第二上桥臂开关管122、第三上桥臂开关管123、第一下桥臂开关管124、第二下桥臂开关管125与第三下桥臂开关管126全部为图11所示的SiC MOS和SiC SBD管或GaN SBD管的组合方式的开关管。
请参阅图12至图14，UH驱动电路101、VH驱动电路102、WH驱动电路103的结构相同，图12、图13以及图14分别为UH驱动电路101、VH驱动电路102与WH驱动电路103的实施例。以下说明书将分别对应介绍UH驱动电路101、VH电路102以及WH电路103的结构。
请参阅图12，在某些实施方式中，UH驱动电路101包括：第一输入子电路1011、第一开关管1012、第二开关管1013、第三开关管1014、第四开关管1021、输出子电路1017、第一电压输出子电路1023、第二电压输出子电 路1024。第一输入子电路1011与控制输入端SS相连。第一输入子电路1011包括第一输出端、第二输出端、第三输出端与第四输出端。其中，当控制输入端SS为第一电平时，第一输出端与第二输出端输出触发脉冲，第三输出端输出第一时间长度的触发脉冲；当控制输入端SS为第二电平时，第一输出端与第二输出端输出触发脉冲，第三输出端输出第二时间长度的触发脉冲，第一时间长度小于第二时间长度；当控制输入端SS为第三电平时，第一输出端与第二输出端输出触发脉冲，第四输出端输出第一时间长度的触发脉冲。
第一开关管1012与第一输出端相连，在第一输出端输出触发脉冲时，第一开关管1012导通；第二开关管1013与第二输出端相连，在第二输出端输出触发脉冲时，第二开关管1013导通；第三开关管1014与第三输出端相连，在第三输出端输出触发脉冲时，第三开关1014导通；第四开关管1021与第四输出端相连，在第四输出端输出触发脉冲时，第四开关管1021导通。
第一电压输出子电路1023分别与第一开关管1012、第二开关管1013及第三开关管1014相连；第二电压输出子电路1024与第四开关管1021相连；输出子电路1017分别与第一电压输出子电路1023及第二电压输出子电路1024连接。
请参阅图12，在某些实施方式中，第一电压输出子电路1023包括与第一开关管1012及第二开关管1013相连的锁存及降压电路1016、第一切换模块1018、与第三开关管1014相连的第一锁存电路1015。第一切换模块1018分别与锁存及降压电路1016和电源相连；当第三开关管1014导通第一时间长度时，第一锁存电路1015用于控制第一切换模块1018动作以将电源的电压作为第一电压输出子电路1023的输出电压；当第三开关管1014导通第二时间长度时，第一锁存电路1015用于控制第一切换模块1018动作以将锁存及降压电路1016的输出电压作为第一电压输出子电路1023的输出电压。
请参阅图12，在某些实施方式中，第二电压输出子电路1024包括第一降压电路1022、第二切换模块1019、与第四开关管1021相连的第二锁存电路1020。第二切换模块1019分别与第一电压输出子电路1023和第一降压电路1022相连，第二锁存电路1020对第二切换模块1019进行控制，当第四开关管1021未导通时，将输出子电路1017与第一电压输出子电路1023相连，当第四开关管1021导通第一时间长度时，将输出子电路1017与第一降压电路1022相连。
请参阅图1与图12，在UH驱动电路101内部，VCC端与第一输入子电路1011的供电电源正端相连，HIN1与第一输入子电路1011的输入端相连，控制输入端SS与第一输入子电路1011的控制端相连。第一输入子电路1011的第一输出端与第一开关管1012的栅极相连，第一输入子电路1011的第二输出端与第二开关管1013的栅极相连，第一输入子电路1011的第三输出端与高压第三开关管1014的栅极相连，第一输入子电路1011的第四输出端与第四开关管1021的栅极相连。GND端与第一输入子电路1011的供电电源负端、第一开关管1012的衬底和源极、第二开关管1013的衬底和源极、第三开关管1014的衬底和源极相连、第四开关管1021的衬底和源极相连。
第一开关管1012的漏极进入高压区与锁存及降压电路1016的第一输入端相连；第二开关管1013的漏极进入高压区与锁存及降压电路1016的第二输入端相连；第三开关管1014的漏极进入高压区与第一锁存电路1015的使能端端相连；第四开关管1021的漏极进入高压区与锁存电路1020的使能端端相连。锁存及降压电路1016的第一输出端与模拟开关1018的1选择端相连；锁存及降压电路1016的第二输出端与输出电路1017的输入端相连；锁存电路1015的输出端与模拟开关1018的控制端相连；模拟开关1018的固定端与输出电路1017的供电电源正端相连；降压电路1022的输出端与第二切换模块1019的活动端相连；第二锁存电路1020的输出端与第二切换模块1019的控制端相连。VB1与第一锁存电路1015的供电电源正端、第二锁存电路1020的供电电源正端、锁存与降压电路1016的供电电源正端、第一降压电路1022的供电电源正端、模拟开关1018的0选择端相连。VS1与第一锁存电路1015的供电电源负端、第二锁存电路1020的供电电源负端、锁存与降压电路1016的供电电源负端、第一降压电路1022的供电电源负端、输出子电路1017的供电电源负端相连。HO1与输出子电路1017的输出端相连。
第一输入子电路1011的作用是：在第一输入子电路1011输入端信号的上升沿，在第一输入子电路1011的第一输出端输出一个脉冲宽度为300ns左右的脉冲信号；在第一输入子电路1011输入端信号的下降沿，在第一输入 子电路1011的第二输出端输出一个脉冲宽度为300ns左右的脉冲信号；当第一输入子电路1011的控制输入端为VCC电平时，在第一输入子电路1011的第三输出端输出一个脉冲宽度为600ns左右的脉冲信号；当第一输入子电路1011的控制输入端为0电平时，在第一输入子电路1011的第三输出端输出一个脉冲宽度为300ns左右的脉冲信号；当第一输入子电路1011的控制输入端为VCC/2电平时，在第一输入子电路1011的第四输出端输出一个脉冲宽度为300ns左右的脉冲信号。
第一锁存电路1015的作用是：当第一锁存电路1015输入端信号出现600ns的低电平时，第一锁存电路1015的输出端输出高电平，当第一锁存电路1015输入端信号出现300ns的低电平时，第一锁存电路1015的输出端输出低电平，当第一锁存电路1015输入端信号从未出现低电平时，第一锁存电路1015的输出端输出VCC/2电压。
锁存及降压电路1016的作用是：在锁存及降压电路1016的第一输入端出现300ns低电平时，在锁存及降压电路1016的第二输出端输出持续高电平；在锁存及降压电路1016的第二输入端出现300ns低电平时，在锁存及降压电路1016的第二输出端输出持续低电平，即将HIN1的信号在第一输入子电路1011两个输出端分解出的两个脉冲信号重新整合成完整的信号。并且，锁存及降压电路1016内部有降压电路，在锁存及降压电路1016的第二输出端输出对VS1为3V的电压。
第二锁存电路1020的作用是：在锁存及降压电路1016的第一输入端出现300ns低电平时，在锁存及降压电路1016的第二输出端输出持续高电平，否则输出低电平。输出子电路1017的作用是：输出一个高电平时电压值与其供电电源正端一致、低电平时电压值与其供电电源负端一致的相位与HIN1一致的信号。在此，使用300ns或600ns的窄脉冲信号控制第一开关管1012、第二开关管1013、第三开关管1014与第四开关管1021，是为了通过缩短第一开关管1012、第二开关管1013、第三开关管1014与第四开关管1021的导通时间降低其功耗。
上述通过缩短第一开关管1012、第二开关管1013、第三开关管1014与第四开关管1021的导通时间降低其功耗的工作原理是：
HIN1的信号经过第一输入子电路1011后，分别在信号的上升沿和下降沿在第一输入子电路1011的第一输出端和第二输出端输出一个300ns的窄脉冲，该窄脉冲分别控制第一开关管1012和第二开关管1013导通300ns，使锁存及降压电路1016的第一输入端和第二输入端分别产生300ns的低电平，锁存及降压电路1016内部具有RS触发器等装置，使两个低电平信号被重新组合成完整的与HIN1同相的信号；
1、当上桥臂开关管127与下桥臂开关管128均包含SiC MOS管时，控制输入端SS为0电平，从而第一输入子电路1011的第四输出端不会出现高电平，第四开关管1021不会开通，第二锁存电路1020的输入端不会出现低电平，则第二锁存电路1020的输出端保持低电平，模拟开关1019处于断开状态。并且第一输入子电路1011的第三输出端出现300ns(第一时间长度)高电平脉冲，第三开关管1014出现300ns的导通，第一锁存电路1015的输入端出现300ns低电平，则第一锁存电路1015的输出端输出从高到低电平，输出子电路1017的供电电源正端与VB1相连，即输出子电路1017输出0～20V的高低电平。
2、当上桥臂开关管127与下桥臂开关管128均包含GaN MOS管，控制输入端SS为VCC电平，从而第一输入子电路1011的第四输出端不会出现高电平，第四开关管1021不会开通，第二锁存电路1020的输入端不会出现低电平，则第二锁存电路1020的输出端保持低电平，第二切换模块1019处于断开状态。并且第一输入子电路1011的第三输出端出现600ns(第二时间长度)高电平脉冲，第三开关管1014出现600ns的导通，第一锁存电路1015的输入端出现600ns低电平，则第一锁存电路1015的输出端输出从低到高电平，输出子电路1017的供电电源正端与锁存及降压电路1016的输出端相连，即输出子电路1017输出0～3V的高低电平。
3、当上桥臂开关管127与下桥臂开关管128均包含Si IGBT管，控制输入端SS为VCC/2电平，从而第一输入子电路1011的第三输出端不会出现高电平，第三开关管1014不会开通，第一锁存电路1015的输入端不会出现低电平，则第一锁存电路1015的输出端一直在低电平，第一切换模块1018处于悬空状态。并且第一输入子电路1011的第四输出端出现300ns(第一时间长度)高电平脉冲，第四开关管1021出现300ns的导通，第二锁存电路1020的输入端出现300ns低电平，则第二锁存电路1020的输出端输出高电平，输出子电路1017的供电电源正端与第二 降压电路1022的输出端相连，即输出子电路1017输出0～15V的高低电平。
请参阅图13，在某些实施方式中，VH驱动电路102包括：第一输入子电路1211、输出子电路1217、第一开关管1212、第二开关管1213、第三开关管1214、第四开关管1221、第一电压输出子电路1223、第二电压输出子电路1224。第一输入子电路1211与控制输入端SS相连，第一输入子电路1211包括第一输出端、第二输出端、第三输出端与第四输出端，其中，当控制输入端SS为第一电平时，第一输出端与第二输出端输出触发脉冲，第三输出端输出第一时间长度的触发脉冲；当控制输入端SS为第二电平时，第一输出端与第二输出端输出触发脉冲，第三输出端输出第二时间长度的触发脉冲，第一时间长度小于第二时间长度；当控制输入端SS为第三电平时，第一输出端与第二输出端输出触发脉冲，第四输出端输出第一时间长度的触发脉冲。
第一开关管1212与第一输出端相连，在第一输出端输出触发脉冲时，第一开关管1212导通；第二开关管1213与第二输出端相连，在第二输出端输出触发脉冲时，第二开关管1213导通；第三开关管1214与第三输出端相连，在第三输出端输出触发脉冲时，第三开关1214导通；第四开关管1221与第四输出端相连，在第四输出端输出触发脉冲时，第四开关管1221导通。
第一电压输出子电路1223分别与第一开关管1212、第二开关管1213及第三开关管1214相连。第二电压输出子电路1224与第四开关管1221相连。输出子电路1217分别与第一电压输出子电路1223及第二电压输出子电路1224连接。
请参阅图13，在某些实施方式中，第一电压输出子电路1223包括与第一开关管1212及第二开关管1213相连的锁存及降压电路1216、第一切换模块1218、与第三开关管1214相连的第一锁存电路1215。第一切换模块1218分别与锁存及降压电路1216和电源相连；当第三开关管1214导通第一时间长度时，第一锁存电路1215用于控制第一切换模块1218动作以将电源的电压作为第一电压输出子电路1223的输出电压；当第三开关管1214导通第二时间长度时，第一锁存电路1215用于控制第一切换模块1218动作以将锁存及降压电路1216的输出电压作为第一电压输出子电路1223的输出电压。
请参阅图13，在某些实施方式中，第二电压输出子电路1224包括第一降压电路1222、第二切换模块1219、与第四开关管1221相连的第二锁存电路1220。第二切换模块1219分别与第一电压输出子电路1223和第一降压电路1222相连，第二锁存电路1220对第二切换模块1219进行控制，当第四开关管1221未导通时，将输出子电路1217与第一电压输出子电路1223相连，当第四开关管1221导通第一时间长度时，将输出子电路1217与第一降压电路1222相连。
请参阅图1与图13，在VH驱动电路102内部，VCC端与第一输入子电路1211的供电电源正端相连，HIN1与第一输入子电路1211的输入端相连，控制输入端SS与第一输入子电路1211的控制端相连。第一输入子电路1211的第一输出端与第一开关管1212的栅极相连，第一输入子电路1211的第二输出端与第二开关管1213的栅极相连，第一输入子电路1211的第三输出端与高压第三开关管1214的栅极相连，第一输入子电路1211的第四输出端与第四开关管1221的栅极相连。
GND端与第一输入子电路1211的供电电源负端、第一开关管1212的衬底和源极、第二开关管1213的衬底和源极、第三开关管1214的衬底和源极相连、第四开关管1221的衬底和源极相连。第一开关管1212的漏极进入高压区与锁存及降压电路1216的第一输入端相连；第二开关管1213的漏极进入高压区与锁存及降压电路1216的第二输入端相连；第三开关管1214的漏极进入高压区与第一锁存电路1215的使能端端相连；第四开关管1221的漏极进入高压区与锁存电路1220的使能端端相连。
锁存及降压电路1216的第一输出端与模拟开关1218的1选择端相连；锁存及降压电路1216的第二输出端与输出电路1217的输入端相连；锁存电路1215的输出端与模拟开关1218的控制端相连；模拟开关1218的固定端与输出电路1217的供电电源正端相连；降压电路1222的输出端与第二切换模块1219的活动端相连；第二锁存电路1220的输出端与第二切换模块1219的控制端相连。VB1与第一锁存电路1215的供电电源正端、第二锁存电路1220的供电电源正端、锁存与降压电路1216的供电电源正端、第一降压电路1222的供电电源正端、模拟开关1218的 0选择端相连。VS1与第一锁存电路1215的供电电源负端、第二锁存电路1220的供电电源负端、锁存与降压电路1216的供电电源负端、第一降压电路1222的供电电源负端、输出子电路1217的供电电源负端相连。HO1与输出子电路1217的输出端相连。
第一输入子电路1211的作用是：在第一输入子电路1211输入端信号的上升沿，在第一输入子电路1211的第一输出端输出一个脉冲宽度为300ns左右的脉冲信号；在第一输入子电路1211输入端信号的下降沿，在第一输入子电路1211的第二输出端输出一个脉冲宽度为300ns左右的脉冲信号；当第一输入子电路1211的控制输入端为VCC电平时，在第一输入子电路1211的第三输出端输出一个脉冲宽度为600ns左右的脉冲信号；当第一输入子电路1211的控制输入端为0电平时，在第一输入子电路1211的第三输出端输出一个脉冲宽度为300ns左右的脉冲信号；当第一输入子电路1211的控制输入端为VCC/2电平时，在第一输入子电路1211的第四输出端输出一个脉冲宽度为300ns左右的脉冲信号。
第一锁存电路1215的作用是：当第一锁存电路1215输入端信号出现600ns的低电平时，第一锁存电路1215的输出端输出高电平，当第一锁存电路1215输入端信号出现300ns的低电平时，第一锁存电路1215的输出端输出低电平，当第一锁存电路1215输入端信号从未出现低电平时，第一锁存电路1215的输出端输出VCC/2电压。
锁存及降压电路1216的作用是：在锁存及降压电路1216的第一输入端出现300ns低电平时，在锁存及降压电路1216的第二输出端输出持续高电平；在锁存及降压电路1216的第二输入端出现300ns低电平时，在锁存及降压电路1216的第二输出端输出持续低电平，即将HIN1的信号在第一输入子电路1211两个输出端分解出的两个脉冲信号重新整合成完整的信号。并且，锁存及降压电路1216内部有降压电路，在锁存及降压电路1216的第二输出端输出对VS1为3V的电压。
第二锁存电路1220的作用是：在锁存及降压电路1216的第一输入端出现300ns低电平时，在锁存及降压电路1216的第二输出端输出持续高电平，否则输出低电平。输出子电路1217的作用是：输出一个高电平时电压值与其供电电源正端一致、低电平时电压值与其供电电源负端一致的相位与HIN1一致的信号。在此，使用300ns或600ns的窄脉冲信号控制第一开关管1212、第二开关管1213、第三开关管1214与第四开关管1221，是为了通过缩短第一开关管1212、第二开关管1213、第三开关管1214与第四开关管1221的导通时间降低其功耗。
上述通过缩短第一开关管1212、第二开关管1213、第三开关管1214与第四开关管1221的导通时间降低其功耗的工作原理是：
HIN1的信号经过第一输入子电路1211后，分别在信号的上升沿和下降沿在第一输入子电路1211的第一输出端和第二输出端输出一个300ns的窄脉冲，该窄脉冲分别控制第一开关管1212和第二开关管1213导通300ns，使锁存及降压电路1216的第一输入端和第二输入端分别产生300ns的低电平，锁存及降压电路1216内部具有RS触发器等装置，使两个低电平信号被重新组合成完整的与HIN1同相的信号；
1、当上桥臂开关管127与下桥臂开关管128均包含SiC MOS管时，控制输入端SS为0电平，从而第一输入子电路1211的第四输出端不会出现高电平，第四开关管1221不会开通，第二锁存电路1220的输入端不会出现低电平，则第二锁存电路1220的输出端保持低电平，模拟开关1219处于断开状态。并且第一输入子电路1211的第三输出端出现300ns(第一时间长度)高电平脉冲，第三开关管1214出现300ns的导通，第一锁存电路1215的输入端出现300ns低电平，则第一锁存电路1215的输出端输出从高到低电平，输出子电路1217的供电电源正端与VB1相连，即输出子电路1217输出0～20V的高低电平。
2、当上桥臂开关管127与下桥臂开关管128均包含GaN MOS管，控制输入端SS为VCC电平，从而第一输入子电路1211的第四输出端不会出现高电平，第四开关管1221不会开通，第二锁存电路1220的输入端不会出现低电平，则第二锁存电路1220的输出端保持低电平，第二切换模块1219处于断开状态。并且第一输入子电路1211的第三输出端出现600ns(第二时间长度)高电平脉冲，第三开关管1214出现600ns的导通，第一锁存电路1215的输入端出现600ns低电平，则第一锁存电路1215的输出端输出从低到高电平，输出子电路1217的供电电源正端与锁存及降压电路1216的输出端相连，即输出子电路1217输出0～3V的高低电平。
3、当上桥臂开关管127与下桥臂开关管128均包含Si IGBT管，控制输入端SS为VCC/2电平，从而第一输入子电路1211的第三输出端不会出现高电平，第三开关管1214不会开通，第一锁存电路1215的输入端不会出现低电平，则第一锁存电路1215的输出端一直在低电平，第一切换模块1218处于悬空状态。并且第一输入子电路1211的第四输出端出现300ns(第一时间长度)高电平脉冲，第四开关管1221出现300ns的导通，第二锁存电路1220的输入端出现300ns低电平，则第二锁存电路1220的输出端输出高电平，输出子电路1217的供电电源正端与第二降压电路1222的输出端相连，即输出子电路1217输出0～15V的高低电平。
请参阅图14，在某些实施方式中，WH驱动电路103包括：第一输入子电路1311、输出子电路1317、第一开关管1312、第二开关管1313、第三开关管1314、第四开关管1321、第一电压输出子电路1323、第二电压输出子电路1324。第一输入子电路1311与控制输入端SS相连，第一输入子电路1311包括第一输出端、第二输出端、第三输出端与第四输出端，其中，当控制输入端SS为第一电平时，第一输出端与第二输出端输出触发脉冲，第三输出端输出第一时间长度的触发脉冲；当控制输入端SS为第二电平时，第一输出端与第二输出端输出触发脉冲，第三输出端输出第二时间长度的触发脉冲，第一时间长度小于第二时间长度；当控制输入端SS为第三电平时，第一输出端与第二输出端输出触发脉冲，第四输出端输出第一时间长度的触发脉冲。
第一开关管1312与第一输出端相连，在第一输出端输出触发脉冲时，第一开关管1312导通；第二开关管1313与第二输出端相连，在第二输出端输出触发脉冲时，第二开关管1313导通；第三开关管1314与第三输出端相连，在第三输出端输出触发脉冲时，第三开关1314导通；第四开关管1321与第四输出端相连，在第四输出端输出触发脉冲时，第四开关管1321导通。
第一电压输出子电路1323分别与第一开关管1312、第二开关管1313及第三开关管1314相连；第二电压输出子电路1324与第四开关管1321相连；输出子电路1317分别与第一电压输出子电路1323及第二电压输出子电路1324连接。
请继续参阅图14，在某些实施方式中，第一电压输出子电路1323包括与第一开关管1312及第二开关管1313相连的锁存及降压电路1316、第一切换模块1318、与第三开关管1314相连的第一锁存电路1315。第一切换模块1318分别与锁存及降压电路1316和电源相连；当第三开关管1314导通第一时间长度时，第一锁存电路1315用于控制第一切换模块1318动作以将电源的电压作为第一电压输出子电路1323的输出电压；当第三开关管1314导通第二时间长度时，第一锁存电路1315用于控制第一切换模块1318动作以将锁存及降压电路1316的输出电压作为第一电压输出子电路1323的输出电压。
请参阅图14，在某些实施方式中，第二电压输出子电路1324包括第一降压电路1322、第二切换模块1319、与第四开关管1321相连的第二锁存电路1320。第二切换模块1319分别与第一电压输出子电路1323和第一降压电路1322相连，第二锁存电路1320对第二切换模块1319进行控制，当第四开关管1321未导通时，将输出子电路1317与第一电压输出子电路1323相连，当第四开关管1321导通第一时间长度时，将输出子电路1317与第一降压电路1322相连。
请参阅图1与图14，在WH驱动电路103内部，VCC端与第一输入子电路1311的供电电源正端相连，HIN1与第一输入子电路1311的输入端相连，控制输入端SS与第一输入子电路1311的控制端相连。第一输入子电路1311的第一输出端与第一开关管1312的栅极相连，第一输入子电路1311的第二输出端与第二开关管1313的栅极相连，第一输入子电路1311的第三输出端与高压第三开关管1314的栅极相连，第一输入子电路1311的第四输出端与第四开关管1321的栅极相连。
GND端与第一输入子电路1311的供电电源负端、第一开关管1312的衬底和源极、第二开关管1313的衬底和源极、第三开关管1314的衬底和源极相连、第四开关管1321的衬底和源极相连。第一开关管1312的漏极进入高压区与锁存及降压电路1316的第一输入端相连；第二开关管1313的漏极进入高压区与锁存及降压电路1316的第二输入端相连；第三开关管1314的漏极进入高压区与第一锁存电路1315的使能端端相连；第四开关管1321的漏极进入高压区与锁存电路1320的使能端端相连。
锁存及降压电路1316的第一输出端与模拟开关1318的1选择端相连；锁存及降压电路1316的第二输出端与输出电路1317的输入端相连；锁存电路1315的输出端与模拟开关1318的控制端相连；模拟开关1318的固定端与输出电路1317的供电电源正端相连；降压电路1322的输出端与第二切换模块1319的活动端相连；第二锁存电路1320的输出端与第二切换模块1319的控制端相连。VB1与第一锁存电路1315的供电电源正端、第二锁存电路1320的供电电源正端、锁存与降压电路1316的供电电源正端、第一降压电路1322的供电电源正端、模拟开关1318的0选择端相连。VS1与第一锁存电路1315的供电电源负端、第二锁存电路1320的供电电源负端、锁存与降压电路1316的供电电源负端、第一降压电路1322的供电电源负端、输出子电路1317的供电电源负端相连。HO1与输出子电路1317的输出端相连。
第一输入子电路1311的作用是：在第一输入子电路1311输入端信号的上升沿，在第一输入子电路1311的第一输出端输出一个脉冲宽度为300ns左右的脉冲信号；在第一输入子电路1311输入端信号的下降沿，在第一输入子电路1311的第二输出端输出一个脉冲宽度为300ns左右的脉冲信号；当第一输入子电路1311的控制输入端为VCC电平时，在第一输入子电路1311的第三输出端输出一个脉冲宽度为600ns左右的脉冲信号；当第一输入子电路1311的控制输入端为0电平时，在第一输入子电路1311的第三输出端输出一个脉冲宽度为300ns左右的脉冲信号；当第一输入子电路1311的控制输入端为VCC/2电平时，在第一输入子电路1311的第四输出端输出一个脉冲宽度为300ns左右的脉冲信号。
第一锁存电路1315的作用是：当第一锁存电路1315输入端信号出现600ns的低电平时，第一锁存电路1315的输出端输出高电平，当第一锁存电路1315输入端信号出现300ns的低电平时，第一锁存电路1315的输出端输出低电平，当第一锁存电路1315输入端信号从未出现低电平时，第一锁存电路1315的输出端输出VCC/2电压。
锁存及降压电路1316的作用是：在锁存及降压电路1316的第一输入端出现300ns低电平时，在锁存及降压电路1316的第二输出端输出持续高电平；在锁存及降压电路1316的第二输入端出现300ns低电平时，在锁存及降压电路1316的第二输出端输出持续低电平，即将HIN1的信号在第一输入子电路1311两个输出端分解出的两个脉冲信号重新整合成完整的信号。并且，锁存及降压电路1316内部有降压电路，在锁存及降压电路1316的第二输出端输出对VS1为3V的电压。
第二锁存电路1320的作用是：在锁存及降压电路1316的第一输入端出现300ns低电平时，在锁存及降压电路1316的第二输出端输出持续高电平，否则输出低电平。输出子电路1317的作用是：输出一个高电平时电压值与其供电电源正端一致、低电平时电压值与其供电电源负端一致的相位与HIN1一致的信号。在此，使用300ns或600ns的窄脉冲信号控制第一开关管1312、第二开关管1313、第三开关管1314与第四开关管1321，是为了通过缩短第一开关管1312、第二开关管1313、第三开关管1314与第四开关管1321的导通时间降低其功耗。
上述通过缩短第一开关管1312、第二开关管1313、第三开关管1314与第四开关管1321的导通时间降低其功耗的工作原理是：
HIN1的信号经过第一输入子电路1311后，分别在信号的上升沿和下降沿在第一输入子电路1311的第一输出端和第二输出端输出一个300ns的窄脉冲，该窄脉冲分别控制第一开关管1312和第二开关管1313导通300ns，使锁存及降压电路1316的第一输入端和第二输入端分别产生300ns的低电平，锁存及降压电路1316内部具有RS触发器等装置，使两个低电平信号被重新组合成完整的与HIN1同相的信号；
1、当上桥臂开关管127与下桥臂开关管128均包含SiC MOS管时，控制输入端SS为0电平，从而第一输入子电路1311的第四输出端不会出现高电平，第四开关管1321不会开通，第二锁存电路1320的输入端不会出现低电平，则第二锁存电路1320的输出端保持低电平，模拟开关1319处于断开状态。并且第一输入子电路1311的第三输出端出现300ns(第一时间长度)高电平脉冲，第三开关管1314出现300ns的导通，第一锁存电路1315的输入端出现300ns低电平，则第一锁存电路1315的输出端输出从高到低电平，输出子电路1317的供电电源正端与VB1相连，即输出子电路1317输出0～20V的高低电平。
2、当上桥臂开关管127与下桥臂开关管128均包含GaN MOS管，控制输入端SS为VCC电平，从而第一输入子 电路1311的第四输出端不会出现高电平，第四开关管1321不会开通，第二锁存电路1320的输入端不会出现低电平，则第二锁存电路1320的输出端保持低电平，第二切换模块1319处于断开状态。并且第一输入子电路1311的第三输出端出现600ns(第二时间长度)高电平脉冲，第三开关管1314出现600ns的导通，第一锁存电路1315的输入端出现600ns低电平，则第一锁存电路1315的输出端输出从低到高电平，输出子电路1317的供电电源正端与锁存及降压电路1316的输出端相连，即输出子电路1317输出0～3V的高低电平。
3、当上桥臂开关管127与下桥臂开关管128均包含Si IGBT管，控制输入端SS为VCC/2电平，从而第一输入子电路1311的第三输出端不会出现高电平，第三开关管1314不会开通，第一锁存电路1315的输入端不会出现低电平，则第一锁存电路1315的输出端一直在低电平，第一切换模块1318处于悬空状态。并且第一输入子电路1311的第四输出端出现300ns(第一时间长度)高电平脉冲，第四开关管1321出现300ns的导通，第二锁存电路1320的输入端出现300ns低电平，则第二锁存电路1320的输出端输出高电平，输出子电路1317的供电电源正端与第二降压电路1322的输出端相连，即输出子电路1317输出0～15V的高低电平。
请参阅图15，UL/VL/WL驱动电路104包括第二输入子电路1041、第一降压子电路1048、第二降压子电路1050、开关电路1049、及与第二输入子电路1041、开关电路1049、第一降压子电路1048及第二降压子电路1050相连的第三电压输出子电路1051。第二输入子电路1041包括第一输出端、第二输出端、第三输出端、第四输出端及第五输出端，其中，当控制输入端SS输入第一电平时，第四输出端输出第一触发脉冲；当控制输入端SS输入第二电平时，第四输出端输出第二触发脉冲，第一触发脉冲与第二触发脉冲反向；当控制输入端SS输出第三电平时，第五输出端输出触发脉冲；第一降压子电路1048将电源电压降压至第二电压范围；第二降压子电路1050将电源电压降压至第三电压范围；开关电路1049与第一降压子电路1048相连，开关电路1049由第五输出端控制；其中，当第四输出端输出第一触发脉冲时，第三电压输出子电路1051输出第一电压范围的高低电平信号；第四输出端输出第二触发脉冲时，第三电压输出子电路1051输出第二电压范围的高低电平信号；当第五输出端输出触发脉冲时，第三电压输出子电路1051输出第三电压范围的高低电平信号。
请参阅图15，在某些实施方式中，第三电压输出子电路1051包括分别与第二输入子电路1041的第一输出端、第二输出端及第三输出端相连的UL输出模块1042、VL输出模块1043及WL输出模块1044，以及分别与UL输出模块1042、VL输出模块1043及WL输出模块1044相连的第三切换模块1045、第四切换模块1046及第五切换模块1047。其中，第三切换模块1045、第四切换模块1046及第五切换模块1047根据第二输入子电路1041的第四输出端，选择电源电压或第二降压子电路1050的输出电压作为第三电压输出子电路1051的输出电压。
如图15所示，在UL/VL/WL驱动电路104内部，VCC端与第二输入子电路1041的供电电源正端、第二降压子电路1050的供电电源正端、第一降压子电路1048的供电电源正端、第三切换模块1045的0选择端、第四切换模块1046的0选择端、第五切换模块1047的0选择端相连。LIN1与第二输入子电路1041的第一输入端相连。LIN2与第二输入子电路1041的第二输入端相连。LIN3与第二输入子电路1041的第三输入端相连。
控制输入端SS与第二输入子电路1041的控制端相连，第二输入子电路1041的第一输出端与UL输出电路1042的输入端相连；第二输入子电路1041的第二输出端与VL输出电路1042的输入端相连；第二输入子电路1041的第三输出端与VL输出电路1043的输入端相连；第一输入子电路1011的第三输出端分别与第三切换模块1045的控制端、第四切换模块1046的控制端、第五切换模块1047的控制端相连。
GND端与第二输入子电路1041的供电电源负端、第二降压子电路1048的供电电源负端、UL输出电路1042的供电电源负端、VL输出电路1043的供电电源负端、WL输出电路1044的供电电源负端相连；第二降压子电路1048的输出端分别于与第三切换模块1045的1选择端、第四切换模块1046的1选择端、第五切换模块1047的1选择端相连；LO1与UL输出电路1042的输出端相连、LO2与VL输出电路1043的输出端相连、LO3与WL输出电路1043的输出端相连。
第二输入子电路1041的作用是：在第二输入子电路1041第一输出端输出与第二输入子电路1041第一输入端同相的信号；在第二输入子电路1041第二输出端输出与第二输入子电路1041第二输入端同相的信号；在第二输入 子电路1041第三输出端输出与第二输入子电路1041第三输入端同相的信号。
当第二输入子电路1041的控制输入端SS为VCC电平时，在第二输入子电路1041的第五输出端输出高电平，当第二输入子电路1041的控制输入端SS为0电平时，在第二输入子电路1041的第四输出端输出低电平，当第二输入子电路1041的控制输入端SS为VCC/2电平时，在第二输入子电路1041的第四输出端输出高电平。第一降压子电路1048的作用是：在第一降压子电路1048的输出端输出对GND端为3V的电压。第二降压子电路1050的作用是：在第二降压子电路1050的输出端输出对GND端为15V的电压。
UL输出电路1042的作用是输出一个高电平时电压值与其供电电源正端一致、低电平时电压值与其供电电源负端一致的相位与LIN1一致的信号；VL输出电路1043的作用是输出一个高电平时电压值与其供电电源正端一致、低电平时电压值与其供电电源负端一致的相位与LIN2一致的信号；WL输出电路1044的作用是输出一个高电平时电压值与其供电电源正端一致、低电平时电压值与其供电电源负端一致的相位与LIN3一致的信号。
得到与LIN1一致的信号、得到与LIN2一致的信号、得到与LIN3一致的信号的工作原理是：LIN1、LIN2、LIN3经过第二输入子电路1041后，分别在第二输入子电路1041的第一、第二、第三输出端输出相位分别与LIN1、LIN2、LIN3相同，信号经过整形的方波；
当上桥臂开关管127与下桥臂开关管128均包括SiC MOS管，控制输入端SS为0电平，从而UL/VL/WL驱动电路104的第四输出端输出从高到低的电平(第一脉冲)，第三切换模块1045的固定端与第三切换模块1045的0选择端相连、第四切换模块1046的固定端与第四切换模块1046的0选择端相连、第五切换模块1047的固定端与第五切换模块1047的0选择端相连，使LO1输出0～20V的与UL输出电路1042输入端同相的信号、使LO2输出0～20V的与VL输出电路1043输入端同相的信号、使LO3输出0～20V的与WL输出电路1044输入端同相的信号；
当上桥臂开关管127与下桥臂开关管128均包括GaN MOS管，控制输入端SS为VCC电平，从而UL/VL/WL驱动电路104的第四输出端输出从低到高的电平(第二脉冲)，第三切换模块1045的固定端与第三切换模块1045的1选择端相连、第四切换模块1046的固定端与第四切换模块1046的1选择端相连、第五切换模块1047的固定端与第五切换模块1047的1选择端相连，使LO1输出0～3V的与UL输出电路1042输入端同相的信号、使LO2输出0～3V的与VL输出电路1043输入端同相的信号、使LO3输出0～3V的与WL输出电路1044输入端同相的信号；
当上桥臂开关管127与下桥臂开关管128均包括Si IGBT管，控制输入端SS为VCC/2电平，从而UL/VL/WL驱动电路104的第四输出端输出保持低电平，第三切换模块1045悬空状态、第四切换模块1046悬空状态、第五切换模块1047悬空状态，UL/VL/WL驱动电路104的第五输出端输出高电平，开关电路1049的固定端与第一降压子电路1050的输出端相连，使LO1输出0～15V的与UL输出电路1042输入端同相的信号、使LO2输出0～15V的与VL输出电路1043输入端同相的信号、使LO3输出0～15V的与WL输出电路1044输入端同相的信号。
请参阅图16，本申请实施方式的电器1000包括上述任一项实施方式的功率器件100和处理器200，处理器200连接功率器件100。
本申请实施方式的电器1000及功率器件100中，通过上述的功率器件100，能够提高Si IGBT管、GaN MOS管以及SiC MOS管的适配性，使Si IGBT管、GaN MOS管以及SiC MOS管的技术优势都能得到发挥。处理器200连接功率器件100的控制器10，当用户操作电器1000时，处理器200向功率器件100的控制器130发出信号，控制器130控制控制输入端SS接入第一电平、第二电平或第三电平，使电器1000切换想要的功能。
上述电器1000可以为空调、洗衣机、冰箱或电磁炉等，并且其中的功率器件100可以实现前述部分中描述的功率器件100的功能。
在本说明书的描述中，参考术语“某些实施方式”、“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”的描述意指结合所述实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个所述特征。在本申请的描述中，“多个”的含义是至少两个，例如两个，三个，除非另有明确具体的限定。
尽管上面已经示出和描述了本申请的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本申请的限制，本领域的普通技术人员在本申请的范围内可以对上述实施例进行变化、修改、替换和变型，本申请的范围由权利要求及其等同物限定。

Claims (20)

  1. 一种功率器件，其特征在于，包括：
    控制输入端；
    上桥臂开关管和下桥臂开关管；
    与所述控制输入端相连且用于驱动所述上桥臂开关管的第一驱动电路；和
    与所述控制输入端相连且用于驱动所述下桥臂开关管的第二驱动电路，所述控制输入端能够接入第一电平、第二电平或第三电平，当所述控制输入端接入第一电平时，所述第一驱动电路及所述第二驱动电路输出第一电压范围的高低电平信号；当所述控制输入端接入第二电平时，所述第一驱动电路及所述第二驱动电路输出第二电压范围的高低电平信号；当所述控制输入端接入第三电平时，所述第一驱动电路及所述第二驱动电路输出第三电压范围的高低电平信号，所述第一电压范围、所述第二电压范围及所述第三电压范围不同。
  2. 根据权利要求1所述的功率器件，其特征在于，所述功率器件还包括GND端、VCC端与参考电压源，当所述控制输入端通过邦定线与所述GND端连接时，所述控制输入端接入所述第一电平；
    当所述控制输入端通过邦定线与所述VCC端连接时，所述控制输入端接入所述第二电平；
    当所述控制输入端通过邦定线与所述参考电压源连接时，所述控制输入端接入所述第三电平。
  3. 根据权利要求1所述的功率器件，其特征在于，所述功率器件包括控制器，所述控制输入端与所述控制器连接，所述控制器用于控制所述控制输入端接入所述第一电平、所述第二电平或所述第三电平。
  4. 根据权利要求3所述的功率器件，其特征在于，所述控制器包括用于输出所述第一电平、所述第二电平和所述第三电平的数字电路。
  5. 根据权利要求2所述的功率器件，其特征在于，所述功率器件包括第一连接部、第二连接部与SSS端，所述第一连接部用于连接所述VCC端与VDD端，所述第二连接部用于连接所述GND端与COM端，所述SSS端用于连接SS端与参考电压源Vreg。
  6. 根据权利要求5所述的功率器件，其特征在于，所述第一连接部与所述第二连接部包括具备导电传输功能的导线、电极等。
  7. 根据权利要求5所述的功率器件，其特征在于，所述参考电压源Vreg是在所述功率器件的高压集成电路管内部生成的一个电压值为VCC/2的电压源。
  8. 根据权利要求2所述的功率器件，其特征在于，所述第一电平为0，所述第二电平为电源电平VCC，所述第三电平为二分之一所述电源电平VCC，所述第一电压范围为0～20V，所述第二电压范围为0～3V，所述第三电压范围为0～15V。
  9. 根据权利要求1至8任一项所述的功率器件，其特征在于，所述第一驱动电路包括UH驱动电路、VH驱动电路与WH驱动电路，所述第二驱动电路包括UL/VL/WL驱动电路，所述上桥臂开关管包括第一上桥臂开关管、第二上桥臂开关管与第三上桥臂开关管，所述下桥臂开关包括第一下桥臂开关管、第二下桥臂开关管与第三下桥臂开关管；其中
    所述控制输入端均与所述UH驱动电路、VH驱动电路和WH驱动电路相连，且所述UH驱动电路、VH驱动电路与WH驱动电路分别驱动所述第一上桥臂开关管、所述第二上桥臂开关管与所述第三上桥臂开关管；所述UH驱动电路与所述第一上桥臂开关管相连，所述VH驱动电路与所述第二上桥臂开关管相连，所述WH驱动电路与所述第三上桥臂开关相连；
    所述控制输入端与所述UL/VL/WL驱动电路相连，且所述UL/VL/WL驱动电路驱动所述第一下桥臂开关管、所述第二下桥臂开关管与所述第三下桥臂开关管，所述UL/VL/WL驱动电路分别与所述第一下桥臂开关管、所述第二下桥臂开关管与所述第三下桥臂开关管连接。
  10. 根据权利要求9所述的功率器件，其特征在于，当所述第一上桥臂开关管、所述第二上桥臂开关管、所述 第三上桥臂开关管、所述第一下桥臂开关管、所述第二下桥臂开关管与所述第三下桥臂开关管均包括SiC器件时，向所述控制输入端输入的信号的电平为第一电平；
    当所述第一上桥臂开关管、所述第二上桥臂开关管、所述第三上桥臂开关管、所述第一下桥臂开关管、所述第二下桥臂开关管与所述第三下桥臂开关管均包括GaN器件时，向所述控制输入端输入的信号的电平为第二电平；
    当所述第一上桥臂开关管、所述第二上桥臂开关管、所述第三上桥臂开关管、所述第一下桥臂开关管、所述第二下桥臂开关管与所述第三下桥臂开关管均包括Si器件时，向所述控制输入端输入的信号的电平为第三电平。
  11. 根据权利要求10所述的功率器件，其特征在于，所述第一上桥臂开关管、所述第二上桥臂开关管、所述第三上桥臂开关管、所述第一下桥臂开关管、所述第二下桥臂开关管与所述第三下桥臂开关管的结构一致。
  12. 根据权利要求10所述的功率器件，其特征在于，所述UH驱动电路、所述VH驱动电路或所述WH驱动电路包括:
    第一输入子电路，所述第一输入子电路与所述控制输入端相连，所述第一输入子电路包括第一输出端、第二输出端、第三输出端与第四输出端，其中，当所述控制输入端为第一电平时，所述第一输出端与所述第二输出端输出触发脉冲，所述第三输出端输出第一时间长度的触发脉冲；当所述控制输入端为第二电平时，所述第一输出端与所述第二输出端输出触发脉冲，所述第三输出端输出第二时间长度的触发脉冲，所述第一时间长度小于所述第二时间长度；当所述控制输入端为第三电平时，所述第一输出端与所述第二输出端输出触发脉冲，所述第四输出端输出第一时间长度的触发脉冲；
    第一开关管、第二开关管、第三开关管与第四开关管，所述第一开关管与所述第一输出端相连，在所述第一输出端输出所述触发脉冲时，所述第一开关管导通；所述第二开关管与所述第二输出端相连，在所述第二输出端输出所述触发脉冲时，所述第二开关管导通；所述第三开关管与所述第三输出端相连，在所述第三输出端输出触发脉冲时，所述第三开关导通；所述第四开关管与所述第四输出端相连，在所述第四输出端输出触发脉冲时，所述第四开关管导通；
    第一电压输出子电路，所述第一电压输出子电路分别与所述第一开关管、所述第二开关管及所述第三开关管相连；
    第二电压输出子电路，所述第二电压输出子电路与所述第四开关管相连；和
    输出子电路，所述输出子电路分别与所述第一电压输出子电路及所述第二电压输出子电路连接。
  13. 根据权利要求12所述的功率器件，其特征在于，所述第一电压输出子电路包括：
    与所述第一开关管及所述第二开关管相连的锁存及降压电路；
    第一切换模块，所述第一切换模块分别与所述锁存及降压电路和电源相连；和
    与所述第三开关管相连的第一锁存电路，当所述第三开关管导通第一时间长度时，所述锁存电路用于控制所述第一切换模块动作以将所述电源的电压作为所述第一电压输出子电路的输出电压；当所述第三开关管导通第二时间长度时，所述锁存电路用于控制所述第一切换模块动作以将所述锁存及降压电路的输出电压作为所述第一电压输出子电路的输出电压。
  14. 根据权利要求12所述的功率器件，其特征在于，所述第二电压输出子电路包括：
    第一降压电路；
    第二切换模块，所述第二切换模块分别与所述第一电压输出子电路和所述第一降压电路相连；和
    与所述第四开关管相连的第二锁存电路，所述第二锁存电路对所述第二切换模块进行控制，当所述第四开关管未导通时，将所述输出子电路与所述第一电压输出子电路相连；当所述第四开关管导通第一时间长度时，将所述输出子电路与所述第一降压电路相连。
  15. 根据权利要求9所述的功率器件，其特征在于，所述UL/VL/WL驱动电路包括：
    第二输入子电路，所述第二输入子电路包括第一输出端、第二输出端、第三输出端、第四输出端及第五输出端，其中，当所述控制输入端输入第一电平时，所述第四输出端输出第一触发脉冲；当所述控制输入端输入第二电平时， 所述第四输出端输出第二触发脉冲，所述第一触发脉冲与所述第二触发脉冲反向；当所述控制输入端输出第三电平时，所述第五输出端输出触发脉冲；
    第一降压子电路，所述第一降压子电路将电源电压降压至所述第二电压范围；
    第二降压子电路，所述第二降压子电路将电源电压降压至所述第三电压范围；
    开关电路，所述开关电路与所述第一降压子电路相连，所述开关电路由所述第五输出端控制；和
    与所述第二输入子电路、所述开关电路、所述第一降压子电路及所述第二降压子电路相连的第三电压输出子电路，其中，当所述第四输出端输出第一触发脉冲时，所述第三电压输出子电路输出第一电压范围的高低电平信号；所述第四输出端输出第二触发脉冲时，所述第三电压输出子电路输出第二电压范围的高低电平信号；当所述第五输出端输出触发脉冲时，所述第三电压输出子电路输出第三电压范围的高低电平信号。
  16. 根据权利要求15所述的功率器件，其特征在于，所述第三电压输出子电路包括：
    分别与所述第二输入子电路的所述第一输出端、所述第二输出端及所述第三输出端相连的UL输出模块、VL输出模块及WL输出模块；和
    分别与所述UL输出模块、所述VL输出模块及WL输出模块相连的第三切换模块、第四切换模块及第五切换模块，其中，所述第三切换模块、所述第四切换模块及第五切换模块根据所述第二输入子电路的第四输出端，选择电源电压或所述第二降压子电路的输出电压作为所述第三电压输出子电路的输出电压。
  17. 根据权利要求15所述的功率器件，其特征在于，在所述UL/VL/WL驱动电路内部，所述VCC端与所述第二输入子电路的供电电源正端、所述第二降压子电路的供电电源正端、所述第一降压子电路的供电电源正端、所述第三切换模块的0选择端、所述第四切换模块的0选择端、所述第五切换模块的0选择端相连。
  18. 根据权利要求17所述的功率器件，其特征在于，所述功率器件的LIN1与所述第二输入子电路的第一输入端相连。所述功率器件的LIN2与所述第二输入子电路的第二输入端相连。所述功率器件的LIN3与所述第二输入子电路的第三输入端相连。
  19. 一种电器，其特征在于，包括：
    权利要求1-18任一项所述的功率器件；和
    处理器，所述处理器连接所述功率器件。
  20. 根据权利要求19所述的电器，其特征在于，所述电器为空调。
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