WO2020186455A1

WO2020186455A1 - Data storage method and storage chip

Info

Publication number: WO2020186455A1
Application number: PCT/CN2019/078724
Authority: WO
Inventors: 金龙; 周伟伟; 商捷
Original assignee: 华为技术有限公司
Priority date: 2019-03-19
Filing date: 2019-03-19
Publication date: 2020-09-24
Also published as: CN113574497A

Abstract

A data storage method and a storage chip. The method can be applied in a storage chip, and comprises: obtaining the effective data volume of a fast storage region, a storage form of data in the fast storage region being a first storage form (401); and when the effective data volume of the fast storage region is greater than a first threshold, converting the fast storage region into a normal storage region, a storage form of data in the normal storage region being a second storage form (402). The use of the method can effectively improve the response speed of an application.

Description

Data storage method and storage chip

Technical field

This application relates to the field of chip technology, and in particular to a data storage method and a storage chip.

Background technique

Generally, basic indicators for measuring the basic performance of a storage device of a terminal device may include sequential reading, sequential writing, random reading, and random writing. At the same time, typical scenarios of storage experience that users can perceive when using terminal devices are application cold start scenarios. The application cold start speed is strongly correlated with random reading indicators.

Among them, the cold start of an application not only occurs when the user starts the application for the first time, but may also occur when the application exits to the background, is kicked out due to insufficient memory, and is switched back to the foreground by the user again.

Therefore, how to improve the response speed of the application needs to be solved urgently.

Summary of the invention

The embodiment of the present application discloses a data storage method and a storage chip, which can effectively improve the response speed of the application.

In the first aspect, an embodiment of the present application discloses a data storage method, the method is applied to a memory chip, and the method includes: acquiring the effective data amount of a fast storage area, and the storage form of the data in the fast storage area is the first A storage form; in the case where the effective data amount of the fast storage area is greater than the first threshold, the fast storage area is converted to a normal storage area, and the storage form of the data in the normal storage area is the second storage form .

In the embodiment of the present application, the storage chip includes a fast storage area to improve the response speed of the application; and when the effective data amount in the fast storage area is too large, such as greater than the first threshold, it indicates that the main chip (also referred to as the host Side, etc.) The space to be used is getting larger and larger. At this time, the memory chip can switch the storage form, that is, the memory chip can convert the first storage form of the data in the fast storage area into the second storage form of the data in the ordinary storage area. Second, storage form, so as to expand the physical space of the storage chip without sacrificing the user's visible logical space. It can be understood that the fast storage area is different from the ordinary storage area in the storage form of data. For example, the storage form of data in the fast storage area is the first storage form, and the storage form of data in the ordinary storage area is the second storage form. That is to say, when the storage form in the storage chip is converted, the names of the storage areas in the storage chip can be mutually converted.

With reference to the first aspect, in a possible implementation manner, the method further includes: acquiring the effective data amount of the ordinary storage area; in the case that the effective data amount of the ordinary storage area is less than a second threshold, The normal storage area is converted into the fast storage area.

In the embodiment of the present application, when the effective data amount in the common storage area is less than the second threshold, it indicates that the space to be used by the main chip may be reduced. At this time, the storage chip can store data in the common storage area in the second storage mode. It is converted into the first storage form of data in the fast storage area, thereby improving the response speed of related data in the storage area of the memory chip.

In the embodiment of the present application, the storage form of the data in the storage chip is converted mutually through the effective data amount in the fast storage area or the normal storage area in the storage chip. Therefore, when the application-related data is stored in the storage chip, the storage mode can be changed as needed. For example, the storage mode can be switched between the first storage mode and the second storage mode. It is understandable that the two storage modes are different Therefore, the read and write speeds of the first storage mode and the second storage mode are also different. Furthermore, if the read and write speed of the first storage form is greater than that of the second storage form, and when the second storage form is converted to the first storage form (that is, the normal storage area is converted to a fast storage area), the storage The read performance of the data in the chip is improved, and the response speed of the application is improved. Another example is when the first storage form is converted to the second storage form (that is, the fast storage area is converted to a normal storage area), the physical storage space of the storage chip can be effectively increased, so that more data can be cached or stored in the storage chip .

It can be understood that in the embodiment of the present application, the data stored in the storage chip may not only include data related to various applications (application, APP), but also include key databases, file system metadata, and data related to the virtual memory exchange mechanism. And so on, the embodiment of this application does not limit the data stored in the memory chip. Further, the data listed above can be stored in the fast storage area of the memory chip.

It can be understood that in the embodiment of the present application, there is a storage space size conversion relationship between the storage space of the first storage form and the storage space of the second storage form, and the read and write speeds of the first storage form and the second storage form are different, as in the first storage form. The read and write speed of one storage form is greater than that of the second storage form. It can be understood that because the read and write speeds of the first storage form and the second storage form are different, the read and write response speed of the fast storage area is different from that of the ordinary storage area. For example, the read and write response speed of the fast storage area is greater than that of ordinary storage. The read and write response speed of the area.

With reference to the first aspect or any one of the possible implementation manners of the first aspect, in the case that the effective data amount of the fast storage area is greater than a first threshold, converting the fast storage area into a normal storage area includes : In the case where the effective data amount of the fast storage area is greater than the first threshold, according to the size of the effective data amount of the fast storage area and the storage space of the first storage form and the second storage form The conversion relationship converts the fast storage area into the normal storage area.

In the embodiments of the present application, when converting the fast storage area to the normal storage area, the conversion can be performed according to the user's usage, that is, according to the usage of the data in the storage chip; more specifically, according to the usage of the data and the storage space The relationship converts the fast storage area to the normal storage area; thus avoiding the situation that the area is converted too large and not effectively used.

With reference to the first aspect or any one of the possible implementation manners of the first aspect, in the case that the effective data amount of the ordinary storage area is less than a second threshold, the ordinary storage area is converted into the fast storage area , Including: in the case that the effective data amount of the ordinary storage area is less than the second threshold, according to the size of the effective data amount of the ordinary storage area and the difference between the first storage form and the second storage form The storage space conversion relationship converts the ordinary storage area into the fast storage area.

In the embodiments of this application, when converting a normal storage area to a fast storage area, the conversion can be based on the user's usage, that is, according to the usage of the data in the storage chip; more specifically, the conversion can be based on the usage of the data and the storage space The relationship converts the ordinary storage area into the fast storage area; thereby avoiding the situation that the data cannot be stored or cached due to the conversion of too many fast storage areas.

With reference to the first aspect or any one of the possible implementation manners of the first aspect, the converting the ordinary storage area into the fast storage area includes: the case where the wear times of the fast storage area is less than the wear times threshold Next, convert the normal storage area into the fast storage area.

In the embodiment of the present application, by setting the threshold of the number of wear times, the normal storage area and the fast storage area, that is, the first storage mode and the second storage mode, can be converted mutually within the range of the wear frequency threshold.

With reference to the first aspect or any one of the possible implementation manners of the first aspect, the method further includes: in the case that the wear times of the fast storage area is not less than the wear times threshold, complete the fast storage area Converted to the normal storage area.

In the embodiment of the present application, the precondition that the fast storage area and the ordinary storage area can be interchanged may be that the wear times of the fast storage area are less than the wear times threshold, and if the wear times of the fast storage area exceeds the wear times threshold, the fast storage area The storage area cannot be converted to the ordinary storage area, that is, the fast storage area will be completely converted into the ordinary storage area, that is, the first storage form can be completely converted into the second storage form.

With reference to the first aspect or any one of the possible implementation manners of the first aspect, before the obtaining the effective data amount of the fast storage area, the method further includes: allocating the storage chip to the storage chip according to the usage of the application data Fast storage area.

In the embodiment of the present application, the storage chip can allocate a fast storage area based on user application behavior analysis, so that the size of the fast storage area can be more in line with the user's usage, that is, it can be more in line with the data in the storage chip. Storage usage.

With reference to the first aspect or any possible implementation manner of the first aspect, the first storage form and the second storage form belong to different storage forms of the same storage medium.

With reference to the first aspect or any possible implementation manner of the first aspect, the first storage form includes a single-level cell (SLC), and the second storage form includes a three-level storage cell (trinary cell). -level cell, TLC); or, the first storage form includes SLC, and the second storage form includes multi-level cell (MLC); or, the first storage form includes MLC, so The second storage form includes TLC; or, the first storage form includes SLC, and the second storage form includes four-layer memory cells QLC.

In a second aspect, an embodiment of the present application discloses a memory chip, including: an acquiring unit configured to acquire the effective data amount of a fast storage area, the storage form of the data in the fast storage area is the first storage form; a conversion unit, When the effective data amount of the fast storage area is greater than the first threshold, the fast storage area is converted into a normal storage area, and the storage form of the data in the normal storage area is the second storage form.

With reference to the second aspect, in a possible implementation manner, the acquiring unit is further configured to acquire the effective data amount of the ordinary storage area; the conversion unit is further configured to obtain valid data in the ordinary storage area If the amount is less than the second threshold, the normal storage area is converted to the fast storage area.

With reference to the second aspect or any one of the possible implementation manners of the second aspect, the conversion unit is specifically configured to: when the effective data amount of the fast storage area is greater than the first threshold, according to the fast storage The size of the effective data amount of the area and the storage space conversion relationship between the first storage form and the second storage form convert the fast storage area into the normal storage area.

With reference to the second aspect or any one of the possible implementation manners of the second aspect, the conversion unit is specifically configured to, when the effective data amount of the common storage area is less than the second threshold, perform according to the common storage The size of the effective data amount of the area and the storage space conversion relationship between the first storage form and the second storage form convert the ordinary storage area into the fast storage area.

With reference to the second aspect or any one of the possible implementation manners of the second aspect, the conversion unit is specifically configured to convert the ordinary storage area into a case where the wear count of the fast storage area is less than the wear count threshold. The fast storage area.

With reference to the second aspect or any of the possible implementation manners of the second aspect, the conversion unit is further configured to store the fast storage area when the wear times of the fast storage area are not less than the wear times threshold. The area is completely converted into the normal storage area.

With reference to the second aspect or any of the possible implementation manners of the second aspect, the storage chip further includes: an allocation unit configured to allocate the fast storage area to the storage chip according to a usage situation of application data.

With reference to the second aspect or any possible implementation manner of the second aspect, the first storage form and the second storage form belong to different storage forms of the same storage medium.

With reference to the second aspect or any one of the possible implementation manners of the second aspect, the first storage format includes SLC, and the second storage format includes TLC; or, the first storage format includes SLC, and the second storage format includes SLC. The storage format includes MLC; or, the first storage format includes MLC, and the second storage format includes TLC.

In a third aspect, an embodiment of the present application discloses a memory chip including a controller and a memory array (such as a NAND flash array), and the controller is configured to execute the method described in the first aspect.

In a fourth aspect, an embodiment of the present application discloses a terminal device. The terminal device includes a processor and a storage chip. The processor is used to read and write data by interacting with the storage chip. Perform the method described in the first aspect above.

In a fifth aspect, the embodiments of the present application provide a computer-readable storage medium that stores instructions in the computer-readable storage medium, and when the instructions run on a computer, the computer executes the methods described in the above aspects .

In a sixth aspect, the embodiments of the present application provide a computer program product including instructions, which when the computer program product runs on a computer, cause the computer to execute the methods described in the foregoing aspects.

Description of the drawings

FIG. 1 is a schematic structural diagram of a main chip provided by an embodiment of the present application;

2 is a schematic structural diagram of a memory chip provided by an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a terminal device provided by an embodiment of the present application;

FIG. 4 is a schematic flowchart of a data storage method provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of a scene of a data storage method provided by an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a memory chip provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of another memory chip provided by an embodiment of the present application;

Fig. 8 is a schematic structural diagram of another terminal device provided by an embodiment of the present application.

detailed description

The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

In a specific implementation, the four basic indicators for measuring the basic performance of the mobile phone memory can include sequential read, sequential write, random read, and random write. The typical scenarios of the storage experience that the user can perceive are often related to random reading. Therefore, how to improve the response speed of the cold start of the application when the user uses the mobile phone is a problem that is being studied by those skilled in the art.

Among them, a cold start can be understood as the user launching the application for the first time, or a cold start can also be understood as the application retreating from the foreground to the background, and the application is forcibly closed due to insufficient memory, but is called out of the foreground. It is understandable that the boot described here can be understood as booting from the storage medium instead of booting from the memory. It is understandable that the applications described in the embodiments of the present application not only refer to the APP installed in the terminal device, but can also refer to various operating system applications, and some other applications of the system in the terminal device. The understanding is not limited. Among them, the data generated by some other applications of the system in the terminal device may be key databases, file system metadata, data related to the virtual memory exchange mechanism, and so on.

In order to effectively improve the response speed of application cold start, embodiments of the present application provide a data storage method and a storage chip.

The main chip and memory chip involved in the embodiments of the present application will be described in detail below.

Referring to Fig. 1, Fig. 1 is a schematic structural diagram of a main chip provided by an embodiment of the present application. In this embodiment of the application, the main chip can access the storage chip using a storage interface protocol, where the storage interface protocol can include universal flash storage (UFS) interface protocol, embedded multimedia (embedded multimedia card, EMMC) Interface protocol and high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIE) interface protocol, etc. The embodiment of the present application does not limit the type of the storage interface protocol. The following will take the UFS interface protocol as an example to illustrate the main chip and the storage chip involved in the embodiments of the present application.

As shown in Figure 1, the main chip may include a central processing unit (CPU), a UFS main controller, and a double data rate synchronous dynamic random access memory (DDR SDRAM) controller , DDR SDRAM memory, peripheral controllers and peripherals (peripherals). It can be understood that in the embodiments of the present application, DDR SDRAM may also be referred to as DDR for short.

The processor (that is, the main CPU) is used to read and write data by interacting with the storage chip. For example, the processor can be used to couple with the storage chip to execute program instructions stored in the storage chip and so on. Another example is that the processor can be used to run software running on the main chip such as operating systems, applications, and drivers. The embodiment of the present application does not limit how the processor interacts with the storage chip.

The UFS main controller can be used to issue one or more of a read request and a write request conforming to the UFS protocol information unit (UPIU) protocol frame. The UFS main controller can be used to issue a read request conforming to the UPIU protocol frame, thereby requesting to read the data stored in the memory chip. For example, the read request issued by the UFS main controller can be used to read data related to applications (such as hotspot applications or high-frequency applications) and stored in the storage chip.

In other words, in the embodiment of the present application, the main chip can be used to couple with the storage chip, so as to read the data and instructions stored in the storage chip. Further, the storage chip includes a fast storage area and a normal storage area. When the main chip needs to read data in the storage chip, it can read the data in the fast storage area or the normal storage area respectively as needed. Specifically, the main chip can issue a command according to the logical unit number (LUN) encapsulated in the UPIU protocol frame to access the fast storage area or the normal storage area in the storage chip. It can be understood that for a detailed description of the fast storage area and the common storage area in the memory chip, reference may be made to the memory chip shown in FIG. 2, which will not be detailed here.

The DDR controller can be used to control the DDR. For example, the DDR controller can be used to control and update the mapping relationship between the logical address and the physical address in the DDR and so on.

Peripheral devices may include input and output interfaces, external memory, analog-to-digital converters, digital-to-analog converters, peripheral processors, and so on. For example, the peripheral device may include a touch screen, a camera, a fingerprint collection, a near field communication element, and various sensors, etc., the embodiment of the present application does not limit the peripheral device. Among them, the peripheral device controller can be used to control the peripheral device.

It is understandable that the main chip may be chips of various forms, for example, the main chip may be integrated on a system-on chip (SOC). Optionally, the main chip can be applied to various terminal devices. For example, the main chip can be applied to a mobile phone or a notebook computer, etc., which is not limited in the embodiment of the present application.

It can be understood that the main chip shown in FIG. 1 is only an example provided by the embodiment of the present application, and the main chip may have more or less components than the components shown, and two or more components may be combined. Or it can have different configurations of different components and so on.

Referring to FIG. 2, FIG. 2 is a schematic structural diagram of a memory chip provided by an embodiment of the present application, and the memory chip can be connected to the UPIU. As shown in Figure 2, the memory chip includes a controller and a memory array such as a NAND flash array. The controller and the storage array can be connected to each other through wires.

Specifically, the controller is the core device of the memory chip, which can be used to rationally allocate the data load on each storage array, and the controller can also be used for data transfer, connecting the storage array and an external serial interface.

Optionally, the controller may further include a hardware chip. For example, the hardware chip may be an application-specific integrated circuit (ASIC), or the hardware chip may also be a field programmable logic gate array (field programmable logic gate array). gate array, FPGA), etc., which are not limited in the embodiment of the present application.

Further, the controller may include static random access memory (SRAM).

Optionally, the storage chip can be a chip of various forms. Optionally, the storage chip can be applied to various storage devices. For example, the storage chip can be applied to a solid state disk (SSD), etc., which is not limited in the embodiment of the present application. Optionally, the memory chip can also be applied to various terminal devices, for example, the memory chip can be applied to a mobile phone or a notebook computer.

In the embodiment of the present application, the storage chip may include application-related data or programs, etc., and the storage chip may also be divided into different areas, so that the divided areas store different data, and the storage chip Different storage formats or storage media can also be converted mutually. For specific conversion conditions, reference may be made to the method shown in FIG. 5 and/or FIG. 6, which will not be described in detail here.

In the embodiment of the present application, the memory chip may be divided into a fast storage area and a normal storage area. More specifically, the storage array in the memory chip may include a fast storage area and a normal storage area. The fast storage area and the normal storage area have different access speeds. That is, the access speed of the fast storage area is greater than that of the ordinary storage area. It can be understood that, in the embodiment of the present application, the fast storage area can also be converted into a normal storage area. Therefore, the memory chip can be divided into a fast storage area and a first normal storage area. After the fast storage area is converted into a normal storage area, the normal storage area converted from the fast storage area can be understood as the second normal storage area. At this time, the memory chip may include a first normal storage area and a second normal storage area. The storage form of the fast storage area data can correspond to the first storage form, and the storage form of the second general storage area data can correspond to the second storage form. The storage form of the first general storage area data is not limited in this embodiment. It can be understood that, as specifically illustrated in the figure, the ordinary storage area in this application can be understood as the second ordinary storage area. Specifically, if the storage medium type in the storage chip is NAND, the fast storage area may be an area in NAND. It is understandable that the location of the fast storage area in the storage chip can be known by the main chip through LUN. It can be understood that the embodiment of the present application does not limit the specific location of the fast storage area in the storage chip.

Among them, the data stored in the fast storage area may include not only application-related data, but also key databases, file system metadata, and data related to the virtual memory exchange mechanism, etc. The embodiment of the present application relates to the fast storage area The stored data is not limited. Specifically, data related to hot applications can be stored in the fast storage area. The hot applications can also be understood as high-frequency applications, that is, frequently used applications (APP) in terminal devices. For example, the high-frequency applications can be understood as An application whose frequency of use exceeds the frequency threshold within a period of time, or the high-frequency application can also be understood as some applications defined by the user and so on. The embodiments of this application do not limit how to define or set high-frequency applications.

It can be understood that the embodiment of the present application does not limit the specific type of the memory chip. It can be understood that the memory chip shown in FIG. 2 is only an example provided by the embodiment of the present application, and the memory chip may have more or fewer components than the components shown, and two or more components may be combined. Or it can have different configurations of different components and so on.

It can be understood that the fast storage area in the embodiments of the present application may also be referred to as a turbo zone, and the ordinary storage area may be referred to as a slow disk. It should be noted that the slow disk is relative to the access speed of the fast disk. For example, the slow disk may also be called a normal disk, etc., which is not limited in the embodiment of the present application.

Refer to FIG. 3, which is a schematic structural diagram of a terminal device according to an embodiment of the present application. As shown in Figure 3, the terminal device may include a screen, a main chip and a memory chip. The main chip may be the main chip shown in FIG. 1, for example, the main chip may include a screen controller, a peripheral device controller, a DDR, a DDR controller, a UFS host controller, a main CPU, and so on. The memory chip may be the memory chip shown in FIG. 2, wherein the components included in the memory chip are not shown in FIG. 3. It can be understood that the terminal device shown in FIG. 3 also includes peripheral devices and so on.

Specifically, the UFS main controller is connected to the storage chip, and the UFS main controller can be used to interact with the storage chip, so that the terminal device can read the data in the storage chip through the UFS main controller. In the embodiment of the present application, the main CPU may be used to issue a read request to the storage chip, thereby reading data in the storage chip. It can be understood that the embodiment of the present application does not limit the UFS main controller. For example, the device interacting with the storage chip in the terminal device may be other devices. The embodiment of the present application does not limit whether the UFS main controller exists.

Specifically, the main CPU may include a RISC microprocessor (advanced RISC machines, ARM), etc. The embodiment of the present application does not limit the specific type or model of the main CPU.

It can be understood that the terminal device shown in FIG. 3 is only an example, and it should not be understood as a limitation to the embodiment of the present application.

Referring to FIG. 4, FIG. 4 is a schematic flowchart of a data storage method provided by an embodiment of the present application. The method can be applied to the memory chip shown in FIG. 2, and the method can also be applied to the terminal device shown in FIG. As shown in Figure 4, the data storage method includes:

401. The storage chip acquires the effective data amount of the fast storage area, and the storage form of the data in the fast storage area is the first storage form.

It can be understood that, for the description of the fast storage area included in the memory chip, reference may be made to the foregoing embodiment, which will not be described in detail here. In the embodiment of this application, the data stored in the fast storage area may include not only application-related data, but also key databases, file system metadata, and data related to the virtual memory exchange mechanism. The data stored in the fast storage area is not limited. Therefore, the effective data volume acquired by the memory chip can be understood as the data volume of the data stored in the fast storage area acquired by the memory chip. Alternatively, the effective data amount may also be referred to as physical effective data, etc., which is not limited in the embodiment of the present application. As an example, if the effective data amount acquired by the memory chip may be 20G, or xG, etc., the embodiment of the present application does not limit the specific value of the effective data amount, and the specific value may be determined according to actual conditions. .

402. When the effective data amount of the fast storage area is greater than the first threshold, the storage chip converts the fast storage area into a normal storage area, and the storage form of the data in the normal storage area is the second storage form.

In the embodiment of the present application, the storage mode of the data in the storage chip can be converted mutually, for example, between the first storage mode and the second storage mode. It can be understood that the storage form of the data in the storage core in the embodiment of the present application may also include a third storage form, so that the storage form of the data in the memory chip is between the first storage form, the second storage form, and the third storage form. Convert each other. Among them, the first storage form, the second storage form, and the third storage form can be understood as different storage forms belonging to the same storage medium. As an example, it can be different storage forms of NAND. It can be understood that the embodiment of the present application does not limit the name of the area corresponding to the third storage form. It can be understood that the fast storage area is different from the ordinary storage area in the storage form of data. For example, the storage form of data in the fast storage area is the first storage form, and the storage form of data in the ordinary storage area is the second storage form. That is to say, when the storage form in the storage chip is converted, the names of the storage areas in the storage chip can be mutually converted. It can be understood that the reading and writing speed of the first storage form and the third storage form, and the reading and writing speed of the second storage form and the third storage form are not limited in the embodiment of the present application.

In the embodiment of the present application, the first storage form and the second storage form may also be the same storage medium, such as fast NAND and slow NAND.

As an example, if the first storage form includes single-level cells (SLC), the second storage form includes three-level cells (trinary-level cells, TLC); or, the first storage form includes SLC, and the second storage form includes SLC. The second storage form includes multi-level cell (MLC); or, the first storage form includes MLC, and the second storage form includes TLC; or, the first storage form includes SLC, and the second storage form includes QLC. As an example, when converting SLC to TLC, the data in the storage particles of the SLC can be moved away, thereby converting the SLC to TLC, and then using TLC to store the data. When converting TLC to SLC, two-thirds of the data in the TLC storage particles can be moved away, thereby converting TLC to SLC, and then using SLC to store the data. As an example, SLC is 1bit/cell, which is fast and has a long life span of 100,000 cycles per month; MLC is 2bit/cell, and has a general life span, about 3000 to 10,000 cycles; TLC is 3bit/cell, which is slow Life period, about 500 erasing and writing life; QLC is 4bit/cell, about 150 erasing and writing life.

That is to say, in the embodiment of the present application, taking SLC and TLC as examples, the fast storage area can also correspond to the SLC area, and after the fast storage area is converted to the normal storage area, the normal storage area can correspond to the TLC area.

In the embodiment of this application, when the effective data amount in the fast storage area is too large, such as greater than the first threshold, it means that the space to be used by the main chip (also called the host side, etc.) is getting larger and larger. At this time, the storage The chip can convert the storage form of the fast storage area data from the first storage form to the second storage form of the ordinary storage area data, thereby expanding the physical space of the storage area without sacrificing the user's visible space.

403. The storage chip obtains the effective data amount of the ordinary storage area.

In the embodiment of the present application, the relevant description of the effective data amount of the ordinary storage area may refer to the relevant description of the effective data amount of the fast storage area, which will not be detailed here.

404. In a case where the effective data amount of the ordinary storage area is less than the second threshold, the storage chip converts the ordinary storage area into the fast storage area.

In the embodiment of the present application, the values of the first threshold and the second threshold may be the same or different, which is not limited in the embodiment of the present application. Optionally, the first threshold may be greater than the second threshold, etc. The embodiment of the present application does not limit the first threshold and the second threshold. It can be understood that the first threshold and the second threshold may be independently set by the memory chip, or set by the terminal device, or set by the user, etc., which are not limited in the embodiment of the present application.

In the embodiment of this application, when the effective data amount in the common storage area is less than the second threshold, it means that the space to be used by the main chip may be reduced. At this time, the storage chip can change the storage form of the common storage area data from the second The conversion of the storage form to the first storage form is to convert the ordinary storage area into a fast storage area, thereby improving the response speed of related data in the fast storage area.

As an example, if an application frequently used by a user (called a high-frequency application or a hot application) is installed in a fast storage area, when the application is cold-started, the response speed of the application can be improved. Another example is to store the application context state in the fast storage area. When the memory shortage is forcibly closed, when it is recalled again, the response speed of the application can be improved and user satisfaction can be improved. Another example is storing the key data of the system in the fast storage area, which can increase the speed of the system and make the system run more smoothly. It can be understood that the above are only examples provided in this application, and should not be construed as limiting the application.

In the embodiment of the present application, the storage chip may determine whether to convert the fast storage area into a normal storage area according to the data size of the effective data amount of the fast storage area. It can be understood that, in the embodiment of the present application, there is a storage space size conversion relationship between the storage space of the first storage form and the storage space of the second storage form, and the read and write speeds of the first storage form and the second storage form are different. The read and write speed of the first storage form is greater than that of the second storage form.

In the embodiments of the present application, the storage form of the data in the fast storage area is mutually converted by the effective data amount in the fast storage area in the storage chip; thus, when the application-related data is stored in the fast storage area, it can be used as needed To switch the storage format, such as switching the storage format between the first storage format and the second storage format. Or, when other key data of the system is stored in the fast storage area, the storage chip can change the storage form as needed, thereby improving the response speed of the key data.

Optionally, in the case that the effective data amount of the fast storage area is greater than a first threshold, converting the fast storage area into a normal storage area includes:

In the case where the effective data amount of the quick storage area is greater than the first threshold, the quick storage is based on the size of the effective data amount of the quick storage area and the storage space conversion relationship between the first storage mode and the second storage mode. The area is converted to the normal storage area described above.

In the embodiment of this application, the storage space conversion relationship between the first storage form and the second storage form may be 1:2, or 1:3, or 2:3, or 1:4, and so on. That is, as an example, the xG space when the storage format is the first storage format can be converted to the 3xG space when the storage format is the second storage format.

In the embodiment of the present application, the storage chip can switch the storage mode of the data in the fast storage area according to the amount of used data and the space conversion relationship between the first storage mode and the second storage mode. As an example, if the space conversion relationship between SLC and TLC is 1:3, and the first threshold is 15G, the effective data amount acquired by the memory chip is 17G, and data may need to be stored in the memory chip. Therefore, The memory chip can convert 10G SLC to 30G TLC to store data, which not only does not sacrifice the user’s visible space, such as the user’s inability to feel the loss of space, etc., but also expands the data storage space to For storage chips to store or cache data. For another example, if the amount of data acquired by the memory chip is 30G or greater, the memory chip can convert 20G SLC into 60G TLC to store more data. It can be understood that each of the above values is only an example, and should not be construed as a limitation to the application.

Optionally, in the case that the effective data amount of the ordinary storage area is less than a second threshold, converting the ordinary storage area into the fast storage area includes:

In the case where the effective data amount of the ordinary storage area is less than the second threshold, the ordinary storage is based on the size of the effective data amount of the ordinary storage area and the storage space conversion relationship between the first storage form and the second storage form. The area is converted to the above fast storage area.

In the embodiment of the present application, the storage chip can switch the storage mode of the data in the fast storage area according to the amount of used data and the space conversion relationship between the first storage mode and the second storage mode. As an example, if the spatial conversion relationship between SLC and TLC is 1:3, and the second threshold is 8G, the effective data amount acquired by the memory chip is 7G, and there may be no need to store data in the memory chip. Therefore, The memory chip can convert 30G TLC to 10G SLC to store data, which not only does not sacrifice the user's visible space, such as the user cannot feel the loss of space, etc., but also because the speed of TLC is slower than that of SLC , So it can also improve data read and write performance. It can be understood that each of the above values is only an example, and should not be construed as a limitation to the application.

It is understandable that the storage modes in the memory chip can be interchanged, and there may also be preconditions. For example, in the case that the wear times of the fast storage area is less than the wear times threshold, the first storage mode in the memory chip can be the same as the second storage mode. Mutual conversion, that is, the fast storage area can be converted to the ordinary storage area. In the case where the wear count of the fast storage area is not less than the wear count threshold, the storage form of the relevant area in the memory chip is completely converted from the first storage form to the second storage form, that is, the fast storage area Fully converted to normal storage area. In other words, the precondition for mutual conversion between the first storage form and the second storage form may be that the wear times of the fast storage area is less than the wear times threshold, and if the wear times of the fast storage area exceeds the wear times threshold, then It shows that the storage modes of the fast storage area cannot be converted to each other, that is, the first storage mode can be completely converted to the second storage mode. The threshold of the number of wear times may be determined by the performance of the memory chip, etc. The embodiment of the present application does not limit the setting of the threshold of the number of wear times.

It is understandable that the embodiment of the present application also provides a method of how to set the amount of data stored in the fast storage area, that is, before obtaining the effective data amount of the fast storage area, the above method further includes: according to the usage of application data, The storage chip allocates the fast storage area.

In other words, the storage chip can allocate fast storage areas based on user application behavior analysis. Alternatively, the storage chip may allocate the fast storage area and the first common storage area described in FIG. 2 based on the analysis of user application behavior. That is, the storage chip can first analyze the user's use of the terminal device. For example, after analyzing the user's use of the application data through the terminal device, the storage chip can allocate the fast storage area and the first common storage area according to the user's application situation the size of. For example, by analyzing the usage of application data, the memory chip can use the 10G space in the memory chip as a fast storage area (for example, the second ordinary storage area that can be converted to 30G), and the 20G space in the memory chip as the first ordinary storage area. It can be understood that the numbers shown above are only examples and should not be construed as limiting the application.

For a more vivid understanding of the data storage method provided by the embodiment of this application, refer to FIG. 5. FIG. 5 is a schematic diagram of a data storage method provided by the embodiment of this application. As shown in FIG. 5, the fast storage area is The reserved area of the SLC area can be understood as a virtual space. For example, the storage form of the fast storage area is the SLC storage form. When the amount of data in the memory chip becomes larger and larger (as shown by the dotted arrow in the second line of Figure 5), if it is larger than xGB, the SLC area can be converted into a TLC area. That is, the storage mode of the data is converted from the SLC storage mode to the TLC storage mode (see the solid arrow in the second row in Figure 5). And when the amount of data in the memory chip is getting smaller and smaller (as shown by the dotted arrow in the third row of Figure 5), if it is less than yGB, the TLC area can be converted to SLC area, that is, the storage form of the data can be converted from TLC storage form to SLC storage form (the solid arrow in the third row in Figure 5). It can be understood that LUm can be understood as the first general storage area described in FIG. 2, and its logical unit number is m. After the SLC is converted to TLC, the logical unit number of the TLC area, that is, the second general storage area described in FIG. 2 may be LUn. Wherein, x and y can be any positive numbers, and the application does not limit specific values.

Further, the schematic diagram shown in Figure 5 can be divided into three periods, such as:

The fast storage area enable period, when the wear times of the fast storage area is less than the wear threshold, such as the erase count (EC) technical specification, the total amount of effective data in the fast storage area is within the threshold z1GB, The read performance of the fast storage area all hits the SLC, where z1 is any positive number. It can be understood that, in the embodiment of the present application, the number of wear times can also be understood as the number of erasing EC values.

During the fast storage area suspension period, when the wear times of the fast storage area are less than the wear threshold, the total amount of effective data in the fast storage area is outside the threshold z1GB, and the fast storage area starts the SLC to TLC return (after returning to the TLC, the fast The storage area can be called a normal storage area). For another example, if the total amount of valid data in the ordinary storage area is within the threshold z2GB, the ordinary storage area starts TLC to SLC reverse return, where z2 is any positive number.

During the fast storage area shutdown period, when the wear times of the fast storage area are not less than the wear threshold, the fast storage area is permanently closed, that is, the storage form of the data in the memory chip can be completely converted from SLC to TLC, and no longer Continue to convert from TLC to SLC.

It can be understood that the above is only an example of the present application, and the data volume size or the data volume threshold therein should not be understood as a limitation on the present application.

The foregoing describes the method of the embodiment of the present application in detail, and the device of the embodiment of the present application is provided below.

Referring to FIG. 6, FIG. 6 is a schematic structural diagram of a memory chip provided by an embodiment of the present application. As shown in FIG. 6, the memory chip may include:

The acquiring unit 601 is configured to acquire the effective data amount of the fast storage area, and the storage form of the data in the fast storage area is the first storage form;

The conversion unit 602 is configured to convert the fast storage area into a normal storage area when the effective data amount of the fast storage area is greater than the first threshold, and the storage form of the data in the normal storage area is the second storage form.

In the embodiment of the present application, the storage chip includes a fast storage area to improve the response speed of the application; and when the effective data amount in the fast storage area is too large, such as greater than the first threshold, it indicates that the main chip (also referred to as the host Side, etc.) The space to be used is getting larger and larger. At this time, the memory chip can switch the storage form, that is, the memory chip can convert the first storage form of the data in the fast storage area into the second storage form of the data in the ordinary storage area. 2. Storage form, so as to expand the physical space of the storage area without sacrificing the user's visible logical space.

In a possible implementation manner, the above-mentioned obtaining unit 601 is further configured to obtain the effective data amount of the above-mentioned ordinary storage area;

The conversion unit 602 is further configured to convert the normal storage area into the fast storage area when the effective data amount of the normal storage area is less than a second threshold.

In the embodiment of the present application, when the effective data amount in the common storage area is less than the second threshold, it indicates that the space to be used by the main chip may be reduced. At this time, the storage chip can store data in the common storage area in the second storage mode It is converted into the first storage form of data in the fast storage area, thereby improving the response speed of related data in the storage area of the memory chip.

In a possible implementation manner, the conversion unit 602 is specifically configured to, when the effective data amount of the fast storage area is greater than the first threshold, according to the size of the effective data amount of the fast storage area and the first The storage space conversion relationship between the storage mode and the second storage mode converts the fast storage area into the normal storage area.

In a possible implementation manner, the conversion unit 602 is specifically configured to, when the effective data amount of the ordinary storage area is less than the second threshold, according to the size of the effective data amount of the ordinary storage area and the first The storage space conversion relationship between the storage format and the second storage format converts the ordinary storage area into the fast storage area.

In a possible implementation manner, the conversion unit 602 is specifically configured to convert the ordinary storage area into the fast storage area when the wear count of the fast storage area is less than the wear count threshold.

In a possible implementation manner, the conversion unit 602 is further configured to convert the ordinary storage area into the fast storage area when the wear count of the fast storage area is not less than the wear count threshold.

In a possible implementation manner, as shown in FIG. 7, the foregoing memory chip further includes:

The allocating unit 603 is configured to allocate the fast storage area to the storage chip according to the usage of the application data.

In a possible implementation manner, the first storage form and the second storage form belong to different storage forms of the same storage medium.

In a possible implementation manner, the first storage format includes SLC, and the second storage format includes TLC; or, the first storage format includes SLC, and the second storage format includes MLC; or, the first storage format is Including MLC, and the second storage format includes TLC; or, the first storage format includes SLC, and the second storage format includes four-layer memory cells QLC.

It should be noted that the implementation of each unit may also correspond to the corresponding description of the method embodiment shown in FIG. 4 and/or FIG. 5. It should be noted that each unit refers to a logical division, and does not mean that it corresponds to a specific hardware. Specifically, the function of each unit can be implemented based on various hardware, for example, a processor based on a support instruction set can read The code stored in the memory is implemented by reading the configuration file based on field programmable gate array (FPGA), or based on application-specific integrated circuit (ASIC), or a combination of these The method is not limited in this application.

Referring to FIG. 8, FIG. 8 is a schematic structural diagram of a terminal device according to an embodiment of the present application. The terminal device can be used to execute the method shown in FIG. 4 and/or FIG. 5. As shown in FIG. 8, the terminal device may include The memory chip, the memory chip may be the memory chip shown in FIG. 6 and/or FIG. 7. It can be understood that the memory chip units included in the terminal device can refer to the foregoing embodiments, which will not be described in detail here.

It is understandable that the terminal device may also include other chips, which will not be described in detail here.

The embodiment of the present application also provides a computer-readable storage medium. All or part of the procedures in the foregoing method embodiments may be completed by a computer program instructing relevant hardware. The program may be stored in the foregoing computer storage medium. When the program is executed, it may include the procedures of the foregoing method embodiments.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in the form of a computer program product in whole or in part. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center integrated with one or more available media. The usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)), etc.

The steps in the method of the embodiment of the present application can be adjusted, merged, and deleted in order according to actual needs.

The modules in the devices in the embodiments of the present application may be combined, divided, and deleted according to actual needs.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present application, not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, a person of ordinary skill in the art should understand that: The technical solutions recorded in the embodiments are modified, or some of the technical features are equivalently replaced; these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

A data storage method, characterized in that the method is applied to a storage chip, and the method includes:

Acquiring the effective data amount of the fast storage area, where the storage form of the data in the fast storage area is the first storage form;

In a case where the effective data amount of the fast storage area is greater than the first threshold, the fast storage area is converted to a normal storage area, and the storage form of the data in the normal storage area is the second storage form.
The method of claim 1, wherein the method further comprises:

Acquiring the effective data amount of the common storage area;

In the case that the effective data amount of the normal storage area is less than the second threshold, the normal storage area is converted into the fast storage area.
The method according to claim 1 or 2, wherein the converting the fast storage area into a normal storage area when the effective data amount of the fast storage area is greater than a first threshold value comprises:

In the case that the effective data amount of the fast storage area is greater than the first threshold, the storage space conversion between the first storage form and the second storage form is based on the size of the effective data volume of the fast storage area The relationship converts the fast storage area into the normal storage area.
The method according to claim 2 or 3, wherein the converting the ordinary storage area into the fast storage area in the case that the effective data amount of the ordinary storage area is less than a second threshold value includes :

In the case where the effective data amount of the normal storage area is less than the second threshold, the storage space conversion between the first storage mode and the second storage mode is based on the size of the effective data amount of the normal storage area The relationship converts the ordinary storage area into the fast storage area.
The method according to any one of claims 2-4, wherein the converting the ordinary storage area into the fast storage area comprises:

In a case where the wear count of the fast storage area is less than the wear count threshold, the normal storage area is converted into the fast storage area.
The method of claim 5, wherein the method further comprises:

In a case where the wear count of the fast storage area is not less than the wear count threshold, the fast storage area is completely converted into the normal storage area.
The method according to any one of claims 1 to 6, characterized in that, before the obtaining the effective data amount of the fast storage area, the method further comprises:

According to the usage of application data, the fast storage area is allocated to the storage chip.
The method according to any one of claims 1-7, wherein the first storage form and the second storage form belong to different storage forms of the same storage medium.
The method according to any one of claims 1-8, wherein:

The first storage form includes a single-layer storage cell SLC, and the second storage form includes a three-layer storage cell TLC;

Alternatively, the first storage form includes SLC, and the second storage form includes a multi-layer memory cell MLC;

Alternatively, the first storage form includes MLC, and the second storage form includes TLC;

Alternatively, the first storage form includes SLC, and the second storage form includes four-layer memory cells QLC.
A memory chip, characterized in that it comprises:

An obtaining unit, configured to obtain the effective data amount of the fast storage area, and the storage form of the data in the fast storage area is the first storage form;

The conversion unit is configured to convert the fast storage area into a normal storage area when the effective data amount of the fast storage area is greater than the first threshold, and the storage form of the data in the normal storage area is the second storage form.
The memory chip of claim 10, wherein:

The obtaining unit is also used to obtain the effective data amount of the common storage area;

The conversion unit is further configured to convert the normal storage area into the fast storage area when the effective data amount of the normal storage area is less than a second threshold.
The memory chip according to claim 10 or 11, wherein:

The conversion unit is specifically configured to, when the effective data amount of the quick storage area is greater than the first threshold, according to the size of the effective data amount of the quick storage area and the first storage form and the The storage space conversion relationship of the second storage form converts the fast storage area into the normal storage area.
The memory chip according to claim 11 or 12, wherein:

The conversion unit is specifically configured to: when the effective data amount of the ordinary storage area is less than the second threshold, according to the size of the effective data amount of the ordinary storage area and the difference between the first storage form and the The storage space conversion relationship of the second storage form converts the ordinary storage area into the fast storage area.
The memory chip according to any one of claims 11-13, wherein:

The conversion unit is specifically configured to convert the ordinary storage area into the fast storage area when the wear count of the fast storage area is less than the wear count threshold.
The memory chip according to claim 14, wherein:

The conversion unit is further configured to completely convert the fast storage area into the normal storage area when the wear count of the fast storage area is not less than the wear count threshold.
15. The memory chip according to any one of claims 10-15, wherein the memory chip further comprises:

The allocation unit is configured to allocate the fast storage area to the storage chip according to the usage situation of the application data.
The memory chip according to any one of claims 10-16, wherein the first storage form and the second storage form belong to different storage forms of the same storage medium.
The memory chip according to any one of claims 10-17, wherein:

The first storage form includes a single-layer storage cell SLC, and the second storage form includes a three-layer storage cell TLC;

Alternatively, the first storage form includes SLC, and the second storage form includes a multi-layer memory cell MLC;

Alternatively, the first storage form includes MLC, and the second storage form includes TLC;

Alternatively, the first storage form includes SLC, and the second storage form includes four-layer memory cells QLC.
A memory chip, characterized in that the memory chip includes a controller and a memory array, and the controller is configured to execute the method according to any one of claims 1-9.
A terminal device, characterized in that, the terminal device includes a processor and a storage chip, the processor is used to read and write data by interacting with the storage chip, and the storage chip is used to execute 9. The method of any one.
A computer-readable storage medium, characterized in that instructions are stored in the computer-readable storage medium, and when the instructions are run on a computer, the method according to any one of claims 1-9 can be implemented.