CN113574497A

CN113574497A - Data storage method and storage chip

Info

Publication number: CN113574497A
Application number: CN201980094038.0A
Authority: CN
Inventors: 金龙; 周伟伟; 商捷
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-03-19
Filing date: 2019-03-19
Publication date: 2021-10-29
Also published as: WO2020186455A1

Abstract

A data storage method and a memory chip are provided, wherein the method can be applied to the memory chip, and the method comprises the following steps: acquiring the effective data volume of a fast storage area, wherein the storage form of the data of the fast storage area is a first storage form (401); when the effective data amount of the fast storage area is larger than a first threshold value, the fast storage area is converted into a normal storage area, and the storage form of the data of the normal storage area is a second storage form (402). The method can effectively improve the response speed of application.

Description

Data storage method and storage chip

Technical Field

The present application relates to the field of chip technologies, and in particular, to a data storage method and a memory chip.

Background

In general, the basic indicators measuring the basic performance of the storage device of the terminal device may include sequential read, sequential write, random read, and random write. Meanwhile, a user can sense a typical scene of storage experience when using the terminal device, such as an application cold start scene, and the application cold start speed is strongly related to a random reading index.

The application cold start not only occurs when the user starts the application for the first time, but also may occur when the application is retreated to the background, and is switched back to the foreground again by the user after being kicked out due to insufficient memory.

Therefore, how to improve the response speed of the application is urgently needed to be solved.

Disclosure of Invention

The embodiment of the application discloses a data storage method and a storage chip, which can effectively improve the response speed of application.

In a first aspect, an embodiment of the present application discloses a data storage method, where the method is applied to a memory chip, and the method includes: acquiring effective data volume of a quick storage area, wherein the storage form of data in the quick storage area is a first storage form; and converting the quick storage area into a common storage area under the condition that the effective data volume of the quick storage area is greater than a first threshold, wherein the storage form of the data in the common storage area is a second storage form.

In the embodiment of the application, the memory chip comprises the quick memory area, so that the response speed of the application can be improved; when the effective data amount in the fast storage area is too large, such as larger than the first threshold, it indicates that the space to be used by the main chip (also referred to as the host side, etc.) is larger and larger, and at this time, the memory chip can convert the storage form, that is, the memory chip can convert the first storage form of the data in the fast storage area into the second storage form of the data in the normal storage area, so as to expand the physical space of the memory chip without sacrificing the user visible logic space. It is understood that the fast storage area is different from the normal storage area in the storage form of data, for example, the storage form of data in the fast storage area is a first storage form, and the storage form of data in the normal storage area is a second storage form. That is, when converting the storage form in the memory chip, the names of the storage areas in the memory chip are converted to each other.

With reference to the first aspect, in a possible implementation manner, the method further includes: obtaining the effective data volume of the common storage area; and converting the normal storage area into the fast storage area under the condition that the effective data volume of the normal storage area is smaller than a second threshold value.

In the embodiment of the application, when the effective data amount in the ordinary storage area is smaller than the second threshold, it indicates that the space to be used by the main chip may be reduced, and at this time, the memory chip may convert the second storage form of the data in the ordinary storage area into the first storage form of the data in the fast storage area, so as to improve the response speed of the relevant data in the storage area of the memory chip.

In the embodiment of the application, the storage forms of the data in the memory chip are mutually converted through the effective data amount in the fast storage area or the common storage area in the memory chip. Therefore, when data related to an application is stored in the memory chip, the memory form can be converted according to needs, for example, the memory form is converted between the first memory form and the second memory form. If the read-write speed of the first storage form is higher than that of the second storage form, and the second storage form is converted into the first storage form (i.e. the common storage area is converted into the fast storage area), the read performance of the data in the storage chip can be improved, and the response speed of the application can be improved. For another example, when the first storage form is converted into the second storage form (i.e., the fast storage area is converted into the normal storage area), the physical storage space of the memory chip can be effectively increased, so that more data can be cached or stored in the memory chip.

It is understood that, in the embodiment of the present application, the data stored in the memory chip may include not only data related to various Applications (APPs), but also data related to a key database, file system metadata, a virtual memory exchange mechanism, and the like. Further, the above listed data can be stored in the fast storage area of the memory chip.

It can be understood that, in the embodiment of the present application, there is a storage space size conversion relationship between the storage space of the first storage form and the storage space of the second storage form, and the read/write speed of the first storage form is different from that of the second storage form, for example, the read/write speed of the first storage form is greater than that of the second storage form. It can be understood that, since the read-write speeds of the first storage form and the second storage form are different, the read-write response speed of the fast storage area is different from the read-write response speed of the normal storage area, for example, the read-write response speed of the fast storage area is greater than the read-write response speed of the normal storage area.

With reference to the first aspect or any possible implementation manner of the first aspect, in the case that an effective data amount of the fast storage area is greater than a first threshold, the converting the fast storage area into an ordinary storage area includes: and under the condition that the effective data volume of the quick storage area is larger than the first threshold, converting the quick storage area into the ordinary storage area according to the size of the effective data volume of the quick storage area and the storage space conversion relation between the first storage form and the second storage form.

In the embodiment of the application, when the fast storage area is converted into the ordinary storage area, the conversion can be carried out according to the use condition of a user, namely the use condition of data in the storage chip; more specifically, the fast storage area is converted into the ordinary storage area according to the use condition of the data and the storage space conversion relation; thereby avoiding the situation that the area conversion is too large and is not effectively utilized.

With reference to the first aspect or any possible implementation manner of the first aspect, in the case that an effective data amount of the normal storage area is smaller than a second threshold, the converting the normal storage area into the fast storage area includes: and under the condition that the effective data volume of the ordinary storage area is smaller than the second threshold, converting the ordinary storage area into the fast storage area according to the size of the effective data volume of the ordinary storage area and the storage space conversion relation between the first storage form and the second storage form.

In the embodiment of the application, when the common storage area is converted into the fast storage area, the conversion can be carried out according to the use condition of a user, namely the use condition of data in the storage chip; more specifically, the ordinary storage area is converted into the fast storage area according to the use condition of the data and the storage space conversion relation; therefore, the situation that data cannot be stored or cached due to the fact that too many fast storage areas are converted is avoided.

With reference to the first aspect or any possible implementation manner of the first aspect, the converting the normal storage area into the fast storage area includes: and converting the ordinary storage area into the fast storage area under the condition that the abrasion times of the fast storage area are smaller than an abrasion time threshold value.

In the embodiment of the application, by setting the wear-out time threshold, the common storage area and the fast storage area, namely the first storage form and the second storage form, can be mutually converted within the wear-out time threshold.

With reference to the first aspect or any possible implementation manner of the first aspect, the method further includes, when the number of times of wear of the fast storage area is not less than the wear number threshold, completely converting the fast storage area into the normal storage area.

In this embodiment of the application, a precondition that the fast storage area and the normal storage area can be mutually converted may be that the wear-out number of the fast storage area is smaller than a wear-out number threshold, and if the wear-out number of the fast storage area exceeds the wear-out number threshold, it indicates that the fast storage area cannot be mutually converted with the normal storage area, that is, the fast storage area is completely converted into the normal storage area, that is, the first storage form may be completely converted into the second storage form.

With reference to the first aspect or any possible implementation manner of the first aspect, before the obtaining the effective data amount of the fast storage area, the method further includes: and allocating the fast storage area to the storage chip according to the use condition of the application data.

In the embodiment of the application, the memory chip can allocate the quick memory area on the basis of the user application behavior analysis, so that the size of the quick memory area can better accord with the use condition of a user, namely the storage use condition of data in the memory chip.

With reference to the first aspect or any one of the possible implementation manners of the first aspect, the first storage modality and the second storage modality belong to different storage modalities of a same storage medium.

With reference to the first aspect or any possible implementation manner of the first aspect, the first storage form includes a single-level cell (SLC), and the second storage form includes a triple-level cell (TLC); alternatively, the first storage modality includes SLC, and the second storage modality includes multi-level cells (MLC); alternatively, the first storage modality comprises MLC and the second storage modality comprises TLC; alternatively, the first storage form comprises SLC and the second storage form comprises four-layer memory cells QLC.

In a second aspect, an embodiment of the present application discloses a memory chip, including: the device comprises an acquisition unit, a storage unit and a processing unit, wherein the acquisition unit is used for acquiring the effective data volume of a quick storage area, and the storage form of the data of the quick storage area is a first storage form; the conversion unit is used for converting the quick storage area into a common storage area under the condition that the effective data volume of the quick storage area is larger than a first threshold, and the storage form of the data of the common storage area is a second storage form.

With reference to the second aspect, in a possible implementation manner, the obtaining unit is further configured to obtain an effective data amount of the common storage area; the conversion unit is further configured to convert the normal storage area into the fast storage area when the effective data amount of the normal storage area is smaller than a second threshold.

With reference to the second aspect or any possible implementation manner of the second aspect, the conversion unit is specifically configured to, when the effective data amount of the fast storage area is greater than the first threshold, convert the fast storage area into the normal storage area according to the size of the effective data amount of the fast storage area and a storage space conversion relationship between the first storage form and the second storage form.

With reference to the second aspect or any possible implementation manner of the second aspect, the conversion unit is specifically configured to, when the effective data amount of the normal storage area is smaller than the second threshold, convert the normal storage area into the fast storage area according to the size of the effective data amount of the normal storage area and a storage space conversion relationship between the first storage form and the second storage form.

With reference to the second aspect or any possible implementation manner of the second aspect, the conversion unit is specifically configured to convert the ordinary storage area into the fast storage area when the wear-out number of the fast storage area is smaller than a wear-out number threshold.

With reference to the second aspect or any possible implementation manner of the second aspect, the conversion unit is further configured to completely convert the fast storage area into the normal storage area when the wear-out number of the fast storage area is not less than the wear-out number threshold.

With reference to the second aspect or any possible implementation manner of the second aspect, the memory chip further includes: and the allocation unit is used for allocating the quick storage area to the storage chip according to the use condition of the application data.

With reference to the second aspect or any possible implementation manner of the second aspect, the first storage form and the second storage form belong to different storage forms of a same storage medium.

With reference to the second aspect or any possible implementation manner of the second aspect, the first storage modality includes SLC, and the second storage modality includes TLC; alternatively, the first storage modality comprises SLC, the second storage modality comprises MLC; alternatively, the first storage modality comprises MLC and the second storage modality comprises TLC.

In a third aspect, an embodiment of the present application discloses a memory chip, where the memory chip includes a controller and a memory array (such as a NAND flash array), and the controller is configured to execute the method of the first aspect.

In a fourth aspect, an embodiment of the present application discloses a terminal device, where the terminal device includes a processor and a memory chip, the processor is configured to read and write data by interacting with the memory chip, and the memory chip is configured to execute the method according to the first aspect.

In a fifth aspect, the present application provides a computer-readable storage medium, which stores instructions that, when executed on a computer, cause the computer to perform the method of the above aspects.

In a sixth aspect, the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of the above aspects.

Drawings

Fig. 1 is a schematic structural diagram of a main chip provided in an embodiment of the present application;

fig. 2 is a schematic structural diagram of a memory chip according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a terminal device according to an embodiment of the present application;

FIG. 4 is a schematic flow chart illustrating a data storage method according to an embodiment of the present application;

fig. 5 is a schematic view of a scenario of a data storage method provided in an embodiment of the present application;

fig. 6 is a schematic structural diagram of a memory chip according to an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of another memory chip provided in an embodiment of the present application;

fig. 8 is a schematic structural diagram of another terminal device provided in an embodiment of the present application.

Detailed Description

The embodiments of the present application will be described below with reference to the drawings.

In a specific implementation, the four basic indicators for measuring the basic performance of the mobile phone memory may include sequential reading, sequential writing, random reading, and random writing. A typical scenario of the storage experience that the user can perceive is often related to random reading, and therefore, how to improve the response speed of the application cold start in the process of using the mobile phone by the user is a problem being researched by those skilled in the art.

The cold start may be understood as that the user starts the application for the first time, or the cold start may be understood as that the application is backed from the foreground to the background, and the application is forced to be closed but is called out of the foreground due to insufficient memory. It is to be understood that the boot described herein is to be understood as being booted from the storage medium, not from memory. It is understood that the application described in this embodiment of the present application refers not only to the APP installed in the terminal device, but also to various operating system applications, some other applications of the system in the terminal device, and the like, and this embodiment of the present application is not limited to understanding this application. The data generated by some other applications of the system in the terminal device may be a key database, file system metadata, data related to a virtual memory exchange mechanism, and the like.

In order to effectively improve the response speed of application cold start, the embodiment of the application provides a data storage method and a storage chip.

Hereinafter, the main chip and the memory chip provided in the embodiment of the present application will be described in detail.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a main chip according to an embodiment of the present disclosure. In this embodiment of the present application, the main chip may access the memory chip by using a storage interface protocol, where the storage interface protocol may include a Universal Flash Storage (UFS) interface protocol, an embedded multimedia (EMMC) interface protocol, a Peripheral Component Interconnect Express (PCIE) interface protocol, and the like, and the type of the storage interface protocol is not limited in this embodiment of the present application. The main chip and the memory chip according to the embodiments of the present application will be described below by taking the UFS interface protocol as an example.

As shown in fig. 1, the main chip may include a main Central Processing Unit (CPU), a UFS main controller, a double data rate synchronous dynamic random access memory (DDR SDRAM) controller, a DDR SDRAM memory, a peripheral device controller, and peripheral devices (peripherals). It is understood that in the embodiment of the present application, DDR SDRAM may also be referred to as DDR for short.

Wherein the processor (i.e., the main CPU) is configured to read and write data by interacting with the memory chip, e.g., the processor may be configured to couple with the memory chip to execute program instructions and the like stored in the memory chip. Also, for example, the processor may be used to run software running on the main chip, such as an operating system, applications, drivers, and the like. The embodiment of the application does not limit how the processor is specifically interfaced with the memory chip.

The UFS host controller may be configured to issue one or more of a read request and a write request in compliance with a UFS Protocol Information Unit (UPIU) protocol frame. The UFS host controller may be configured to issue a read request in compliance with a UPIU protocol frame to request reading of data stored in the memory chip. Such as a read request issued by the UFS host controller, may be used to read data associated with an application, such as a hot spot application or a high frequency application, and stored in a memory chip.

That is, in the embodiment of the present application, the main chip may be configured to couple with the memory chip, so as to read data and instructions stored in the memory chip. Furthermore, the memory chip includes a fast storage area and a normal storage area, and when the main chip needs to read data in the memory chip, the main chip can read data in the fast storage area or the normal storage area respectively according to needs. Specifically, the host chip may issue a command according to a Logical Unit Number (LUN) encapsulated in the UPIU protocol frame, so as to access a fast storage area or a normal storage area in the memory chip. It is understood that the detailed description of the fast storage area and the normal storage area in the memory chip can refer to the memory chip shown in fig. 2, which will not be detailed herein.

The DDR controller can be used for controlling DDR, for example, the DDR controller can be used for controlling and updating the mapping relation between the logical address and the physical address in the DDR, and the like.

The peripheral devices may include input and output interfaces, external memory, analog-to-digital converters, digital-to-analog converters, and peripheral processors, among others. If the peripheral device may include a touch screen, a camera, a fingerprint sensor, a near field communication element, various sensors, and the like, the embodiment of the present application is not limited to the peripheral device. Wherein the peripheral device controller is operable to control the peripheral device.

It is understood that the main chip may be a chip of various types, for example, the main chip may be integrated on a System On Chip (SOC). Optionally, the main chip may be applied to various terminal devices, for example, the main chip may be applied to a mobile phone or a notebook computer, and the embodiment of the present application is not limited.

It is understood that the main chip shown in fig. 1 is only one example provided by the embodiments of the present application, and the main chip may have more or less components than those shown, may combine two or more components, or may have different configuration implementations of different components, and so on.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a memory chip provided in an embodiment of the present application, where the memory chip is connectable to a UPIU. As shown in fig. 2, the memory chip includes a controller and a memory array such as a NAND flash array. The controller and the memory array may be interconnected by wiring.

Specifically, the controller is a core device of the memory chip, and can be used for reasonably allocating loads of data on each memory array, and the controller can also be used for data transfer to connect the memory array and an external serial interface.

Optionally, the controller may further include a hardware chip, for example, the hardware chip may be an application-specific integrated circuit (ASIC), or the hardware chip may also be a Field Programmable Gate Array (FPGA), and the like, and the embodiments of the present application are not limited thereto.

Further, a Static Random Access Memory (SRAM) may be included in the controller.

Alternatively, the memory chip may be a chip of various forms. Alternatively, the memory chip may be applied to various storage devices, for example, the memory chip may be applied to a Solid State Disk (SSD), and the like, and the embodiment of the present application is not limited thereto. Optionally, the memory chip may also be applied to various terminal devices, for example, the memory chip may be applied to a mobile phone or a notebook computer, etc.

In the embodiment of the present application, the memory chip may include data or programs related to applications, and the memory chip may be further divided into different regions, so that the divided regions store different data, and different storage forms or storage media in the memory chip may be further converted into each other. Reference may be made to the methods illustrated in fig. 5 and/or fig. 6 for specific transition conditions, which will not be described in detail herein.

In the embodiment of the present application, the memory chip may be divided into a fast storage area and a normal storage area, and more specifically, the memory array in the memory chip may include the fast storage area and the normal storage area. The access speeds of the fast storage area and the normal storage area are different. I.e. the access speed of the fast storage area is greater than the access speed of the normal storage area. It can be understood that in the embodiment of the present application, the fast storage area can also be converted into the normal storage area. Therefore, the memory chip can be divided into a fast storage area and a first normal storage area, and after the fast storage area is converted into the normal storage area, the converted normal storage area of the fast storage area can be understood as a second normal storage area. The storage form of the fast storage area data may correspond to the first storage form, and the storage form of the second normal storage area data may correspond to the second storage form, and the embodiment of the present application is not limited to the storage form of the first normal storage area data. It is understood that the general storage area in the present application can be understood as the second general storage area, as particularly illustrated in the drawings. Specifically, if the storage medium type in the storage chip is NAND, the fast storage area may be an area in NAND, and it is understood that the location of the fast storage area in the storage chip can be known by the LUN. It can be understood that the embodiment of the present application does not limit the specific location of the flash memory region in the memory chip.

The data stored in the fast storage area may include not only data related to an application, but also data related to a key database, file system metadata, a virtual memory exchange mechanism, and the like. Specifically, the fast storage area may store data related to a hot application, which may also be understood as a high frequency application, that is, an Application (APP) frequently used in the terminal device, for example, the high frequency application may be understood as an application whose usage frequency exceeds a frequency threshold for a period of time, or may also be understood as some applications defined by a user, and so on. The embodiments of the present application are not limited as to how the high frequency application is defined or set.

It is understood that the embodiment of the present application is not limited to the specific type of the memory chip. It is understood that the memory chip shown in fig. 2 is only one example provided in the embodiments of the present application, and the memory chip may have more or less components than those shown, may combine two or more components, or may have different configuration implementations of different components, and the like.

It is understood that the fast storage area in the embodiment of the present application may also be referred to as a fast disk (turbo zone), and the normal storage area may be referred to as a slow disk. It should be noted that the slow disc is referred to as a fast disc, for example, the slow disc may also be referred to as a normal disc, and the embodiment of the present application is not limited thereto.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a terminal device according to an embodiment of the present application. As shown in fig. 3, the terminal device may include a screen, a main chip, and a memory chip. The main chip may be the main chip shown in fig. 1, for example, the main chip may include a screen controller, a peripheral controller, a DDR controller, a UFS main (host) controller, a main CPU, and so on. The memory chip may be the memory chip shown in fig. 2, wherein the components contained in the memory chip are not shown in fig. 3. It is understood that the terminal device shown in fig. 3 further includes peripheral devices and the like.

Specifically, the UFS host controller is connected to the memory chip, and the UFS host controller can be used to interact with the memory chip, so that the terminal device can read data in the memory chip through the UFS host controller. In this embodiment, the main CPU may be configured to send a read request to the memory chip, so as to read data in the memory chip. It can be understood that, in the embodiment of the present application, the UFS host controller is not limited, for example, a device interacting with a memory chip in a terminal device may also be another device, and the like.

Specifically, the host CPU may include an advanced RISC processors (ARM), and the like, and the embodiment of the present application is not limited to a specific type or model of the host CPU.

It is understood that the terminal device shown in fig. 3 is only an example, and should not be construed as limiting the embodiments of the present application.

Referring to fig. 4, fig. 4 is a schematic flowchart of a data storage method provided in an embodiment of the present application, where the method is applicable to the memory chip shown in fig. 2, and the method is also applicable to the terminal device shown in fig. 3. As shown in fig. 4, the data storage method includes:

401. the storage chip acquires the effective data volume of a fast storage area, and the storage form of the data of the fast storage area is a first storage form.

It is understood that the description of the fast memory region included in the memory chip may refer to the foregoing embodiments, and is not described in detail herein. In this embodiment of the present application, the data stored in the fast storage area may include not only data related to an application, but also data related to a key database, file system metadata, a virtual memory exchange mechanism, and the like. Therefore, the effective data amount acquired by the memory chip can be understood as the data amount of the data stored in the fast memory area acquired by the memory chip. Alternatively, the valid data amount may also be referred to as physical valid data, and the like, and the embodiment of the present application is not limited. For example, if the effective data amount obtained by the memory chip may be 20G, or xG, etc., the embodiment of the present application does not limit a specific value of the effective data amount, and the specific value may be determined according to an actual situation.

402. When the effective data amount of the fast storage area is larger than a first threshold value, the memory chip converts the fast storage area into a normal storage area, and the storage form of the data of the normal storage area is a second storage form.

In the embodiment of the present application, the storage forms of the data in the storage chip may be mutually converted, such as between a first storage form and a second storage form. It can be understood that the storage form of the data in the memory core in the embodiment of the present application may further include a third storage form, so that the storage form of the data in the memory chip is mutually converted between the first storage form, the second storage form and the third storage form. The first storage mode, the second storage mode and the third storage mode may be different storage modes belonging to the same storage medium. As an example, different memory modalities such as NAND may be used. It is understood that the names of the areas corresponding to the third storage mode are not limited in the embodiments of the present application. It is understood that the fast storage area is different from the normal storage area in the storage form of data, for example, the storage form of data in the fast storage area is a first storage form, and the storage form of data in the normal storage area is a second storage form. That is, when converting the storage form in the memory chip, the names of the storage areas in the memory chip are converted to each other. It is understood that the read/write speed of the first storage mode and the third storage mode, and the read/write speed of the second storage mode and the third storage mode are not limited in the embodiments of the present application.

In the embodiment of the present application, the first storage form and the second storage form may also be the same storage medium, such as fast NAND and slow NAND.

As an example, the first storage form includes a single-level cell (SLC), and the second storage form includes a triple-level cell (TLC); alternatively, the first storage modality includes SLC, and the second storage modality includes multi-level cells (MLC); alternatively, the first storage modality comprises MLC and the second storage modality comprises TLC; alternatively, the first storage modality includes SLC and the second storage modality includes QLC. As an example, data in the SLC's storage granules may be moved away, such as when converting SLC to TLC, to convert SLC to TLC, and then use TLC to store the data. When the TLC is converted to the SLC, the data in the TLC stored particles, such as two-thirds of the data, can be moved away to convert the TLC to the SLC, and then the SLC is used to store the data. As an example, SLC, i.e. 1bit/cell, has a fast speed and a long life, and has an erasing life of 10 ten thousand times per month; MLC is 2bit/cell, the speed is generally life-span, about 3000 to 10000 times of erasing life-span; TLC (thin layer chromatography), namely 3bit/cell, with a slow speed and a lifetime of about 500 times of erasing and writing; QLC, 4bit/cell, about 150 erase lifetimes.

That is, in the embodiment of the present application, as for example SLC and TLC, the fast storage region may also correspond to an SLC region, and after the fast storage region is converted into a normal storage region, the normal storage region may correspond to a TLC region.

In the embodiment of the present application, when the effective data amount in the fast storage area is too large, for example, larger than the first threshold, it indicates that the space to be used by the host chip (also referred to as host side, etc.) is larger and larger, and at this time, the memory chip may convert the storage form of the fast storage area data from the first storage form to the second storage form of the normal storage area data, so as to expand the physical space of the storage area without sacrificing the user visible space.

403. The memory chip obtains the effective data volume of the common memory area.

In the embodiment of the present application, the description of the effective data amount of the normal storage area may refer to the description of the effective data amount of the fast storage area, and is not detailed here.

404. And under the condition that the effective data volume of the ordinary storage area is smaller than a second threshold value, the storage chip converts the ordinary storage area into the fast storage area.

In this embodiment of the present application, values of the first threshold and the second threshold may be the same or different, and this embodiment of the present application is not limited. Optionally, the first threshold may be greater than the second threshold, and so on, and the first threshold and the second threshold are not limited in this application. It is understood that the first threshold and the second threshold may be set autonomously by the memory chip, or by the terminal device, or by the user, and the like, and the embodiments of the present application are not limited thereto.

In the embodiment of the application, when the effective data amount in the ordinary storage area is smaller than the second threshold, it indicates that the space to be used by the main chip may be reduced, and at this time, the storage chip may convert the storage form of the ordinary storage area data from the second storage form to the first storage form, that is, convert the ordinary storage area to the fast storage area, so as to improve the response speed of the relevant data in the fast storage area.

As an example, an application frequently used by a user (referred to as a high frequency application or a hot spot application) is installed in a fast storage area, so that when the application is cold-started, the response speed of the application can be increased. If the application context state is stored in the fast storage area, when the memory is forcibly closed and called again, the response speed of the application can be improved, and the user satisfaction degree can be improved. If the key data of the system is stored in the quick storage area, the running speed of the system can be increased, and the system can run more smoothly. It is to be understood that the foregoing is only illustrative of the present application and is not to be construed as limiting thereof.

In the embodiment of the present application, the memory chip may determine whether to convert the fast storage area into the normal storage area according to the data size of the effective data size of the fast storage area. It can be understood that, in the embodiment of the present application, there is a conversion relationship between the storage space of the first storage form and the storage space of the second storage form, and the read/write speed of the first storage form is different from that of the second storage form, for example, the read/write speed of the first storage form is greater than that of the second storage form.

In the embodiment of the application, the storage forms of the data in the quick storage areas are mutually converted through the effective data volume in the quick storage areas in the storage chip; thus, when data related to the application is stored in the fast storage area, the storage form can be converted according to the requirement, such as converting the storage form between the first storage form and the second storage form. Or when other system key data are stored in the fast storage area, the storage chip can convert the storage form according to the requirement, thereby improving the response speed of the key data.

Optionally, when the effective data amount of the fast storage area is greater than a first threshold, converting the fast storage area into an ordinary storage area includes:

and if the effective data amount of the fast storage area is larger than the first threshold, converting the fast storage area into the normal storage area according to the size of the effective data amount of the fast storage area and the storage space conversion relationship between the first storage form and the second storage form.

In an embodiment of the present application, a storage space transformation relationship between the first storage form and the second storage form may be 1: 2, or 1:3, or 2: 3, or 1: 4, etc. That is, for example, the xG space when the storage form is the first storage form may be converted into the 3xG space when the storage form is the second storage form.

In the embodiment of the application, the memory chip can convert the storage form of the data in the fast storage area according to the size of the used data volume and the space conversion relationship between the first storage form and the second storage form. For example, if the space conversion relationship between the SLC and the TLC is 1:3, and the first threshold is 15G, if the amount of valid data acquired by the memory chip is 17G, it may be necessary to store data in the memory chip, so that the memory chip may convert the SLC of 10G into TLC of 30G to store data, thereby not only not sacrificing the visible space of the user, such as the user cannot feel the loss of space, but also expanding the storage space of data for the memory chip to store or cache data. For another example, if the amount of data acquired by the memory chip is 30G or more, the memory chip may convert the SLC of 20G to TLC of 60G, so as to store more data. It is to be understood that the above numerical values are merely exemplary and should not be construed as limiting the present application.

Optionally, when the effective data amount of the normal storage area is smaller than a second threshold, converting the normal storage area into the fast storage area includes:

and if the effective data amount of the normal storage area is smaller than the second threshold, converting the normal storage area into the fast storage area according to the size of the effective data amount of the normal storage area and the storage space conversion relationship between the first storage form and the second storage form.

In the embodiment of the application, the memory chip can convert the storage form of the data in the fast storage area according to the size of the used data volume and the space conversion relationship between the first storage form and the second storage form. For example, if the space conversion relationship between the SLC and the TLC is 1:3, and the second threshold is 8G, if the amount of valid data acquired by the memory chip is 7G, it may not be necessary to store data in the memory chip, and therefore, the memory chip may convert 30G of TLC into 10G of SLC to store data, thereby not only not sacrificing the visible space of the user, such as the user may not feel the loss of space, but also improving the read/write performance of data because the speed of TLC is slower than that of SLC. It is to be understood that the above numerical values are merely exemplary and should not be construed as limiting the present application.

It is understood that the storage forms in the memory chip can be mutually converted, and there may also be a precondition that, for example, in the case that the wear-out number of the fast storage area is smaller than the wear-out number threshold, the first storage form in the memory chip can be mutually converted with the second storage form, that is, the fast storage area can be mutually converted with the normal storage area. And under the condition that the wear frequency of the quick storage area is not less than the wear frequency threshold, completely converting the storage form of the relevant area in the memory chip from the first storage form to the second storage form, namely completely converting the quick storage area to a common storage area. That is, the precondition that the first storage form and the second storage form can be mutually converted may be that the wear-out number of the fast storage area is less than a wear-out number threshold, and if the wear-out number of the fast storage area exceeds the wear-out number threshold, it indicates that the storage forms of the fast storage area cannot be mutually converted, that is, the first storage form can be completely converted into the second storage form. The wear threshold may be determined by the performance of the memory chip, and the like, and the setting of the wear threshold is not limited in the embodiment of the present application.

It can be understood that, the embodiment of the present application further provides a method how to set the size of the data amount stored in the fast storage area, that is, before the obtaining the effective data amount of the fast storage area, the method further includes: and allocating the fast storage area to the memory chip according to the use condition of the application data.

That is, the memory chip may allocate a fast memory area based on the user application behavior analysis. Still alternatively, the memory chip may allocate the fast memory area and the first normal memory area described in fig. 2 based on the user application behavior analysis. That is, the memory chip may analyze the situation of the user using the terminal device, for example, after analyzing the data situation of the user using the application through the terminal device, the memory chip may allocate the sizes of the fast storage area and the first normal storage area according to the situation of the user using the application. For example, the memory chip may use the 10G space in the memory chip as a fast storage region (e.g., a second normal storage region convertible to 30G) and use the 20G space in the memory chip as a first normal storage region by analyzing the usage of the application data. It is to be understood that the numbers shown above are merely examples and should not be construed as limiting the present application.

For a more visual understanding of the data storage method provided by the embodiment of the present application, referring to fig. 5, fig. 5 is a schematic view of a scenario of the data storage method provided by the embodiment of the present application, as shown in fig. 5, a fast storage region, i.e. an SLC region in the figure, and a reserved region may be understood as a virtual space. If the storage form of the fast storage region is the SLC storage form, when the amount of data in the memory chip is larger and larger (as shown by the dashed arrow on the second row in fig. 5), and is larger than xGB, the SLC region can be converted to the TLC region, i.e. the storage form of the data is converted from the SLC storage form to the TLC storage form (as shown by the solid arrow on the second row in fig. 5). When the amount of data in the memory chip is smaller (as shown by the third row of the dashed arrow in fig. 5), such as smaller than yGB, the TLC region may be converted into the SLC region, i.e. the memory pattern of the data is converted from the TLC memory pattern into the SLC memory pattern (as shown by the third row of the solid arrow in fig. 5). It is understood that LUm can be understood as the first general storage area depicted in fig. 2, with logical unit number m. And after the SLC is converted to TLC, the logical unit number of the TLC region, i.e., the second general storage region depicted in fig. 2, may be LUn. Wherein x and y can be any positive number, and the application is not limited with respect to specific values.

Further, the schematic diagram shown in fig. 5 can be divided into three periods, such as:

and in the fast storage area enabling period, under the condition that the wear time of the fast storage area is less than a wear time threshold, such as in an erase time (EC) specification, the total effective data amount of the fast storage area is within a threshold z1GB, and the read performance of the fast storage area is fully hit on the SLC, wherein z1 is any positive number. It is understood that, in the embodiment of the present application, the number of times of wear may also be understood as the value of the number of times of erasure EC.

A fast storage region suspension period, in which the total amount of valid data of the fast storage region is outside the threshold z1GB in the case that the wear time of the fast storage region is less than the wear time threshold, the fast storage region initiates SLC to TLC return (after return to TLC, the fast storage region may be referred to as normal storage region). As another example, when the total amount of valid data in the normal storage region is within the threshold z2GB, the normal storage region initiates TLC to SLC reverse return, where z2 is any positive number.

And a fast storage area closing period, wherein the fast storage area is permanently closed under the condition that the abrasion times of the fast storage area is not less than the abrasion time threshold value, namely, the storage form of the data in the storage chip can be completely converted from the SLC to the TLC, and the conversion from the TLC to the SLC can not be continued.

It is understood that the above is only an example of the present application, and the data amount size or the data amount threshold value thereof should not be construed as limiting the present application.

The method of the embodiments of the present application is set forth above in detail and the apparatus of the embodiments of the present application is provided below.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a memory chip provided in an embodiment of the present application, and as shown in fig. 6, the memory chip may include:

an obtaining unit 601, configured to obtain an effective data amount of a fast storage area, where a storage form of data in the fast storage area is a first storage form;

a conversion unit 602, configured to, when the effective data amount of the fast storage area is greater than a first threshold, convert the fast storage area into a normal storage area, where a storage form of data in the normal storage area is a second storage form.

In the embodiment of the application, the memory chip comprises the quick memory area, so that the response speed of the application can be improved; when the effective data amount in the fast storage area is too large, such as larger than the first threshold, it indicates that the space to be used by the main chip (also referred to as the host side, etc.) is larger and larger, and at this time, the memory chip can convert the storage form, that is, the memory chip can convert the first storage form of the data in the fast storage area into the second storage form of the data in the normal storage area, so as to expand the physical space of the storage area without sacrificing the user-visible logic space.

In a possible implementation manner, the obtaining unit 601 is further configured to obtain an effective data amount of the general storage area;

the converting unit 602 is further configured to convert the normal storage area into the fast storage area when the effective data amount of the normal storage area is smaller than a second threshold.

In a possible implementation manner, the converting unit 602 is specifically configured to, when the effective data amount of the fast storage area is greater than the first threshold, convert the fast storage area into the normal storage area according to a size of the effective data amount of the fast storage area and a storage space conversion relationship between the first storage form and the second storage form.

In a possible implementation manner, the converting unit 602 is specifically configured to, when the effective data amount of the normal storage area is smaller than the second threshold, convert the normal storage area into the fast storage area according to the size of the effective data amount of the normal storage area and a storage space conversion relationship between the first storage form and the second storage form.

In a possible implementation manner, the converting unit 602 is specifically configured to convert the normal storage area into the fast storage area when the number of times of wear of the fast storage area is smaller than a wear number threshold.

In a possible implementation manner, the converting unit 602 is further configured to convert the normal storage area into the fast storage area if the number of times of wear of the fast storage area is not less than the wear number threshold.

In a possible implementation manner, as shown in fig. 7, the memory chip further includes:

an allocating unit 603, configured to allocate the fast storage area to the memory chip according to a usage of the application data.

In one possible implementation, the first storage form and the second storage form belong to different storage forms of the same storage medium.

In a possible implementation, the first storage form includes SLC, and the second storage form includes TLC; or, the first storage form comprises SLC, and the second storage form comprises MLC; alternatively, the first storage mode comprises MLC and the second storage mode comprises TLC; alternatively, the first storage mode includes SLC, and the second storage mode includes four-layer memory cells QLC.

It should be noted that the implementation of each unit may also correspond to the corresponding description of the method embodiment shown in fig. 4 and/or fig. 5. It should be noted that each unit refers to a logical partition, and does not mean that the unit corresponds to a specific piece of hardware, and specifically, the function of each unit may be implemented based on various pieces of hardware, for example, based on a processor supporting an instruction set by reading code stored in a memory, or based on a Field Programmable Gate Array (FPGA) reading configuration file, or based on an application-specific integrated circuit (ASIC), or by combining these implementations, which is not limited in this application.

Referring to fig. 8, fig. 8 is a schematic structural diagram of a terminal device according to an embodiment of the present disclosure, where the terminal device may be configured to perform the method shown in fig. 4 and/or fig. 5, and as shown in fig. 8, the terminal device may include a memory chip, and the memory chip may be the memory chip shown in fig. 6 and/or fig. 7. It is understood that the units of the memory chip included in the terminal device can refer to the foregoing embodiments, and are not described in detail herein.

It is understood that other chips may be included in the terminal device, and are not described in detail here.

The embodiment of the application also provides a computer readable storage medium. All or part of the processes in the above method embodiments may be performed by relevant hardware instructed by a computer program, which may be stored in the above computer storage medium, and when executed, may include the processes in the above method embodiments.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in or transmitted over a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.

The modules in the device can be merged, divided and deleted according to actual needs.

The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

A data storage method is applied to a storage chip, and comprises the following steps:

acquiring effective data volume of a quick storage area, wherein the storage form of data in the quick storage area is a first storage form;

and converting the quick storage area into a common storage area under the condition that the effective data volume of the quick storage area is greater than a first threshold, wherein the storage form of the data in the common storage area is a second storage form.
The method of claim 1, further comprising:

obtaining the effective data volume of the common storage area;

and converting the normal storage area into the fast storage area under the condition that the effective data volume of the normal storage area is smaller than a second threshold value.
The method according to claim 1 or 2, wherein the converting the fast storage area into a normal storage area in the case that the effective data amount of the fast storage area is greater than a first threshold value comprises:

and under the condition that the effective data volume of the quick storage area is larger than the first threshold, converting the quick storage area into the ordinary storage area according to the size of the effective data volume of the quick storage area and the storage space conversion relation between the first storage form and the second storage form.
The method according to claim 2 or 3, wherein the converting the normal storage area into the fast storage area in the case that the effective data amount of the normal storage area is smaller than a second threshold value comprises:

and under the condition that the effective data volume of the ordinary storage area is smaller than the second threshold, converting the ordinary storage area into the fast storage area according to the size of the effective data volume of the ordinary storage area and the storage space conversion relation between the first storage form and the second storage form.
The method according to any one of claims 2-4, wherein said converting said normal storage area into said fast storage area comprises:

and converting the ordinary storage area into the fast storage area under the condition that the abrasion times of the fast storage area are smaller than an abrasion time threshold value.
The method of claim 5, further comprising:

and under the condition that the abrasion times of the quick storage area is not less than the abrasion time threshold value, completely converting the quick storage area into the ordinary storage area.
The method of any of claims 1-6, wherein prior to obtaining the effective amount of data for the fast storage area, the method further comprises:

and allocating the fast storage area to the storage chip according to the use condition of the application data.
The method according to any of claims 1-7, wherein the first storage modality and the second storage modality belong to different storage modalities of the same storage medium.
The method according to any one of claims 1 to 8,

the first storage form comprises a single-layer memory cell SLC, and the second storage form comprises a three-layer memory cell TLC;

or, the first storage modality comprises SLC, and the second storage modality comprises MLC;

alternatively, the first storage modality comprises MLC and the second storage modality comprises TLC;

alternatively, the first storage form comprises SLC and the second storage form comprises four-layer memory cells QLC.
A memory chip, comprising:

the device comprises an acquisition unit, a storage unit and a processing unit, wherein the acquisition unit is used for acquiring the effective data volume of a quick storage area, and the storage form of the data of the quick storage area is a first storage form;

the conversion unit is used for converting the quick storage area into a common storage area under the condition that the effective data volume of the quick storage area is larger than a first threshold, and the storage form of the data of the common storage area is a second storage form.
The memory chip of claim 10,

the obtaining unit is further configured to obtain an effective data amount of the common storage area;

the conversion unit is further configured to convert the normal storage area into the fast storage area when the effective data amount of the normal storage area is smaller than a second threshold.
The memory chip according to claim 10 or 11,

the conversion unit is specifically configured to, when the effective data amount of the fast storage area is greater than the first threshold, convert the fast storage area into the normal storage area according to the size of the effective data amount of the fast storage area and a storage space conversion relationship between the first storage form and the second storage form.
The memory chip according to claim 11 or 12,

the conversion unit is specifically configured to, when the effective data amount of the normal storage area is smaller than the second threshold, convert the normal storage area into the fast storage area according to the size of the effective data amount of the normal storage area and the storage space conversion relationship between the first storage form and the second storage form.
The memory chip according to any one of claims 11 to 13,

the conversion unit is specifically configured to convert the normal storage area into the fast storage area when the wear count of the fast storage area is smaller than a wear count threshold.
The memory chip of claim 14,

the conversion unit is further configured to completely convert the fast storage area into the normal storage area when the wear count of the fast storage area is not less than the wear count threshold.
The memory chip of any one of claims 10-15, wherein the memory chip further comprises:

and the allocation unit is used for allocating the quick storage area to the storage chip according to the use condition of the application data.
The memory chip of any one of claims 10 to 16, wherein the first storage modality and the second storage modality belong to different storage modalities of a same storage medium.
The memory chip according to any one of claims 10 to 17,

the first storage form comprises a single-layer memory cell SLC, and the second storage form comprises a three-layer memory cell TLC;

or, the first storage modality comprises SLC, and the second storage modality comprises MLC;

alternatively, the first storage modality comprises MLC and the second storage modality comprises TLC;

alternatively, the first storage form comprises SLC and the second storage form comprises four-layer memory cells QLC.
A memory chip, characterized in that the memory chip comprises a controller and a memory array, the controller being configured to perform the method according to any of claims 1-9.
A terminal device, characterized in that the terminal device comprises a processor for reading and writing data by interacting with a memory chip for performing the method according to any one of claims 1-9.
A computer-readable storage medium having stored thereon instructions which, when executed on a computer, implement the method of any of claims 1-9.