CN117785619B - Method and system for monitoring chip storage state - Google Patents
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Abstract
The invention discloses a method and a system for monitoring the storage state of a chip, which monitor the storage state of the storage chip through parameters of multiple dimensions, determine the number of available storage chips, determine the scheduling scheme of target data on the available storage chips according to the number of required storage chips and the number of available storage chips, and store or read data to be stored in a blocking mode according to the storage state according to the scheduling scheme. The method can realize the quick and lossless storage of the data to be stored and the quick and lossless reading of the stored data.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a method and system for monitoring a chip storage state.
Background
The storage capability of the storage chip is fast moving according to the rule of moore's law, so that the storage chip at the consumer level or the storage chip at the server level always stores massive data information, and the existing large-scale storage device is usually an array storage device. Compared with the traditional memory chip, the array memory chip adopts a parallel access mode, so that faster reading and writing speeds and lower delay can be realized. When accessing an array memory device in a parallel access manner, it is theoretically necessary to examine the working state of each individual memory chip and perform an algorithmic scheduling based on the working state of each chip, and each individual memory chip often has a large number of operating parameters to be monitored, including but not limited to a memory space, working conditions (temperature, humidity, etc.), clock frequency, fault conditions, and the like. In the prior art, comprehensive monitoring of the parameters (particularly physical parameters) is often difficult to realize, and no proper algorithm is available for reasonably summarizing and utilizing the data obtained by monitoring.
Therefore, it is necessary to develop a method for monitoring the memory chips to monitor the real-time working condition of each memory chip, and perform reasonable algorithm processing according to the monitored data, so as to implement reasonable access scheduling according to the monitored data, so as to achieve faster and more lossless access of the target data.
Disclosure of Invention
In order to solve the problem that the working state of a memory chip cannot be comprehensively monitored at present and meanwhile, the algorithm processing is carried out based on monitoring data to realize accurate data access, the invention provides a method and a system for monitoring the memory state of the chip.
In a first aspect, the present invention provides a method for monitoring a memory state of a chip, including quantifiable monitoring parameters of multiple dimensions, including: monitoring the physical state of the memory chip through the sensor and reading the monitoring data of the sensor by a reading circuit; monitoring by clock frequency: detecting abnormal running speed or fluctuation of clock frequency by monitoring the clock frequency of the chip; storage space monitoring: monitoring the use condition and the residual capacity of the memory chip so as to make adjustment or backup work in time; fault detection is applied: and monitoring the error, breakdown or fault of the chip, and taking corresponding processing measures. Data integrity verification: the integrity of the data stored in the chip is verified by a verification algorithm to prevent corruption or tampering.
Specifically, a first aspect of the present invention provides a method for monitoring a memory state of a chip, including:
The target data is obtained and the data is stored,
Determining the number N of memory chips required for the target data, and
In a target process, determining the number M of available memory chips, and determining a scheduling scheme of the target data on the M available memory chips according to the number N of the required memory chips and the number M of the available memory chips, wherein N, M is a natural number which is more than or equal to 1;
The determining process of the number M of the available memory chips is as follows:
Traversing all L memory chips to obtain Q characteristic parameters X 1、X2……Xj of each memory chip, and enabling
Zi=I= … n, α j is a coefficient;
The Sigmoid transformation of Z i is as follows:
Fi（Zi）=∈（0,1），i=1…n
presetting a judging threshold A of Fi, wherein A epsilon (0, 1) is judged:
F i（Zi) by F i（Zi) A
F i（Zi) does not pass F i（Zi) < A
Obtaining the number M of all the memory chips with F i（Zi) more than or equal to A;
The target process is a process of storing the target data into the memory chip.
In a preferred case, the method further comprises a scheduling algorithm, and the scheduling method comprises the following steps: determining a target total storage space required by executing the target process according to the total data amount of the target data; the number of memory chips that can be called is determined based on the total memory space required. And determining K initial scheduling schemes according to the required target total storage space and the number of the callable storage chips.
In a preferred case, each of the K initial scheduling schemes includes: at least one available memory chip participating in the target process, and an actual available memory space of the at least one available memory chip participating in the target process.
Under the preferable condition, the K initial allocation schemes meet the condition that the storable space of each available memory chip is larger than or equal to the total amount of the corresponding target data, and K is an integer more than or equal to 1; and determining a first target allocation scheme from the K initial allocation schemes for execution based on the optimization purpose.
In a preferred case, the optimization purposes include: the target data storage speed is maximized and/or the target data reading speed is maximized.
In a preferred case, if the number N of memory chips is greater than the number M of available memory chips, the number of memory chips to be finally used is M, and if the number N of memory chips is less than or equal to the number M of available memory chips, the number of memory chips to be finally used is N.
In a preferred case, the characteristic parameters include: the residual memory space of the memory chip, the data transmission speed of the storage medium and the working state of the memory chip.
In a preferred case, the working states of the memory chip at least include: the working temperature and the working humidity of the memory chip.
In a preferred embodiment, the operating state of the memory chip is acquired by a temperature sensor and a humidity sensor.
On the other hand, the invention also provides a memory scheduling scheme based on the monitoring method of the chip storage state, which comprises the following steps: determining a target total storage space required in a target process of storing target data according to the total data amount of the target data; determining the number of available memory chips to be called according to the required total memory space; and determining an initial scheduling scheme according to the required target total storage space and the number of the available storage chips to be called, and determining one optimal scheduling scheme or a scheme for reading stored data by using the same method.
Specifically, another aspect of the present invention provides a monitoring system for a chip memory state, including:
the first memory chip is used for storing at least one group of instruction sets, wherein the at least one group of instruction sets are used for performing memory scheduling in the process of storing target data into a target of the target memory chip; and
The processing circuit is in communication connection with the first memory chip and the target memory chip;
wherein, when the data processing apparatus is running, the processing circuitry executes the at least one set of instructions:
The target data is obtained and the data is stored,
Determining the number N of memory chips required for the target data, and
In the target process, determining the number M of available memory chips in a target memory chip, and determining a scheduling scheme of the target data on the M available memory chips according to the number N of the required memory chips and the number M of the available memory chips, wherein N, M is a natural number which is more than or equal to 1;
The determining process of the number M of the available memory chips is as follows:
Traversing all L memory chips to obtain Q characteristic parameters X 1、X2……Xj of each memory chip, and enabling
Zi=I= … n, α j is a coefficient;
The Sigmoid transformation of Z i is as follows:
Fi（Zi）=∈（（0,1），i=1…n
presetting a judging threshold A of Fi, wherein A epsilon (0, 1) is judged:
F i（Zi) by F i（Zi) A
F i（Zi) does not pass F i（Zi) < A
Obtaining the number M of all the memory chips with F i（Zi) more than or equal to A;
The target process is a process of storing the target data into the target memory chip.
Compared with the prior art, the invention has at least the following beneficial technical effects:
According to the invention, the sensor module for monitoring the working condition of the memory chip is arranged, the memory state of the multi-dimensional parameter monitoring memory chip is obtained, the multi-element linear regression model is constructed to carry out algorithm processing on the obtained parameters, then the constructed model is subjected to Sigmoid conversion, the normalization processing of the monitoring parameters of different dimensions of the memory chip is realized, the threshold value judgment of whether the memory chip is available or not is carried out according to the processing result, and the block parallel access is carried out on the target memory data based on the judgment result, so that the data can be accessed more quickly and more nondestructively.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present description, the following description will briefly explain the drawings needed in the description of the embodiments, and it is obvious that the drawings in the following description are only some embodiments of the present description, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a schematic diagram of an application scenario provided according to an embodiment of the present application;
FIG. 2 illustrates a schematic diagram of another application scenario provided in accordance with an embodiment of the present application;
FIG. 3 is a schematic diagram of a memory module according to an embodiment of the present application;
FIG. 4 is a schematic diagram showing another structure of a memory module according to an embodiment of the present application;
FIG. 5 is a schematic diagram showing another structure of a memory module according to an embodiment of the present application;
FIG. 6 illustrates a schematic diagram of one configuration of an integrated sensor module provided in accordance with an embodiment of the present application;
FIG. 7 is a flow chart of a data processing method for monitoring the memory status of a chip according to an embodiment of the application;
FIG. 8 shows a flow diagram of a method of data processing for scheduling of target data stores, provided in accordance with an embodiment of the present application.
Detailed Description
The following description is presented to enable one of ordinary skill in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the disclosure. Thus, the present description is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. For example, as used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. The terms "comprises," "comprising," "includes," and/or "including," when used in this specification, are taken to specify the presence of stated integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
These and other features of the present specification, as well as the operation and function of the related elements of structure, as well as the combination of parts and economies of manufacture, may be significantly improved in view of the following description. All of which form a part of this specification, reference is made to the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended as a definition of the limits of the description. It should also be understood that the drawings are not drawn to scale.
The flowcharts used in this specification illustrate operations implemented by systems according to some embodiments in this specification. It should be clearly understood that the operations of the flow diagrams may be implemented out of order. Rather, operations may be performed in reverse order or concurrently. Further, one or more other operations may be added to the flowchart. One or more operations may be removed from the flowchart.
The memory chip provided in the present specification is an integrated circuit chip for storing and reading data, and may be used for storing data such as personal files, photographs, videos, music, and the like. In computers and mobile devices, memory chips are often used in Solid State Drives (SSDs) and flash memories (such as memory cards and USB flash drives), providing high-speed read/write operations and large-capacity storage space; but also to store operating systems, application programs, and software code. In computers, cell phones, tablet computers, etc., memory chips are commonly used as main memory (RAM) and firmware storage (e.g., flash memory) for loading and running operating systems and applications; also used as a cache memory to provide fast read-write access to speed up data processing of a computer, a processor or the like typically includes a cache memory for temporarily storing frequently used data for faster access and processing; but also for data backup and restore, which may provide backup storage for computers and electronic devices to protect data from accidental loss or damage, and for data restore operations, the embodiments of the present application are not limited in this regard.
Fig. 1-2 show a schematic diagram of an application scenario provided according to an embodiment of the present application, fig. 1 shows a process of storing target data from a process medium 12 into a memory chip 11, fig. 2 shows a process of reading target data from the memory chip 11 to the process medium 12, and a communication connection is adopted between the process medium 12 and the memory chip 11, where the process medium 12 may be another medium for temporarily storing the target data, such as a usb disk, a removable hard disk, etc.
As an example, referring to fig. 3, the memory chips 11 are generally arranged in an array in a memory module 3, and the memory module 3 may include different types of memory chips 11, such as a flash memory 1101, an SSD1102, a hard disk 1103, a RAM1104, and the like. Of course, only one type or a combination of several types of memory chips 11 may be provided in the memory module 33, such as a memory array composed of a plurality of identical L memory chips 11, referring to fig. 4.
Fig. 5 shows another schematic structure of a memory module 33 according to an embodiment of the present application, where the memory module 33 includes a memory array formed by L memory chips 11, and the memory chips 11 are communicatively and electrically connected to each other, and an integrated sensor module 44 electrically and communicatively connected to each of the individual memory chips 11 is further disposed in the memory module 33, for monitoring a memory status of each of the individual memory chips 11.
Fig. 6 shows a schematic structural diagram of the integrated sensor module 4 provided in fig. 5 according to an embodiment of the present application, where the integrated sensor module 4 includes at least one or more temperature sensors 401 and humidity sensors 402, and is configured to monitor the real-time temperature and real-time humidity of the memory chip 11 and output the monitoring results and the respective characteristic parameters to the memory chip 11 for feedback; the integrated sensor module 4 may further be provided with a clock frequency monitoring module 403, a storage space monitoring module 404, an application fault detection module 405, and a data integrity verification module 406, which are configured to monitor the clock frequency of the chip, and detect an abnormal running speed or fluctuation of the clock frequency, respectively; monitoring the use condition and the residual capacity of the memory chip so as to make adjustment or backup work in time; monitoring the error, breakdown or fault of the chip, and taking corresponding processing measures; the verification algorithm verifies the integrity of the data stored in the chip to prevent corruption or tampering. The sensing modules are configured to acquire the characteristic parameters of the operation of the memory chip 11 and output the result to the memory chip 11.
In some embodiments, the memory module 3 is externally packaged with a hard shell for the memory module 3 to allow structural integrity to protect internal devices when the memory module 3 is damaged by external forces such as dropping, impact, stamping, etc.
The following describes a method for monitoring a chip memory state according to an embodiment of the present application, and please refer to a flowchart of a data processing method shown in fig. 7. Specifically, a single memory chip 11 or a memory module 3 composed of two or more memory chips 11 may perform the data processing method P100, and as shown in fig. 7, the data processing method P100 may include steps S510 to S550.
S510: traversing all the characteristic parameters.
In some embodiments, the memory chip 11 or the memory module 3 reads the characteristic parameters of all the sensor modules. The characteristic parameter is quantized data of the state of the memory chip 11 monitored by the sensor in the sensing module, for example, the working temperature of each memory chip 11 at this time, whether each memory chip 11 is damaged (the damaged characteristic parameter may be 0, the undamaged characteristic parameter may be 1), the remaining memory capacity of each memory chip 11, the current memory/read speed of each memory chip 11, and the like. Traversing all L memory chips to obtain Q characteristic parameters X of each memory chip 1、X2……Xj.
S520: constructing multiple linear regression model for the obtained LxQ characteristic parameters
Zi=I= … n, α j is a coefficient
A multiple linear regression model is a model commonly used in statistics and machine learning to establish the relationship between independent variable(s) and dependent variables. In multiple linear regression, it is assumed that there is a linear relationship between the dependent variable and a plurality of independent variables, and the value of the dependent variable is predicted by finding the best fit line. In the present application, it is assumed that each individual memory chip 11 has a linear relationship with its corresponding Q characteristic parameters X 1、X2……Xj.
S530: sigmoid conversion is performed on the multiple linear regression model (Z i).
Fi（Zi）=∈（0,1），i=1…n
Sigmoid conversion is a mathematical function conversion that can map data between 0 and 1, often used to normalize or scale input features. By performing Sigmoid conversion on the input, the range of the original data can be limited within a certain interval, so that the characteristics have better comparability and interpretation.
S540: and judging the threshold value of the transformed model.
Presetting a judging threshold A of Fi, wherein A epsilon (0, 1) is judged:
F i（Zi) by F i（Zi) A
F i（Zi) does not pass F i（Zi) < A
In the present application, the value of a (a e (0, 1)) may be the final threshold value for determining the memory chip 11, which is finally obtained after training by machine learning. Specifically, the machine algorithm for obtaining the decision threshold a in the present application may include the steps of: 1. collecting a data set: and collecting state data of a plurality of groups of memory chips, wherein the state data comprise characteristic parameters such as working temperature, damage or not, storage speed and the like. 2. Preparing a data set: the data set is divided into a training set and a test set. Here, the majority of the data (> 80%) was used for training and the minority (less than 20%) was used for testing. 3. Feature selection and data preprocessing: the data is pre-processed, including normalized or normalized, to ensure that the features have closely related dimensions, depending on the particular problem and the relevance of the features. 4. In the application, the data is subjected to model training by adopting a Deep Neural Network (DNN) algorithm, and the DNN has the advantages of automatically learning characteristic representation from the data, reducing the burden of characteristic engineering, improving the generalization capability of the model, having better performance on a large-scale data set and obtaining better generalization effect under the condition of sufficient training. 5. And (3) result feedback: using the test set to evaluate the performance of the model, various evaluation metrics, including accuracy, precision, recall, may be used to evaluate the accuracy and performance of the model. 6. Obtaining a set threshold value: and obtaining a threshold A according to the data storage and reading requirement threshold, and dividing the storage chips into two types of passing or non-passing according to the threshold. 7. Model application and prediction: and predicting the new memory chip data by using the trained model, and judging whether the new memory chip data passes or not according to the threshold A.
S550: the number M of individual memory chips 11 available for target data storage is obtained from the final determination result.
In the present application, the number M of the single memory chips 11 available for target data storage may be used for storage scheduling of target data.
The scheduling algorithm for target data storage provided by the embodiment of the application is specifically described below. In some embodiments, determining a target total storage space required to perform the target process based on a total amount of data of the target data; and determining the number of the available memory chips to be called according to the required total memory space. And determining K initial scheduling schemes according to the required target total storage space and the number of available storage chips to be called. It should be understood that each of the K initial allocation schemes satisfies that the storable space of each of the available memory chips is greater than or equal to the total amount of the target data (K is an integer greater than or equal to 1), and at least one memory chip 11 is called as a memory chip of the target data during the storing process.
Please refer to a flowchart of the data processing method shown in fig. 8. Specifically, the single memory chip 11 or the memory module 3 composed of two or more memory chips 11 or the process medium 12 storing the target data may perform the data processing method P200, and as shown in fig. 8, the data processing method P200 may include steps S610 to 640.
S610: target data is obtained.
In some embodiments, the target data is stored in the process medium 12, and when the process medium 12 establishes a communication connection with the memory chip 11, the process medium 12 is configured to identify the stored data and obtain the target data. In some embodiments, the target data is stored in the process medium 12, and when the process medium 12 establishes a communication connection with the memory chip 11, the memory chip 11 is configured to identify the stored data and obtain the target data.
S620: the number of memory chips N required for the target data is determined.
In some embodiments, the process medium 12 or the memory chip 11 is configured to block-pack the target data and determine the number of copies to pack, i.e., the number of memory chips N required for the target data.
S630: the number M of available memory chips is determined.
In some embodiments, the process medium 12 or the memory chip 11 is configured to directly invoke the data processing method described in P100 to determine the number M of available memory chips.
S640: storing the target data into the memory chip.
In some embodiments, the number N of the required memory chips and the number M of the available memory chips are compared, if the number N of the required memory chips > the number M of the available memory chips, the number of the memory chips finally used is M, and if the number N of the memory chips is less than or equal to the number M of the available memory chips, the number of the memory chips finally used is N. Wherein N, M are natural numbers equal to or greater than 1.
In some embodiments, the target data scheduling method scheduled by the data processing method P200 is configured as a first scheduling method of the K initial scheduling schemes, which is performed by the process medium 12 or the memory chip 11. The first scheduling method is a parallel storage method, and can greatly improve the storage speed of target data.
The present application also provides a reading scheme of stored target data, in some embodiments, the reading scheme first uses a data processing method as described in P100 to monitor a storage state of the stored data storage chip 11, and then uses a data processing method as described in P200 to read the stored data, which is not described herein again.
It should be clear that the final objective of the read/storage scheme of target data referred to in the present application is to maximize the target data storage speed and/or to maximize the target data read speed.
Another aspect of the present disclosure provides a non-transitory memory chip comprising processing circuitry storing at least one set of executable instructions for performing signal processing. When executed by processing circuitry, the executable instructions direct the processor to perform the steps of the data processing methods P100 and P200 described herein. In some possible implementations, aspects of the specification can also be implemented in the form of a program product including program code. The program code means for causing the memory module 3 to carry out the steps of the data processing methods P100 and P200 described in the present description when said program product is run on a computer device. The program product for implementing the above method may employ a portable compact disc read only memory (CD-ROM) comprising program code and may run on a computer device. However, the program product of the present specification is not limited thereto, and in the present specification, the readable storage chip may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system. The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable memory chip. The readable storage chip may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing.
While the basic concepts have been described above, it will be apparent to those skilled in the art that the foregoing detailed disclosure is by way of example only and is not intended to be limiting. Although not explicitly described herein, various modifications, improvements, and adaptations to the present disclosure may occur to one skilled in the art. Such modifications, improvements, and modifications are intended to be suggested within this specification, and therefore, such modifications, improvements, and modifications are intended to be included within the spirit and scope of the exemplary embodiments of the present invention.
Claims (10)
1. The method for monitoring the memory state of the chip is characterized by comprising the following steps of:
The target data is obtained and the data is stored,
Determining the number N of memory chips required for the target data, and
In a target process, determining the number M of available memory chips, and determining a scheduling scheme of the target data on the M available memory chips according to the number N of the required memory chips and the number M of the available memory chips, wherein N, M is a natural number which is more than or equal to 1;
The determining process of the number M of the available memory chips is as follows:
Traversing all L memory chips to obtain Q characteristic parameters X 1、X2……Xj of each memory chip, wherein the characteristic parameters are quantized data of the states of the memory chips monitored by a sensor in a sensing module, and the quantized data comprise the working temperature of each memory chip, whether each memory chip is damaged or not and the current storage speed of each memory chip;
Constructing a multiple linear regression model for the obtained L.times.Q characteristic parameters:
Zi= I= … n, α j is a coefficient;
The Sigmoid transformation of Z i is as follows:
Fi（Zi）=∈（（0,1），i=1…n
presetting a judging threshold A of Fi, wherein A epsilon (0, 1) is judged:
F i（Zi) by F i（Zi) A
F i（Zi) does not pass F i（Zi) < A
Obtaining the number M of all the memory chips with F i（Zi) more than or equal to A;
the target process is a process of storing the target data into a target memory chip.
2. The monitoring method of claim 1, further comprising a scheduling method comprising:
Determining a target total storage space required by executing the target process according to the total data amount of the target data;
determining the number of memory chips which can be called according to the total memory space required;
and determining K initial scheduling schemes according to the required target total storage space and the number of the callable storage chips.
3. The monitoring method according to claim 2, wherein each of the K initial scheduling schemes comprises: at least one available memory chip participating in the target process, and an actual available memory space of the at least one available memory chip participating in the target process.
4. The monitoring method according to claim 3, wherein the K initial allocation schemes all satisfy that storable space of each of the available memory chips is greater than or equal to a total amount of the target data corresponding thereto, and K is an integer greater than or equal to 1; and
Based on the optimization purpose, a first target allocation scheme is determined to be executed from the K initial allocation schemes.
5. The monitoring method according to claim 4, wherein the optimization purpose includes:
The target data storage speed is maximized and/or the target data reading speed is maximized.
6. The method according to claim 5, wherein if the number N of memory chips is greater than the number M of available memory chips, the number of memory chips eventually used is M, and if the number N of memory chips is less than or equal to the number M of available memory chips, the number of memory chips eventually used is N.
7. The monitoring method according to claim 1, wherein the characteristic parameters include: the method comprises the steps of remaining storage space of the storage chip, data transmission speed of the storage chip and working state of the storage chip.
8. The method according to claim 7, wherein the operating state of the memory chip includes at least: the working temperature and the working humidity of the memory chip.
9. The method of claim 8, wherein the operating state of the memory chip is obtained by a temperature sensor and a humidity sensor.
10. A monitoring system for a memory state of a chip, comprising:
the first memory chip is used for storing at least one group of instruction sets, wherein the at least one group of instruction sets are used for performing memory scheduling in the process of storing target data into a target of the target memory chip; and
The processing circuit is in communication connection with the first memory chip and the target memory chip;
Wherein, when the data processing apparatus is running, the processing circuitry executes the at least one set of instructions:
The target data is obtained and the data is stored,
Determining the number N of memory chips required for the target data, and
In the target process, determining the number M of available memory chips in a target memory chip, and determining a scheduling scheme of the target data on the M available memory chips according to the number N of the required memory chips and the number M of the available memory chips, wherein N, M is a natural number which is more than or equal to 1;
The determining process of the number M of the available memory chips is as follows:
Traversing all L memory chips to obtain Q characteristic parameters X 1、X2……Xj of each memory chip, wherein the characteristic parameters are quantized data of the states of the memory chips monitored by a sensor in a sensing module, and the quantized data comprise the working temperature of each memory chip, whether each memory chip is damaged or not and the current storage speed of each memory chip;
Constructing a multiple linear regression model for the obtained L.times.Q characteristic parameters:
Zi= I= … n, α j is a coefficient;
The Sigmoid transformation of Z i is as follows:
Fi（Zi）=∈（（0,1），i=1…n
presetting a judging threshold A of Fi, wherein A epsilon (0, 1) is judged:
F i（Zi) by F i（Zi) A
F i（Zi) does not pass F i（Zi) < A
Obtaining the number M of all the memory chips with F i（Zi) more than or equal to A;
The target process is a process of storing the target data into the target memory chip.
Priority Applications (1)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2020186455A1 (en) * | 2019-03-19 | 2020-09-24 | 华为技术有限公司 | Data storage method and storage chip |
| WO2022052704A1 (en) * | 2020-09-10 | 2022-03-17 | 哲库科技(北京)有限公司 | Task scheduling method and device, chip, terminal and storage medium |
| WO2023035113A1 (en) * | 2021-09-07 | 2023-03-16 | 华为技术有限公司 | Control method and apparatus for storage apparatus |
| WO2023035664A1 (en) * | 2021-09-10 | 2023-03-16 | 中兴通讯股份有限公司 | Resource allocation method, cloud host, and computer-readable storage medium |
| WO2023137845A1 (en) * | 2022-01-19 | 2023-07-27 | 长鑫存储技术有限公司 | Test method and apparatus for storage chip, and storage medium and electronic device |
| WO2023159568A1 (en) * | 2022-02-28 | 2023-08-31 | 华为技术有限公司 | Task scheduling method, npu, chip, electronic device and readable medium |
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| US20200218599A1 (en) * | 2019-01-09 | 2020-07-09 | Hewlett Packard Enterprise Development Lp | Methods and systems for smart memory data integrity checking |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2020186455A1 (en) * | 2019-03-19 | 2020-09-24 | 华为技术有限公司 | Data storage method and storage chip |
| WO2022052704A1 (en) * | 2020-09-10 | 2022-03-17 | 哲库科技(北京)有限公司 | Task scheduling method and device, chip, terminal and storage medium |
| WO2023035113A1 (en) * | 2021-09-07 | 2023-03-16 | 华为技术有限公司 | Control method and apparatus for storage apparatus |
| WO2023035664A1 (en) * | 2021-09-10 | 2023-03-16 | 中兴通讯股份有限公司 | Resource allocation method, cloud host, and computer-readable storage medium |
| WO2023137845A1 (en) * | 2022-01-19 | 2023-07-27 | 长鑫存储技术有限公司 | Test method and apparatus for storage chip, and storage medium and electronic device |
| WO2023159568A1 (en) * | 2022-02-28 | 2023-08-31 | 华为技术有限公司 | Task scheduling method, npu, chip, electronic device and readable medium |
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