WO2020182126A1 - 显示基板及终端 - Google Patents

显示基板及终端 Download PDF

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Publication number
WO2020182126A1
WO2020182126A1 PCT/CN2020/078622 CN2020078622W WO2020182126A1 WO 2020182126 A1 WO2020182126 A1 WO 2020182126A1 CN 2020078622 W CN2020078622 W CN 2020078622W WO 2020182126 A1 WO2020182126 A1 WO 2020182126A1
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WO
WIPO (PCT)
Prior art keywords
notch
cut
source
display module
box test
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Application number
PCT/CN2020/078622
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English (en)
French (fr)
Inventor
王跃林
徐敬义
任艳伟
刘铁男
韩帅
郭智昂
张慧杰
窦艳秋
智国磊
刘鹏
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Publication of WO2020182126A1 publication Critical patent/WO2020182126A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present disclosure relates to but is not limited to the field of display technology, and in particular to a display substrate and a terminal.
  • notch displays also known as notch displays
  • the cutout is generally located above the display screen, and the cutout area of the display screen has uneven display brightness, which is called the Mura effect.
  • the embodiments of the present disclosure provide a display substrate, including: a base substrate, a plurality of box test CT circuits located on the base substrate, a plurality of source switches, and a plurality of source traces; wherein,
  • a notch to be cut is provided on one side of the base substrate, and the CT circuit is arranged on the base substrate near the area where the notch to be cut is located, and is used to output test signals for box testing;
  • the source switch is configured to turn on or off each source trace for box testing.
  • the display module includes: an integrated circuit for driving a display, wherein the CT circuit and the integrated circuit are located on opposite sides of the base substrate.
  • the multiple source switches include a first part and a second part, the first part of the source switch is distributed below the cutting line of the notch to be cut, and the second part of the source switch is distributed on the to-be-cut notch. Cut both sides of the notch.
  • the first part of the source switch is arranged around the cutting line of the notch to be cut and is located outside the notch to be cut, and the second part of the source switch is along a line parallel to the base substrate where the notch to be cut is located. The direction of the side is lined up.
  • each source switch is used to: during the box test phase, turn on the corresponding source trace to transmit the test signal from the CT circuit; during the CT non-test phase, disconnect the corresponding source trace Wire, so that the corresponding source trace that transmits the test signal is in a floating state.
  • each source switch includes: a first thin film transistor TFT, and a first electrode of the first TFT is connected to a corresponding source wiring.
  • the multiple CT circuits are distributed above the dividing line.
  • the multiple CT circuits are arranged in a row, and the arrangement direction of the multiple CT circuits is parallel to the side of the base substrate where the notch to be cut is located.
  • the CT circuit includes a plurality of second TFTs, and the first pole of each second TFT is connected to the second pole of the corresponding first TFT.
  • the cutting line of the notch to be cut is U-shaped, arc-shaped, V-shaped, or drop-shaped.
  • the CT circuit located in the area of the notch to be cut and the notch to be cut are cut along the cutting line together.
  • the plurality of CT circuits and the plurality of source switches have the same number and have a one-to-one correspondence.
  • An embodiment of the present disclosure also provides a terminal, including: a display screen including a display module; wherein, the display module is the display module described in any of the above embodiments and cuts the to-be-cut along the cutting line.
  • the display module formed after notch.
  • Figure 1 is a schematic diagram of the composition of a display substrate in the related art
  • FIG. 2 is a structural block diagram of a display substrate according to an embodiment of the disclosure.
  • FIG. 3 is a schematic diagram showing the distribution of substrate dividing lines according to an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of a display substrate according to another embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of a terminal provided by an embodiment of the disclosure.
  • the display screen includes a plurality of gate lines and a plurality of source lines, the plurality of gate lines and the plurality of source lines define a plurality of pixels, and each gate line and source line is used to control the corresponding pixel to emit light.
  • gate-source capacitance is generated, and the larger the overlapping area, the larger the gate-source capacitance.
  • notch display there are fewer pixel units in each column of the notch area than in other display areas, so the overlap area of gate-source signal lines in the notch area is smaller than that of other display areas.
  • the area, and the gate-source capacitance of the cut-out area is smaller than that of other display areas, resulting in uneven display brightness of the cut-out display screen and the Mura effect. Therefore, it is necessary to compensate the gate-source capacitance in the cut area and communicate with the gate lines on the left and right sides of the cut.
  • FIG. 1 is a schematic diagram of the composition of the display substrate in the related art. As shown in Figure 1, the CT circuit is connected with the box test positive drive (CTD-ODD), the box test negative drive (CTD-EVEN) and the box test switch (CTSW); During the production process of the substrate, the color film (CF) surface (along the CF boundary) cutting, single-layer area wiping and cleaning, etc. all have the risk of electrostatic discharge (ESD) damage to the CT circuit, causing the display to appear dark lines and other defects problem.
  • CCD-ODD box test positive drive
  • CCD-EVEN box test negative drive
  • CTSW box test switch
  • Fig. 2 is a structural block diagram of a display module according to an embodiment of the disclosure, and the display substrate is used to make a cut-out display screen. As shown in Figure 2, it includes: multiple box test (CT) circuits 1 and multiple source switches 2 and multiple source traces; among them,
  • CT box test
  • the CT circuit 1 is arranged in the notch area of the concave groove of the notch to be cut, and is used to output a test signal for box test;
  • Source switch 2 is used to: turn on or disconnect each source trace used for box testing.
  • the display module includes: an integrated circuit (IC) for driving a display, wherein the CT circuit 1 and the integrated circuit 3 are located on opposite sides of the base substrate.
  • the CT circuit 1 is located on the side of the base substrate close to the notch
  • the integrated circuit 3 is located on the side of the base substrate far away from the notch, that is, on the color filter (CF) substrate. outer.
  • the display module in the area where the notch is located includes an array substrate and a color filter substrate.
  • the base substrate of the array substrate and the color filter substrate is generally made of glass, so the display module in the area where the notch is located has double glass;
  • the display module in the area where the integrated circuit 3 is located does not include the color filter substrate, but only includes the array substrate, and has a single layer of glass.
  • the CT circuit in the related art is located in the area where the integrated circuit on the base substrate is located, that is, on the single-layer glass.
  • the coating and bonding process of the single-layer glass area is likely to cause ESD damage to the CT unit and cause dark line defects.
  • the CT circuit is located on the side of the base substrate close to the notch, and the CT circuit is located on the double-layer glass.
  • the risk of ESD caused by the manufacturing process is small, and the generation of module manufacturing processes such as cutting and bonding can be reduced. ESD damages the risk of dark lines in the CT unit.
  • Figures 2-4 illustrate the boundary of the color filter (CF) substrate. Above the CF boundary is the display area, and below the CF boundary is the non-display area. Figures 2-4 only illustrate the position of the CF boundary, and do not limit the specific ratio of the display area to the non-display area. In actual production, the non-display area where the integrated circuit is located is generally made as small as possible.
  • CF color filter
  • the source switch 2 of the embodiment of the present disclosure includes: a first part 2-1 and a second part 2-2, the second part 2-1 of the source switch is distributed on the left and right sides of the notch to be cut, so The first part 2-2 of the source switch is distributed below the cutting line of the notch to be cut.
  • the cutting line of the notch to be cut is the dashed line shown in FIG. 2.
  • the second part 2-1 of the source switch is arranged in a row along a direction parallel to the side of the base substrate where the notch to be cut is located, that is, in a straight line along the horizontal direction.
  • the first part 2-1 of the source switch is arranged under the metal line near the IC side.
  • the first part 2-1 of the source switch is arranged around the cutting line of the notch to be cut and is located outside the notch to be cut.
  • circuit distribution of the source switches in the embodiments of the present disclosure can be determined by those skilled in the art according to the circuit distribution.
  • the distance between the first part of the source switch and the metal line and the distance between the second part and the dividing line can be analyzed and set with reference to the relevant principles of circuit board design.
  • the source switch 2 of the embodiment of the present disclosure is specifically used for:
  • the corresponding source trace is disconnected, so that the corresponding source trace transmitting the test signal is in a floating state.
  • disconnecting the source wiring for inputting CT circuit signals may include: during box test, the source switch outputs a high level and controls all switches to be in an open state. At this time, the output of the CT circuit The test signal is transmitted to each Source trace; after the box test, the source switch outputs low level, and all source switches are controlled to be off. Each Source trace is in a floating state, and the display module displays normally; among them, the box
  • the time after the test can include: After the CT circuit is ground or cut with the notch to be cut, the source switch (SW-Source) is in the off state and the source traces are in a floating state, so the risk of ESD introduced through the metal wire can be avoided , Reliability is risk-free.
  • the source switch 2 of the embodiment of the present disclosure includes: a thin film transistor (TFT) switch.
  • TFT thin film transistor
  • the gate of the TFT is connected to a metal wire
  • the first pole is connected to the corresponding source wiring
  • the second stage is connected to the corresponding CT circuit.
  • all the CT circuits 1 in the embodiment of the present disclosure are distributed above the dividing line.
  • the CT circuits 1 described in the embodiments of the present disclosure are all arranged in a straight line along the horizontal direction, and the arrangement direction of the plurality of CT circuits 1 is parallel to the side of the base substrate where the notch to be cut is located.
  • CT circuit in the embodiment of the present disclosure is arranged above the dividing line in a straight line, avoiding the impact on the capacitance compensation of the concave groove position and the gate wiring arrangement, and will not cause notch (notch). ) The border of the area increases.
  • the plurality of CT circuits include a plurality of thin film transistors TFT, and the gates of the plurality of TFTs are connected to the same driving line.
  • the CT circuit also includes: box test positive drive (CTD-ODD), box test negative drive (CTD-EVEN), used to test the uniformity of the pixel display before assembling the array substrate and the color film substrate into a box .
  • CCD-ODD box test positive drive
  • CCD-EVEN box test negative drive
  • the number of the multiple CT circuits and the multiple source switches are the same and have a one-to-one correspondence.
  • the second pole of each source switch 2 is connected to the first pole of the TFT of the corresponding CT circuit, for transmitting the signal in the source line to the CT circuit.
  • the cutting line of the notch to be cut is U-shaped, arc-shaped, V-shaped, or drop-shaped.
  • the display module after cutting or grinding along the cutting line has a notch, which can form a notch display screen.
  • the shape and size of the notch can be comprehensively designed according to the actual situation, market demand, aesthetics, and functionality, and the present disclosure is not limited thereto.
  • FIG. 3 is a schematic diagram showing the distribution of the dividing line of the substrate according to the embodiment of the present disclosure.
  • the display substrate includes: Test positive drive (CTD-ODD), box test negative drive (CTD-EVEN), and line pixel switches of the display screen (red (R) green (G) blue (B) pixel switches in the figure), the dotted line in the figure Is the position of the dividing line.
  • the CT circuits in the embodiments of the present disclosure are all distributed above the dividing line, which may include: the CT circuit at the notch position is arranged at the upper position of the dividing line, and the distance from the dividing line can be determined by analysis by those skilled in the art;
  • the CT circuits on both sides of the notch are arranged on the side of the metal line close to the integrated circuit, parallel to the metal line (row pixel connection line), and the distance to the metal line can be determined by analysis by those skilled in the art.
  • the source (Source) trace of the grinding position is flush with the cutting boundary, electrostatic discharge (ESD) is easily generated through the source trace, and high and low voltages or electrochemical corrosion occur during the reliability process.
  • FIG. 4 is a schematic diagram of a display substrate according to another embodiment of the present disclosure. As shown in FIG. 4, after grinding or laser cutting along the dividing line, the CT circuit showing the position of the notch in the substrate is removed.
  • TFT thin film transistor
  • the CT circuit is designed on the opposite side of the IC, and the CT circuit at the position of the notch to be cut can be linearly designed. After the box test, the CT circuit at the position of the notch to be cut is ground away with the notch. Considering factors such as ESD and wiring corrosion, the embodiment of the present disclosure adds a TFT switch design in the CT circuit position, so that the source wiring of the CT circuit is ground in a floating state, which avoids ESD and wiring corrosion. Dark line risk, which improves the dark line defect caused by CT circuit damage caused by ESD.
  • the multiple CT circuits are arranged around the notch to be cut, but in the embodiment of the present disclosure, the multiple CT circuits are arranged in a straight line at the position of the notch to be cut.
  • the CT circuit at the slot position has been reduced from "5 wire 1 switch” to "1 wire 1 switch". That is, in the embodiment of the present disclosure, all the CT circuits at the notch position are controlled and driven by only one metal wire, while in the related art, all the CT circuits at the notch position are arranged along the cutting line, which is generally controlled by 5 metal wires. TFT is driven, so the embodiment of the present disclosure saves the space of 4 wires.
  • a source switch is added to the Source trace to achieve dual protection of the Source trace.
  • the technical solution of the present application includes: multiple box test CT circuits and source switches; wherein the CT circuit is arranged in a notch area close to the concave groove for outputting test signals for box testing ;
  • the source switch is used to: turn on or disconnect each source trace used for box testing.
  • the embodiments of the present disclosure avoid the risk of dark lines caused by electrostatic discharge (ESD) and line corrosion, and improve the dark line defects caused by CT circuit damage caused by ESD.
  • the embodiment of the present disclosure also provides a terminal.
  • the terminal includes: a display screen 20 and a notch 10.
  • the display screen 20 includes the display module formed by cutting the notch to be cut along the cutting line of the display module described in the above embodiment.
  • the display module before cutting includes:
  • a plurality of CT circuits arranged in the notch area of the concave groove for outputting test signals for box testing;
  • Multiple source switches are used to turn on or off each source trace used for box testing to transmit test signals from the CT circuit.
  • the notch 10 is U-shaped, arc-shaped, V-shaped, or drop-shaped.
  • the notch 10 is generally located directly above the display screen, and different shapes, sizes and positions can be set according to actual needs.
  • the display module includes: an integrated circuit (IC) for driving a display, wherein the CT circuit 1 and the integrated circuit 3 are located on opposite sides of the base substrate.
  • IC integrated circuit
  • the source switch of the embodiment of the present disclosure includes:
  • the first part arranged below the metal wire on the side close to the IC, and the second part arranged below the dividing line of the concave groove.
  • circuit distribution of the source switches in the embodiments of the present disclosure can be determined by those skilled in the art according to the circuit distribution.
  • the distance between the first part of the source switch and the metal line and the distance between the second part and the dividing line can be analyzed and set with reference to the relevant principles of circuit board design.
  • the source switch described in the embodiment of the present disclosure is specifically used for:
  • each of the source wires is disconnected, so that each of the source wires that transmit the test signal is in a floating state.
  • disconnecting the source wiring for inputting CT circuit signals may include: during box test, the source switch outputs a high level and controls all switches to be in an open state. At this time, the output of the CT circuit The test signal is transmitted to each Source trace; after the box test, the source switch outputs a low level to control all switches to be closed, and each Source trace is in a floating state, indicating that the substrate is displayed normally; among them, the The time can include: when the display substrate is lit, since the SW-Source is closed due to the metal wiring, the introduction of ESD risk can be avoided, and the reliability is not risky.
  • the source switch in the embodiment of the present disclosure includes: a thin film transistor (TFT) switch.
  • TFT thin film transistor
  • all the CT circuits in the embodiments of the present disclosure are arranged above the dividing line in a straight line; or,
  • the CT circuits described in the embodiments of the present disclosure are all arranged above the dividing line. It should be noted that the CT circuit in the embodiment of the present disclosure is arranged above the dividing line in a straight line, so as to avoid affecting the capacitance compensation at the position of the concave groove (U groove) and the wiring arrangement of the gate (Gate). The border of the notch area increases.
  • the CT circuit is designed on the side of the display screen opposite to the IC.
  • the CT circuit at the position of the notch to be cut can be linearly designed. After the box test, the CT circuit at the position of the notch to be cut is ground away with the notch.
  • the embodiment of the present disclosure adds a TFT switch design in the CT circuit position, so that the source wiring of the CT circuit is ground in a floating state, which avoids ESD and wiring corrosion. Dark line risk, which improves the dark line defect caused by CT circuit damage caused by ESD.
  • the multiple CT circuits are arranged around the notch to be cut, but in the embodiment of the present disclosure, the multiple CT circuits are arranged in a straight line at the position of the notch to be cut.
  • the CT circuit at the slot position has been reduced from "5 wire 1 switch” to "1 wire 1 switch". That is, in the embodiment of the present disclosure, all the CT circuits at the notch position are controlled and driven by only one metal wire, while in the related art, all the CT circuits at the notch position are arranged along the cutting line, which is generally controlled by 5 metal wires. Therefore, the embodiment of the present disclosure saves the space of 4 wires.
  • a source switch is added to the Source trace to achieve dual protection of the Source trace.
  • the technical solution of the present application includes: multiple box test CT circuits and source switches; wherein the CT circuit is arranged in the notch area of the concave groove for: outputting test signals for box testing ;
  • the source switch is used to: turn on or disconnect the source traces used for box testing to transmit the test signal from the CT circuit.
  • the embodiments of the present disclosure avoid the risk of dark lines caused by electrostatic discharge (ESD) and line corrosion, and improve the dark line defects caused by CT circuit damage caused by ESD.
  • a program instructing relevant hardware such as a processor
  • the program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk, or an optical disk. Wait.
  • all or part of the steps of the foregoing embodiments may also be implemented by using one or more integrated circuits.
  • each module/unit in the above-mentioned embodiment can be implemented in the form of hardware, for example, an integrated circuit to achieve its corresponding function, or it can be implemented in the form of a software function module, for example, the processor executes the stored in the memory. Program/instruction to realize its corresponding function.
  • the present disclosure is not limited to the combination of any specific form of hardware and software.

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Abstract

一种显示模组和终端，显示模组包括：衬底基板、位于衬底基板上的多个盒测试电路（1）、多个源极开关（2）和多个源极走线；其中，衬底基板的一侧设置有待切割槽口，盒测试电路（1）设置于衬底基板上靠近待切割槽口所在区域，用于输出进行盒测试的测试信号；源极开关（2）被配置为导通或断开用于盒测试的各源极走线。

Description

显示基板及终端
相关申请的交叉引用
本申请主张在2019年3月14日在中国提交的中国专利申请No.201910192213.1的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板及终端。
背景技术
随着全面屏的发展，切口显示屏(又称为异型显示屏，notch display)被广泛应用于电子设备，目前主要包括“齐刘海(straight bangs shaped notch)”和“水滴角(waterdrop shaped notch)”等显示屏设计。切口一般位于显示屏的上方，显示屏的切口区域存在显示亮度不均匀情况，被称为Mura效应。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板，包括：衬底基板、位于衬底基板上的多个盒测试CT电路、多个源极开关和多个源极走线；其中，
所述衬底基板的一侧设置有待切割槽口notch，所述CT电路设置于衬底基板上靠近待切割notch所在区域，用于输出进行盒测试的测试信号；
所述源极开关被配置为导通或断开用于盒测试的各源极走线。
可选地，所述显示模组包括：用于驱动显示的集成电路，其中，所述CT电路和所述集成电路位于所述衬底基板的对侧。
可选地，所述多个源极开关包括第一部分和第二部分，所述源极开关的第一部分分布于待切割notch的切割线的下方，所述源极开关的第二部分分布于待切割notch的两侧。
可选地，所述源极开关的第一部分围绕待切割notch的切割线设置且位 于待切割notch的外侧，所述源极开关的第二部分沿着平行于待切割notch所在的衬底基板的侧边的方向排成一行。
可选地，每个源极开关用于：在盒测试阶段，导通相应的源极走线，以传输来自所述CT电路的测试信号；在CT非测试阶段，断开相应的源极走线，以使传输所述测试信号的相应的源极走线处于悬空状态。
可选地，每个源极开关包括：第一薄膜晶体管TFT，所述第一TFT的第一极连接相应的源极走线。
可选地，所述多个CT电路分布于分割线上方。
可选地，所述多个CT电路排成一行，且所述多个CT电路的排列方向平行于待切割notch所在的衬底基板的侧边。
可选地，所述CT电路包括多个第二TFT，每个第二TFT的第一极连接相应的第一TFT的第二极。
可选地，所述待切割notch的切割线为U型、圆弧形、V型、或水滴型。
可选地，位于待切割notch区域中的CT电路和待切割notch一同沿着所述切割线被切割掉。
可选地，所述多个CT电路与所述多个源极开关的数量相同，且具有一一对应关系。
本公开实施例还提供了一种终端，包括：包含显示模组的显示屏；其中，所述显示模组是以上任一实施例所述的显示模组沿着切割线切掉所述待切割notch后形成的显示模组。
本公开的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开而了解。本公开的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例或相关技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中显示基板的组成示意图；
图2为本公开实施例显示基板的结构框图；
图3为本公开实施例显示基板分割线的分布示意图；
图4为本公开另一实施例显示基板的示意图；
图5为本公开实施例提供的一种终端的示意图；
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行。并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
显示屏包括多个栅极线和多个源极线，多个栅极线和多个源极线限定出多个像素，每个栅极线和源极线用于控制相应的像素发光。在栅极线和源极线的交叠区域，有栅源电容产生，并且交叠的面积越大，栅源电容越大。在切口显示屏(notch display)中，切口区域每列的像素单元比其他显示区域每列的像素单元少，所以切口区域的栅源信号线交叠面积小于其他显示区域的栅源信号线交叠面积，进而切口区域的栅源电容小于其他显示区域的栅源电容，导致切口显示屏的显示亮度不均匀，出现Mura效应。因此，需要对切口区域的栅源电容进行补偿，和切口左右两侧的栅极线连通。
由于切口区域没有足够的空间排布盒测试(Cell Test，CT)单元，切口显示屏的CT电路一般设计在显示屏的集成电路(IC)所在区域，即盒(Cell)的单层区。图1为相关技术中显示基板的组成示意图，如图1所示，CT电路与盒测试正驱动(CTD-ODD)、盒测试负驱动(CTD-EVEN)及盒测试开关(CTSW)连接；显示基板在制作过程中，彩膜(CF)面(沿CF边界)切割、单层区擦拭清洁等工序均存在静电释放(electrostatic discharge,ESD)击伤CT电路的风险，使显示屏出现暗线等不良问题。
图2为本公开实施例显示模组的结构框图，所述显示基板用于制作切口 显示屏。如图2所示，包括：多个盒测试(CT)电路1和多个源极开关2和多个源极走线；其中，
CT电路1设置于待切割槽口的凹形槽的槽口(notch)区域，用于输出进行盒测试的测试信号；
源极开关2用于：导通或断开用于盒测试的各源极走线。
可选地，所述显示模组包括：用于驱动显示的集成电路(IC)，其中，所述CT电路1和所述集成电路3位于所述衬底基板的对侧。如图2所示，所述CT电路1位于衬底基板上靠近notch的一侧，所述集成电路3位于衬底基板上远离notch的一侧，即位于彩膜(color filter,CF)基板之外。
可选地，notch所在区域的显示模组包括阵列基板和彩膜基板，阵列基板和彩膜基板的衬底基板一般由玻璃制成，故notch所在区域的显示模组具有双层玻璃；所述集成电路3所在区域的显示模组不包括彩膜基板，仅包括阵列基板，具有单层玻璃。
可以理解，相关技术中的CT电路位于衬底基板上集成电路所在区域，即位于单层玻璃上，单层玻璃区涂胶、Bonding工艺，易造成ESD击伤CT单元，造成暗线不良。而本公开实施例中，所述CT电路位于衬底基板上靠近notch的一侧，CT电路位于双层玻璃上，受制程产生的ESD风险较小，可以降低因切割、Bonding等模组制程产生ESD击伤CT单元出现暗线的风险。
图2-4示意了彩膜(CF)基板的边界，CF边界以上为显示区，CF边界以下为非显示区。图2-4仅示意了CF边界的位置，并不限定具体的显示区和非显示区的比例。在实际生产中，集成电路所在非显示区一般会做的尽可能小。
可选地，本公开实施例源极开关2包括：第一部分2-1和第二部分2-2，所述源极开关的第二部分2-1分布于待切割notch的左右两侧，所述源极开关的第一部分2-2分布于待切割notch的切割线的下方，。所述待切割notch的切割线为图2所示的虚线。
可选地，所述源极开关的第二部分2-1沿着平行于待切割notch所在的衬底基板的侧边的方向排成一行，即，沿着水平方向呈直线排列。如图2所示，述源极开关的第一部分2-1设置于靠近IC一侧的金属线下方。所述源极开关 的第一部分2-1围绕待切割notch的切割线设置且位于待切割notch的外侧。
需要说明的是，本公开实施例源极开关的电路分布，可以由本领域技术人员根据线路分布进行确定。源极开关第一部分与金属线的距离，和第二部分与分割线的距离可以参照电路板设计相关原理进行分析设定。
可选地，本公开实施例源极开关2具体用于：
在盒测试阶段，导通相应的源极走线，以传输来自所述CT电路的测试信号；
在CT非测试阶段，断开相应的源极走线，以使传输所述测试信号的相应的源极走线处于悬空状态。
需要说明的是，本公开实施例断开用于输入CT电路信号的源极走线可以包括：盒测试时，源极开关输出高电平，控制所有开关为打开状态，此时CT电路输出的测试信号传输到各Source走线；盒测试后，源极开关输出低电平，控制所有源极开关为关闭状态，各Source走线处于悬空(Floating)状态，显示模组正常显示；其中，盒测试后的时间可以包括：CT电路随待切割notch被研磨掉或切割后，由于源极开关(SW-Source)处于关闭状态，各Source走线处于悬空状态，因此可以避免通过金属导线引入ESD风险，信赖性无风险。
可选地，本公开实施例源极开关2包括：薄膜晶体管(TFT)开关。如图2所示，所述TFT的栅极连接金属线，第一极连接相应的源极走线，第二级连接相应的CT电路。
可选地，本公开实施例所有所述CT电路1分布于分割线上方。
可选地，本公开实施例所述CT电路1均沿着水平方向呈直线排列，所述多个CT电路1的排列方向平行于待切割notch所在的衬底基板的侧边
需要说明的是，本公开实施例CT电路按照直线排布设置于分割线上方，避免对凹形槽位置的电容补偿和栅极(Gate)走线排布造成影响，不会使得槽口(notch)区域的边框增大。
可选地，所述多个CT电路包括多个薄膜晶体管TFT，所述多个TFT的栅极连接于同一驱动线。
如图2所示，CT电路还包括：盒测试正驱动(CTD-ODD)、盒测试负驱 动(CTD-EVEN)，用于在组装阵列基板和彩膜基板成盒之前测试像素显示的均匀性。
可选地，所述多个CT电路与多个源极开关的数量相同，且具有一一对应关系。如图2或3所示，每个源极开关2的第二极连接相应CT电路的TFT的第一极，用于将源极线中的信号传输至CT电路。
可选地，所述待切割notch的切割线为U型、圆弧形、V型、或水滴型。沿着切割线切割或研磨后的显示模组具有notch，可形成切口显示屏。所述notch的形状和大小可根据实际情况、市场需求、美观和功能性等多方面考虑综合设计，本公开并不以此为限。
本公开实施例盒测试后，notch区域的CT电路随玻璃研磨或激光切割沿分割线去除；图3为本公开实施例显示基板分割线的分布示意图，如图3所示，显示基板包含：盒测试正驱动(CTD-ODD)、盒测试负驱动(CTD-EVEN)、和显示屏的行像素开关(图示的红(R)绿(G)蓝(B)像素开关)，图中的虚线是分割线的位置。参见图3，本公开实施例CT电路均分布于所述分割线上方，这可以包括：槽口位置的CT电路设置在分割线往上位置，与分割线的距离可以由本领域技术人员分析确定；槽口两侧的CT电路设置在金属线靠近集成电路一侧，与金属线(行像素连接线)平行，与金属线的距离可以由本领域技术人员分析确定。考虑到研磨位置源极(Source)走线与切割边界平齐，易通过源极走线产生静电释放(ESD)，且信赖性过程出现高低电压或出现电化学腐蚀。在金属线下方增加薄膜晶体管(TFT)开关—源极开关(SW-Source)。盒测试后，由于源极开关(SW-Source)处于关闭状态，各Source走线处于悬空状态，因此可以避免通过金属导线引入ESD风险，信赖性无风险。图4为本公开另一实施例显示基板的示意图，如图4所示，沿分割线研磨或激光切割后，显示基板中槽口位置的CT电路被切除。
本公开实施例将CT电路设计在IC对侧，待切割槽口位置处的CT电路可以为直线设计，盒测试后将待切割槽口位置的CT电路随槽口研磨掉。考虑ESD和走线腐蚀等因素，本公开实施例在CT电路位置增加TFT开关设计，使研磨掉CT电路的源极(Source)走线处于悬空(Floating)状态，避免了ESD和线路腐蚀导致的暗线风险，改善了因ESD造成CT电路击伤而产生 的暗线不良。相关技术中多个CT电路围绕待切割槽口设置，而本公开实施例中多个CT电路在待切割槽口的位置为直线排列。与相关技术相比，槽口位置处的CT电路由“5线1开关”减少至“1线1开关”。即，本公开实施例中的槽口位置处的所有CT电路仅由一条金属线控制驱动即可，而相关技术中槽口位置处的所有CT电路延切割线排列，一般由5条金属线控制TFT驱动，因此本公开实施例节省4根走线的空间。另外，在Source走线处增设源极开关，实现了Source走线双重保护。
与相关技术相比，本申请技术方案包括：多个盒测试CT电路和源极开关；其中，CT电路设置于靠近凹形槽的槽口(notch)区域，用于输出进行盒测试的测试信号；源极开关用于：导通或断开用于盒测试的各源极走线。本公开实施例避免了静电释放(ESD)和线路腐蚀导致的暗线风险，改善了因ESD造成CT电路击伤而产生的暗线不良。
本公开实施例还提供一种终端。如图5所示，所述终端包括：包含显示屏20和槽口notch 10。其中，所述显示屏20包括上述实施例所述的显示模组沿着切割线切掉所述待切割notch后形成的显示模组。所述切割前的显示模组包括：
设置于凹形槽的槽口(notch)区域的多个CT电路，用于输出进行盒测试的测试信号；
多个源极开关，用于导通或断开用于盒测试的各源极走线，以传输来自CT电路的测试信号。
可选地，所述槽口notch 10为U型、圆弧形、V型、或水滴型。所述槽口notch 10一般位于显示屏的正上方，可根据实际需求设置不同的形状、大小和位置。
可选地，所述显示模组包括：用于驱动显示的集成电路(IC)，其中，所述CT电路1和所述集成电路3位于所述衬底基板的对侧。
可选地，本公开实施例源极开关包括：
设置于靠近IC一侧的金属线下方的第一部分，和设置于凹形槽分割线下方的第二部分。
需要说明的是，本公开实施例源极开关的电路分布，可以由本领域技术 人员根据线路分布进行确定。源极开关第一部分与金属线的距离，和第二部分与分割线的距离可以参照电路板设计相关原理进行分析设定。
可选地，本公开实施例所述源极开关具体用于：
盒测试时，导通各所述源极走线，以传输来自所述CT电路的测试信号；
盒测试后，断开各所述源极走线，以使传输所述测试信号的各所述源极走线处于悬空状态。
需要说明的是，本公开实施例断开用于输入CT电路信号的源极走线可以包括：盒测试时，源极开关输出高电平，控制所有开关为打开状态，此时CT电路输出的测试信号传输到各Source走线；盒测试后，源极开关输出低电平，控制所有开关为关闭状态，各Source走线处于悬空(Floating)状态，显示基板正常显示；其中，盒测试后的时间可以包括：显示基板点灯时，由于金属走线由于SW-Source处于关闭状态，因此可以避免引入ESD风险，信赖性无风险。
可选地，本公开实施例所述源极开关包括：薄膜晶体管(TFT)开关。
可选地，本公开实施例所有所述CT电路按照直线排布设置于所述分割线上方；或，
可选地，本公开实施例所述CT电路均排布设置于所述分割线上方。需要说明的是，本公开实施例CT电路按照直线排布设置于分割线上方，避免对凹形槽(U槽)位置的电容补偿和栅极(Gate)走线排布造成影响，不会造成槽口(notch)区域的边框增大。
本公开实施例将CT电路设计在显示屏上与IC相对一侧，待切割槽口位置处的CT电路可以为直线设计，盒测试后将待切割槽口位置的CT电路随槽口研磨掉。考虑ESD和走线腐蚀等因素，本公开实施例在CT电路位置增加TFT开关设计，使研磨掉CT电路的源极(Source)走线处于悬空(Floating)状态，避免了ESD和线路腐蚀导致的暗线风险，改善了因ESD造成CT电路击伤而产生的暗线不良。相关技术中多个CT电路围绕待切割槽口设置，而本公开实施例中多个CT电路在待切割槽口的位置为直线排列。与相关技术相比，槽口位置处的CT电路由“5线1开关”减少至“1线1开关”。即，本公开实施例中的槽口位置处的所有CT电路仅由一条金属线控制驱动即可，而 相关技术中槽口位置处的所有CT电路延切割线排列，一般由5条金属线控制驱动，因此本公开实施例节省4根走线的空间。另外，在Source走线处增设源极开关，实现了Source走线双重保护。
与相关技术相比，本申请技术方案包括：多个盒测试CT电路和源极开关；其中，CT电路设置于凹形槽的槽口(notch)区域，用于：输出进行盒测试的测试信号；源极开关用于：导通或断开用于盒测试的各源极走线，以传输来自CT电路的测试信号。本公开实施例避免了静电释放(ESD)和线路腐蚀导致的暗线风险，改善了因ESD造成CT电路击伤而产生的暗线不良。
本领域普通技术人员可以理解上述方法中的全部或部分步骤可通过程序来指令相关硬件(例如处理器)完成，所述程序可以存储于计算机可读存储介质中，如只读存储器、磁盘或光盘等。可选地，上述实施例的全部或部分步骤也可以使用一个或多个集成电路来实现。相应地，上述实施例中的每个模块/单元可以采用硬件的形式实现，例如通过集成电路来实现其相应功能，也可以采用软件功能模块的形式实现，例如通过处理器执行存储于存储器中的程序/指令来实现其相应功能。本公开不限制于任何特定形式的硬件和软件的结合。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (13)

  1. 一种显示模组，包括：衬底基板、位于衬底基板上的多个盒测试电路、多个源极开关和多个源极走线；其中，
    所述衬底基板的一侧设置有待切割槽口，所述盒测试电路设置于衬底基板上靠近待切割槽口所在区域，用于输出进行盒测试的测试信号；
    所述源极开关被配置为导通或断开用于盒测试的各源极走线。
  2. 根据权利要求1所述的显示模组，包括：用于驱动显示的集成电路，其中，所述盒测试电路和所述集成电路位于所述衬底基板的相对侧。
  3. 根据权利要求1所述的显示模组，其中，所述多个源极开关包括第一部分和第二部分，所述源极开关的第一部分分布于待切割notch的切割线的下方，所述源极开关的第二部分分布于待切割槽口的两侧。
  4. 根据权利要求1所述的显示模组，其中，所述源极开关的第一部分围绕待切割槽口的切割线设置且位于待切割槽口的外侧，
    所述源极开关的第二部分沿着平行于待切割槽口所在的衬底基板的侧边的方向排成一行。
  5. 根据权利要求1至4中的任一项所述的显示模组，其中，每个源极开关被配置为：
    在盒测试阶段，导通相应的源极走线，以传输来自所述盒测试电路的测试信号；
    在非盒测试测试阶段，断开相应的源极走线，以使传输所述测试信号的相应的源极走线处于悬空状态。
  6. 根据权利要求1至4中的任一项所述的显示模组，其中，每个源极开关包括：第一薄膜晶体管TFT，所述第一TFT的第一极连接相应的源极走线。
  7. 根据权利要求1或2所述的显示模组，其中，所述多个盒测试电路分布于分割线上方。
  8. 根据权利要求7所述的显示模组，其中，所述多个盒测试电路排成一行，且所述多个盒测试电路的排列方向平行于待切割槽口所在的衬底基板的侧边。
  9. 根据权利要求6所述的显示模组，其中，所述多个盒测试电路包括多个第二TFT，每个第二TFT的第一极连接相应的第一TFT的第二极。
  10. 根据权利要求1至9中的任一项所述的显示基板，其中，所述待切割槽口的切割线为U型、圆弧形、V型、或水滴型。
  11. 根据权利要求1所述的显示模组，其中，位于待切割槽口区域中的盒测试电路和待切割槽口一同沿着所述切割线被切割掉。
  12. 根据权利要求1所述的显示基板，其中，所述多个盒测试电路与所述多个源极开关的数量相同，且具有一一对应关系。
  13. 一种终端，包括：包括显示模组的显示屏；其中，显示模组如权利要求1至12中任一项所述的显示模组沿着切割线切掉所述待切割槽口后形成的显示模组。
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