WO2020177709A1 - 马达驱动电路及终端设备 - Google Patents
马达驱动电路及终端设备 Download PDFInfo
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- WO2020177709A1 WO2020177709A1 PCT/CN2020/077737 CN2020077737W WO2020177709A1 WO 2020177709 A1 WO2020177709 A1 WO 2020177709A1 CN 2020077737 W CN2020077737 W CN 2020077737W WO 2020177709 A1 WO2020177709 A1 WO 2020177709A1
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- terminal
- transistor
- motor
- gate
- switch delay
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P29/00—Arrangements for regulating or controlling electric motors, appropriate for both AC and DC motors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/292—Modifications for introducing a time delay before switching in thyristor, unijunction transistor or programmable unijunction transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
Definitions
- the present disclosure relates to the field of communication technology, and in particular to a motor drive circuit and terminal equipment.
- terminal equipment With the rapid development of terminal technology, terminal equipment has become an indispensable tool in people's lives, and has brought great convenience to all aspects of users' lives.
- motors on terminal devices in related technologies When the terminal device receives some messages or there is an incoming call, the motor may vibrate to remind the user.
- the coil of the motor will generate induced electromotive force when the motor changes from forward to reverse rotation, or from reverse to forward rotation, and the induced electromotive force cancels part of the electromotive force of the power source, thereby causing the drive power to drive
- the force is relatively small.
- the embodiments of the present disclosure provide a motor drive circuit and a terminal device to solve the problem that the coil of the motor of the terminal device generates an induced electromotive force, which will offset a part of the electromotive force of the power source, resulting in a relatively small driving force of the driving power source.
- embodiments of the present disclosure provide a motor drive circuit, including a motor, a first transistor, a second transistor, a third transistor, and a fourth transistor.
- the first terminal of the motor is connected to the first transistor through the first transistor.
- a power source, and the first terminal of the motor is also grounded through the second transistor, the second terminal of the motor is connected to a second power source through the third transistor, and the second terminal of the motor is also connected to the ground through the second transistor.
- the fourth transistor is grounded, and the motor drive circuit further includes a first switch delay module and a second switch delay module, wherein:
- the first terminal of the first switch delay module is connected to the first terminal of the motor, the second terminal of the first switch delay module is grounded, and the first terminal of the second switch delay module is connected to the first terminal of the motor.
- the second terminal of the motor is connected, and the second terminal of the second switch delay module is grounded. If the first terminal of the motor is at the first voltage, the second terminal of the motor is at the second voltage, and the The first transistor, the second transistor, the third transistor, and the fourth transistor are all in an off state, the first switch delay module is turned on for a first specific period of time, and the second switch delays The module is turned on for a second specific duration;
- the first voltage at the first terminal and the second voltage at the second terminal of the motor are both voltages generated by induced electromotive force, and the first voltage is smaller than the second voltage.
- embodiments of the present disclosure also provide a terminal device, including the above-mentioned motor drive circuit.
- a motor drive circuit includes a motor, a first transistor, a second transistor, a third transistor, and a fourth transistor.
- the first terminal of the motor is connected to the first transistor through the first transistor.
- a power source, and the first terminal of the motor is also grounded through the second transistor, the second terminal of the motor is connected to a second power source through the third transistor, and the second terminal of the motor is also connected to the ground through the second transistor.
- the fourth transistor is grounded, and the motor drive circuit further includes a first switch delay module and a second switch delay module, wherein: the first end of the first switch delay module is connected to the first end of the motor, The second terminal of the first switch delay module is grounded, the first terminal of the second switch delay module is connected to the second terminal of the motor, and the second terminal of the second switch delay module is grounded, If the first terminal of the motor is the first voltage, the second terminal of the motor is the second voltage, and the first transistor, the second transistor, the third transistor, and the fourth transistor are all Is in the off state, the first switch delay module is turned on for a first specific time period, and the second switch delay module is turned on for a second specific time period; wherein, the first voltage at the first end of the motor The second voltage at and the second terminal are both voltages generated by induced electromotive force, and the first voltage is less than the second voltage. In this way, the induced electromotive force generated by the motor has a closed loop, which can be used for self-discharge, thereby
- Figure 1 is one of the structural diagrams of a motor drive circuit provided by an embodiment of the present disclosure
- FIG. 3 is the third structural diagram of the motor drive circuit provided by the embodiment of the present disclosure.
- FIG. 4 is a structural diagram of a first switch delay unit provided by an embodiment of the present disclosure.
- FIG. 5 is the fourth structural diagram of the motor drive circuit provided by the embodiment of the present disclosure.
- FIG. 1 is a structural diagram of a motor drive circuit provided by an embodiment of the present disclosure. As shown in FIG. 1, it includes a motor M, a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4.
- the first terminal of the motor M is connected to the first power supply V1 through the first transistor, and the first terminal of the motor M is also grounded through the second transistor Q2, and the second terminal of the motor M is connected to the ground through the second transistor Q2.
- the third transistor Q3 is connected to the second power supply V2, and the second end of the motor M is also grounded through the fourth transistor Q4.
- the motor drive circuit further includes a first switch delay module 1 and a second switch delay module 2.
- the first end of the first switch delay module 1 is connected to the first end of the motor M, the second end of the first switch delay module 1 is grounded, and the second switch delay
- the first terminal of the module 2 is connected to the second terminal of the motor M, and the second terminal of the second switch delay module 2 is grounded.
- the motor M If the first terminal of the motor M is at the first voltage, the motor M The second terminal of is the second voltage, and the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all in the off state, the first switch is delayed
- the module 1 is turned on for a first specific time period, and the second switch delay module 2 is turned on for a second specific time period; wherein, the first voltage at the first terminal of the motor M and the second voltage at the second terminal Both are voltages generated by induced electromotive force, and the first voltage is less than the second voltage.
- the first transistor Q1, the second transistor Q2, the third transistor Q3, or the fourth transistor Q4 may be an N-channel Metal Oxide Semiconductor (NMOS) tube, or may also be It is a P-channel metal oxide semiconductor (P-channel Metal Oxide Semiconductor, PMOS) tube, which transistor can be selected according to actual needs.
- NMOS N-channel Metal Oxide Semiconductor
- PMOS P-channel Metal Oxide Semiconductor
- first power supply V1 and second power supply V2 may be the same or different.
- first specific duration and second specific duration may optionally be equal, but the first specific duration may be slightly larger or slightly smaller than the second specific duration.
- the first switch delay module 1 is turned on for a first specific time period
- the second switch delay module 2 is turned on for a second specific time period.
- the motor drive circuit further includes a third switch delay module 3 and a fourth switch delay module 4, wherein:
- the first terminal of the third switch delay module 3 is connected to the first terminal of the motor M, the second terminal of the third switch delay module 3 is grounded, and the first terminal of the fourth switch delay module 4 is grounded.
- One end is connected to the second end of the motor M, and the second end of the fourth switch delay module 4 is grounded. If the first end of the motor M is at the third voltage, the second end of the motor is The fourth voltage, and the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all in the off state, the third switch delay module 3 is turned on Three specific durations, and the fourth switch delay module 4 is turned on for a fourth specific duration;
- the third voltage at the first terminal and the fourth voltage at the second terminal of the motor M are both voltages generated by induced electromotive force, and the third voltage is greater than the fourth voltage.
- the third specific duration and the fourth specific duration can be selected to be equal, but the third specific duration may be slightly larger or slightly smaller than the fourth specific duration.
- FIG. 2 is a structure diagram of a motor drive circuit provided by an embodiment of the disclosure.
- the first end of the third switch delay module 3 is connected to the first end of the motor M, the second end of the third switch delay module 3 is grounded, and the fourth switch The first end of the delay module 4 is connected to the second end of the motor M, and the second end of the fourth switch delay module 4 is grounded.
- the first switch delay module 1 is turned on for a first specific time period
- the second switch delay module 2 is turned on for a second specific time period.
- the third switch delay module 3 is turned on for a third specific time period
- the fourth switch delay module 4 is turned on for a fourth specific time period.
- the induced electromotive force generated by the motor M can be closed loop. Therefore, it is possible to self-discharge the induced electromotive force generated during different state changes of the motor according to different closed loops, and eliminate the induced electromotive force. Since there is no induced electromotive force, the power source electromotive force will not be offset by the induced electromotive force, thereby increasing the driving force of the driving power source.
- the first transistor Q1 is a first NMOS tube
- the second transistor Q2 is a second NMOS tube
- the third transistor Q3 is a third NMOS tube
- the fourth transistor Q4 is a fourth NMOS tube. tube;
- the drain of the first NMOS transistor is connected to the first power supply V1, the source of the first NMOS transistor is connected to the first end of the motor M; the source of the second NMOS transistor is grounded, so The drain of the second NMOS transistor is connected to the first end of the motor M; the source of the third NMOS transistor is connected to the second end of the motor M; the drain of the third NMOS transistor is connected to the The second power supply V2 is connected; the source of the fourth NMOS transistor is grounded; the drain of the fourth NMOS transistor is connected to the second end of the motor M.
- the first transistor Q1 is a first NMOS transistor
- the second transistor Q2 is a second NMOS transistor
- the third transistor Q3 is a third NMOS transistor
- the fourth transistor Q4 is a fourth transistor.
- NMOS tube; then the first NMOS tube, the second NMOS tube, the third NMOS tube, and the fourth NMOS tube are all turned on when the gate receives a high level.
- the first switch delay module 1 includes a first switch delay unit 11 and a first diode D1, and the first terminal of the first switch delay unit 11 is connected to the first terminal of the motor M.
- the second terminal of the first switch delay unit 11 is connected to the cathode of the first diode D1, and the anode of the first diode D1 is grounded. If the first terminal of the motor M Is the first voltage, the second terminal of the motor M is the second voltage, and the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 Are in the off state, the first switch delay unit 11 is turned on for the first specific time period;
- the second switch delay module 2 includes a second switch delay unit 21 and a second diode D2.
- the first end of the second switch delay unit 21 is connected to the second end of the motor M, so The second terminal of the second switch delay unit 21 is connected to the anode of the second diode D2, and the cathode of the second diode D2 is grounded. If the first terminal of the motor M is the first terminal A voltage, the second terminal of the motor M is the second voltage, and the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all in an off state , The second switch delay unit 21 is turned on for the second specific duration.
- the first switch delay module 1 includes a first switch delay unit 11 and a first diode D1.
- the first end of the first switch delay unit 11 is connected to the motor M.
- the first terminal is connected, the second terminal of the first switch delay unit 11 is connected to the cathode of the first diode D1, and the anode of the first diode D1 is grounded.
- the second switch delay module 2 includes a second switch delay unit 21 and a second diode D2.
- the first end of the second switch delay unit 21 is connected to the second end of the motor M, so The second terminal of the second switch delay unit 21 is connected to the anode of the second diode D2, and the cathode of the second diode D2 is grounded.
- the direction of the induced electromotive force generated by the motor M is positive on the right and negative on the left, that is, the first terminal of the motor M is the first voltage ,
- the second terminal of the motor M is the second voltage.
- the first diode D1 and the second diode D2 are turned on, and the induced electromotive force generated by the motor M has a closed loop, so this loop can be used to self-discharge and eliminate the induced electromotive force.
- the first switch delay unit 11 and the second switch delay unit 21 will be turned off after being turned on for a certain period of time, so that the subsequent operations of the second transistor Q2 and the third transistor Q3 will not be affected.
- the first switch delay unit 11 includes a first NOT gate, a first resistor, a first capacitor, a first comparator, a first AND gate, and a fifth NMOS transistor;
- the input terminal of the first NOT gate is connected to the gate of the first NMOS transistor, and the output terminal of the first NOT gate is connected to the first terminal of the first resistor;
- the second terminal of the first resistor is connected to the first input terminal of the first comparator
- the first end of the first capacitor is connected to the second end of the first resistor, and the second end of the first capacitor is grounded;
- a second input terminal of the first comparator is connected to a first reference voltage terminal, and an output terminal of the first comparator is connected to a first input terminal of the first AND gate;
- the second input terminal of the first AND gate is connected to the output terminal of the first NOT gate, the output terminal of the first AND gate is connected to the gate of the fifth NMOS transistor, and the fifth NMOS transistor
- the drain of is connected to the first end of the motor, and the source of the five NMOS transistor is connected to the negative electrode of the first diode;
- the second switch delay unit 21 includes a second NOT gate, a second resistor, a second capacitor, a second comparator, a second AND gate and a sixth NMOS transistor;
- the input terminal of the second NOT gate is connected to the gate of the first NMOS transistor, and the output terminal of the second NOT gate is connected to the first terminal of the second resistor;
- the second terminal of the second resistor is connected to the first input terminal of the second comparator
- the first end of the second capacitor is connected to the second end of the second resistor, and the second end of the second capacitor is grounded;
- a second input terminal of the second comparator is connected to a second reference voltage terminal, and an output terminal of the second comparator is connected to a first input terminal of the second AND gate;
- the second input terminal of the second AND gate is connected to the output terminal of the second NOT gate, the output terminal of the second AND gate is connected to the gate of the sixth NMOS transistor, and the sixth NMOS transistor
- the drain of is connected to the second end of the motor, and the source of the six NMOS transistor is connected to the anode of the second diode.
- the first switch delay unit 11 includes a first NOT gate 111, a first resistor R, a first capacitor C, a first comparator 112, a first AND gate 113, and a fifth NMOS transistor Q5;
- the input terminal of the first NOT gate 111 is connected to the gate of the first NMOS transistor, and the output terminal of the first NOT gate 111 is connected to the first terminal of the first resistor R;
- the first resistor The second terminal of R is connected to the first input terminal of the first comparator 112;
- the first terminal of the first capacitor C is connected to the second terminal of the first resistor R, and the first terminal of the first capacitor C
- the second terminal is grounded;
- the second input terminal of the first comparator 112 is connected to the first reference voltage terminal REF, and the output terminal of the first comparator 112 is
- the gate of the first transistor Q1 passes through the first NOT gate 111, one end is connected to the negative input end of the first comparator 112, and one end is connected to the input end of the first AND gate 113.
- the positive input terminal of the first comparator 112 receives the voltage input from the first reference voltage terminal REF.
- the output of the first AND gate 113 is used to drive the fifth NMOS transistor Q5. Since the structure of the second switch delay unit 21 is similar to the structure of the first switch delay unit 11, it will not be repeated here.
- the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all turned on at a high level. Then when the first transistor Q1 and the fourth transistor Q4 are turned off (the gate of the first transistor Q1 is at low level at this time), before the second transistor Q2 and the third transistor Q3 are turned on, the low level of the gate of Q1 passes through After the NOT gates (first and second NOT gates) are high level, after passing through the RC circuits of the first switch delay unit 11 and the second switch delay unit 21, the capacitors (first capacitor and second capacitor ) Charging, the charging time is determined by the specific values of the respective resistance and capacitance.
- the first comparator and the second comparator both output a high level.
- the output of the AND gate and the second AND gate are both high, and at this time the fifth NMOS transistor and the sixth NMOS transistor are turned on. Then the first diode D1, the second diode D2 and the motor M form a closed loop, which cancels the induced electromotive force.
- both the first comparator and the second comparator output a low level.
- both the output of the first AND gate and the second AND gate are low.
- the fifth NMOS transistor and the sixth NMOS transistor are turned off, which will not affect the operation of the subsequent second transistor Q2 and the third transistor Q3.
- the third switch delay module 3 includes a third switch delay unit 31 and a third diode D3, and the first end of the third switch delay unit 31 is connected to the first terminal of the motor M.
- the second terminal of the third switch delay unit 31 is connected to the anode of the third diode D3, and the cathode of the third diode D3 is grounded. If the first terminal of the motor M Is the third voltage, the second terminal of the motor M is the fourth voltage, and the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 Are in the off state, the third switch delay unit 31 is turned on for the third specific time period;
- the fourth switch delay module 4 includes a fourth switch delay unit 41 and a fourth diode D4.
- the first end of the fourth switch delay unit 41 is connected to the second end of the motor M, so The second terminal of the fourth switch delay unit 41 is connected to the cathode of the fourth diode D4, and the anode of the fourth diode D4 is grounded. If the first terminal of the motor M is the first terminal Three voltages, the second terminal of the motor M is the fourth voltage, and the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all in an off state , The fourth switch delay unit 41 is turned on for the fourth specific duration.
- the third switch delay module 3 includes a third switch delay unit 31 and a third diode D3.
- the first end of the third switch delay unit 31 is connected to the motor M.
- the first terminal is connected, the second terminal of the third switch delay unit 31 is connected to the anode of the third diode D3, and the cathode of the third diode D3 is grounded.
- the fourth switch delay module 4 includes a fourth switch delay unit 41 and a fourth diode D4.
- the first end of the fourth switch delay unit 41 is connected to the second end of the motor M, so The second end of the fourth switch delay unit 41 is connected to the cathode of the fourth diode D4, and the anode of the fourth diode D4 is grounded.
- the direction of the induced electromotive force generated by the motor M is negative on the right and positive on the left, that is, the first terminal of the motor M is the third voltage ,
- the second terminal of the motor M is the fourth voltage.
- the third diode D3 and the fourth diode D4 are turned on, and the induced electromotive force generated by the motor M has a closed loop, so this loop can be used to self-discharge and eliminate the induced electromotive force.
- the third switch delay unit 31 and the fourth switch delay unit 41 will be turned off after being turned on for a certain period of time, so that the subsequent operations of the first transistor Q1 and the fourth transistor Q4 will not be affected.
- the third switch delay unit includes a third NOT gate, a third resistor, a third capacitor, a third comparator, a third AND gate, and a seventh NMOS transistor;
- the input terminal of the third NOT gate is connected to the gate of the third NMOS transistor, and the output terminal of the third NOT gate is connected to the first terminal of the third resistor;
- the second terminal of the third resistor is connected to the first input terminal of the third comparator
- the first end of the third capacitor is connected to the second end of the third resistor, and the second end of the third capacitor is grounded;
- the second input terminal of the third comparator is connected with a third reference voltage terminal, and the output terminal of the third comparator is connected with the first input terminal of the third AND gate;
- the second input terminal of the third AND gate is connected to the output terminal of the third NOT gate, the output terminal of the third AND gate is connected to the gate of the seventh NMOS transistor, and the seventh NMOS transistor
- the drain of is connected to the first end of the motor, and the source of the seven NMOS transistor is connected to the anode of the third diode;
- the fourth switch delay unit includes a fourth NOT gate, a fourth resistor, a fourth capacitor, a fourth comparator, a fourth AND gate and an eighth NMOS transistor;
- the input terminal of the fourth NOT gate is connected to the gate of the third NMOS transistor, and the output terminal of the fourth NOT gate is connected to the first end of the fourth resistor;
- the second terminal of the fourth resistor is connected to the first input terminal of the fourth comparator
- the first end of the fourth capacitor is connected to the second end of the fourth resistor, and the second end of the fourth capacitor is grounded;
- the second input terminal of the fourth comparator is connected with a fourth reference voltage terminal, and the output terminal of the fourth comparator is connected with the first input terminal of the fourth AND gate;
- the second input terminal of the fourth AND gate is connected to the output terminal of the fourth NOT gate, the output terminal of the fourth AND gate is connected to the gate of the eighth NMOS transistor, and the eighth NMOS transistor
- the drain of is connected to the second end of the motor, and the source of the eight NMOS transistor is connected to the cathode of the fourth diode.
- the structure and principle of the third switch delay unit and the fourth switch delay unit can be referred to the first switch delay unit, which will not be repeated here. It should be noted that the first diode D1, the second diode D2, the third diode D3, and the fourth diode D4 can be made into MOSFET body diodes, so that the circuit area can be reduced.
- a motor drive circuit includes a motor M, a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4, and the first end of the motor M is connected through the first transistor The first power source V1, and the first terminal of the motor M is also grounded through the second transistor Q2, the second terminal of the motor M is connected to the second power source V2 through the third transistor Q3, and the motor M The second end of the second terminal is also grounded through the fourth transistor Q4, and the motor drive circuit further includes a first switch delay module 1 and a second switch delay module 2, wherein: the first switch delay module 1 One end is connected to the first end of the motor M, the second end of the first switch delay module 1 is grounded, and the first end of the second switch delay module 2 is connected to the second end of the motor M Connected, the second terminal of the second switch delay module 2 is grounded, if the first terminal of the motor M is at the first voltage, the second terminal of the motor M is at the second voltage, and the first transistor Q1, the second transistor Q
- the embodiment of the present disclosure also provides a terminal device, including the above-mentioned motor drive circuit.
- the aforementioned terminal device may be a mobile phone, a tablet (Personal Computer), a laptop (Laptop Computer), a personal digital assistant (personal digital assistant, PDA), a mobile Internet device (Mobile Internet Device, MID) Or wearable devices (Wearable Device) and so on.
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Abstract
本公开提供一种马达驱动电路及终端设备,该马达驱动电路包括马达、第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一开关延时模块和第二开关延时模块,其中:第一开关延时模块的第一端与马达的第一端连接,第一开关延时模块的第二端接地,第二开关延时模块的第一端与马达的第二端连接,第二开关延时模块的第二端接地,若马达的第一端为第一电压,马达的第二端为第二电压,且第一晶体管、第二晶体管、第三晶体管和第四晶体管均处于截止状态,则第一开关延时模块导通第一特定时长,且第二开关延时模块导通第二特定时长。
Description
相关申请的交叉引用
本申请主张在2019年3月7日在中国提交的中国专利申请号No.201910172298.7的优先权,其全部内容通过引用包含于此。
本公开涉及通信技术领域,尤其涉及一种马达驱动电路及终端设备。
随着终端技术的迅速发展,终端设备已经成为人们生活中必不可少的一种工具,并且为用户生活的各个方面带来了极大的便捷。相关技术中的终端设备上都存在马达,当终端设备接收到一些消息,或者存在来电时,马达可以发生振动从而对用户进行提醒。
但是相关技术中,马达在正转向反转的变化过程中,或者反转向正转的变化过程中,马达自带的线圈会产生感应电动势,感应电动势会抵消一部分电源电动势,从而导致驱动电源的驱动力比较小。
发明内容
本公开实施例提供一种马达驱动电路及终端设备,以解决终端设备的马达自带的线圈会产生感应电动势,感应电动势会抵消一部分电源电动势,从而导致驱动电源的驱动力比较小的问题。
为了解决上述技术问题,本公开是这样实现的:
第一方面,本公开实施例提供了一种马达驱动电路,包括马达、第一晶体管、第二晶体管、第三晶体管和第四晶体管,所述马达的第一端通过所述第一晶体管连接第一电源,且所述马达的第一端还通过所述第二晶体管接地,所述马达的第二端通过所述第三晶体管连接第二电源,且所述马达的第二端还通过所述第四晶体管接地,所述马达驱动电路还包括第一开关延时模块和第二开关延时模块,其中:
所述第一开关延时模块的第一端与所述马达的第一端连接,所述第一开关延时模块的第二端接地,所述第二开关延时模块的第一端与所述马达的第二端连接,所述第二开关延时模块的第二端接地,若所述马达的第一端为第一电压,所述马达的第二端为第二电压,且所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管均处于截止状态,则所述第一开关延时模块导通第一特定时长,且所述第二开关延时模块导通第二特定时长;
其中,所述马达第一端的所述第一电压和第二端的所述第二电压均为感应电动势产生的电压,所述第一电压小于所述第二电压。
第二方面,本公开实施例还提供一种终端设备,包括上述马达驱动电路。
本公开实施例的一种马达驱动电路,所述马达驱动电路包括马达、第一晶体管、第二晶体管、第三晶体管和第四晶体管,所述马达的第一端通过所述第一晶体管连接第一电源,且所述马达的第一端还通过所述第二晶体管接地,所述马达的第二端通过所述第三晶体管连接第二电源,且所述马达的第二端还通过所述第四晶体管接地,所述马达驱动电路还包括第一开关延时模块和第二开关延时模块,其中:所述第一开关延时模块的第一端与所述马达的第一端连接,所述第一开关延时模块的第二端接地,所述第二开关延时模块的第一端与所述马达的第二端连接,所述第二开关延时模块的第二端接地,若所述马达的第一端为第一电压,所述马达的第二端为第二电压,且所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管均处于截止状态,则所述第一开关延时模块导通第一特定时长,且所述第二开关延时模块导通第二特定时长;其中,所述马达第一端的所述第一电压和第二端的所述第二电压均为感应电动势产生的电压,所述第一电压小于所述第二电压。这样,马达产生的感应电动势有了闭合回路,可以用此回路进行自放电,从而提高了驱动电源的驱动力。
为了更清楚地说明本公开实施例的技术方案,下面将对本公开实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本公开的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳 动性的前提下,还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的马达驱动电路的结构图之一;
图2是本公开实施例提供的马达驱动电路的结构图之二;
图3是本公开实施例提供的马达驱动电路的结构图之三;
图4是本公开实施例提供的第一开关延时单元的结构图;
图5是本公开实施例提供的马达驱动电路的结构图之四。
下面将结合本公开实施例中的附图,对本公开实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本公开一部分实施例,而不是全部的实施例。基于本公开中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本公开保护的范围。
参见图1,图1是本公开实施例提供的马达驱动电路的结构图,如图1所示,包括马达M、第一晶体管Q1、第二晶体管Q2、第三晶体管Q3和第四晶体管Q4,所述马达M的第一端通过所述第一晶体管连接第一电源V1,且所述马达M的第一端还通过所述第二晶体管Q2接地,所述马达M的第二端通过所述第三晶体管Q3连接第二电源V2,且所述马达M的第二端还通过所述第四晶体管Q4接地,所述马达驱动电路还包括第一开关延时模块1和第二开关延时模块2,其中:所述第一开关延时模块1的第一端与所述马达M的第一端连接,所述第一开关延时模块1的第二端接地,所述第二开关延时模块2的第一端与所述马达M的第二端连接,所述第二开关延时模块2的第二端接地,若所述马达M的第一端为第一电压,所述马达M的第二端为第二电压,且所述第一晶体管Q1、所述第二晶体管Q2、所述第三晶体管Q3和所述第四晶体管Q4均处于截止状态,则所述第一开关延时模块1导通第一特定时长,且所述第二开关延时模块2导通第二特定时长;其中,所述马达M第一端的所述第一电压和第二端的所述第二电压均为感应电动势产生的电压,所述第一电压小于所述第二电压。
本实施例中,上述第一晶体管Q1、第二晶体管Q2、第三晶体管Q3或第四晶体管Q4,可以是N沟道金属氧化物半导体(N-channel Metal Oxide Semiconductor,NMOS)管,或者也可以是P沟道金属氧化物半导体(P-channel Metal Oxide Semiconductor,PMOS)管,具体为哪一种晶体管可以根据实际的需求来进行选择。
本实施例中,上述第一电源V1和第二电源V2可以相同,也可以不同。上述第一特定时长和第二特定时长可选相等,但第一特定时长略大于或者略小于第二特定时长也可以。
本实施例中,若所述马达M的第一端为第一电压,所述马达M的第二端为第二电压,且所述第一晶体管Q1、所述第二晶体管Q2、所述第三晶体管Q3和所述第四晶体管Q4均处于截止状态,则所述第一开关延时模块1导通第一特定时长,且所述第二开关延时模块2导通第二特定时长。这样,马达产生的感应电动势有了闭合回路,可以用此回路进行自放电,消除感应电动势。由于没有感应电动势,电源电动势就不会被感应电动势所抵消,从而提高了驱动电源的驱动力。
可选的,所述马达驱动电路还包括第三开关延时模块3和第四开关延时模块4,其中:
所述第三开关延时模块3的第一端与所述马达M的第一端连接,所述第三开关延时模块3的第二端接地,所述第四开关延时模块4的第一端与所述马达M的第二端连接,所述第四开关延时模块4的第二端接地,若所述马达M的第一端为第三电压,所述马达的第二端为第四电压,且所述第一晶体管Q1、所述第二晶体管Q2、所述第三晶体管Q3和所述第四晶体管Q4均处于截止状态,则所述第三开关延时模块3导通第三特定时长,且所述第四开关延时模块4导通第四特定时长;
其中,所述马达M第一端的所述第三电压和第二端的所述第四电压均为感应电动势产生的电压,所述第三电压大于所述第四电压。
该实施方式中,上述第三特定时长和第四特定时长可选相等,但第三特定时长略大于或者略小于第四特定时长也可以。
为了更好的理解上述电路结构,可以参阅图2,图2为本公开实施例提供的马达驱动电路的结构图。如图2所示,所述第三开关延时模块3的第一端与所述马达M的第一端连接,所述第三开关延时模块3的第二端接地,所 述第四开关延时模块4的第一端与所述马达M的第二端连接,所述第四开关延时模块4的第二端接地。
该实施方式中,若所述马达M的第一端为第一电压,所述马达M的第二端为第二电压,且所述第一晶体管Q1、所述第二晶体管Q2、所述第三晶体管Q3和所述第四晶体管Q4均处于截止状态,则所述第一开关延时模块1导通第一特定时长,且所述第二开关延时模块2导通第二特定时长。若所述马达M的第一端为第三电压,所述马达的第二端为第四电压,且所述第一晶体管Q1、所述第二晶体管Q2、所述第三晶体管Q3和所述第四晶体管Q4均处于截止状态,则所述第三开关延时模块3导通第三特定时长,且所述第四开关延时模块4导通第四特定时长。
这样,不管马达M是在正转向反转的状态变化的过程中,还是反转向正转的状态变化的过程中,都可以使马达M产生的感应电动势存在闭合回路。从而,可以根据不同的闭合回路对马达不同的状态变化的过程产生的感应电动势进行自放电,消除感应电动势。由于没有感应电动势,电源电动势就不会被感应电动势所抵消,从而提高了驱动电源的驱动力。
可选的,所述第一晶体管Q1为第一NMOS管,所述第二晶体管Q2为第二NMOS管,所述第三晶体管Q3为第三NMOS管,所述第四晶体管Q4为第四NMOS管;
所述第一NMOS管的漏极与所述第一电源V1连接,所述第一NMOS管的源极与所述马达M的第一端连接;所述第二NMOS管的源极接地,所述第二NMOS管的漏极与所述马达M的第一端连接;所述第三NMOS管的源极与所述马达M的第二端连接;所述第三NMOS管的漏极与所述第二电源V2连接;所述第四NMOS管的源极接地;所述第四NMOS管的漏极与所述马达M的第二端连接。
该实施方式中,所述第一晶体管Q1为第一NMOS管,所述第二晶体管Q2为第二NMOS管,所述第三晶体管Q3为第三NMOS管,所述第四晶体管Q4为第四NMOS管;那么第一NMOS管、第二NMOS管、第三NMOS管和第四NMOS管均在栅极接收到高电平时导通。
可选的,所述第一开关延时模块1包括第一开关延时单元11和第一二极 管D1,所述第一开关延时单元11的第一端与所述马达M的第一端连接,所述第一开关延时单元11的第二端与所述第一二极管D1的负极连接,所述第一二极管D1的正极接地,若所述马达M的第一端为所述第一电压,所述马达M的第二端为所述第二电压,且所述第一晶体管Q1、所述第二晶体管Q2、所述第三晶体管Q3和所述第四晶体管Q4均处于截止状态,则所述第一开关延时单元11导通所述第一特定时长;
所述第二开关延时模块2包括第二开关延时单元21和第二二极管D2,所述第二开关延时单元21的第一端与所述马达M的第二端连接,所述第二开关延时单元21的第二端与所述第二二极管D2的正极连接,所述第二二极管D2的负极接地,若所述马达M的第一端为所述第一电压,所述马达M的第二端为所述第二电压,且所述第一晶体管Q1、所述第二晶体管Q2、所述第三晶体管Q3和所述第四晶体管Q4均处于截止状态,则所述第二开关延时单元21导通所述第二特定时长。
为了更好的理解上述电路结构,可以参阅图3,图3是本公开实施例提供的马达驱动电路的结构图。如图3所示,所述第一开关延时模块1包括第一开关延时单元11和第一二极管D1,所述第一开关延时单元11的第一端与所述马达M的第一端连接,所述第一开关延时单元11的第二端与所述第一二极管D1的负极连接,所述第一二极管D1的正极接地。所述第二开关延时模块2包括第二开关延时单元21和第二二极管D2,所述第二开关延时单元21的第一端与所述马达M的第二端连接,所述第二开关延时单元21的第二端与所述第二二极管D2的正极连接,所述第二二极管D2的负极接地。
该实施方式中,当第一晶体管Q1和第四晶体管Q4从导通状态切换到截止状态时,马达M产生的感应电动势方向为右边正极,左边负极,即马达M的第一端为第一电压,马达M的第二端为第二电压。此时,第一二极管D1和第二二极管D2导通,马达M产生的感应电动势有了闭合回路,因此可以用此回路进行自放电,消除感应电动势。第一开关延时单元11和第二开关延时单元21导通特定时长之后会截止,从而不会影响接下来的第二晶体管Q2和第三晶体管Q3的工作。
可选的,所述第一开关延时单元11包括第一非门、第一电阻、第一电容、 第一比较器、第一与门和第五NMOS管;
所述第一非门的输入端与所述第一NMOS管的栅极连接,所述第一非门的输出端与所述第一电阻的第一端连接;
所述第一电阻的第二端与所述第一比较器的第一输入端连接;
所述第一电容的第一端与所述第一电阻的第二端连接,所述第一电容的第二端接地;
所述第一比较器的第二输入端与第一参考电压端连接,所述第一比较器的输出端与所述第一与门的第一输入端连接;
所述第一与门的第二输入端与所述第一非门的输出端连接,所述第一与门的输出端与所述第五NMOS管的栅极连接,所述第五NMOS管的漏极与所述马达的第一端连接,所述五NMOS管的源极与所述第一二极管的负极连接;
所述第二开关延时单元21包括第二非门、第二电阻、第二电容、第二比较器、第二与门和第六NMOS管;
所述第二非门的输入端与所述第一NMOS管的栅极连接,所述第二非门的输出端与所述第二电阻的第一端连接;
所述第二电阻的第二端与所述第二比较器的第一输入端连接;
所述第二电容的第一端与所述第二电阻的第二端连接,所述第二电容的第二端接地;
所述第二比较器的第二输入端与第二参考电压端连接,所述第二比较器的输出端与所述第二与门的第一输入端连接;
所述第二与门的第二输入端与所述第二非门的输出端连接,所述第二与门的输出端与所述第六NMOS管的栅极连接,所述第六NMOS管的漏极与所述马达的第二端连接,所述六NMOS管的源极与所述第二二极管的正极连接。
为了更好的理解开关延时单元的结构,可以以第一开关延时单元为例来理解。请参阅图4,图4为本公开实施例提供的第一开关延时单元的结构图。如图4所示,所述第一开关延时单元11包括第一非门111、第一电阻R、第一电容C、第一比较器112、第一与门113和第五NMOS管Q5;所述第一非 门111的输入端与所述第一NMOS管的栅极连接,所述第一非门111的输出端与所述第一电阻R的第一端连接;所述第一电阻R的第二端与所述第一比较器112的第一输入端连接;所述第一电容C的第一端与所述第一电阻R的第二端连接,所述第一电容C的第二端接地;所述第一比较器112的第二输入端与第一参考电压端REF连接,所述第一比较器112的输出端与所述第一与门113的第一输入端连接;所述第一与门113的第二输入端与所述第一非门111的输出端连接,所述第一与门113的输出端与所述第五NMOS管Q5的栅极连接,所述五NMOS管Q5的漏极与所述马达M的第一端连接,所述五NMOS管Q5的源极与所述第一二极管D1的负极连接。
该实施方式中,第一晶体管Q1的栅极经过第一非门111后,一端接入第一比较器112的负极输入端,一端接入第一与门113的输入端。第一比较器112的正极输入端接收第一参考电压端REF输入的电压。第一与门113的输出用于驱动第五NMOS管Q5。由于第二开关延时单元21的结构与第一开关延时单元11的结构类似,在此不再赘述。
该实施方式中,第一晶体管Q1、第二晶体管Q2、第三晶体管Q3和第四晶体管Q4均为高电平导通。则当第一晶体管Q1和第四晶体管Q4截止(此时第一晶体管Q1的栅极为低电平)时,第二晶体管Q2和第三晶体管Q3导通前,Q1的栅极的低电平经过非门(第一非门和第二非门)后为高电平,经过第一开关延时单元11和第二开关延时单元21的RC电路后会向电容(第一电容和第二电容)充电,充电时间由各自的电阻和电容的具体数值定。
在第一电容上的电压比第一参考电压端的电压小,以及第二电容上的电压比第二参考电压端的电压小之前,第一比较器和第二比较器均输出高电平,第一与门和第二与门均输出高,此时第五NMOS管和第六NMOS管导通。那么第一二极管D1、第二二极管D2和马达M形成了闭合回路,抵消了产生的感应电动势。
在第一电容上的电压比第一参考电压端的电压大,以及第二电容上的电压比第二参考电压端的电压大之后,第一比较器和第二比较器均输出低电平。此时第一与门和第二与门均输出低,此时第五NMOS管和第六NMOS管截止,不会影响接下来的第二晶体管Q2和第三晶体管Q3的工作。
可选的,所述第三开关延时模块3包括第三开关延时单元31和第三二极管D3,所述第三开关延时单元31的第一端与所述马达M的第一端连接,所述第三开关延时单元31的第二端与所述第三二极管D3的正极连接,所述第三二极管D3的负极接地,若所述马达M的第一端为所述第三电压,所述马达M的第二端为所述第四电压,且所述第一晶体管Q1、所述第二晶体管Q2、所述第三晶体管Q3和所述第四晶体管Q4均处于截止状态,则所述第三开关延时单元31导通所述第三特定时长;
所述第四开关延时模块4包括第四开关延时单元41和第四二极管D4,所述第四开关延时单元41的第一端与所述马达M的第二端连接,所述第四开关延时单元41的第二端与所述第四二极管D4的负极连接,所述第四二极管D4的正极接地,若所述马达M的第一端为所述第三电压,所述马达M的第二端为所述第四电压,且所述第一晶体管Q1、所述第二晶体管Q2、所述第三晶体管Q3和所述第四晶体管Q4均处于截止状态,则所述第四开关延时单元41导通所述第四特定时长。
为了更好的理解上述电路结构,可以参阅图5,图5是本公开实施例提供的马达驱动电路的结构图。如图5所示,所述第三开关延时模块3包括第三开关延时单元31和第三二极管D3,所述第三开关延时单元31的第一端与所述马达M的第一端连接,所述第三开关延时单元31的第二端与所述第三二极管D3的正极连接,所述第三二极管D3的负极接地。所述第四开关延时模块4包括第四开关延时单元41和第四二极管D4,所述第四开关延时单元41的第一端与所述马达M的第二端连接,所述第四开关延时单元41的第二端与所述第四二极管D4的负极连接,所述第四二极管D4的正极接地。
该实施方式中,当第二晶体管Q2和第三晶体管Q3从导通状态切换到截止状态时,马达M产生的感应电动势方向为右边负极,左边正极,即马达M的第一端为第三电压,马达M的第二端为第四电压。此时,第三二极管D3和第四二极管D4导通,马达M产生的感应电动势有了闭合回路,因此可以用此回路进行自放电,消除感应电动势。第三开关延时单元31和第四开关延时单元41导通特定时长之后会截止,从而不会影响接下来的第一晶体管Q1和第四晶体管Q4的工作。
可选的,所述第三开关延时单元包括第三非门、第三电阻、第三电容、第三比较器、第三与门和第七NMOS管;
所述第三非门的输入端与所述第三NMOS管的栅极连接,所述第三非门的输出端与所述第三电阻的第一端连接;
所述第三电阻的第二端与所述第三比较器的第一输入端连接;
所述第三电容的第一端与所述第三电阻的第二端连接,所述第三电容的第二端接地;
所述第三比较器的第二输入端与第三参考电压端连接,所述第三比较器的输出端与所述第三与门的第一输入端连接;
所述第三与门的第二输入端与所述第三非门的输出端连接,所述第三与门的输出端与所述第七NMOS管的栅极连接,所述第七NMOS管的漏极与所述马达的第一端连接,所述七NMOS管的源极与所述第三二极管的正极连接;
所述第四开关延时单元包括第四非门、第四电阻、第四电容、第四比较器、第四与门和第八NMOS管;
所述第四非门的输入端与所述第三NMOS管的栅极连接,所述第四非门的输出端与所述第四电阻的第一端连接;
所述第四电阻的第二端与所述第四比较器的第一输入端连接;
所述第四电容的第一端与所述第四电阻的第二端连接,所述第四电容的第二端接地;
所述第四比较器的第二输入端与第四参考电压端连接,所述第四比较器的输出端与所述第四与门的第一输入端连接;
所述第四与门的第二输入端与所述第四非门的输出端连接,所述第四与门的输出端与所述第八NMOS管的栅极连接,所述第八NMOS管的漏极与所述马达的第二端连接,所述八NMOS管的源极与所述第四二极管的负极连接。
该实施方式中,第三开关延时单元和第四开关延时单元的结构和原理可以参照第一开关延时单元,在此不再赘述。需要说明的是,第一二极管D1、第二二极管D2、第三二极管D3和第四二极管D4可以做成MOSFET的体二 极管,从而可以减小电路面积。
本公开实施例的一种马达驱动电路,包括马达M、第一晶体管Q1、第二晶体管Q2、第三晶体管Q3和第四晶体管Q4,所述马达M的第一端通过所述第一晶体管连接第一电源V1,且所述马达M的第一端还通过所述第二晶体管Q2接地,所述马达M的第二端通过所述第三晶体管Q3连接第二电源V2,且所述马达M的第二端还通过所述第四晶体管Q4接地,所述马达驱动电路还包括第一开关延时模块1和第二开关延时模块2,其中:所述第一开关延时模块1的第一端与所述马达M的第一端连接,所述第一开关延时模块1的第二端接地,所述第二开关延时模块2的第一端与所述马达M的第二端连接,所述第二开关延时模块2的第二端接地,若所述马达M的第一端为第一电压,所述马达M的第二端为第二电压,且所述第一晶体管Q1、所述第二晶体管Q2、所述第三晶体管Q3和所述第四晶体管Q4均处于截止状态,则所述第一开关延时模块1导通第一特定时长,且所述第二开关延时模块2导通第二特定时长;其中,所述马达M第一端的所述第一电压和第二端的所述第二电压均为感应电动势产生的电压,所述第一电压小于所述第二电压。这样,马达产生的感应电动势有了闭合回路,可以用此回路进行自放电,从而提高了驱动电源的驱动力。
本公开实施例还提供一种终端设备,包括上述马达驱动电路。
本实施例中,上述终端设备可以是手机、平板电脑(Tablet Personal Computer)、膝上型电脑(Laptop Computer)、个人数字助理(personal digital assistant,PDA)、移动上网装置(Mobile Internet Device,MID)或可穿戴式设备(Wearable Device)等等。
需要说明的是,在本文中,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上面结合附图对本公开的实施例进行了描述,但是本公开并不局限于上 述的具体实施方式,上述的具体实施方式仅仅是示意性的,而不是限制性的,本领域的普通技术人员在本公开的启示下,在不脱离本公开宗旨和权利要求所保护的范围情况下,还可做出很多形式,均属于本公开的保护之内。
Claims (8)
- 一种马达驱动电路,包括马达、第一晶体管、第二晶体管、第三晶体管和第四晶体管,所述马达的第一端通过所述第一晶体管连接第一电源,且所述马达的第一端还通过所述第二晶体管接地,所述马达的第二端通过所述第三晶体管连接第二电源,且所述马达的第二端还通过所述第四晶体管接地,所述马达驱动电路还包括第一开关延时模块和第二开关延时模块,其中:所述第一开关延时模块的第一端与所述马达的第一端连接,所述第一开关延时模块的第二端接地,所述第二开关延时模块的第一端与所述马达的第二端连接,所述第二开关延时模块的第二端接地,若所述马达的第一端为第一电压,所述马达的第二端为第二电压,且所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管均处于截止状态,则所述第一开关延时模块导通第一特定时长,且所述第二开关延时模块导通第二特定时长;其中,所述马达第一端的所述第一电压和第二端的所述第二电压均为感应电动势产生的电压,所述第一电压小于所述第二电压。
- 根据权利要求1所述的马达驱动电路,还包括第三开关延时模块和第四开关延时模块,其中:所述第三开关延时模块的第一端与所述马达的第一端连接,所述第三开关延时模块的第二端接地,所述第四开关延时模块的第一端与所述马达的第二端连接,所述第四开关延时模块的第二端接地,若所述马达的第一端为第三电压,所述马达的第二端为第四电压,且所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管均处于截止状态,则所述第三开关延时模块导通第三特定时长,且所述第四开关延时模块导通第四特定时长;其中,所述马达第一端的所述第三电压和第二端的所述第四电压均为感应电动势产生的电压,所述第三电压大于所述第四电压。
- 根据权利要求2所述的马达驱动电路,其中,所述第一晶体管为第一NMOS管,所述第二晶体管为第二NMOS管,所述第三晶体管为第三NMOS管,所述第四晶体管为第四NMOS管;所述第一NMOS管的漏极与所述第一电源连接,所述第一NMOS管的 源极与所述马达的第一端连接;所述第二NMOS管的源极接地,所述第二NMOS管的漏极与所述马达的第一端连接;所述第三NMOS管的源极与所述马达的第二端连接,所述第三NMOS管的漏极与所述第二电源连接;所述第四NMOS管的源极接地,所述第四NMOS管的漏极与所述马达的第二端连接。
- 根据权利要求3所述的马达驱动电路,其中,所述第一开关延时模块包括第一开关延时单元和第一二极管,所述第一开关延时单元的第一端与所述马达的第一端连接,所述第一开关延时单元的第二端与所述第一二极管的负极连接,所述第一二极管的正极接地,若所述马达的第一端为所述第一电压,所述马达的第二端为所述第二电压,且所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管均处于截止状态,则所述第一开关延时单元导通所述第一特定时长;所述第二开关延时模块包括第二开关延时单元和第二二极管,所述第二开关延时单元的第一端与所述马达的第二端连接,所述第二开关延时单元的第二端与所述第二二极管的正极连接,所述第二二极管的负极接地,若所述马达的第一端为所述第一电压,所述马达的第二端为所述第二电压,且所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管均处于截止状态,则所述第二开关延时单元导通所述第二特定时长。
- 根据权利要求4所述的马达驱动电路,其中,所述第一开关延时单元包括第一非门、第一电阻、第一电容、第一比较器、第一与门和第五NMOS管;所述第一非门的输入端与所述第一NMOS管的栅极连接,所述第一非门的输出端与所述第一电阻的第一端连接;所述第一电阻的第二端与所述第一比较器的第一输入端连接;所述第一电容的第一端与所述第一电阻的第二端连接,所述第一电容的第二端接地;所述第一比较器的第二输入端与第一参考电压端连接,所述第一比较器的输出端与所述第一与门的第一输入端连接;所述第一与门的第二输入端与所述第一非门的输出端连接,所述第一与 门的输出端与所述第五NMOS管的栅极连接,所述第五NMOS管的漏极与所述马达的第一端连接,所述五NMOS管的源极与所述第一二极管的负极连接;所述第二开关延时单元包括第二非门、第二电阻、第二电容、第二比较器、第二与门和第六NMOS管;所述第二非门的输入端与所述第一NMOS管的栅极连接,所述第二非门的输出端与所述第二电阻的第一端连接;所述第二电阻的第二端与所述第二比较器的第一输入端连接;所述第二电容的第一端与所述第二电阻的第二端连接,所述第二电容的第二端接地;所述第二比较器的第二输入端与第二参考电压端连接,所述第二比较器的输出端与所述第二与门的第一输入端连接;所述第二与门的第二输入端与所述第二非门的输出端连接,所述第二与门的输出端与所述第六NMOS管的栅极连接,所述第六NMOS管的漏极与所述马达的第二端连接,所述六NMOS管的源极与所述第二二极管的正极连接。
- 根据权利要求3至5中任一项所述的马达驱动电路,其中,所述第三开关延时模块包括第三开关延时单元和第三二极管,所述第三开关延时单元的第一端与所述马达的第一端连接,所述第三开关延时单元的第二端与所述第三二极管的正极连接,所述第三二极管的负极接地,若所述马达的第一端为所述第三电压,所述马达的第二端为所述第四电压,且所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管均处于截止状态,则所述第三开关延时单元导通所述第三特定时长;所述第四开关延时模块包括第四开关延时单元和第四二极管,所述第四开关延时单元的第一端与所述马达的第二端连接,所述第四开关延时单元的第二端与所述第四二极管的负极连接,所述第四二极管的正极接地,若所述马达的第一端为所述第三电压,所述马达的第二端为所述第四电压,且所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管均处于截止状态,则所述第四开关延时单元导通所述第四特定时长。
- 根据权利要求6所述的马达驱动电路,其中,所述第三开关延时单元包括第三非门、第三电阻、第三电容、第三比较器、第三与门和第七NMOS管;所述第三非门的输入端与所述第三NMOS管的栅极连接,所述第三非门的输出端与所述第三电阻的第一端连接;所述第三电阻的第二端与所述第三比较器的第一输入端连接;所述第三电容的第一端与所述第三电阻的第二端连接,所述第三电容的第二端接地;所述第三比较器的第二输入端与第三参考电压端连接,所述第三比较器的输出端与所述第三与门的第一输入端连接;所述第三与门的第二输入端与所述第三非门的输出端连接,所述第三与门的输出端与所述第七NMOS管的栅极连接,所述第七NMOS管的漏极与所述马达的第一端连接,所述七NMOS管的源极与所述第三二极管的正极连接;所述第四开关延时单元包括第四非门、第四电阻、第四电容、第四比较器、第四与门和第八NMOS管;所述第四非门的输入端与所述第三NMOS管的栅极连接,所述第四非门的输出端与所述第四电阻的第一端连接;所述第四电阻的第二端与所述第四比较器的第一输入端连接;所述第四电容的第一端与所述第四电阻的第二端连接,所述第四电容的第二端接地;所述第四比较器的第二输入端与第四参考电压端连接,所述第四比较器的输出端与所述第四与门的第一输入端连接;所述第四与门的第二输入端与所述第四非门的输出端连接,所述第四与门的输出端与所述第八NMOS管的栅极连接,所述第八NMOS管的漏极与所述马达的第二端连接,所述八NMOS管的源极与所述第四二极管的负极连接。
- 一种终端设备,包括权利要求1至7中任一项所述的马达驱动电路。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004274817A (ja) * | 2003-03-05 | 2004-09-30 | Yazaki Corp | モータ正転・逆転駆動回路 |
CN101442284A (zh) * | 2007-11-21 | 2009-05-27 | 三洋电机株式会社 | 马达驱动电路、风扇马达、电子设备及笔记本个人计算机 |
CN105656364A (zh) * | 2014-11-28 | 2016-06-08 | 美蓓亚株式会社 | 马达驱动控制装置以及旋转状态检测方法 |
WO2018142828A1 (ja) * | 2017-01-31 | 2018-08-09 | 日本電産株式会社 | モータ駆動装置、および電動パワーステアリング装置 |
CN109921770A (zh) * | 2019-03-07 | 2019-06-21 | 维沃移动通信有限公司 | 一种马达驱动电路及终端设备 |
Family Cites Families (9)
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CN100356671C (zh) * | 2004-08-06 | 2007-12-19 | 台达电子工业股份有限公司 | 驱动电路改善方法 |
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CN103560728A (zh) * | 2013-11-13 | 2014-02-05 | 中国兵器工业集团第二一四研究所苏州研发中心 | 一种带死区延时的电机驱动电路 |
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-
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004274817A (ja) * | 2003-03-05 | 2004-09-30 | Yazaki Corp | モータ正転・逆転駆動回路 |
CN101442284A (zh) * | 2007-11-21 | 2009-05-27 | 三洋电机株式会社 | 马达驱动电路、风扇马达、电子设备及笔记本个人计算机 |
CN105656364A (zh) * | 2014-11-28 | 2016-06-08 | 美蓓亚株式会社 | 马达驱动控制装置以及旋转状态检测方法 |
WO2018142828A1 (ja) * | 2017-01-31 | 2018-08-09 | 日本電産株式会社 | モータ駆動装置、および電動パワーステアリング装置 |
CN109921770A (zh) * | 2019-03-07 | 2019-06-21 | 维沃移动通信有限公司 | 一种马达驱动电路及终端设备 |
Non-Patent Citations (1)
Title |
---|
HUANG, HU ET AL.: " Electrical System Design Monograph", BEIHANG UNIVERSITY PRESS, 28 February 2009 (2009-02-28), pages 183 - 189, XP009523052 * |
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