WO2020177092A1 - Circuit d'interface - Google Patents

Circuit d'interface Download PDF

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Publication number
WO2020177092A1
WO2020177092A1 PCT/CN2019/077113 CN2019077113W WO2020177092A1 WO 2020177092 A1 WO2020177092 A1 WO 2020177092A1 CN 2019077113 W CN2019077113 W CN 2019077113W WO 2020177092 A1 WO2020177092 A1 WO 2020177092A1
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WO
WIPO (PCT)
Prior art keywords
switch
circuit
interface circuit
coupled
interface
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PCT/CN2019/077113
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English (en)
Chinese (zh)
Inventor
张津海
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980089091.1A priority Critical patent/CN113302570B/zh
Priority to PCT/CN2019/077113 priority patent/WO2020177092A1/fr
Publication of WO2020177092A1 publication Critical patent/WO2020177092A1/fr

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

Definitions

  • This application relates to the field of power electronics technology, and in particular to an interface circuit.
  • the interface circuit protocol of the chip has not changed accordingly.
  • E1 and T1 defined by ITU-T the telecommunications standardization department of the International Telecommunication Union
  • Such interface protocols are all high-voltage interface protocols.
  • the interface circuit amplifies the low-voltage input signal of the chip through an amplifier and outputs it to the interface load. Therefore, when the chip with a higher process process uses the above-mentioned high-voltage interface protocol, the output swing of the chip interface circuit must be increased, and even the interface circuit is required to perform Full swing output, when the interface circuit works with a higher output swing, the reliability of the operation of each device in the interface circuit will be threatened.
  • the op amp response of the interface circuit usually has a certain delay
  • the output signal of the amplifier will have an overshot phenomenon, which will affect the interface circuit.
  • the reliability of the switch tube and other electronic devices poses a threat, accelerates the loss of the switch tube and other electronic devices, and shortens the life of the interface circuit.
  • the present application provides an interface circuit, which does not cause overshoot when it operates with a higher swing output or even full swing output, thereby improving the reliability of the interface circuit and prolonging the life of the interface circuit.
  • the interface circuit includes an amplifier, a first switch, a second switch, and a third switch, wherein the input terminal of the amplifier is coupled to the input node of the interface circuit, and the output terminal of the amplifier is coupled to the control terminal of the second switch
  • the output terminal of the amplifier is also coupled to the ground through the third switch, the first switch and the second switch are connected in series between the power supply voltage and the ground, and the output node of the interface circuit is arranged between the first switch and the second switch.
  • one end of the interface load is coupled to the supply voltage, and the other end is coupled to the output node.
  • the amplifier provides output gain for the second switch, so that the second switch generates an output signal to drive the interface load; when the first switch and the third switch are turned on, the output of the amplifier
  • the signal is coupled to the ground through the third switch, so that the second switch is turned off, and the first switch increases the voltage of the interface load to the supply voltage. Therefore, when the input signal is on the rising edge, the first switch and the third switch are turned off in the first half of the rising edge, and the first switch and the third switch are turned on in the second half of the rising edge, so that the amplifier is on the rising edge.
  • the second half does not participate in the signal amplification process, thereby eliminating overshoot and improving the reliability and service life of the interface circuit.
  • the first switch is a P-type oxide semiconductor PMOS transistor
  • the gate of the first switch is the control terminal
  • the drain of the first switch is coupled to the supply voltage
  • the source of the first switch is coupled to the output node. Therefore, the gate of the first switching tube is used to input the control signal.
  • the control signal is a high signal
  • the first switching tube is turned off; when the control signal is a low signal, the first switching tube is turned on, which will load the interface The voltage is pulled up to the supply voltage.
  • the second switch is an N-type metal oxide semiconductor NMOS transistor
  • the gate of the second switch is the control terminal
  • the drain of the second switch is coupled to ground
  • the source of the second switch is coupled to the output. node.
  • the third switch is an NMOS transistor
  • the gate of the third switch is the control terminal
  • the drain of the third switch is coupled to the output terminal of the amplifier
  • the source of the third switch is coupled to the ground.
  • the interface circuit further includes control logic, which is used to: when the input signal of the input node is at the rising edge, the first switch and the third switch are turned off before the time T0, and the first switch The and the third switch are turned on after the time T0, where the time T0 is any time when the input signal is located between the low level and the high level of the rising edge.
  • control logic which is used to: when the input signal of the input node is at the rising edge, the first switch and the third switch are turned off before the time T0, and the first switch The and the third switch are turned on after the time T0, where the time T0 is any time when the input signal is located between the low level and the high level of the rising edge.
  • control logic is also used to: before the input signal of the input node enters the falling edge, the first switch and the third switch are turned on before time T1, and the first switch and the third switch are turned on at time T1. Then it turns off, where T1 is any time before the input signal enters the falling edge. Therefore, when the input signal is at a low level, the amplifier and the second switch constitute a signal amplifying circuit, which can amplify and output the input signal, thereby driving the interface load.
  • the output nodes of the two interface circuits are coupled to both ends of the interface load to form a differential interface circuit, and the two interface circuits serve as the first half circuit and the second half circuit of the differential interface circuit.
  • the input node of the first half circuit and the input node of the second half circuit are respectively used to input two half signals of the differential signal.
  • the control logic of the interface circuit is used to: when the input signal of the input node of the first half circuit is on the rising edge, the first switch of the second half circuit Keep on, the third switch of the second half of the circuit remains off, the first switch and the third switch of the first half of the circuit are turned off before T0, the first switch and the third switch of the first half of the circuit are at T0 Then turn on, where T0 time is any time when the input signal is between the low level and the high level of the rising edge.
  • the amplifier of the first half circuit, the second switch, and the first switch and interface load of the second half circuit constitute a working circuit, which can amplify and output the input signal of the input node of the first half circuit.
  • the interface load is driven; after T0, the first switch of the first half of the circuit, the first switch of the second half of the circuit, and the interface load are coupled, so that the voltage of the interface load is increased to the supply voltage. Therefore, the amplifier does not participate in the signal amplification process in the second half of the rising edge, and the control logic can eliminate the overshoot phenomenon of the interface circuit and improve the reliability and service life of the interface circuit.
  • control logic is also used to: before the input signal of the input node of the first half circuit enters the falling edge, the first switch of the second half circuit is kept on, and the third switch of the second half circuit is turned on.
  • the switch remains off, the first switch and the third switch of the first half of the circuit are turned on before time T1, and the first switch and the third switch of the first half of the circuit are turned off after the time T1, where T1 is the input signal Any time before the falling edge.
  • the amplifier of the first half circuit, the second switch, and the first switch of the second half circuit and the interface load constitute a signal amplifying circuit, which can amplify the input signal Output to drive the interface load.
  • Figure 1 is a schematic diagram of a traditional interface circuit
  • Figure 2 is a schematic diagram of the signal waveform of the overshoot phenomenon in the traditional interface circuit
  • FIG. 3 is a schematic structural diagram of an interface circuit provided by this application.
  • FIG. 4 is a schematic diagram of an operating state of the interface circuit provided by this application.
  • FIG. 5 is a schematic diagram of another operating state of the interface circuit provided by this application.
  • FIG. 6 is a diagram of the relationship between the control logic and the circuit operating state provided by this application.
  • FIG. 7 is a diagram of the relationship between the control logic and the circuit operating state provided by this application.
  • Fig. 8 is a test diagram of the output signal waveform of the interface circuit of the application.
  • FIG. 9 is a schematic structural diagram of a differential interface circuit provided by this application.
  • 11 is a schematic diagram of the working state of the differential interface circuit in the first stage of the control logic
  • 13 is a schematic diagram of the working state of the differential interface circuit in the third stage of the control logic
  • 15 is a schematic diagram of the working state of the differential interface circuit in the fifth stage of the control logic
  • FIG. 16 is a schematic diagram of the output signal waveform of the differential interface circuit of this application.
  • the technological process of computer chips continues to improve, the power supply voltage of the chip is getting smaller and smaller, and the carrying capacity of the chip to high voltage is also declining.
  • the chip's interface circuit still uses high-voltage protocols such as TI and E1, and is not optimized for low-voltage chips. Therefore, in low-voltage chips, the interface circuit usually needs to operate under a higher output swing in order to adapt to the high-voltage protocol, which will threaten the reliability of the operation of each device in the interface circuit and shorten the life of the interface circuit.
  • the chip in this application may be, for example, a system chip (system on a chip, SOC), a modem chip, etc.
  • FIG. 1 is a schematic diagram of the structure of a traditional interface circuit.
  • the traditional interface circuit is mainly composed of operational amplifier Amp, N-type metal oxide semiconductor NMOS transistor and feedback circuit.
  • the gate of the NMOS transistor is coupled to the output terminal of the operational amplifier Amp
  • the drain of the NMOS transistor is coupled to ground
  • the source of the NMOS transistor is coupled to the output node Vout of the interface circuit
  • the non-inverting input terminal of the operational amplifier Amp (+ ) Is coupled to the input node Vin of the interface circuit, and the reverse input terminal (-) is coupled to the common mode bias node Vcom
  • the feedback circuit is composed of differential resistors R1 and R2, where R1 and R2 are connected in series to the common mode bias node Vcom and Between the output node Vout of the interface circuit, the intersection of the series-connected differential resistors R1 and R2 is coupled to the inverting input terminal (-) of the operational amplifier Amp.
  • Figure 2 is a schematic diagram of the signal waveform of the overshoot phenomenon in the traditional interface circuit. Due to the continuous decrease of chip voltage, in order to make the interface circuit compatible with the traditional high voltage protocol, it is necessary to increase the output swing of the interface circuit, and even requires the interface circuit to output at full swing. However, as shown in Figure 2, due to the delay in the response of the op amp of the interface circuit, when the signal changes from low to high, the interface circuit will produce overshoot during the response of the op amp.
  • NMOS transistors and other devices in the interface circuit It poses a serious threat to the reliability of NMOS transistors and other devices in the interface circuit, and accelerates the loss of the devices, especially when the chip process is high and the chip voltage is low, the NMOS transistors and other devices in the interface circuit have a higher resistance to overshoot. Weak, if overshoot occurs, the device may be damaged by breakdown, thereby reducing the reliability of the interface circuit and shortening the life of the interface circuit.
  • this application provides an interface circuit. There will be no overshoot in high swing or even full swing operation, thereby improving the reliability of NMOS transistors and other devices in the interface circuit and prolonging the life of the interface circuit.
  • FIG. 3 is a schematic structural diagram of an interface circuit provided by this application.
  • the interface circuit includes an amplifier, a first switch K1, a second switch K2, and a third switch K3.
  • the input of the amplifier is coupled to the input node Vin of the interface circuit, and the output of the amplifier is coupled To the control terminal of the second switch K2, the output terminal of the amplifier is also coupled to the ground through the third switch K3.
  • the first switch K1 and the second switch K2 are connected in series between the supply voltage Vcc and the ground, and the output node Vout of the interface circuit It is arranged between the first switch K1 and the second switch K2.
  • the amplifier may be, for example, an operational amplifier Amp, which includes a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. Among them, one of the non-inverting input terminal (+) and the inverting input terminal (-) is coupled to the input node Vin of the interface circuit, and the other is coupled to the common mode bias node Vcom.
  • the interface circuit also includes a feedback circuit.
  • the feedback circuit is composed of differential resistors R1 and R2. R1 and R2 are connected in series between the common mode bias node Vcom and the output node Vout of the interface circuit. The intersection of the differential resistors R1 and R2 in series Coupled to an input terminal of the operational amplifier Amp.
  • the inverting input terminal (-) of the operational amplifier Amp is coupled to the input node Vin
  • the non-inverting input terminal (+) of the operational amplifier Amp is coupled to the intersection of the differential resistors R1 and R2 in series
  • the operational amplifier The non-inverting input terminal (+) of Amp is coupled to the input node Vin
  • the inverting input terminal (-) of the operational amplifier Amp is coupled to the intersection of the differential resistors R1 and R2 in series.
  • the first switch K1 and the third switch K3 both include a control terminal for receiving a control signal, and the first switch K1 and the third switch K3 are turned on or off under the action of the control signal.
  • the control signal can be, for example, a phase control signal, and can be turned off by a signal generator.
  • the first switch K1, the second switch K2 and the third switch K3 may all use MOS transistors.
  • the first switch K1 and the third switch K3 are turned on and off under the control of the control signals en1 and en2, respectively, and a P-type oxide semiconductor PMOS transistor or an N-type metal oxide semiconductor NMOS transistor can be arbitrarily selected.
  • the gate of the second switch K2 is grounded through the third switch K3 and is coupled to the output terminal of the amplifier Amp at the same time. Therefore, in the embodiment of the present invention, the second switch K2 can select an NMOS transistor; however, since the signal level can be Inversion is performed by a device or circuit such as an inverter, so the second switch K2 can also select a PMOS transistor.
  • the first switch K1 may be a P-type oxide semiconductor PMOS transistor, the gate of the first switch K1 is the control terminal, and the drain of the first switch K1 is coupled to the supply voltage Vcc, The source of the first switch K1 is coupled to the output node Vout.
  • the gate of the first switch K1 is used to input a control signal.
  • the second switch K2 can be an N-type metal oxide semiconductor NMOS transistor, the gate of the second switch K2 is the control terminal, the drain of the second switch K2 is coupled to the ground, and the second switch K2 The source is coupled to the output node Vout.
  • the second switch K2 when the first switch K1 is turned off, the second switch K2 generates an output signal under the action of the output gain of the operational amplifier Amp to provide the driving ability for the interface load Load;
  • the third switch K3 may be an NMOS transistor, and the third switch The gate of K3 is the control terminal, the drain of the third switch K3 is coupled to the output terminal of the amplifier, and the source of the third switch K3 is coupled to the ground.
  • the third switch K3 when the third switch K3 is turned on, the output terminal of the amplifier is coupled to the ground, so that the second switch K2 is turned off.
  • the output node Vout is coupled to one end of the interface load Load, and the other end of the interface load Load is coupled to the supply voltage Vcc.
  • the interface circuit of the present application can have at least two operating states.
  • FIG. 4 is a schematic diagram of an operating state of the interface circuit provided by this application.
  • the first switch K1 and the third switch K3 are turned off, and the operational amplifier Amp, the second switch K2, the interface load Load and the feedback circuit in the interface circuit form a working circuit.
  • the input signal of the input node Vin is amplified and output by the operational amplifier Amp and the second switch K2 to drive the interface load Load.
  • FIG. 5 is a schematic diagram of another operating state of the interface circuit provided by this application.
  • the first switch K1 and the third switch K3 are turned on, and the output signal of the operational amplifier Amp is coupled to the ground through the third switch K3.
  • the second switch is an NMOS transistor
  • the second switch The gate of K2 is turned off because it is grounded.
  • the first switch K1 in the interface circuit and the interface load Load form a working circuit.
  • the voltage across the interface load Load can be pulled up to the supply voltage Vcc, so that the interface load
  • the energy storage devices (capacitors and inductors) are discharged and restored to the no-load state.
  • the interface circuit of the present application may also include a control logic, which can eliminate the overshoot phenomenon in the interface circuit.
  • FIG. 6 is a diagram of the relationship between the control logic and the operating state of the circuit provided by this application.
  • control logic is used to: when the input signal of the input node Vin is at the rising edge, the first switch K1 and the third switch K3 are turned off before the time T0, and the first switch K1 and the third switch K3 are at Turn on after T0, where T0 is any moment when the input signal is between the low level and the high level of the rising edge.
  • Figure 6 also shows the waveform diagram of the input signal and output signal.
  • Both the input signal and the output signal are digital signals.
  • the digital signal is theoretically a square wave signal, that is, the rising and falling edges are perpendicular to the time axis, but in fact, the digital
  • the conversion of the high and low levels of the signal takes a certain time to complete, so that the rising and falling edges of the input signal and the output signal shown in FIG. 6 have a certain slope.
  • the control logic of the present application is mainly used to control the on and off states of each switch in the interface circuit during the high and low level conversion of the input signal to eliminate overshoot.
  • the first switch K1 is a PMOS transistor
  • the second switch K2 is an NMOS transistor
  • the third switch K3 is an NMOS transistor.
  • the control signal en1 of the gate of the first switch K1 is a high signal, which turns off the first switch K1
  • the control signal en2 of the gate of the third switch K3 is a low signal, which turns off the third switch K3 OFF
  • the output gain of the operational amplifier Amp acts on the second switch K2, so that the operational amplifier Amp, the second switch K2, the interface load and the feedback circuit form a working circuit
  • the second switch K2 generates an output under the action of the output gain of the operational amplifier Amp
  • the signal provides the ability to drive the interface load, so that the voltage of the interface load gradually increases.
  • the control signal en1 of the gate of the first switch K1 is a low signal, turning on the first switch K1, and the control signal en2 of the gate of the third switch K3 is a high signal, turning the third switch K3 on Is turned on, the output terminal of the operational amplifier Amp is coupled to the ground through the third switch K3, so that the output gain of the operational amplifier Amp will not act on the second switch K2, causing the second switch K2 to be turned off.
  • the first switch K1 It forms a working circuit with the interface load Load, and the voltage across the interface load Load is pulled up to the supply voltage Vcc, so that the energy storage devices (capacitors and inductors) in the interface load Load are discharged and restored to the no-load state.
  • the operational amplifier Amp and the second switch K2 amplify the output signal and increase the voltage of the interface load Load; when the input signal enters the rise In the second half of the edge (that is, after T0 time), the output terminal of the operational amplifier Amp is coupled to cause the second switch K2 to be turned off.
  • the first switch K1 takes over the work of the operational amplifier Amp and continues to load the interface The voltage of Load is pulled up to the supply voltage Vcc. Therefore, the operational amplifier Amp does not participate in amplifying the input signal when the input signal is at the end of the rising edge, thereby avoiding the occurrence of overshoot.
  • control logic is also used to: before the input signal enters the falling edge, the first switch K1 and the third switch K3 are turned on before time T1, and the first switch K1 and the third switch K3 are turned off after time T1, where , T1 time is any time before the input signal enters the falling edge.
  • FIG. 7 is a diagram of the relationship between the control logic and the operating state of the circuit provided by this application.
  • the first switch K1 is a PMOS transistor
  • the second switch K2 is an NMOS transistor
  • the third switch K3 is an NMOS transistor.
  • the control signal en1 of the gate of the first switch K1 is a low signal, which turns on the first switch K1
  • the control signal en2 of the gate of the third switch K3 is a high signal, which turns on the third switch
  • the operational amplifier The output terminal of Amp is coupled to the ground through the third switch K3, so that the output gain of the operational amplifier Amp will not act on the second switch K2, causing the second switch K2 to be turned off.
  • the first switch K1 and the interface load Load To form a working circuit, the voltage across the interface load Load is pulled up to the power supply voltage Vcc, so that the energy storage devices (capacitors and inductors) in the interface load Load are discharged and restored to the no-load state.
  • the control signal en1 of the gate of the first switch K1 is a high signal, turning off the first switch K1
  • the control signal en2 of the gate of the third switch K3 is a low signal, turning off the third switch K3, and the calculation
  • the output gain of the amplifier Amp acts on the second switch K2, so that the operational amplifier Amp, the second switch K2, the interface load, and the feedback circuit form a working circuit. In this state, the working circuit completes the operational amplifier preparation and can amplify the input signal Output.
  • Fig. 8 is a test diagram of the output signal waveform of the interface circuit of the application. It can be seen from the comparison between FIG. 2 and FIG. 8 that in the output signal of the interface circuit of the present application, the overshoot phenomenon is completely eliminated. It can be seen that the interface circuit of the present application has higher reliability and longer service life.
  • FIG. 9 is a schematic structural diagram of a differential interface circuit provided by this application.
  • the output nodes Vout of the two interface circuits of the present application are coupled to the two ends of the interface load Load to form a differential interface circuit, and the two interface circuits respectively serve as half circuits of the differential interface circuit.
  • the first switches K11 and K12 of the two half-side circuits are P-type oxide semiconductor PMOS transistors, and the second switches K12 and K22 and the third switches K13 and K23 are N-type.
  • Metal oxide semiconductor NMOS transistor For ease of description, this application refers to one of the interface circuits as the first half circuit Nhalf, and the other interface circuit as the second half circuit Phalf. The first half circuit Nhalf and the second half circuit Phalf are actually the same interface circuit. .
  • the amplifier of the half-side circuit can be, for example, an operational amplifier Amp, which includes a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. Among them, one of the non-inverting input terminal (+) and the inverting input terminal (-) is coupled to the input node Vin of the interface circuit, and the other is coupled to the common mode bias node Vcom.
  • Each half circuit also includes a feedback circuit.
  • the feedback circuit is composed of differential resistors R1 and R2.
  • R1 and R2 are connected in series between the common mode bias node Vcom and the output node Vout of the half circuit.
  • the differential resistors R1 and R2 are connected in series.
  • the cross point is coupled to an input terminal of the operational amplifier Amp.
  • the inverting input terminal (-) of the operational amplifier Amp is coupled to the input node Vin
  • the non-inverting input terminal (+) of the operational amplifier Amp is coupled to the intersection of the differential resistors R1 and R2 in series
  • the operational amplifier The non-inverting input terminal (+) of Amp is coupled to the input node Vin
  • the inverting input terminal (-) of the operational amplifier Amp is coupled to the intersection of the differential resistors R1 and R2 in series.
  • the operational amplifier Amp is used to receive the first input signal
  • the control terminal of the first switch K11 is used to receive the control signal en1
  • the control terminal of the third switch K13 is used to receive the control signal en2
  • the control signal en1 and the control signal en2 have the same timing
  • the operational amplifier Amp is used to receive the second input signal
  • the control terminal of the first switch K21 is used to receive the control signal en3
  • the third switch K23 The control terminal of is used to receive the control signal en4, where the timing of the control signal en3 and the control signal en4 is the same.
  • This application also provides a control logic for a differential interface circuit, which can eliminate the overshoot phenomenon of the differential interface circuit.
  • the control logic of the differential interface circuit can be implemented by timing control, where the timing control signal can be generated by a signal generator, for example, and specifically can be implemented by setting a delay lock loop (DLL).
  • DLL delay lock loop
  • FIG. 10 is a timing diagram of the control logic of the differential interface circuit provided by this application.
  • Figure 9 contains 6 time nodes, namely A, B, C, D, E, and F.
  • node C corresponds to the moment when the first input signal starts to enter the falling edge
  • node B corresponds to any moment T1 before the first input signal enters the falling edge
  • node A is the moment before T1
  • node D corresponds to the first input signal starts to rise
  • the node E corresponds to any time T0 when the first input signal is between the low level and the high level of the rising edge
  • the node F is the time when the first input signal rises to the high level.
  • the control logic can include five stages. The five truncations of the control logic will be described in detail below in conjunction with Figs. 11-15.
  • the first switches K11 and K21 are PMOS transistors
  • the second switches K12 and K22 are NMOS transistors
  • the third switches K13H and K23 are NMOS transistors.
  • the first stage (node A-node B):
  • Figure 11 is a schematic diagram of the working state of the differential interface circuit in the first stage of the control logic.
  • the first input signal is at a high level, and the control signal en1 is at a low signal, so that the first switch K11 of the first half circuit Nhalf is turned on; the control signal en2 is at a high signal, so The third switch K13 of the first half circuit Nhalf is turned on, and the output terminal of the operational amplifier Amp of the first half circuit Nhalf is coupled to the ground through the third switch K13, so that the second switch K12 is turned off; the control signal en3 is a low signal , The first switch K21 of the second half circuit Phalf is turned on; the control signal en4 is a high signal, and the third switch K23 of the second half circuit Phalf is turned on.
  • the output terminal of the operational amplifier Amp of the second half circuit Phalf passes through the The three switches K23 are coupled to the ground, so that the second switch K22 is turned off.
  • the first switch K11 of the first half circuit Nhalf, the first switch K21 of the second half circuit Phalf and the interface load Load are working circuits. Therefore, the voltage of the interface load Load can be pulled up to the power supply voltage Vcc within this time, so that the energy storage devices (capacitors and inductors) in the interface load Load are discharged and restored to the no-load state.
  • the second stage (node B-node C):
  • Figure 12 is a schematic diagram of the working state of the differential interface circuit in the second stage of the control logic.
  • the first input signal is at a high level; the control signal en1 is a high signal to turn off the first switch K11 of the first half circuit Nhalf; and the control signal en2 is a low signal, so
  • the third switch K13 of the first half circuit Nhalf is turned off; the control signal en3 is a low signal to turn on the first switch K21 of the second half circuit Phalf; the control signal en4 is a high signal to make the third switch of the second half circuit Phalf
  • the switch K23 is turned on, and the output terminal of the operational amplifier Amp of the second half circuit Phalf is coupled to the ground through the third switch K23, so that the second switch K22 is turned off.
  • the operational amplifier Amp of the first half circuit Nhalf, the second switch K12, the feedback circuit, and the first switch K21 of the second half circuit Phalf and the interface load Load are the working circuits, which can be regarded as a traditional interface
  • the circuit can amplify and output the first input signal.
  • the third stage (node C-node D):
  • Fig. 13 is a schematic diagram of the working state of the differential interface circuit in the third stage of the control logic.
  • the first input signal changes from a falling edge to a low level;
  • the control signal en1 is a high signal to turn off the first switch K11 of the first half circuit Nhalf;
  • the control signal en2 is A low signal means that the third switch K13 of the first half circuit Nhalf is turned off and the second switch K12 is turned on;
  • the control signal en3 is a low signal, which turns on the first switch K21 of the second half circuit Phalf;
  • the control signal en4 is high
  • the signal turns on the third switch K23 of the second half circuit Phalf, and the output terminal of the operational amplifier Amp of the second half circuit Phalf is coupled to the ground through the third switch K23, so that the second switch K22 is turned off.
  • the operational amplifier Amp of the first half circuit Nhalf, the second switch K12, the feedback circuit, and the first switch K21 of the second half circuit Phalf and the interface load Load are the working circuits.
  • the first input signal is generated by the first half circuit Nhalf.
  • the operational amplifier Amp and the second switch K12 amplify the output, and the output signal Vout forms the solid line part in FIG. 13.
  • the fourth stage (node D-node E):
  • Fig. 14 is a schematic diagram of the working state of the differential interface circuit in the fourth stage of the control logic.
  • the first input signal starts to enter the rising edge;
  • the control signal en1 is a high signal, which makes the first switch K11 of the first half circuit Nhalf turn off;
  • the control signal en2 is a low signal, so The third switch K13 of the first half circuit Nhalf is turned off, and the second switch K12 is turned on;
  • the control signal en3 is a low signal, so that the first switch K21 of the second half circuit Phalf is turned on;
  • the control signal en4 is a high signal, so that the The third switch K23 of the second half circuit Phalf is turned on, and the output terminal of the operational amplifier Amp of the second half circuit Phalf is coupled to the ground through the third switch K23, so that the second switch K22 is turned off.
  • the operational amplifier Amp of the first half circuit Nhalf, the second switch K12, the feedback circuit, and the first switch K21 and interface load Load of the second half circuit Phalf are working circuits.
  • the amplification and output process of the first input signal is determined by The operational amplifier Amp and the second switch K12 are executed, and the output signal Vout forms the solid line part in FIG. 14.
  • Figure 15 is a schematic diagram of the working state of the differential interface circuit in the fifth stage of the control logic.
  • the first input signal continues to rise to the high level at the rising edge;
  • the control signal en1 is a low signal, so that the first switch K11 of the first half circuit Nhalf is turned on;
  • the control signal en2 Is a high signal, the third switch K13 of the first half circuit Nhalf is turned on, and the second switch K12 is turned off;
  • the control signal en3 is a low signal, and the first switch K21 of the second half circuit Phalf is turned on;
  • the control signal en4 is The high signal turns on the third switch K23 of the second half circuit Phalf, and the output terminal of the operational amplifier Amp of the second half circuit Phalf is coupled to the ground through the third switch K23, so that the second switch K22 is turned off.
  • the first switch K11 of the first half of the circuit Nhalf, the first switch K21 of the second half of the circuit Phalf, and the interface load Load are working circuits.
  • the voltage of the interface load Load is continuously pulled up to the supply voltage Vcc at this stage.
  • the energy storage devices (capacitors and inductors) in the load Load are discharged and return to the no-load state, and the output signal Vout forms the waveform of the solid line in FIG. 15.
  • the control logic for the differential interface circuit provided in the present application, when the first input signal is located in the first half of the rising edge (that is, before the TO time), the amplification and output process of the first input signal is performed by the first half circuit Nhalf The operational amplifier Amp and the second switch K12 are executed.
  • the first switch K11 of the first half circuit Nhalf and the first switch K11 of the second half circuit Phalf The switch K21 continues to increase the voltage of the interface load Load to the supply voltage Vcc, so that when the output signal is at the end of the rising edge, the operational amplifier Amp of the first half circuit Nhalf no longer participates in the amplification process of the first input signal. Therefore, it does not Will produce overshoot.
  • FIG. 16 is a schematic diagram of the output signal waveform of the differential interface circuit of this application. It can be seen from Figure 16 that the overshoot of the output signal is completely eliminated. It can be seen that the differential interface circuit provided by the present application can eliminate the overshoot phenomenon of the interface circuit and improve the reliability and service life of the interface circuit.

Abstract

La présente invention concerne un circuit d'interface, comprenant un amplificateur, un premier commutateur, un deuxième commutateur et un troisième commutateur, une extrémité d'entrée de l'amplificateur étant couplée à un nœud d'entrée du circuit d'interface, une extrémité de sortie de l'amplificateur étant couplée à une extrémité de commande du deuxième commutateur, l'extrémité de sortie de l'amplificateur étant en outre couplée à la terre au moyen du troisième commutateur, le premier commutateur et le deuxième commutateur étant connectés en série entre une tension d'alimentation électrique et la terre, et un nœud de sortie du circuit d'interface étant disposé entre le premier commutateur et le deuxième commutateur. Selon le circuit d'interface prévu par la présente invention, le nœud de sortie est couplé à une extrémité d'une charge d'interface, et l'autre extrémité de la charge d'interface est couplée à la tension d'alimentation électrique. Lorsqu'un signal d'entrée du circuit d'interface se trouve sur un front montant, le premier commutateur et le troisième commutateur sont éteints au niveau de la moitié avant du front montant et sont allumés au niveau de la moitié arrière du front montant, de sorte que l'amplificateur du circuit d'interface ne participe pas à un processus d'amplification de signal au niveau de la moitié arrière du front montant du signal d'entrée, ce qui permet d'éliminer un phénomène de dépassement et d'améliorer la fiabilité et la durée de vie du circuit d'interface.
PCT/CN2019/077113 2019-03-06 2019-03-06 Circuit d'interface WO2020177092A1 (fr)

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CN201980089091.1A CN113302570B (zh) 2019-03-06 2019-03-06 一种接口电路
PCT/CN2019/077113 WO2020177092A1 (fr) 2019-03-06 2019-03-06 Circuit d'interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/077113 WO2020177092A1 (fr) 2019-03-06 2019-03-06 Circuit d'interface

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WO2020177092A1 true WO2020177092A1 (fr) 2020-09-10

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Citations (3)

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TW200641577A (en) * 2005-05-31 2006-12-01 Phison Electronics Corp Adjusting apparatus
CN103076831B (zh) * 2012-12-20 2015-12-02 上海华虹宏力半导体制造有限公司 具有辅助电路的低压差稳压器电路
CN105700605A (zh) * 2014-12-11 2016-06-22 三星电子株式会社 基于反相放大器的双环电压调节器及其电压调节方法

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US4779270A (en) * 1987-04-15 1988-10-18 International Business Machines Corporation Apparatus for reducing and maintaining constant overshoot in a high speed driver
EP0547891B1 (fr) * 1991-12-17 2001-07-04 STMicroelectronics, Inc. Circuit d'attaque de sortie à précharge
CN102118155B (zh) * 2009-12-31 2013-01-09 群联电子股份有限公司 输入/输出接口的驱动电路
CN105024682A (zh) * 2015-05-31 2015-11-04 镇江天美信息科技有限公司 自动控制噪声的i/o接口驱动电路

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200641577A (en) * 2005-05-31 2006-12-01 Phison Electronics Corp Adjusting apparatus
CN103076831B (zh) * 2012-12-20 2015-12-02 上海华虹宏力半导体制造有限公司 具有辅助电路的低压差稳压器电路
CN105700605A (zh) * 2014-12-11 2016-06-22 三星电子株式会社 基于反相放大器的双环电压调节器及其电压调节方法

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