WO2020156161A9 - 数字模拟转换器、数字功放子系统、数字功放系统 - Google Patents

数字模拟转换器、数字功放子系统、数字功放系统 Download PDF

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Publication number
WO2020156161A9
WO2020156161A9 PCT/CN2020/072166 CN2020072166W WO2020156161A9 WO 2020156161 A9 WO2020156161 A9 WO 2020156161A9 CN 2020072166 W CN2020072166 W CN 2020072166W WO 2020156161 A9 WO2020156161 A9 WO 2020156161A9
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Prior art keywords
switch
digital
field effect
analog converter
signal
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PCT/CN2020/072166
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English (en)
French (fr)
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WO2020156161A1 (zh
Inventor
杨志飞
张海军
姚炜
杜黎明
程剑涛
Original Assignee
上海艾为电子技术股份有限公司
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Priority claimed from CN201910096697.XA external-priority patent/CN109842381A/zh
Priority claimed from CN201910097381.2A external-priority patent/CN109842382A/zh
Application filed by 上海艾为电子技术股份有限公司 filed Critical 上海艾为电子技术股份有限公司
Publication of WO2020156161A1 publication Critical patent/WO2020156161A1/zh
Publication of WO2020156161A9 publication Critical patent/WO2020156161A9/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for

Definitions

  • This application relates to the field of circuit technology, and in particular to a digital-to-analog converter, a digital power amplifier subsystem, and a digital power amplifier system.
  • the digital power amplifier has the advantages of low distortion, low noise, large dynamic range and strong anti-interference ability.
  • the advantages of transparency of sound quality, resolution, quietness of the background, and low-frequency shocking strength greatly exceed the traditional analog power amplifier and class D power amplifier.
  • the power supply is often not clean, and there are power supply ripples of different frequencies. If the power supply rejection ratio (PSRR) of the audio power amplifier chip is not good enough, the audio noise on the power supply will pass through the audio power amplifier chip Transmitted to the speaker, causing irritating audio noise, affecting the sense of voice or music listening.
  • PSRR power supply rejection ratio
  • embodiments of the present application provide a digital-to-analog converter to reduce the power supply rejection ratio of the digital power amplifier system, reduce output noise, and improve audio output quality when applied to a digital power amplifier system.
  • a digital-to-analog converter including:
  • the first constituent branch and the second constituent branch wherein the first end of the first constituent branch is connected to the voltage input end, and the second end is connected to the second constituent branch; the second constituent branch The first end is electrically connected to the first constituent branch, and the second end is grounded; the connection node of the first constituent branch and the second constituent branch serves as the signal output end of the digital-to-analog converter;
  • the first component branch includes: a first switch and a first current source connected in series, and the first current source includes: a fourth resistor, a first field effect tube, a second field effect tube, and a second operational amplifier, wherein ,
  • One end of the fourth resistor is the first end of the first current source, and the other end is electrically connected to the first end of the first field effect transistor;
  • the second end of the first field effect tube is electrically connected to the first end of the second field effect tube, and the control end of the first field effect tube is electrically connected to the output end of the second operational amplifier;
  • the inverting input terminal of the second operational amplifier is electrically connected to the first terminal of the first field effect transistor, the non-inverting input terminal is electrically connected to a first preset potential, and the first preset potential is equal to the voltage at the voltage input terminal
  • the output terminal is used for outputting a first bias voltage to the first field effect transistor to bias the first field effect transistor in a working state
  • the second end of the second field effect tube is the second end of the first current source, the control end of the second field effect tube is electrically connected to a second bias voltage, and the second bias voltage is used for Biasing the second field effect tube in a working state;
  • the second component branch includes: a second switch and a second current source connected in series, and the second current source includes: a fifth resistor, a third field effect tube, a fourth field effect tube, and a third operational amplifier, wherein ,
  • One end of the fifth resistor is the first end of the second current source, and the other end is electrically connected to the first end of the fourth field effect transistor;
  • the second end of the fourth field effect tube is electrically connected to the first end of the third field effect tube, and the control end of the fourth field effect tube is electrically connected to the output end of the third operational amplifier;
  • the inverting input terminal of the third operational amplifier is electrically connected to the first terminal of the fourth field effect transistor, and the non-inverting input terminal is electrically connected to a second preset potential, and the second preset potential is equal to the reference voltage ,
  • the output terminal is used to output a fourth bias voltage to bias the fourth field effect tube in a working state;
  • the second end of the third field effect transistor is the second end of the second current source, the control end of the third field effect transistor is electrically connected to a third bias voltage, and the third bias voltage is used for Biasing the third field effect tube in a working state;
  • the switching sequence of the first switch and the second switch are opposite.
  • the first field effect tube and the second field effect tube are P-type field effect tubes
  • the third field effect tube and the fourth field effect tube are N-type field effect tubes.
  • the resistance values of the fourth resistor and the fifth resistor are the same.
  • the first switch is located between the voltage input terminal and the first current source; the second switch is located between the ground terminal and the second current source.
  • the first current source is located between the voltage input terminal and the first switch; the second current source is located between the ground terminal and the second switch.
  • the switching state of the first switch is controlled by a first input signal
  • the switching state of the second switch is controlled by a second input signal
  • the first switch and the second switch are transistors of the same type, so The first input signal and the second input signal are square wave signals with opposite phases.
  • the switch state of the first switch is controlled by a first input signal
  • the switch state of the second switch is controlled by a second input signal
  • the first switch and the second switch are transistors of different types, so The first input signal and the second input signal are square wave signals with the same phase.
  • it also includes:
  • a third switch one end of the third switch is electrically connected to the common end of the first switch and the first current source, and the other end is electrically connected to the common mode voltage input end;
  • one end of the fourth switch is electrically connected to the common end of the second switch and the second current source, and the other end is electrically connected to the common mode voltage input end.
  • the switch state of the third switch is controlled by the second input signal
  • the switch state of the fourth switch is controlled by the first input signal
  • the first switch and the fourth switch are of the same type
  • the second switch and the third switch are transistors of the same type.
  • the embodiment of the present application also provides a digital power amplifier subsystem, including:
  • the digital-to-analog converter, the first operational amplifier, the integrator, the PWM comparator, the driver, the first resistor and the first capacitor provided by any one of the above, wherein:
  • the signal output terminal of the digital-to-analog converter is connected to the inverted signal input terminal of the first operational amplifier, and the non-inverted signal input terminal of the first operational amplifier is used to receive a common-mode voltage signal.
  • the signal output terminal of the amplifier is connected to the signal input terminal of the integrator;
  • the signal output terminal of the integrator is connected to the signal input terminal of the PWM comparator, the signal output terminal of the PWM comparator is connected to the signal input terminal of the driver, and the signal output terminal of the driver serves as the above-mentioned digital power amplifier The signal output terminal of the subsystem;
  • One end of the first resistor is connected to the connection node of the digital-to-analog converter and the first operational amplifier, and the other end of the first resistor is connected to the signal output terminal of the driver;
  • One end of the first capacitor is connected to the connection node of the first operational amplifier and the digital-to-analog converter, and the other end of the first capacitor is connected to the connection node of the first operational amplifier and the integrator .
  • the common-mode voltage signal may be one-half of the voltage signal input from the voltage input terminal received by the digital-to-analog converter.
  • the digital power amplifier system includes a first digital power amplifier subsystem and a second digital power amplifier subsystem, wherein the first digital power amplifier subsystem is a VOP channel; the second digital power amplifier subsystem is a VON aisle;
  • At least one of the first digital power amplifier subsystem and the second digital power amplifier subsystem adopts the digital power amplifier subsystem provided by any one of the foregoing.
  • the digital-to-analog converter provided by the embodiment of the present application When the digital-to-analog converter provided by the embodiment of the present application is applied to a digital power amplifier system, the equivalent output impedance of the digital-to-analog converter is greatly increased, and the power supply rejection ratio of the digital power amplifier system is reduced.
  • the digital-to-analog converter when it is applied to a digital power amplifier system, it can not only adjust the first field effect tube, the second field effect tube, the third field effect tube, and the fourth field effect tube.
  • the resistance or transconductance of the tube increases the equivalent impedance of the digital-to-analog converter, and the equivalent impedance of the digital-to-analog converter can also be increased by adjusting the resistance values of the fourth resistor and the fifth resistor, It is also possible to increase the equivalent impedance of the digital-to-analog converter by adjusting the gains of the second operational amplifier and the third operational amplifier, thereby further reducing the power supply rejection ratio of the digital power amplifier system and improving the digital The noise signal suppression capability of the power amplifier system.
  • FIG. 1 is a schematic structural diagram of a digital power amplifier system using a digital-to-analog converter according to an embodiment of the application;
  • Figure 2 is a schematic structural diagram of a digital power amplifier subsystem provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a digital-to-analog converter provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of an equivalent circuit of a digital-to-analog converter provided by an embodiment of the application;
  • FIG. 5 is a schematic structural diagram of a digital-to-analog converter provided by another embodiment of the application.
  • FIG. 6 is a schematic structural diagram of a digital-to-analog converter provided by another embodiment of this application.
  • FIG. 7 is a schematic structural diagram of a digital power amplifier subsystem provided by another embodiment of the application.
  • FIG. 8 is a waveform comparison of the first input signal PWM_P, the second input signal /PWM_P, the common mode voltage signal VCM, the output signal DAC_VOP of the digital-to-analog converter and the output signal VOP of the digital power amplifier subsystem Schematic.
  • FIG. 1 is a schematic structural diagram of a digital power amplifier system in which a digital-to-analog converter is applied in an embodiment of the application, which is used to convert a PWM signal processed by a digital module into an analog signal, which includes a VOP
  • a digital-to-analog converter is applied in an embodiment of the application, which is used to convert a PWM signal processed by a digital module into an analog signal, which includes a VOP
  • VOP the working principles of the two channels of VOP and VON are similar, the following takes the digital power amplifier subsystem of the VOP channel as an example for illustration.
  • FIG. 2 is a schematic structural diagram of a digital power amplifier subsystem of a VOP channel provided by an embodiment of the application.
  • the digital power amplifier subsystem of the VOP channel includes: a digital-analog converter DAC, a first operational amplifier AMP1, and an integral The inverter 21, the PWM comparator 22, the driver 23, the first resistor RF and the capacitor C1, and the common mode voltage signal generating module 24.
  • the signal output terminal of the digital-to-analog converter DAC (that is, the port that outputs the DAC_VOP signal) is connected to the inverting input terminal of the first operational amplifier AMP1, and the non-inverting input terminal of the first operational amplifier AMP1 is connected to the inverting input terminal of the first operational amplifier AMP1.
  • the output terminal (port for outputting the VCM signal) of the common mode voltage signal generating module 24 is connected, and the output terminal AMP_VP1 of the first operational amplifier AMP1 is connected to the input terminal of the integrator 21.
  • the output terminal of the integrator 21 is connected to the input terminal of the PWM comparator 22, the output terminal PWM_P2 of the PWM comparator 22 is connected to the input terminal of the driver 23, and the output terminal of the driver serves as the digital The signal output terminal of the power amplifier subsystem outputs the VOP signal.
  • One end of the first resistor RF is connected to the inverting input end of the first operational amplifier AMP1, and the other end of the first resistor RF is connected to the output end of the driver.
  • One end of the capacitor C1 is connected to the inverting input terminal of the first operational amplifier AMP1, and the other end of the capacitor C1 is connected to the output terminal AMP_VP1 of the first operational amplifier AMP1.
  • the common mode voltage signal generating module 24 includes a second resistor R1 and a third resistor R2, wherein one end of the second resistor R1 is connected to the voltage input terminal VDD, and the other end of the second resistor R1 is connected to the voltage input terminal VDD.
  • One end of the third resistor R2 is connected; the other end of the third resistor R1 is connected to the ground terminal GND; the connection node of the second resistor R1 and the third resistor R2 serves as the common mode voltage generating module 24
  • the signal output by the common-mode voltage signal generating module 24 is the common-mode voltage signal VCM.
  • the signal output end of the digital power amplifier subsystem forms a negative feedback loop through the first resistor RF, the first operational amplifier AMP1, the integrator 21, the PWM comparator 22, and the driver 23, and the digital power amplifier The signal distortion and power supply noise of the subsystem are suppressed.
  • the inventor found through analysis that for the digital power amplifier subsystem of the above-mentioned VOP channel, the loop gain of the digital power amplifier subsystem is very high because the power rejection ratio of the digital-analog converter DAC and the power rejection ratio of the first operational amplifier AMP1 are very high.
  • the power supply noise in the negative feedback loop of the digital power amplifier subsystem can often be well suppressed, which is not the key to affecting the power supply rejection ratio of the digital power amplifier subsystem, and the common mode voltage signal generation module
  • the output terminal to the signal output terminal of the digital power amplifier subsystem forms a co-directional amplifier, and the voltage disturbance on the output terminal of the common-mode voltage signal generating module is amplified in the same direction, which is the key to affecting the power supply rejection ratio of the digital sub-power amplifier system .
  • the digital power amplifier subsystem of the VON channel is the same as the digital power amplifier subsystem of the VOP channel, and will not be explained here.
  • the voltage signal VCM output by the common-mode voltage signal generating module 24 is obtained by dividing the voltage input terminal VDD through the second resistor R1 and the third resistor R2, which is specifically:
  • r0P_dac represents the equivalent output impedance of the digital-analog converter DAC of the VOP channel
  • r0N_dac represents the equivalent output impedance of the digital-analog converter DAC of the VON channel
  • RFP represents the RF resistance of the VOP channel (that is, the first resistance)
  • RFN represents The RF resistance of the VON channel
  • ⁇ VDD represents the fluctuation of the voltage signal VDD received by the digital-to-analog converter DAC.
  • the output fluctuation of the digital power amplifier system is:
  • the output fluctuation of the digital power amplifier system is:
  • the mismatch coefficient ⁇ 1 satisfies the following conditions:
  • r0P_dac (1+ ⁇ 1 )*r0N_dac
  • the mismatch coefficient ⁇ 2 satisfies the following conditions:
  • the power supply rejection ratio PSRR of the digital power amplifier system is:
  • RF represents the resistance value of the RF resistance of the VOP channel or the VON channel
  • r0_dac represents the equivalent output impedance of the digital-to-analog converter DAC of the VOP channel or the VON channel.
  • the power supply rejection ratio in this application document is the ratio of the output fluctuation of the digital power amplifier system to the fluctuation of the voltage signal VDD received by the digital-analog converter DAC.
  • the equivalent output impedance r0_dac of the digital-to-analog converter DAC is on the denominator of the formula, that is, the greater the equivalent output impedance r0_dac of the digital-to-analog converter DAC, the greater the digital power amplifier
  • the power supply rejection ratio of the system is the PSRR, the better the power supply noise rejection capability of the digital power amplifier system.
  • an embodiment of the present application provides a digital-to-analog converter, a digital power amplifier subsystem including the digital-to-analog converter, and a digital power amplifier system including the digital power amplifier subsystem.
  • the digital-to-analog converter provided by the embodiment of the present application includes: a first constituent branch and a second constituent branch, wherein the first end of the first constituent branch is connected to the voltage input terminal VDD, The second end is connected to the second constituent branch; the first end of the second constituent branch is electrically connected to the first constituent branch, and the second end is grounded; the first constituent branch is connected to the first constituent branch.
  • Two connecting nodes forming branches serve as the signal output end of the digital-analog converter DAC, and output the DAC_VOP signal;
  • the first component branch includes: a first switch S1 and a first current source IDAC1 connected in series, and the first current source IDAC1 includes: a fourth resistor RS1, a first field effect tube M1, a second field effect tube M2, and The second operational amplifier AMP2, in which,
  • One end of the fourth resistor RS1 is the first end of the first current source IDAC1, and the other end is electrically connected to the first end of the first field effect transistor M1;
  • the second end of the first field effect tube M1 is electrically connected to the first end of the second field effect tube M2, and the control end of the first field effect tube M1 is connected to the output end of the second operational amplifier AMP2. Electrical connection
  • the inverting input terminal of the second operational amplifier AMP2 is electrically connected to the first terminal of the first field effect transistor M1, and the non-inverting input terminal is electrically connected to a first preset potential, and the first preset potential is equal to the voltage input
  • the difference between the voltage of the terminal VDD and the reference voltage VREF, and the output terminal is used to output a first bias voltage VBP1 to the first field effect transistor to bias the first field effect transistor in a working state;
  • the second end of the second field effect transistor M2 is the second end of the first current source IDAC1, the control end of the second field effect transistor M2 is electrically connected to a second bias voltage VBP2, and the second bias voltage
  • the setting voltage VBP2 is used to bias the second field effect transistor in a working state
  • the second component branch includes: a second switch S2 and a second current source IDAC2 connected in series, and the second current source IDAC2 includes: a fifth resistor RS2, a third field effect transistor M3, a fourth field effect transistor M4, and The third operational amplifier AMP3, in which,
  • One end of the fifth resistor RS2 is the first end of the second current source IDAC2, and the other end is electrically connected to the first end of the fourth field effect transistor M4;
  • the second end of the fourth field effect tube M4 is electrically connected to the first end of the third field effect tube M3, and the control end of the fourth field effect tube M4 is connected to the output end of the third operational amplifier AMP3. Electrical connection
  • the inverting input terminal of the third operational amplifier AMP3 is electrically connected to the first terminal of the fourth field effect transistor M4, and the non-inverting input terminal is electrically connected to a second preset potential, and the second preset potential is equal to a reference voltage VREF, the output terminal outputs a fourth bias voltage VBN2 to bias the fourth field effect transistor in the working state;
  • the second end of the third field effect transistor M3 is the second end of the second current source IDAC2, the control end of the third field effect transistor M3 is electrically connected to a third bias voltage VBN1, and the third bias voltage
  • the setting voltage VBN1 is used to bias the third field effect transistor in the working state.
  • the first bias voltage VBP1 is generated by the second operational amplifier AMP2
  • the fourth bias voltage VBN2 is generated by the third operational amplifier AMP3
  • the first bias voltage VBP1 and the fourth bias voltage are
  • the set voltage VBN2 respectively provides voltages to the grids of the first field effect transistor M1 and the fourth field effect transistor M4 to form a mirror current source and increase the output impedance of the digital-to-analog converter.
  • the second bias voltage VBP2 and the third bias voltage VBN1 are generated by additional current generating branches, and are provided to the first The control ends of the second field effect tube M2 and the third field effect tube M3 form a mirror current source to increase the output impedance of the digital-to-analog converter.
  • the digital-to-analog converter may also include a second bias voltage generating circuit and a third bias voltage generating circuit, so that the The second bias voltage and the third bias voltage are generated inside the digital-to-analog converter, depending on the situation.
  • both the first current source and the second current source adopt a cascode structure, so that the first current source and the second current source can be improved.
  • the output impedance and stability of the source thereby improving the power supply suppression capability of the digital-to-analog converter, and reducing the impact of the DAC_VOP signal output by the output terminal of the digital-to-analog converter on the first current source and the second current source Impact.
  • the first field effect tube and the second field effect tube are P-type field effect tubes
  • the fourth field effect tube is an N-type field effect tube, which is not limited in this application, and it depends on the actual situation.
  • the fourth resistor RS1 and the fifth resistor RS2 are the same, so that the current IDAC1 of the first constituent branch and the current IDAC2 of the second constituent branch are equal.
  • the second operational amplifier AMP2 the first field effect tube M1 and the fourth resistor RS1 form source negative feedback to generate current
  • the third operational amplifier AMP3 the fourth field effect tube M4 and the fifth resistor RS2 forms source negative feedback to generate current, and its current value is:
  • RS1,2 represents the resistance of RS1 or RS2, and the resistance values of RS1 and RS2 are the same.
  • the current source IDAC1 corresponding to the first field effect tube M1 and the current source IDAC2 corresponding to the third field effect tube M3 should be ensured as far as possible
  • the process variation and different temperatures are almost equal to ensure that when the first input signal PWM_P is 50% duty cycle, the VOP signal output from the digital power amplifier subsystem output terminal is also 50% duty cycle, so that the digital power amplifier subsystem outputs
  • the output DC voltage at the terminal is VDD/2.
  • the switching state of the first switch S1 is controlled by the first input signal PWM_P
  • the switching state of the second switch S2 is controlled by the second input signal /PWM_P
  • the The switching timings of the first switch S1 and the second switch S2 are reversed.
  • the first input signal PWM_P and the second input signal /PWM_P are obtained by the digital module in the digital power amplifier system after the received digital input signals such as I2S and TDM undergo sound effect processing, digital gain amplification and digital filtering, usually
  • the PWM signal is a square wave signal.
  • the switching sequence of the first switch S1 and the second switch S2 is reversed, which means that in the same time period, when the first switch S1 is in the closed state, the second switch S2 is in the closed state.
  • the second switch S2 In the off state, when the first switch S1 is in the off state, the second switch S2 is in the closed state, so that the mirror current generated by the first current source IDAC1 or the second current source IDAC2 is output as an output signal.
  • the switching timings of the first switch S1 and the second switch S2 can be reversed by controlling the types of the first switch S1 and the second switch S2, and the first input signal PWM_P and the second switch S2. Two input signal /PWM_P phase to achieve.
  • the first switch S1 and the second switch S2 are transistors of the same type, that is, they are in the same state when simultaneously receiving high-level or low-level signals.
  • the first input signal PWM_P and the second input signal /PWM_P are square wave signals with opposite phases; in another embodiment of the present application, the first switch S1 and the second switch S2 are transistors of different types That is, when receiving high-level or low-level signals at the same time, the state is reversed.
  • the first input signal PWM_P and the second input signal /PWM_P may be square wave signals with the same phase. This application does not limit this, and it depends on the situation.
  • FIG. 4 shows a schematic diagram of an equivalent circuit of a digital-to-analog converter provided by an embodiment of the present application. It can be seen from FIG. 4 that the equivalent output impedance r0_dac of the digital-to-analog converter provided by the embodiment of the present application is:
  • r0_dac (gm_N1*ro3*AV3*gm_N2*ro4*RS2) ⁇ (gm_P2*ro2*AV2*gm_P1*ro1*RS1)
  • gm_N1 represents the transconductance of the third FET
  • gm_N2 represents the transconductance of the fourth FET
  • gm_P1 represents the transconductance of the first FET
  • gm_P2 represents the transconductance of the second FET
  • ro1 represents the first The equivalent resistance of the FET
  • ro2 represents the equivalent resistance of the second FET
  • ro3 represents the equivalent resistance of the third FET
  • ro4 represents the equivalent resistance of the fourth FET
  • AV3 represents the third operational amplifier
  • the gain of AV2 represents the gain of the third operational amplifier.
  • the digital-to-analog converter provided by the embodiment of the present application, when applied to a digital power amplifier system, greatly increases the equivalent output impedance of the digital-to-analog converter, and reduces the power supply rejection ratio of the digital power amplifier system. .
  • the digital-to-analog converter when it is applied to a digital power amplifier system, it can not only adjust the first field effect tube, the second field effect tube, the third field effect tube, and the fourth field effect tube).
  • the resistance or transconductance of the tube increases the equivalent impedance of the digital-to-analog converter, and the equivalent impedance of the digital-to-analog converter can also be increased by adjusting the resistance values of the fourth resistor and the fifth resistor, It is also possible to increase the equivalent impedance of the digital-to-analog converter by adjusting the gains of the second operational amplifier and the third operational amplifier, thereby further reducing the power supply rejection ratio of the digital power amplifier system and improving the digital The noise signal suppression capability of the power amplifier system.
  • the first switch S1 is located between the voltage input terminal VDD and the first current source IDAC1, that is, The first end of the first current source IDAC1 is electrically connected to the first switch S1, the second end of the first current source IDAC1 is electrically connected to the second constituent branch, and the other of the first switch S1 One end is electrically connected to the voltage input terminal VDD; in another embodiment of the present application, as shown in FIG.
  • the first current source IDAC1 is located between the voltage input terminal VDD and the first switch S1, namely The first end of the first current source IDAC1 is electrically connected to the voltage input end, the second end of the first current source IDAC1 is electrically connected to the first switch S1, and the other end of the first switch S1 is electrically connected to the voltage input end.
  • the second constituent branch is electrically connected.
  • the second switch S2 is located between the ground terminal GND and the second current source IDAC2, That is, the first end of the second current source IDAC2 is electrically connected to the second switch S2, the second end of the second current source IDAC2 is electrically connected to the first constituent branch, and the second switch S2 The other end of is electrically connected to the ground terminal GND; in another embodiment of the present application, as shown in FIG.
  • the second current source IDAC2 is located between the ground terminal GND and the second switch S2, namely The first end of the second current source IDAC2 is electrically connected to the ground terminal GND, the second end of the second current source IDAC2 is electrically connected to the second switch S2, and the other end of the second switch S2 is electrically connected to the ground.
  • the first constituent branch is electrically connected.
  • the first current source IDAC1 is located between the voltage input terminal VDD and the first switch S1
  • the second current source IDAC2 is located between the ground terminal GND and the first switch S1.
  • the clock feedthrough effect and channel charge injection phenomenon generated during the switching process of the first switch S1 and the second switch S2 can be prevented from crossing the first current source IDAC1 and the second current
  • the source IDAC2 is loaded in the output signal of the digital-to-analog converter, thereby avoiding the clock feedthrough effect and channel charge injection phenomenon caused by the first switch S1 and the second switch S2 during the switching process on the output signal of the digital-to-analog converter
  • the undesirable influence of the digital power amplifier system reduces the output noise of the digital power amplifier system.
  • the digital-to-analog converter further includes:
  • the third switch S3, one end of the third switch S3 is electrically connected to the common end of the first switch S1 and the first current source IDAC1, and the other end is electrically connected to the common mode voltage input end, the common mode voltage input Input common mode voltage signal VCM at the end;
  • the fourth switch S4, one end of the fourth switch S4 is electrically connected to the common end of the second switch S2 and the second current source IDAC2, and the other end is electrically connected to the common mode voltage input end. .
  • the switching state of the third switch S3 is controlled by the second input signal /PWM_P
  • the switching state of the fourth switch S4 is controlled by the first input signal PWM_P
  • the switching states of the first switch S1 and the fourth switch S4 are both controlled by the first input signal PWM_P
  • the switching states of the second switch S2 and the third switch S3 are both controlled by the second input.
  • Signal/PWM_P control, and the switching timings of the first switch S1 and the second switch S2 are opposite, the switching timings of the first switch S1 and the third switch S3 are opposite, and the second switch S2 and the first switch S2 are opposite to each other.
  • the switching sequence of the four switch S4 is reversed.
  • the first input signal PWM_P and the second input signal /PWM_P are obtained by the digital module in the digital power amplifier system after the received digital input signals such as I2S and TDM undergo sound effect processing, digital gain amplification and digital filtering, usually
  • the PWM signal is a square wave signal.
  • the switching sequence of the first switch S1 and the second switch S2 is reversed, which means that in the same time period, when the first switch S1 is in the closed state, the second switch S2 is in the closed state.
  • the second switch S2 In the off state, when the first switch S1 is in the off state, the second switch S2 is in the closed state, so that the mirror current generated by the first current source IDAC1 or the second current source IDAC2 is output as an output signal.
  • the switching timings of the first switch S1 and the third switch S3 are reversed, which means that in the same time period, when the first switch S1 is in the closed state, the third switch S3 is in the off state, and when the When the first switch S1 is in the off state, the third switch S3 is in the closed state, so that the voltage at the connection node VA of the first switch S1 and the third switch S3 is Maintain the voltage value at the common-mode voltage input terminal without random fluctuations.
  • the first preset voltage is greater than the voltage at the common-mode voltage input terminal, that is, VDD-VREF>VCM, so that the first switch S1 is turned off, During the closing period of the third switch S3, no current flows in the first field effect tube of the current mirror tube, and during the period when the first switch S1 is closed and the third switch S3 is open, the first field effect tube M1 of the current mirror tube can be Turn on faster, and current IDAC1 flows to avoid unnecessary delay.
  • the third switch S3 is closed before the first switch S1 is completely opened, thereby reducing the first switch S1 and the first switch S1.
  • the switching timings of the second switch S2 and the fourth switch S4 are reversed, which means that in the same time period, when the second switch S2 is in the closed state, the fourth switch S4 is in the off state, When the second switch S2 is in the off state, the fourth switch S4 is in the closed state, so that during the period when the second switch S2 is off, the fourth switch S4 is closed so that the second switch S2 and the second switch S4 are closed.
  • the voltage of the connection node VB of the fourth switch S4 is maintained at the voltage value of the common-mode voltage input terminal without random fluctuation.
  • the second preset voltage is less than the voltage at the common-mode voltage input terminal, that is, VREF ⁇ VCM, so that the second switch S2 is turned off, and the fourth During the period when the switch S4 is closed, no current flows in the third field effect tube of the current mirror tube, and during the period when the second switch S2 is closed and the fourth switch S4 is open, the third field effect tube M3 of the current mirror tube can be faster Turning on, the current IDAC2 flows to avoid unnecessary delay.
  • the fourth switch S4 is closed before the second switch S2 is completely opened, thereby reducing the second switch S2 and the second switch S2.
  • the switching timing of the first switch S1 and the third switch S3 can be reversed by controlling the types of the first switch S1 and the third switch S3, and the first input signal PWM_P and the first input signal PWM_P. Two input signal /PWM_P phase to achieve.
  • the first switch S1 and the third switch S3 are transistors of the same type, that is, they are in the same state when simultaneously receiving high-level or low-level signals.
  • the first input signal PWM_P and the second input signal /PWM_P are square wave signals with opposite phases; in another embodiment of the present application, the first switch S1 and the third switch S3 are transistors of different types That is, when receiving high-level or low-level signals at the same time, the state is reversed.
  • the first input signal PWM_P and the second input signal /PWM_P may be square wave signals with the same phase. This application does not limit this, and it depends on the situation.
  • the switching timings of the second switch S2 and the fourth switch S4 can be reversed by controlling the types of the second switch S2 and the fourth switch S4, and the phases of the first input signal PWM_P and the second input signal /PWM_P. .
  • the second switch S2 and the fourth switch S4 are transistors of the same type, that is, they are in the same state when simultaneously receiving high-level or low-level signals.
  • the first input signal PWM_P and the second input signal /PWM_P are square wave signals with opposite phases; in another embodiment of the present application, the second switch S2 and the fourth switch S4 are transistors of different types That is, when receiving high-level or low-level signals at the same time, the state is reversed.
  • the first input signal PWM_P and the second input signal /PWM_P may be square wave signals with the same phase. This application does not limit this, and it depends on the situation.
  • the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are all transistors of the same type.
  • the The first input signal PWM_P and the second input signal /PWM_P are square wave signals with opposite phases; in another embodiment of the present application, the first switch S1 and the fourth switch S4 are transistors of the same type, so The second switch S2 and the third switch S3 are transistors of the same type, the first switch S1 and the third switch S3 are transistors of different types, and the second switch S2 and the fourth switch S4 are transistors of different types.
  • the first input signal PWM_P and the second input signal /PWM_P are square wave signals with the same phase.
  • the first input signal PWM_P is a pulse width modulated square wave signal whose duty cycle is proportional to the amplitude of the input signal.
  • an embodiment of the present application also provides a digital power amplifier subsystem.
  • the digital power amplifier subsystem includes:
  • the digital-to-analog converter DAC, the first operational amplifier AMP1, the integrator 31, the PWM comparator 32, the driver 33, the first resistor RF and the first capacitor C1 provided by any of the above embodiments, wherein:
  • the signal output terminal of the digital-to-analog converter is connected to the inverted signal input terminal of the first operational amplifier, and the non-inverted signal input terminal of the first operational amplifier is used to receive a common mode voltage signal VCM.
  • the signal output terminal of the operational amplifier is connected to the signal input terminal of the integrator;
  • the signal output terminal of the integrator is connected to the signal input terminal of the PWM comparator, the signal output terminal of the PWM comparator is connected to the signal input terminal of the driver, and the signal output terminal of the driver serves as the above-mentioned digital power amplifier
  • the signal output terminal of the subsystem outputs the VOP signal
  • One end of the first resistor RF is connected to the connection node of the digital-to-analog converter and the first operational amplifier, and the other end of the first resistor RF is connected to the signal output terminal of the driver;
  • One end of the first capacitor C1 is connected to the connection node of the first operational amplifier and the digital-to-analog converter, and the other end of the first capacitor C1 is connected to the first operational amplifier and the integrator. Connect the nodes.
  • the first input signal PWM and the second input signal/PWM are the PWM that the digital module converts the received digital input signals such as I2S, TDM, etc., through sound effect processing, digital gain amplification, and digital filtering.
  • the PWM signal is processed by a digital-to-analog converter DAC, and then outputs a PWM square wave after passing through an integrator, a PWM comparator, and a driving module, so as to realize the amplification of the analog gain, thereby greatly improving the digital application of the digital power amplifier subsystem.
  • the power supply suppression capability of the audio power amplifier of the power amplifier system is the PWM that the digital module converts the received digital input signals such as I2S, TDM, etc., through sound effect processing, digital gain amplification, and digital filtering.
  • the PWM signal is processed by a digital-to-analog converter DAC, and then outputs a PWM square wave after passing through an integrator, a PWM comparator, and a driving module, so as to realize the
  • the phases of the first input signal PWM_P and the second input signal /PWM_P are opposite.
  • the first switch S1 is closed, the second switch S2 is open, and the PWM_P is low.
  • the first switch S1 is open and the second switch S2 is closed as an example to describe the working principle of the above-mentioned digital power amplifier subsystem.
  • the first current source IDAC1 charges the first resistor RF and the capacitor plate electrically connected to the first capacitor C1 and the inverting output terminal of the first operational amplifier AMP1, and the output terminal of the first operational amplifier AMP1 charges the first operational amplifier AMP1.
  • the capacitor plate electrically connected to the output terminal of the first operational amplifier AMP1 is discharged, the output voltage AMP_V1 of the first operational amplifier AMP1 is reduced, and the output terminal of the digital power amplifier subsystem is output through the integrator, PWM comparator and driver The signal VOP is low level;
  • the first switch S1 When the PWM_P is at low level, the first switch S1 is opened and the second switch S2 is closed. At this time, the second current source IDAC2 in the digital-to-analog converter acts on the first resistor RF and the first capacitor C1.
  • the capacitor plate electrically connected to the inverting output terminal of the first operational amplifier AMP1 discharges, and the output terminal of the first operational amplifier AMP1 discharges the capacitor plate electrically connected to the first capacitor and the output terminal of the first operational amplifier AMP1.
  • the output voltage AMP_V1 of the first operational amplifier AMP1 increases, and through the integrator, the comparator, and the driver, the signal VOP output by the output terminal of the digital power amplifier subsystem is at a high level.
  • the output signal AMP_V1 of the first operational amplifier AMP1 is a triangular wave signal, and the digital sub-power amplifier system
  • the VOP signal output by the output terminal is a square wave signal, and then after low-pass filtering or the low-pass filtering characteristics of the speaker itself, the audio signal is restored.
  • FIG. 8 shows the first input signal PWM_P, the second input signal /PWM_P, the common mode voltage signal VCM, the output signal DAC_VOP of the digital-to-analog converter and the digital power amplifier
  • the waveform comparison diagram of the output signal VOP of the system As can be seen from FIG. 8, the first input signal PWM_P and the second input signal /PWM_P are input signals with opposite phases. Through the negative feedback of the loop, the digital simulation The DAC_VOP signal output from the output of the converter fluctuates up and down around VCOM to adjust the loop error signal.
  • the output signal of the digital-analog converter and the output signal of the digital power amplifier subsystem are relative to the first input signal PWM_P and the second input signal.
  • the response of the signal/PWM_P has a certain delay LD (Loop Delaytime).
  • the DAC_VOP-VCM differential signal
  • the DAC_VOP signal output from the digital-to-analog converter output has a very high ripple with respect to the common-mode voltage signal VCM. It is small, so that the DAC_VOP signal output from the output terminal of the digital-to-analog converter has small fluctuations centered on the common-mode voltage signal VCM, which greatly improves the output stability of the digital-to-analog converter.
  • the common-mode voltage signal may be the value of the voltage signal input from the voltage input terminal VDD received by the digital-to-analog converter. One-third or one-quarter, etc., depending on the situation.
  • the digital power amplifier subsystem further includes a common mode voltage signal generating module to generate the common mode voltage signal VCM.
  • the common-mode voltage signal generating module includes a second resistor and a third resistor connected in series, wherein an end of the second resistor away from the third resistor is electrically connected to the For the voltage input terminal VDD, one end of the third resistor away from the second resistor is grounded, and the connection node of the second resistor and the third resistor is electrically connected to the non-inverting input terminal of the first operational amplifier.
  • the common-mode voltage signal generating module may also generate the common-mode voltage signal in other ways, depending on the situation.
  • Din is the high-level duty cycle of the first input signal PWM_P or the second input signal/PWM_P
  • IDAC represents the current value generated by the first current source IDAC1 or the second current source IDAC2
  • RF represents the current value generated by the first current source IDAC1 or the second current source IDAC2.
  • the resistance value of the first resistor RF is the resistance value of the first resistor RF.
  • an embodiment of the present application also provides a digital power amplifier system.
  • the digital power amplifier system includes a first digital power amplifier subsystem and a second digital power amplifier subsystem, wherein the first digital power amplifier subsystem is a VOP channel;
  • the second digital power amplifier subsystem is a VON channel; at least one of the first digital power amplifier subsystem and the second digital power amplifier subsystem adopts the digital power amplifier subsystem provided by any one of the above-mentioned embodiments of this application .
  • the digital-to-analog converter, the digital power amplifier subsystem including the digital-to-analog converter, and the digital power amplifier system including the digital-to-analog converter greatly increase the The equivalent output impedance reduces the power supply rejection ratio of the digital power amplifier system.
  • the digital-to-analog converter, the digital power amplifier subsystem including the digital-to-analog converter, and the digital power amplifier system including the digital power amplifier subsystem can not only adjust the first FET, the second The resistance or transconductance of the second field effect tube, the third field effect tube, and the fourth field effect tube increases the equivalent impedance of the digital-to-analog converter. It is also possible to adjust the fourth resistance and the fifth resistance.
  • the resistance value increases the equivalent impedance of the digital-to-analog converter, and the equivalent impedance of the digital-to-analog converter can also be increased by adjusting the gains of the second operational amplifier and the third operational amplifier, thereby further reducing The power supply rejection ratio of the digital power amplifier system is reduced, and the noise signal suppression capability of the digital power amplifier system is improved.

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Abstract

一种数字模拟转换器、数字功放子系统、数字功放系统，该数字转换器包括：第一组成支路和第二组成支路，所述第一组成支路包括：串联的第一开关(S1)和第一电流源(IDAC1)，所述第一电流源(IDAC1)包括：第四电阻(RS1)、第一场效应管(M1)、第二场效应管(M2)和第二运算放大器(AMP2)，所述第二组成支路包括：串联的第二开关(S2)和第二电流源(IDAC2)，所述第二电流源(IDAC2)包括：第五电阻(RS2)、第三场效应管(M3)、第四场效应管(M4)和第三运算放大器(AMP3)，从而在应用于数字功放系统时，大大增加了所述数字模拟转换器的等效输出阻抗，降低了所述数字功放系统的电源抑制比。

Description

数字模拟转换器、数字功放子系统、数字功放系统
本申请要求于2019年01月31日提交中国专利局、申请号为201910096697.X、发明名称为“数字模拟转换器、数字功放子系统、数字功放系统”以及于2019年01月31日提交中国专利局、申请号为201910097831.2、发明名称为“数字模拟转换器、数字功放子系统、数字功放系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电路技术领域，尤其涉及一种数字模拟转换器、数字功放子系统、数字功放系统。
背景技术
数字功放具有失真小、噪音低、动态范围大和抗干扰能力强等优点，在音质的透明度、解析力、背景的宁静以及低频的震撼力度方面的优势大大超过传统的模拟功放和class D功放。
随着DVD家庭影院、迷你音响系统、机顶盒、个人电脑、LCD电视、平板显示器和移动电话等消费类产品的更新，尤其是SACD、DVD Audio等一些高采样频率的新音源规格的出现，以及音响系统从立体声到多声道环绕系统的进化，都加速了数字功放的发展。
在数字功放领域，现有针对HIFI发烧友而出现了一种新的名词“纯数字功放”，其支持很多数字音频格式信号输入，如12S和TDM等，其可以经 过数字DSP处理，实现丰富的音效算法，有很强的RF抗干扰能力，用在手机上，具有天然的优势，数字信号在传输过程中不会带来相位延迟、相位失真和交越失真等问题，听感的好处就是声音会更通透、定位更准以及声音更接近真实。
但是，在一些应用系统中，电源往往不太干净，有不同频率的电源纹波，若音频功放芯片的电源抑制比(PSRR)做得不够好的话，电源上的音频噪声就会通过音频功放芯片传送到喇叭上，引起烦躁的音频噪声，影响语音或音乐听感。
发明内容
为解决上述技术问题，本申请实施例提供了一种数字模拟转换器，以在应用于数字功放系统时，降低所述数字功放系统的电源抑制比，减小输出噪声，提高音频输出质量。
为解决上述问题，本申请实施例提供了如下技术方案：
一种数字模拟转换器，包括：
第一组成支路和第二组成支路，其中，所述第一组成支路第一端与电压输入端连接，第二端与所述第二组成支路连接；所述第二组成支路第一端与所述第一组成支路电连接，第二端接地；所述第一组成支路和所述第二组成支路的连接节点作为所述数字模拟转换器的信号输出端；
所述第一组成支路包括：串联的第一开关和第一电流源，所述第一电流源包括：第四电阻、第一场效应管、第二场效应管和第二运算放大器，其中，
所述第四电阻一端为所述第一电流源的第一端，另一端与第一场效应管的第一端电连接；
所述第一场效应管的第二端与所述第二场效应管的第一端电连接，所述第一场效应管的控制端与所述第二运算放大器的输出端电连接；
所述第二运算放大器的反相输入端与所述第一场效应管的第一端电连接，同相输入端电连接至第一预设电位，所述第一预设电位等于电压输入端的电压与参考电压的差值，输出端用于输出第一偏置电压给所述第一场效应管，将所述第一场效应管偏置在工作状态；
所述第二场效应管的第二端为所述第一电流源的第二端，所述第二场效应管的控制端电连接第二偏置电压，所述第二偏置电压用于将所述第二场效应管偏置在工作状态；
所述第二组成支路包括：串联的第二开关和第二电流源，所述第二电流源包括：第五电阻、第三场效应管、第四场效应管和第三运算放大器，其中，
所述第五电阻一端为所述第二电流源的第一端，另一端与第四场效应管的第一端电连接；
所述第四场效应管的第二端与所述第三场效应管的第一端电连接，所述第四场效应管的控制端与所述第三运算放大器的输出端电连接；
所述第三运算放大器的反相输入端与所述第四场效应管的第一端电连接，同相输入端电连接至第二预设电位，所述第二预设电位等于所述参考电压，输出端用于输出第四偏置电压，将所述第四场效应管偏置在工作状态；
所述第三场效应管的第二端为所述第二电流源的第二端，所述第三场效应管的控制端电连接第三偏置电压，所述第三偏置电压用于将所述第三场效应管偏置在工作状态；
其中，所述第一开关和第二开关的开关时序相反。
可选的，所述第一场效应管和所述第二场效应管为P型场效应管，所述第三场效应管和所述第四场效应管为N型场效应管。
可选的，所述第四电阻和所述第五电阻的阻值相同。
可选的，所述第一开关位于所述电压输入端与所述第一电流源之间；所述第二开关位于所述接地端与所述第二电流源之间。
可选的，所述第一电流源位于所述电压输入端与所述第一开关之间；所述第二电流源位于所述接地端与所述第二开关之间。
可选的，所述第一开关的开关状态由第一输入信号控制，所述第二开关的开关状态由第二输入信号控制，所述第一开关和第二开关为类型相同的晶体管，所述第一输入信号和第二输入信号为相位相反的方波信号。
可选的，所述第一开关的开关状态由第一输入信号控制，所述第二开关的开关状态由第二输入信号控制，所述第一开关和第二开关为类型不同的晶体管，所述第一输入信号和第二输入信号为相位相同的方波信号。
可选的，还包括：
第三开关，所述第三开关一端与所述第一开关和所述第一电流源的公共端电连接，另一端电连接至共模电压输入端；
所述第四开关，所述第四开关的一端与所述第二开关和所述第二电流源的公共端电连接，另一端电连接至所述共模电压输入端电连接。
可选的，所述第三开关的开关状态由所述第二输入信号控制，所述第四开关的开关状态由所述第一输入信号控制，所述第一开关和第四开关为 类型相同的晶体管，所述第二开关和所述第三开关为类型相同的晶体管。
本申请实施例还提供了一种数字功放子系统，包括：
上述任一项所提供的数字模拟转换器、第一运算放大器、积分器、PWM比较器、驱动器、第一电阻和第一电容，其中，
所述数字模拟转换器的信号输出端与所述第一运算放大器的反相信号输入端相连，所述第一运算放大器的正相信号输入端用于接收共模电压信号，所述第一运算放大器的信号输出端与所述积分器的信号输入端相连；
所述积分器的信号输出端与所述PWM比较器的信号输入端相连，所述PWM比较器的信号输出端与所述驱动器的信号输入端相连，所述驱动器的信号输出端作为上述数字功放子系统的信号输出端；
所述第一电阻的一端接于所述数字模拟转换器与所述第一运算放大器的连接节点，所述第一电阻的另一端接于所述驱动器的信号输出端；
所述第一电容的一端接于所述第一运算放大器与所述数字模拟转换器的连接节点，所述第一电容的另一端接于所述第一运算放大器与所述积分器的连接节点。
可选的，所述共模电压信号可以为所述数字模拟转换器接收的电压输入端输入的电压信号的二分之一。
一种数字功放系统，所述数字功放系统包括第一数字功放子系统和第二数字功放子系统，其中，所述第一数字功放子系统为VOP通道；所述第二数字功放子系统为VON通道；
所述第一数字功放子系统和所述第二数字功放子系统中至少一个数字 功放子系统采用上述任一项所提供的数字功放子系统。
与现有技术相比，上述技术方案具有以下优点：
本申请实施例所提供的数字模拟转换器，在应用于数字功放系统时，大大增加了所述数字模拟转换器的等效输出阻抗，降低了所述数字功放系统的电源抑制比。
而且，本申请实施例所提供的数字模拟转换器，在应用于数字功放系统时，不仅可以通过调节所述第一场效应管、第二场效应管、第三场效应管和第四场效应管的电阻或跨导增大所述数字模拟转换器的等效阻抗，也可以通过调节所述第四电阻和所述第五电阻的电阻值增大所述数字模拟转换器的等效阻抗，还可以通过调节所述第二运算放大器和所述第三运算放大器的增益增大所述数字模拟转换器的等效阻抗，从而进一步减小所述数字功放系统的电源抑制比，提高所述数字功放系统的噪声信号抑制能力。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一个实施例所提供的数字模拟转换器的应用的数字功放系统的结构示意图；
图2为本申请一个实施例所提供的数字功放子系统的结构示意图；
图3为本申请一个实施例所提供的数字模拟转换器的结构示意图；
图4为本申请一个实施例所提供的数字模拟转换器的等效电路示意图；
图5为本申请另一个实施例所提供的数字模拟转换器的结构示意图；
图6为本申请又一个实施例所提供的数字模拟转换器的结构示意图；
图7为本申请另一个实施例所提供的数字功放子系统的结构示意图；
图8为所述第一输入信号PWM_P、第二输入信号/PWM_P、所述共模电压信号VCM、所述数字模拟转换器的输出信号DAC_VOP与所述数字功放子系统的输出信号VOP的波形对比示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在下面的描述中阐述了很多具体细节以便于充分理解本申请，但是本申请还可以采用其他不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似推广，因此本申请不受下面公开的具体实施例的限制。
如图1所示，图1为本申请实施例提供的一种数字模拟转换器应用于其中的数字功放系统的结构示意图，用于将数字模块处理后的PWM信号转换成模拟信号，其包括VOP和VON两个通道，由于VOP和VON两个通道的工作原理类似，下面以VOP通道的数字功放子系统为例进行说明。
参考图2，图2为本申请实施例提供的一种VOP通道的数字功放子系统的结构示意图，所述VOP通道的数字功放子系统包括：数字模拟转换器DAC、第一运算放大器AMP1、积分器21、PWM比较器22、驱动器23、第一电阻RF和电容C1和共模电压信号产生模块24。
其中，所述数字模拟转换器DAC的信号输出端(即输出DAC_VOP信号的端口)与所述第一运算放大器AMP1的反相输入端连接，所述第一运算放大器AMP1的同相输入端与所述共模电压信号产生模块24的输出端(输出VCM信号的端口)连接，所述第一运算放大器AMP1的输出端AMP_VP1与所述积分器21的输入端连接。
所述积分器21的输出端与所述PWM比较器22的输入端连接，所述PWM比较器22的输出端PWM_P2与所述驱动器23的输入端连接，所述驱动器的输出端作为所述数字功放子系统的信号输出端，输出VOP信号。
所述第一电阻RF的一端与所述第一运算放大器AMP1的反相输入端连接，所述第一电阻RF的另一端与所述驱动器的输出端连接。
所述电容C1的一端与所述第一运算放大器AMP1的反相输入端连接，所述电容C1的另一端与所述第一运算放大器AMP1的输出端AMP_VP1连接。
其中，所述共模电压信号产生模块24包括：第二电阻R1和第三电阻R2，其中，所述第二电阻R1的一端与电压输入端VDD连接，所述第二电阻R1的另一端与所述第三电阻R2的一端连接；所述第三电阻R1的另一端与接地端GND连接；所述第二电阻R1和所述第三电阻R2的连接节点作为所述共模电压产生模块24的输出端，共模电压信号产生模块24输出 的信号为共模电压信号VCM。
在上述实施例中，所述数字功放子系统的信号输出端通过第一电阻RF、第一运算放大器AMP1、积分器21、PWM比较器22和驱动器23形成负反馈环路，对所述数字功放子系统的信号失真和电源噪声进行抑制。
发明人通过分析发现，对于上述VOP通道的数字功放子系统而言，由于数字模拟转换器DAC的电源抑制比和第一运算放大器AMP1的电源抑制比很高，数字功放子系统的环路增益很大，因此，数字功放子系统的负反馈环路中的电源噪声往往能被很好的抑制，不是影响所述数字功放子系统的电源抑制比的关键，而所述共模电压信号产生模块的输出端到数字功放子系统的信号输出端形成同向放大器，所述共模电压信号产生模块的输出端上的电压躁动被同向放大，是影响所述数字子功放系统的电源抑制比的关键。
同理，VON通道的数字功放子系统与VOP通道的数字功放子系统相同，在此不再阐述。
下面结合图1和图2对数字功放系统的电源抑制比PSRR进行推导，具体如下：
首先，所述共模电压信号产生模块24输出的电压信号VCM由电压输入端VDD通过第二电阻R1和第三电阻R2分压得到，具体为：
Figure PCTCN2020072166-appb-000001
定义，
Figure PCTCN2020072166-appb-000002
那么，VOP通道的数字功放子系统的输出波动为：
ΔVOP＝ΔVDD*α*(1+RFP/r0P_dac)
同理，VON通道的数字功放子系统的输出波动为：
ΔVON＝ΔVDD*α*(1+RFN/r0N_dac)
其中，r0P_dac表示VOP通道的数字模拟转换器DAC的等效输出阻抗，r0N_dac表示VON通道的数字模拟转换器DAC的等效输出阻抗，RFP表示VOP通道的RF电阻(即第一电阻)，RFN表示VON通道的RF电阻，ΔVDD表示数字模拟转换器DAC接收的电压信号VDD的波动。
所述数字功放系统的输出波动为：
ΔVout＝ΔVOP-ΔVON
也就是说，数字功放系统的输出波动为：
Figure PCTCN2020072166-appb-000003
又由于VOP通道和VON通道的数字模拟转换器DAC的电流源存在失配，失配系数δ 1满足以下条件：
r0P_dac＝(1+δ 1)*r0N_dac
由于VOP通道和VON通道的RF电阻也存在失配，失配系数δ 2满足以下条件：
RFP＝(1+δ 2)*RFN
则，所述数字功放系统的输出波动为：
Figure PCTCN2020072166-appb-000004
所述数字功放系统的电源抑制比PSRR为：
Figure PCTCN2020072166-appb-000005
其中，RF表示VOP通道或VON通道的RF电阻的阻值，r0_dac表示VOP通道或VON通道的数字模拟转换器DAC的等效输出阻抗。本申请文件中电源抑制比为数字功放系统的输出波动与数字模拟转换器DAC接收的电压信号VDD的波动之比。
由上述数字功放系统的电源抑制比的公式可知，数字模拟转换器DAC的等效输出阻抗r0_dac在该公式的分母上，即数字模拟转换器DAC的等效输出阻抗r0_dac越大，所述数字功放系统的电源抑制比PSRR越小，所述数字功放系统的电源噪声抑制能力越好。
基于此，本申请实施例提供了一种数字模拟转换器以及包括该数字模拟转换器的数字功放子系统、包括该数字功放子系统的数字功放系统。
如图3所示，本申请实施例所提供的数字模拟转换器包括：第一组成支路和第二组成支路，其中，所述第一组成支路第一端与电压输入端VDD连接，第二端与所述第二组成支路连接；所述第二组成支路第一端与所述第一组成支路电连接，第二端接地；所述第一组成支路和所述第二组成支路的连接节点作为所述数字模拟转换器DAC的信号输出端，输出DAC_VOP信号；
所述第一组成支路包括：串联的第一开关S1和第一电流源IDAC1，所述第一电流源IDAC1包括：第四电阻RS1、第一场效应管M1、第二场效应管M2和第二运算放大器AMP2，其中，
所述第四电阻RS1一端为所述第一电流源IDAC1的第一端，另一端与 第一场效应管M1的第一端电连接；
所述第一场效应管M1的第二端与所述第二场效应管M2的第一端电连接，所述第一场效应管M1的控制端与所述第二运算放大器AMP2的输出端电连接；
所述第二运算放大器AMP2的反相输入端与所述第一场效应管M1的第一端电连接，同相输入端电连接至第一预设电位，所述第一预设电位等于电压输入端VDD的电压与参考电压VREF的差值，输出端用于输出第一偏置电压VBP1给所述第一场效应管，将所述第一场效应管偏置在工作状态；
所述第二场效应管M2的第二端为所述第一电流源IDAC1的第二端，所述第二场效应管M2的控制端电连接第二偏置电压VBP2，所述第二偏置电压VBP2用于将所述第二场效应管偏置在工作状态；
所述第二组成支路包括：串联的第二开关S2和第二电流源IDAC2，所述第二电流源IDAC2包括：第五电阻RS2、第三场效应管M3、第四场效应管M4和第三运算放大器AMP3，其中，
所述第五电阻RS2一端为所述第二电流源IDAC2的第一端，另一端与第四场效应管M4的第一端电连接；
所述第四场效应管M4的第二端与所述第三场效应管M3的第一端电连接，所述第四场效应管M4的控制端与所述第三运算放大器AMP3的输出端电连接；
所述第三运算放大器AMP3的反相输入端与所述第四场效应管M4的第一端电连接，同相输入端电连接至第二预设电位，所述第二预设电位等于参考电压VREF，输出端输出第四偏置电压VBN2，将所述第四场效应管偏 置在工作状态；
所述第三场效应管M3的第二端为所述第二电流源IDAC2的第二端，所述第三场效应管M3的控制端电连接第三偏置电压VBN1，所述第三偏置电压VBN1用于将所述第三场效应管偏置在工作状态。
在上述实施例中，所述第一偏置电压VBP1通过第二运算放大器AMP2产生，所述第四偏置电压VBN2通过第三运算放大器AMP3产生，所述第一偏置电压VBP1和第四偏置电压VBN2分别给第一场效应管M1和第四场效应管M4的栅极提供电压，形成镜像电流源，提高所述数字模拟转换器的输出阻抗。
需要说明的是，在上述实施例的基础上，在本申请的一个实施例中，所述第二偏置电压VBP2和第三偏置电压VBN1由额外的电流产生支路产生，分别提供给第二场效应管M2和第三场效应管M3的控制端，形成镜像电流源，提高所述数字模拟转换器的输出阻抗。但本申请对此并不做限定，在本申请的其他实施例中，所述数字模拟转换器还可以包括第二偏置电压的产生电路和第三偏置电压的产生电路，以在所述数字模拟转换器的内部产生所述第二偏置电压和所述第三偏置电压，具体视情况而定。
由上可知，本申请实施例所提供的数字模拟转换器中，所述第一电流源和所述第二电流源均采用cascode结构，从而可以提高所述第一电流源和所述第二电流源的输出阻抗和稳定性，进而提高所述数字模拟转换器的电源抑制能力，减小所述数字模拟转换器的输出端输出的DAC_VOP信号对所述第一电流源和所述第二电流源的影响。
可选的，在上述实施例的基础上，在本申请的一个实施例中，所述第 一场效应管和所述第二场效应管为P型场效应管，所述第三场效应管和所述第四场效应管为N型场效应管，本申请对此并不做限定，具体视情况而定。
需要说明的是，在本申请实施例中，第四电阻RS1和第五电阻RS2相同，以使得第一组成支路的电流IDAC1和第二组成支路的电流IDAC2相等。
在上述实施例中，所述第二运算放大器AMP2、第一场效应管M1和第四电阻RS1形成源极负反馈，产生电流，第三运算放大器AMP3、第四场效应管M4和第五电阻RS2形成源极负反馈，产生电流，其电流值为：
Figure PCTCN2020072166-appb-000006
其中，RS1,2表示RS1或RS2的电阻，其中，RS1和RS2的电阻值相同。
可选的，在上述任一实施例的基础上，在本申请的一个实施例中，第一场效应管M1对应的电流源IDAC1和第三场效应管M3对应的电流源IDAC2应该尽量保证在工艺变化和不同温度下几乎相等，以保证在第一输入信号PWM_P为50％占空比时，所述数字功放子系统输出端输出的VOP信号也是50％占空比，使得数字功放子系统输出端输出直流电压为VDD/2。
需要说明的是，在本申请实施例中，所述第一开关S1的开关状态由第一输入信号PWM_P控制，所述第二开关S2的开关状态由第二输入信号/PWM_P控制，且所述第一开关S1和第二开关S2的开关时序相反。其中， 所述第一输入信号PWM_P和第二输入信号/PWM_P由数字功放系统中的数字模块对接收到的I2S、TDM等数字输入信号经过音效处理、数字增益放大和数字滤波后获得，通常为PWM信号，即方波信号。
在本申请实施例中，所述第一开关S1和第二开关S2的开关时序相反是指：在同一时间段内，当所述第一开关S1处于闭合状态时，所述第二开关S2处于关断状态，当所述第一开关S1处于关断状态时，所述第二开关S2处于闭合状态，从而使得第一电流源IDAC1或第二电流源IDAC2产生的镜像电流作为输出信号进行输出。
需要说明的是，在本申请实施例中，所述第一开关S1和第二开关S2的开关时序相反可以通过控制第一开关S1和第二开关S2的类型，以及第一输入信号PWM_P和第二输入信号/PWM_P的相位来实现。
具体的，在本申请的一个实施例中，所述第一开关S1和第二开关S2为类型相同的晶体管，即在同时接收高电平或低电平信号时，所处的状态相同，此时，所述第一输入信号PWM_P和第二输入信号/PWM_P为相位相反的方波信号；在本申请的另一个实施例中，所述第一开关S1和第二开关S2为类型不同的晶体管，即在同时接收高电平或低电平信号时，所处的状态相反，此时，所述第一输入信号PWM_P和第二输入信号/PWM_P可以为相位相同的方波信号。本申请对此并不做限定，具体视情况而定。
如图4所示，图4示出了本申请实施例所提供的数字模拟转换器的等效电路示意图。由图4可知，本申请实施例所提供的数字模拟转换器的等效输出阻抗r0_dac为：
r0_dac＝(gm_N1*ro3*AV3*gm_N2*ro4*RS2)∥(gm_P2*ro2*AV2*gm_P1*ro1*RS1)
其中，gm_N1表示第三场效应管的跨导，gm_N2表示第四场效应管的跨导，gm_P1表示第一场效应管的跨导，gm_P2表示第二场效应管的跨导，ro1表示第一场效应管的等效电阻，ro2表示第二场效应管的等效电阻，ro3表示第三场效应管的等效电阻，ro4表示第四场效应管的等效电阻，AV3表示第三运算放大器的增益，AV2表示第三运算放大器的增益。
由上可知，本申请实施例所提供的数字模拟转换器，在应用于数字功放系统时，大大增加了所述数字模拟转换器的等效输出阻抗，降低了所述数字功放系统的电源抑制比。
而且，本申请实施例所提供的数字模拟转换器，在应用于数字功放系统时，不仅可以通过调节所述第一场效应管、第二场效应管、第三场效应管和第四场效应管的电阻或跨导增大所述数字模拟转换器的等效阻抗，也可以通过调节所述第四电阻和所述第五电阻的电阻值增大所述数字模拟转换器的等效阻抗，还可以通过调节所述第二运算放大器和所述第三运算放大器的增益增大所述数字模拟转换器的等效阻抗，从而进一步减小所述数字功放系统的电源抑制比，提高所述数字功放系统的噪声信号抑制能力。
在上述实施例的基础上，在本申请的一个实施例中，继续如图3所示，所述第一开关S1位于所述电压输入端VDD与所述第一电流源IDAC1之间，即所述第一电流源IDAC1的第一端与所述第一开关S1电连接，所述第一电流源IDAC1的第二端与所述第二组成支路电连接，所述第一开关S1的另一端与电压输入端VDD电连接；在本申请的另一个实施例中，如图5所示， 所述第一电流源IDAC1位于所述电压输入端VDD与所述第一开关S1之间，即所述第一电流源IDAC1的第一端与所述电压输入端电连接，所述第一电流源IDAC1的第二端与第一开关S1电连接，所述第一开关S1的另一端与所述第二组成支路电连接。
同理，在上述任一实施例的基础上，在本申请的一个实施例中，继续如图3所示，所述第二开关S2位于接地端GND与所述第二电流源IDAC2之间，即所述第二电流源IDAC2的第一端与所述第二开关S2电连接，所述第二电流源IDAC2的第二端与所述第一组成支路电连接，所述第二开关S2的另一端与接地端GND电连接；在本申请的另一个实施例中，如图5所示，所述第二电流源IDAC2位于所述接地端GND与所述第二开关S2之间，即所述第二电流源IDAC2的第一端与所述接地端GND电连接，所述第二电流源IDAC2的第二端与第二开关S2电连接，所述第二开关S2的另一端与所述第一组成支路电连接。
需要说明的是，相较于图5中所述第一电流源IDAC1位于所述电压输入端VDD与所述第一开关S1之间、所述第二电流源IDAC2位于所述接地端GND与所述第二开关S2之间的方案，图3中所述第一开关S1位于所述电压输入端VDD与所述第一电流源IDAC1之间、所述第二开关S2位于接地端GND与所述第二电流源IDAC2之间的方案中，可以使得第一开关S1和第二开关S2在开关过程中产生的时钟馈通效应和沟道电荷注入现象不会越过第一电流源IDAC1和第二电流源IDAC2加载在数字模拟转换器的输出信号中，从而避免了由于第一开关S1和第二开关S2在开关过程中产生的时钟馈通效应和沟道电荷注入现象对数字模拟转换器的输出信号的不良影响，减 小了所述数字功放系统的输出噪声。
在上述任一实施例的基础上，在本申请的一个实施例中，如图6所示，如果所述第一开关S1位于所述电压输入端VDD与所述第一电流源IDAC1之间、所述第二开关S2位于接地端GND与所述第二电流源IDAC2之间，所述数字模拟转换器还包括：
第三开关S3，所述第三开关S3一端与所述第一开关S1和所述第一电流源IDAC1的公共端电连接，另一端电连接至共模电压输入端，所述共模电压输入端输入共模电压信号VCM；
所述第四开关S4，所述第四开关S4的一端与所述第二开关S2和所述第二电流源IDAC2的公共端电连接，另一端电连接至所述共模电压输入端电连接。
需要说明的是，在上述实施例中，所述第三开关S3的开关状态由第二输入信号/PWM_P控制，所述第四开关S4的开关状态由第一输入信号PWM_P控制，即在本申请实施例中，所述第一开关S1和所述第四开关S4的开关状态均由第一输入信号PWM_P控制，所述第二开关S2和所述第三开关S3的开关状态均由第二输入信号/PWM_P控制，且所述第一开关S1和第二开关S2的开关时序相反，所述第一开关S1和所述第三开关S3的开关时序相反，所述第二开关S2和所述第四开关S4的开关时序相反。其中，所述第一输入信号PWM_P和第二输入信号/PWM_P由数字功放系统中的数字模块对接收到的I2S、TDM等数字输入信号经过音效处理、数字增益放大和数字滤波后获得，通常为PWM信号，即方波信号。
在本申请实施例中，所述第一开关S1和第二开关S2的开关时序相反 是指：在同一时间段内，当所述第一开关S1处于闭合状态时，所述第二开关S2处于关断状态，当所述第一开关S1处于关断状态时，所述第二开关S2处于闭合状态，从而使得第一电流源IDAC1或第二电流源IDAC2产生的镜像电流作为输出信号进行输出。
所述第一开关S1和第三开关S3的开关时序相反是指：在同一时间段内，当所述第一开关S1处于闭合状态时，所述第三开关S3处于关断状态，当所述第一开关S1处于关断状态时，所述第三开关S3处于闭合状态，从而在第一开关S1断开期间，使得所述第一开关S1和所述第三开关S3的连接节点VA的电压保持在共模电压输入端的电压值，而不会随机跳动。
在上述实施例的基础上，在本申请的一个实施例中，所述第一预设电压大于所述共模电压输入端的电压，即VDD-VREF>VCM，从而在第一开关S1断开，第三开关S3闭合期间，使得电流镜像管第一场效应管中无电流流过，并在所述第一开关S1闭合，第三开关S3断开期间，电流镜像管第一场效应管M1可以较快的开启，流过电流IDAC1，避免不必要的延时。
可选的，在上述实施例的基础上，在本申请的一个实施例中，所述第三开关S3在所述第一开关S1完全断开之前闭合，从而减小所述第一开关S1和所述第三开关S3的连接节点VA的电压波动性。
同理，所述第二开关S2和第四开关S4的开关时序相反是指：在同一时间段内，当所述第二开关S2处于闭合状态时，所述第四开关S4处于关断状态，当所述第二开关S2处于关断状态时，所述第四开关S4处于闭合状态，从而在第二开关S2断开期间，通过所述第四开关S4闭合使得所述第二开关S2和所述第四开关S4的连接节点VB的电压保持在共模电压输 入端的电压值，而不会随机跳动。
在上述实施例的基础上，在本申请的一个实施例中，所述第二预设电压小于所述共模电压输入端的电压，即VREF<VCM，从而在第二开关S2断开，第四开关S4闭合期间，使得电流镜像管第三场效应管中无电流流过，并在所述第二开关S2闭合，第四开关S4断开期间，电流镜像管第三场效应管M3可以较快的开启，流过电流IDAC2，避免不必要的延时。
可选的，在上述实施例的基础上，在本申请的一个实施例中，所述第四开关S4在所述第二开关S2完全断开之前闭合，从而减小所述第二开关S2和所述第四开关S4的连接节点VB的电压波动性。
需要说明的是，在本申请实施例中，所述第一开关S1和第三开关S3的开关时序相反可以通过控制第一开关S1和第三开关S3的类型，以及第一输入信号PWM_P和第二输入信号/PWM_P的相位来实现。
具体的，在本申请的一个实施例中，所述第一开关S1和第三开关S3为类型相同的晶体管，即在同时接收高电平或低电平信号时，所处的状态相同，此时，所述第一输入信号PWM_P和第二输入信号/PWM_P为相位相反的方波信号；在本申请的另一个实施例中，所述第一开关S1和第三开关S3为类型不同的晶体管，即在同时接收高电平或低电平信号时，所处的状态相反，此时，所述第一输入信号PWM_P和第二输入信号/PWM_P可以为相位相同的方波信号。本申请对此并不做限定，具体视情况而定。
同理，所述第二开关S2和第四开关S4的开关时序相反可以通过控制第二开关S2和第四开关S4的类型，以及第一输入信号PWM_P和第二输入信号/PWM_P的相位来实现。
具体的，在本申请的一个实施例中，所述第二开关S2和第四开关S4为类型相同的晶体管，即在同时接收高电平或低电平信号时，所处的状态相同，此时，所述第一输入信号PWM_P和第二输入信号/PWM_P为相位相反的方波信号；在本申请的另一个实施例中，所述第二开关S2和第四开关S4为类型不同的晶体管，即在同时接收高电平或低电平信号时，所处的状态相反，此时，所述第一输入信号PWM_P和第二输入信号/PWM_P可以为相位相同的方波信号。本申请对此并不做限定，具体视情况而定。
可选的，在本申请的一个实施例中，所述第一开关S1、第二开关S2、第三开关S3和第四开关S4均为同一类型的晶体管，在本申请实施例中，所述第一输入信号PWM_P和第二输入信号/PWM_P为相位相反的方波信号；在本申请的另一个实施例中，所述第一开关S1与所述第四开关S4为类型相同的晶体管，所述第二开关S2和所述第三开关S3为类型相同的晶体管，所述第一开关S1和第三开关S3为类型不同的晶体管，第二开关S2和第四开关S4为类型不同的晶体管，在本申请实施例中，所述第一输入信号PWM_P和第二输入信号/PWM_P为相位相同的方波信号。可选的，所述第一输入信号PWM_P是占空比与输入信号幅度成正比的脉宽调制方波信号。
相应的，本申请实施例还提供了一种数字功放子系统，如图7所示，该数字功放子系统包括：
上述任一实施例所提供的数字模拟转换器DAC、第一运算放大器AMP1、积分器31、PWM比较器32、驱动器33、第一电阻RF和第一电容C1，其中，
所述数字模拟转换器的信号输出端与所述第一运算放大器的反相信号输入端相连，所述第一运算放大器的正相信号输入端用于接收共模电压信号VCM，所述第一运算放大器的信号输出端与所述积分器的信号输入端相连；
所述积分器的信号输出端与所述PWM比较器的信号输入端相连，所述PWM比较器的信号输出端与所述驱动器的信号输入端相连，所述驱动器的信号输出端作为上述数字功放子系统的信号输出端，输出VOP信号；
所述第一电阻RF的一端接于所述数字模拟转换器与所述第一运算放大器的连接节点，所述第一电阻RF的另一端接于所述驱动器的信号输出端；
所述第一电容C1的一端接于所述第一运算放大器与所述数字模拟转换器的连接节点，所述第一电容C1的另一端接于所述第一运算放大器与所述积分器的连接节点。
具体工作时，所述第一输入信号PWM和所述第二输入信号/PWM为由数字模块将接收到的I2S、TDM等数字输入信号经过音效处理、数字增益放大、数字滤波后转换成的PWM信号，所述PWM信号经过数字模拟转换器DAC处理，并经过积分器、PWM比较器、驱动模块后输出PWM方波，以实现模拟增益的放大，从而大大提高所述数字功放子系统应用的数字功放系统的音频功放的电源抑制能力。
下面以所述第一输入信号PWM_P和所述第二输入信号/PWM_P的相位相反，所述PWM_P为高电平期间，第一开关S1闭合，第二开关S2断 开，所述PWM_P为低电平时，第一开关S1断开，第二开关S2闭合为例，对上述数字功放子系统的工作原理进行描述。
当所述第一输入信号PWM_P为高电平时，所述第二输入信号/PWM_P为低电平，第一开关S1闭合，第二开关S2断开，此时，所述数字模拟转换器中的第一电流源IDAC1对所述第一电阻RF以及第一电容C1与第一运算放大器AMP1的反相输出端电连接的电容板充电，所述第一运算放大器AMP1的输出端对所述第一电容与第一运算放大器AMP1的输出端电连接的电容板放电，第一运算放大器AMP1的输出电压AMP_V1降低，并通过积分器、PWM比较器和驱动器，使得所述数字功放子系统的输出端输出的信号VOP为低电平；
当所述PWM_P为低电平时，第一开关S1断开，第二开关S2闭合，此时，所述数字模拟转换器中的第二电流源IDAC2对所述第一电阻RF以及第一电容C1与第一运算放大器AMP1的反相输出端电连接的电容板进行放电，所述第一运算放大器AMP1的输出端对所述第一电容与第一运算放大器AMP1的输出端电连接的电容板进行充电，第一运算放大器AMP1的输出电压AMP_V1升高，并通过积分器、比较器和驱动器，使得所述数字功放子系统的输出端输出的信号VOP为高电平。
由上可知，本申请实施例所提供的数字功放子系统中，在第一输入信号PWM_P的一个周期内，所述第一运算放大器AMP1的输出信号AMP_V1为三角波信号，所述数字子功放系统的输出端输出的VOP信号为方波信号，然后经过低通滤波或扬声器本身的低通滤波特性后，还原出 音频信号。
如图8所示，图8示出了所述第一输入信号PWM_P、第二输入信号/PWM_P、所述共模电压信号VCM、所述数字模拟转换器的输出信号DAC_VOP与所述数字功放子系统的输出信号VOP的波形对比示意图，从图8中可以看出，所述第一输入信号PWM_P和第二输入信号/PWM_P是相位相反的输入信号，通过环路负反馈作用，所述数字模拟转换器输出端输出的DAC_VOP信号以VCOM为中心进行上下波动、调节环路误差信号。另外，由于环路中各个器件(如积分器和驱动器等)存在延时，所述数字模拟转换器的输出信号和数字功放子系统的输出信号相对于所述第一输入信号PWM_P和第二输入信号/PWM_P的响应存在一定的延时LD(Loop Delaytime)。
另外，由于负反馈环路增益很大，差分信号(DAC_VOP-VCM)的值很小，所以所述数字模拟转换器输出端输出的DAC_VOP信号相对所述共模电压信号VCM上下波动的纹波很小，从而使得所述数字模拟转换器输出端输出的DAC_VOP信号以共模电压信号VCM为中心进行上下微小的波动，极大程度的提高数字模拟转换器的输出稳定性。
在上述任一实施例的基础上，在本申请的一个实施例中，所述共模电压信号可以为所述数字模拟转换器接收的电压输入端VDD输入的电压信号的二分之一，即VCM＝VDD/2，但本申请对此并不做限定，在本申请的其他实施例中，所述共模电压信号可以为所述数字模拟转换器接收的电压输入端VDD输入的电压信号的三分之一或四分之一等，具体视情况而定。
在上述任一实施例的基础上，在本申请的一个实施例中，所述数字功放子系统还包括共模电压信号产生模块，以产生所述共模电压信号VCM。可选的，在本申请的一个实施例中，所述共模电压信号产生模块包括串联的第二电阻和第三电阻，其中，所述第二电阻背离所述第三电阻的一端电连接所述电压输入端VDD，所述第三电阻背离所述第二电阻的一端接地，所述第二电阻和所述第三电阻的连接节点电连接所述第一运算放大器的正相输入端。但本申请对此并不做限定，在本申请的其他实施例中，所述共模电压信号产生模块还可以通过其他方式产生所述共模电压信号，具体视情况而定。
在图7所示的数字功放子系统中，第一输入信号PWM_P或第二输入信号/PWM_P到数字功放子系统最终输出的信号的增益为：AV＝2×(2×Din-1)×IDAC×RF，其中，Din为第一输入信号PWM_P或第二输入信号/PWM_P的高电平占空比，IDAC表示所述第一电流源IDAC1或第二电流源IDAC2产生的电流值，RF表示所述第一电阻RF的电阻值。
此外，本申请实施例还提供了一种数字功放系统，所述数字功放系统包括第一数字功放子系统和第二数字功放子系统，其中，所述第一数字功放子系统为VOP通道；所述第二数字功放子系统为VON通道；所述第一数字功放子系统和所述第二数字功放子系统中至少一个数字功放子系统采用本申请上述任一实施例所提供的数字功放子系统。
综上所述，本申请实施例所提供的数字模拟转换器、包括该数字模拟转换器的数字功放子系统以及包括该数字功放子系统的数字功放系统，大大增加了所述数字模拟转换器的等效输出阻抗，降低了所述数字功放系统 的电源抑制比。
而且，本申请实施例所提供的数字模拟转换器、包括该数字模拟转换器的数字功放子系统以及包括该数字功放子系统的数字功放系统，不仅可以通过调节所述第一场效应管、第二场效应管、第三场效应管和第四场效应管的电阻或跨导增大所述数字模拟转换器的等效阻抗，也可以通过调节所述第四电阻和所述第五电阻的电阻值增大所述数字模拟转换器的等效阻抗，还可以通过调节所述第二运算放大器和所述第三运算放大器的增益增大所述数字模拟转换器的等效阻抗，从而进一步减小所述数字功放系统的电源抑制比，提高所述数字功放系统的噪声信号抑制能力。
本说明书中各个部分采用递进的方式描述，每个部分重点说明的都是与其他部分的不同之处，各个部分之间相同相似部分互相参见即可。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (12)

  1. 一种数字模拟转换器，其特征在于，包括：
    第一组成支路和第二组成支路，其中，所述第一组成支路第一端与电压输入端连接，第二端与所述第二组成支路连接；所述第二组成支路第一端与所述第一组成支路电连接，第二端接地；所述第一组成支路和所述第二组成支路的连接节点作为所述数字模拟转换器的信号输出端；
    所述第一组成支路包括：串联的第一开关和第一电流源，所述第一电流源包括：第四电阻、第一场效应管、第二场效应管和第二运算放大器，其中，
    所述第四电阻一端为所述第一电流源的第一端，另一端与第一场效应管的第一端电连接；
    所述第一场效应管的第二端与所述第二场效应管的第一端电连接，所述第一场效应管的控制端与所述第二运算放大器的输出端电连接；
    所述第二运算放大器的反相输入端与所述第一场效应管的第一端电连接，同相输入端电连接至第一预设电位，所述第一预设电位等于电压输入端的电压与参考电压的差值，输出端用于输出第一偏置电压给所述第一场效应管，将所述第一场效应管偏置在工作状态；
    所述第二场效应管的第二端为所述第一电流源的第二端，所述第二场效应管的控制端电连接第二偏置电压，所述第二偏置电压用于将所述第二场效应管偏置在工作状态；
    所述第二组成支路包括：串联的第二开关和第二电流源，所述第二电流源包括：第五电阻、第三场效应管、第四场效应管和第三运算放大器， 其中，
    所述第五电阻一端为所述第二电流源的第一端，另一端与第四场效应管的第一端电连接；
    所述第四场效应管的第二端与所述第三场效应管的第一端电连接，所述第四场效应管的控制端与所述第三运算放大器的输出端电连接；
    所述第三运算放大器的反相输入端与所述第四场效应管的第一端电连接，同相输入端电连接至第二预设电位，所述第二预设电位等于所述参考电压，输出端用于输出第四偏置电压，将所述第四场效应管偏置在工作状态；
    所述第三场效应管的第二端为所述第二电流源的第二端，所述第三场效应管的控制端电连接第三偏置电压，所述第三偏置电压用于将所述第三场效应管偏置在工作状态；
    其中，所述第一开关和第二开关的开关时序相反。
  2. 根据权利要求1所述的数字模拟转换器，其特征在于，所述第一场效应管和所述第二场效应管为P型场效应管，所述第三场效应管和所述第四场效应管为N型场效应管。
  3. 根据权利要求1所述的数字模拟转换器，其特征在于，所述第四电阻和所述第五电阻的阻值相同。
  4. 根据权利要求1所述的数字模拟转换器，其特征在于，所述第一开关位于所述电压输入端与所述第一电流源之间；所述第二开关位于所述接地端与所述第二电流源之间。
  5. 根据权利要求1所述的数字模拟转换器，其特征在于，所述第一电流源位于所述电压输入端与所述第一开关之间；所述第二电流源位于所述 接地端与所述第二开关之间。
  6. 根据权利要求1所述的数字模拟转换器，其特征在于，所述第一开关的开关状态由第一输入信号控制，所述第二开关的开关状态由第二输入信号控制，所述第一开关和第二开关为类型相同的晶体管，所述第一输入信号和第二输入信号为相位相反的方波信号。
  7. 根据权利要求1所述的数字模拟转换器，其特征在于，所述第一开关的开关状态由第一输入信号控制，所述第二开关的开关状态由第二输入信号控制，所述第一开关和第二开关为类型不同的晶体管，所述第一输入信号和第二输入信号为相位相同的方波信号。
  8. 根据权利要求1-4或6-7任一项所述的数字模拟转换器，其特征在于，还包括：
    第三开关，所述第三开关一端与所述第一开关和所述第一电流源的公共端电连接，另一端电连接至共模电压输入端；
    所述第四开关，所述第四开关的一端与所述第二开关和所述第二电流源的公共端电连接，另一端电连接至所述共模电压输入端电连接。
  9. 根据权利要求8所述的数字模拟转换器，其特征在于，所述第三开关的开关状态由所述第二输入信号控制，所述第四开关的开关状态由所述第一输入信号控制，所述第一开关和第四开关为类型相同的晶体管，所述第二开关和所述第三开关为类型相同的晶体管。
  10. 一种数字功放子系统，其特征在于，该数字功放子系统包括：
    权利要求1-9任一项所提供的数字模拟转换器、第一运算放大器、积分器、PWM比较器、驱动器、第一电阻和第一电容，其中，
    所述数字模拟转换器的信号输出端与所述第一运算放大器的反相信号输入端相连，所述第一运算放大器的正相信号输入端用于接收共模电压信 号，所述第一运算放大器的信号输出端与所述积分器的信号输入端相连；
    所述积分器的信号输出端与所述PWM比较器的信号输入端相连，所述PWM比较器的信号输出端与所述驱动器的信号输入端相连，所述驱动器的信号输出端作为上述数字功放子系统的信号输出端；
    所述第一电阻的一端接于所述数字模拟转换器与所述第一运算放大器的连接节点，所述第一电阻的另一端接于所述驱动器的信号输出端；
    所述第一电容的一端接于所述第一运算放大器与所述数字模拟转换器的连接节点，所述第一电容的另一端接于所述第一运算放大器与所述积分器的连接节点。
  11. 根据权利要求10所述的数字功放子系统，其特征在于，所述共模电压信号可以为所述数字模拟转换器接收的电压输入端输入的电压信号的二分之一。
  12. 一种数字功放系统，其特征在于，所述数字功放系统包括第一数字功放子系统和第二数字功放子系统，其中，所述第一数字功放子系统为VOP通道；所述第二数字功放子系统为VON通道；
    所述第一数字功放子系统和所述第二数字功放子系统中至少一个数字功放子系统采用权利要求10或11所提供的数字功放子系统。
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