WO2020155461A1 - 一种量子比特控制信号生成方法、系统 - Google Patents

一种量子比特控制信号生成方法、系统 Download PDF

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WO2020155461A1
WO2020155461A1 PCT/CN2019/086169 CN2019086169W WO2020155461A1 WO 2020155461 A1 WO2020155461 A1 WO 2020155461A1 CN 2019086169 W CN2019086169 W CN 2019086169W WO 2020155461 A1 WO2020155461 A1 WO 2020155461A1
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code
signal
target
module
quantum
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PCT/CN2019/086169
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English (en)
French (fr)
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孔伟成
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合肥本源量子计算科技有限责任公司
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Priority claimed from CN201910094220.8A external-priority patent/CN109683086B/zh
Priority claimed from CN201910093469.7A external-priority patent/CN109615079B/zh
Application filed by 合肥本源量子计算科技有限责任公司 filed Critical 合肥本源量子计算科技有限责任公司
Priority to US16/624,038 priority Critical patent/US11222280B2/en
Publication of WO2020155461A1 publication Critical patent/WO2020155461A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/20—Models of quantum computing, e.g. quantum circuits or universal quantum computers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/80—Quantum programming, e.g. interfaces, languages or software-development kits for creating or handling programs capable of running on quantum computers; Platforms for simulating or accessing quantum computers, e.g. cloud-based quantum computing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/70—Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes

Definitions

  • the invention belongs to the technical field of signal processing, in particular to a method and system for generating qubit control signals.
  • Quantum chip is the core structure of quantum computer, and qubit is the basic operation unit of quantum chip.
  • qubit is the basic operation unit of quantum chip.
  • the qubit control signal acts on the qubit of the quantum chip, which can make the quantum state of the target qubit undergo a controllable and specified change, so as to realize the operation of the quantum logic gate.
  • it is necessary to implement a series of quantum logic gate operations on the qubit. Therefore, the number and length of the qubit control signal will greatly increase due to the type of quantum logic gate operation and the number of operations.
  • One method for generating qubit control signals in the prior art relies on commercial signal sources such as arbitrary waveform generators.
  • the control signal to be generated needs to be written in advance and temporarily stored in the arbitrary waveform generator, and then the arbitrary waveform generator is controlled by the control signal so that the pre-stored signal is output to the DAC point by point for playback, and then the analog waveform is obtained.
  • the qubit controls the output of the signal.
  • the traditional qubit control signal generation system relies on the storage capacity of the arbitrary waveform generator.
  • the first object of the present invention is to provide a method for generating qubit control signals to solve the deficiencies in the prior art, which can avoid the limitations of traditional qubit control signal generation methods, and can satisfy multi-qubit testing Demand, provide the qubit control signal requirements for multi-qubit testing.
  • the second object of the present invention is to provide a qubit control signal generation system.
  • an embodiment of the first aspect of the present invention proposes a method for generating a qubit control signal.
  • the method for generating a qubit control signal includes:
  • the reference quantum gate set includes a plurality of basic quantum logic gates
  • the basic quantum logic gates include Single quantum logic gate and/or double quantum logic gate
  • said first tag code is used to identify said basic quantum logic gate
  • each said basic quantum logic gate has said fixed first tag code
  • said first The standard signal is a signal for realizing the operation of the basic quantum logic gate
  • the first address code corresponds to the first tag code one to one;
  • Target tag code and target time code corresponding to each basic quantum logic gate in the target quantum program sent by the host computer, wherein the target tag code is all corresponding to the basic quantum logic gate in the target quantum program
  • the first tag code, the target time code is used to identify the execution timing of the basic quantum logic gate in the target quantum program in the target quantum program
  • the receiving target tag code and target time code of each basic quantum logic gate in the target quantum program sent by the host computer includes:
  • the target time code corresponding to each basic quantum logic gate is determined according to the execution timing of each basic quantum logic gate in the target quantum program.
  • Standard signals are used as signals to be processed, including:
  • the method for generating a qubit control signal as described above, wherein, preferably, the setting a clock code and a clock trigger signal according to the target time code includes:
  • the clock trigger signal is formed according to the clock code.
  • the method for generating a qubit control signal as described above, wherein, preferably, the processing the signal to be processed to obtain a qubit control signal includes:
  • the method for generating a qubit control signal as described above wherein, preferably, before the digital-to-analog conversion is performed on the signal to be processed to obtain the qubit control analog signal, the method further includes:
  • the method for generating a qubit control signal as described above wherein, preferably, after the storing the first standard signal and obtaining the first address code corresponding to the first tag code, the method further includes:
  • the standard signal is used as the signal to be processed, and the processing of the signal to be processed to obtain the qubit control signal number includes:
  • the convolver module performs convolution correction processing on the first standard signal through an embedded convolution function to obtain the disappearing true signal.
  • the clock code corresponding to the convolution module is adjusted according to the order of the convolution function.
  • the present invention sets a reference quantum gate set in the host computer that can realize the set of basic quantum logic gates of any quantum program through combination, and then the host computer sends each basic quantum logic in the reference quantum gate set.
  • the first tag code and the first standard signal of the gate are sent to the set signal processing device, that is, the set signal processing device receives the first tag code and first standard of each basic quantum logic gate corresponding to the reference quantum gate set sent by the host computer Signal, set the signal processing device to store the first standard signal, and obtain the first address code identifying the storage location of the first standard signal, and then set the target quantum program composed of basic quantum logic gates in the host computer, and Record the target label code and target time code of each basic quantum logic gate in the target quantum program, and then set the target label code and target time code of each basic quantum logic gate corresponding to the target quantum program sent by the host computer Signal processing equipment, setting the signal processing equipment only needs to obtain the first standard signal corresponding to the basic quantum logic gate in the target quantum program as the signal to be processed according to the target tag code
  • the basic quantum of any quantum program can be realized through combination
  • the set of logic gates ie, the benchmark quantum gate set
  • can realize any target quantum program can provide the qubit control signal required for multi-qubit testing, and meet the needs of multi-qubit testing.
  • an embodiment of the second aspect of the present invention proposes a qubit control signal generation system.
  • the qubit control signal generation system includes an upper computer, a main control module and a control signal generation module, wherein:
  • the host computer is used to obtain and store the quantum logic gate set and the target quantum program, and send the first tag code and first standard signal corresponding to each basic quantum logic gate in the quantum logic gate set to the main control module, And sending the target tag code and target time code corresponding to each basic quantum logic gate of the target quantum program to the main control module, wherein the quantum logic gate set refers to a set of quantum logic gates including multiple quantum programs, Each of the basic quantum logic gates corresponds to a unique first tag code, the first standard signal is a signal for realizing the operation of the basic quantum logic gate, and the target tag code is the target quantum A first tag code corresponding to the basic quantum logic gate in the program, where the target time code is used to identify the execution timing of the basic quantum logic gate in the target quantum program;
  • the control signal generation module is configured to receive the signal to be processed and process the signal to be processed to generate a qubit control signal.
  • the host computer includes a first decomposition module, a first acquisition module, and a first determination module, wherein:
  • the first decomposition module is used to decompose the target quantum program to generate the combination of the basic quantum logic gates;
  • the first obtaining module is configured to obtain the first tag code corresponding to each of the basic quantum logic gates in the target quantum program, and record it as the target tag code;
  • the first determining module is configured to determine the target time code corresponding to each basic quantum logic gate according to the execution timing of each basic quantum logic gate in the target quantum program.
  • main control module includes:
  • the second determining module is configured to determine the clock code according to the time code and the clock period, wherein the clock code is equal to the ratio of the time code to the clock period, and the clock period is the clock period of the processing device ;
  • the first processing module is configured to form the clock trigger signal according to the clock code
  • the first receiving module is configured to receive the clock trigger signal
  • the second acquisition module is used to acquire the clock code corresponding to the clock trigger signal
  • the third obtaining module is used to obtain the target time code corresponding to the clock code
  • the fourth obtaining module is used to obtain the target tag code corresponding to the target time code
  • a fifth acquiring module configured to acquire the first address code corresponding to the target tag code
  • the second processing module is configured to obtain the stored first standard signal corresponding to the first address code as the signal to be processed.
  • the main control module includes a first creation module and a first convolution module, wherein:
  • the first creation module is configured to create a convolver code corresponding to the first address code, wherein the convolver code corresponds to a preset convolver module;
  • the first convolution module is configured to perform convolution correction processing on the first standard signal.
  • main control module further includes:
  • the first setting module is configured to set a clock code and a clock trigger signal according to the target time code, and the clock code and the clock trigger signal have a one-to-one correspondence;
  • the second receiving module is configured to receive the clock trigger signal
  • the sixth obtaining module is used to obtain the clock code corresponding to the clock trigger signal
  • the seventh obtaining module is used to obtain the target time code corresponding to the clock code
  • An eighth obtaining module configured to obtain a target tag code corresponding to the target time code
  • the ninth obtaining module is configured to obtain the first address code corresponding to the target tag code, and record it as the address code to be called;
  • the tenth obtaining module is used to obtain the convolver code mark corresponding to the address code to be called, and is the convolver code to be called;
  • the first loading module is configured to load the first standard signal corresponding to the address code to be called into the convolver module corresponding to the convolver code to be called, and the convolver module performs The first standard signal is subjected to convolution correction processing to obtain a convolution processing signal;
  • the second conversion module is configured to perform digital-to-analog conversion processing on the convolution processing signal to generate the qubit control signal.
  • control signal generating module includes:
  • the first conversion sub-module is used to perform digital-to-analog conversion on the signal to be processed to generate the qubit control analog signal.
  • control signal generating module further includes:
  • the second convolution sub-module is used to perform convolution correction processing on the signal to be processed.
  • the present invention provides a qubit control signal generation system.
  • the main control module controls the control signal generation module to generate qubit control via the target tag code and target time code issued by the host computer.
  • Signal because the control signal corresponding to the quantum logic gate is pre-stored in the main control module in the form of the first standard signal, and the target tag code and the first address code corresponding to the first standard signal are stored in the main control module.
  • Generate signals to be processed greatly reducing the capacity storage requirements of the main control module at the source, and can realize the set of basic quantum logic gates of any quantum program through combination, and output the qubit control signal to realize any target quantum program.
  • the invention can quickly provide the qubit control signal, greatly improves the response speed of the control signal generation module, and ensures the speed of the subsequent stage quantum operation.
  • FIG. 1 is a schematic flowchart of a method for generating a qubit control signal according to Embodiment 1 of the present invention.
  • FIG. 2 is a block diagram of the hardware structure of the qubit control signal generation system in specific embodiment 3 of the present invention.
  • Fig. 3 is a hardware structure block diagram of the qubit control signal generation system in specific embodiment 4 of the present invention.
  • quantum computing applications depending on the complexity of the computing application, hundreds or even tens of thousands of computing steps are required, but the number of basic computing operations used in all computing steps is limited.
  • analog classic computers all computing applications can be implemented using a combination of two basic logic gate operations, NAND gate and XOR gate.
  • quantum computers all quantum computing applications can be implemented using a combination of single quantum logic gate operations and double quantum logic gate operations. For example, in a two-bit quantum chip, all quantum computing applications can use a combination of quantum logic gate operations.
  • all quantum computing applications can use a combination of quantum logic gate operations To achieve; in a four-bit quantum chip, all quantum computing applications can use a combination of quantum logic gate operations To achieve; all quantum computing applications in the five-bit quantum chip can use a combination of quantum logic gate operations Realization, and so on.
  • FIG 1 is a schematic flow chart of the method for generating a qubit control signal in Embodiment 1 of the application.
  • this embodiment provides a method for generating a qubit control signal for converting quantum computing applications into basic The qubit controls the signal and finally sends it to the quantum chip to perform operations.
  • the basic qubit control signal described here is not a control signal used to complete the entire quantum chip calculation application, but a basic signal used to complete an calculation step (that is, a target quantum program).
  • the method for generating the qubit control signal includes:
  • Step S1 Receive the first tag code and the first standard signal corresponding to each basic quantum logic gate in the reference quantum gate set sent by the host computer, wherein the reference quantum gate set includes a plurality of basic quantum logic gates, and the basic quantum gates
  • the logic gates include single quantum logic gates and/or double quantum logic gates
  • the first tag code is used to identify the basic quantum logic gate
  • one of the basic quantum logic gates has a fixed first tag code
  • the first standard signal is a signal for realizing the operation of the basic quantum logic gate.
  • the set of reference quantum gates is:
  • the set of quantum logic gates is:
  • the set of quantum logic gates is:
  • the X gate, Y gate, and Z gate are single-qubit logic gates
  • CZ is a double-qubit logic gate.
  • the number in the upper right corner of the single-qubit logic gate represents the qubit label on the quantum chip
  • the angle in the lower right corner of the single-qubit logic gate represents the angle at which the logical state of the qubit changes due to the operation of the single-qubit logic gate.
  • the numbers in the lower right corner of the dual-qubit logic gate indicate the master qubit and the controlled qubit.
  • Single-qubit logic gates X gates, Y gates, Z gates, and double-qubit logic gates CZ can realize arbitrary quantum logic gates through combination.
  • any complex quantum logic gate can be decomposed into a combination of a single-qubit logic gate and a double-qubit logic gate.
  • single-qubit logic gates X gates, Y gates, Z gates, and double-qubit logic gates CZ are called basic quantum logic gates.
  • a corresponding first tag code is set for any basic quantum logic gate in the reference quantum gate set.
  • the first tag code is used to identify the basic quantum logic gate.
  • One basic quantum logic gate has a fixed first Tag code.
  • a corresponding first standard signal is set for any basic quantum logic gate in the reference quantum gate set, and the first standard signal is a signal used to implement the operation of the corresponding basic quantum logic gate.
  • the host computer is responsible for sending a reference quantum gate set to the setting signal processing device in the format of "first tag code + first standard signal", that is, the setting signal processing device receives each of the corresponding reference quantum gate sets sent by the host computer The first tag code and the first standard signal of the basic quantum logic gate.
  • the set signal processing device may be an FPGA chip.
  • Step S2 Store the first standard signal, and obtain a first address code that identifies the storage location of the first standard signal, wherein the first address code corresponds to the first tag code in a one-to-one correspondence.
  • the signal processing device is set to store the first standard signal, and the first address code identifying the storage location of the first standard signal is obtained; the signal processing device is set to an FPGA chip, and the FPGA chip can be internal
  • the specific areas are divided into control modules and storage modules.
  • the control module communicates with the host computer, receives the format information of the "first tag code + first standard signal" sent by the host computer, and controls the first standard signal to be stored in the storage module, which can be a high-speed cache DDR3 or DDR4.
  • the storage module stores the first standard signal and returns the storage address to the control module. For example: the storage module can directly return the address (ie address code) of the first binary number storing the first standard signal to the control module. After the control module uses the address code, it can transfer the corresponding address in the cache module (ie storage module) The first standard signal of the code is loaded out for subsequent use.
  • Step S3 Receive the target tag code and target time code corresponding to each basic quantum logic gate in the target quantum program sent by the host computer, wherein the target tag code is the basic quantum logic gate in the target quantum program Corresponding to the first tag code, the target time code is used to identify the execution timing of the basic quantum logic gate in the target quantum program in the target quantum program.
  • the target quantum program is a quantum computing application to be run, which is realized by one or a combination of single quantum logic gates, two quantum logic gates, multiple quantum logic gates, and any multiple quantum logic gates can be decomposed into single quantum logic
  • the combination of gate and two quantum logic gates therefore, the target quantum program can be decomposed into the combination of basic quantum logic gates.
  • a basic quantum logic gate has a fixed first label code
  • each basic quantum logic gate is in the target quantum program
  • the position that appears in represents the execution timing of each basic quantum logic gate, specifically the time code is converted from the precise execution time of the corresponding operation step in the quantum operation application (ie the target quantum program), for example, 40ns after the operation starts
  • the time code of the first operation step can be recorded as 40.
  • the target quantum program can be converted into an instruction expressed by the first tag code and the time code, specifically, the first tag code corresponding to each of the basic quantum logic gates in the target quantum program is obtained, It is recorded as the target tag code; the target time code corresponding to each basic quantum logic gate is determined according to the execution timing of each basic quantum logic gate in the target quantum program.
  • the upper computer is responsible for sending a target quantum program to the setting signal processing device in the format of "target tag code + target address code", that is, setting the signal processing device to receive each basic quantum logic in the corresponding target quantum program sent by the upper computer
  • target tag code and target time code of the gate are responsible for sending a target quantum program to the setting signal processing device in the format of "target tag code + target address code", that is, setting the signal processing device to receive each basic quantum logic in the corresponding target quantum program sent by the upper computer.
  • the signal processing device is set to be an FPGA chip, and the FPGA chip can be divided into a control module and a storage module by function
  • the signal processing device is set to receive each of the corresponding target quantum programs sent by the host computer.
  • the target tag code and target time code of the basic quantum logic gate that is, the control module receives the target tag code and target time code of each basic quantum logic gate corresponding to the target quantum program sent by the host computer.
  • Step S4 Obtain the corresponding first standard signal of the basic quantum logic gate in the target quantum program according to the target tag code and the target time code, and use it as a signal to be processed; and process the signal to be processed Signal to generate a qubit control signal.
  • control module since the control module stores a one-to-one correspondence between the first tag code and the first address code, when the control module receives the target tag code and the target time code again, it can use the tag code (target tag code and The first tag code) this bridge, quickly find the first address code corresponding to the target time code, and then call the first standard signal stored at the location of the first address code as the signal to be processed, and then process the signal to be processed to generate quantum Bit control signal.
  • tag code target tag code and The first tag code
  • a reference quantum gate set is set, and the first label code and first standard signal corresponding to the basic quantum logic gates in the reference quantum gate set are set. Store the first tag code and the first standard signal in the setting signal processing device for later use.
  • the reference quantum gate set it is necessary to ensure that the basic quantum logic gates in the reference quantum gate set can realize any quantum program through combination. In essence, the basic quantum logic gates in the reference quantum gate set can realize arbitrary complex quantum logic through combination.
  • the door provides a reference and basis for the later convenient call.
  • the signal processing equipment uses the tag code (target tag code and the first tag code) as a bridge to quickly find the target time code corresponding Then call the first standard signal stored at the position of the first address code as the signal to be processed, and then process the signal to be processed to obtain the qubit control signal, which makes full use of the storage space of the host computer and greatly reduces The capacity and storage requirements of the signal processing equipment are set.
  • any target quantum program can be accurately realized, and it can provide The qubit control signal required for multi-qubit testing meets the needs of multi-qubit testing.
  • the first standard signal corresponding to the basic quantum logic gate in the target quantum program is obtained according to the target tag code and the target time code in step S4 As a signal to be processed, including:
  • Step S41 Set a clock code and a clock trigger signal according to the target time code, wherein the clock code and the clock trigger signal have a one-to-one correspondence;
  • Step S42 receiving the clock trigger signal
  • Step S43 Obtain a clock code corresponding to the clock trigger signal
  • Step S44 Obtain a target time code corresponding to the clock code
  • Step S45 Obtain a target tag code corresponding to the target time code
  • Step S46 Obtain a first address code corresponding to the target tag code
  • Step S47 Obtain the stored first standard signal corresponding to the first address code as the signal to be processed.
  • Steps S41 to S47 describe the process of obtaining the signal to be processed according to the target tag code and the target time code. Not only the object to be processed (ie the signal to be processed) is considered, but also the processing of the signal to be processed is considered.
  • the problem of time is that the clock trigger signal finally determined according to the time code and clock code is used as the basis for the signal to be processed to be triggered.
  • a clock management module is provided in the FPGA chip, and the clock trigger signal of the clock management module is set according to the clock code, where the clock code can be specifically described as the clock code equal to the time code and the time code.
  • the ratio of clock cycles; where: the clock cycle is the clock cycle of the signal processing device. For example: For XilinxV7FPGA chip, its clock frequency is 200MHz, one clock cycle is 5ns, then the conversion relationship from time code to clock code is clock code time code/5. It should be noted that the clock code must be an integer, and this condition can be ensured from the design of the quantum operation application (that is, the target quantum program).
  • the digital-to-analog conversion is performed on the signal to be processed as described in step S4 to obtain a qubit control analog signal.
  • it refers to the high-speed digital-to-analog conversion of the signal to be processed to obtain the qubit control analog signal.
  • the high-speed digital-to-analog conversion can be realized by using a high-speed DAC chip. In specific settings, it can be selected according to the speed of loading the first standard signal from the storage module The sampling rate of the DAC chip.
  • multiple parallel storage modules can be set to ensure the processing efficiency of the first standard signal.
  • the signal to be processed may be subjected to convolution correction processing to compensate for signal distortion caused by circuit defects.
  • this application provides a specific implementation of a method for generating a qubit control signal based on Embodiment 1.
  • the difference between this embodiment and Embodiment 1 is that it clarifies the The preparation work and specific process of the signal to be processed for convolution correction processing are described.
  • the method for generating a qubit control signal further includes: creating a corresponding first address code The convolver code of, wherein the convolution code corresponds to a preset convolver module, and the preset convolver module is used to perform convolution correction processing on the first standard signal.
  • the convolver code and the convolver module are created inside the control module, and the two are corresponding, and the set number of the two is consistent with the number of the first standard signal stored.
  • the convolution module is a module with embedded convolution function, and the specific form of the convolution function can be set as needed. In this embodiment, when convolution processing is performed on the discrete digital signal to be processed, the order of the convolution function determines the time length of the convolution processing.
  • the first standard signal corresponding to the basic quantum logic gate in the target quantum program is obtained according to the target tag code and the target time code in step S4
  • processing the signal to be processed to obtain a qubit control signal includes:
  • Step S51 Set a clock code and a clock trigger signal according to the target time code, wherein the clock code and the clock trigger signal have a one-to-one correspondence;
  • Step S52 receiving the clock trigger signal
  • Step S53 Obtain a clock code corresponding to the clock trigger signal; Obtain a target time code corresponding to the clock code; Obtain a target tag code corresponding to the target time code;
  • Step S54 Obtain the first address code corresponding to the target tag code, and record it as the address code to be called;
  • Step S55 Obtain the convolver code corresponding to the address code to be called, and record it as the convolver code to be called;
  • Step S56 Load the first standard signal corresponding to the address code to be called into the convolver module corresponding to the convolver code to be called, and use the convolution module to The first standard signal undergoes convolution correction processing to obtain a convolution processing signal;
  • Step S57 Perform digital-to-analog conversion processing on the convolution processed signal to generate the qubit control signal.
  • steps S51 to S57 the process of generating corresponding qubit control signals according to the execution order of the quantum logic gates in the target quantum program is realized.
  • the convolver module is controlled by the trigger clock signal, and the trigger clock signal corresponds to the execution timing of the basic quantum logic gate in the target quantum program, which improves the effectiveness of realizing the qubit control signal.
  • the first tag code of the reference quantum gate set in the host computer will be converted into a combination of the first tag code, the first address code, and the first convolver code in the instruction demodulation module, and sent to The method of parallel convolution processing module for processing operation will not cause conflicts.
  • the convolution processing can effectively reduce the system error rate of quantum chips performing quantum computing applications by providing corrections to the qubit control signal.
  • the method for generating qubit control signals can automatically convert any quantum computing application (ie, target quantum program) into a qubit control signal, and send it to the quantum chip to complete the test or computing process.
  • quantum computing application ie, target quantum program
  • all quantum computing applications can be implemented using the following reference quantum gate set.
  • the present invention can greatly alleviate the problem of the shortage of hardware resources in the field of quantum computing.
  • the qubit control signal generation system includes a host computer 1, a main control module 2 and a control signal generation module 3, wherein:
  • the host computer 1 is used to obtain and store a set of quantum logic gates and a target quantum program.
  • the quantum logic gate set refers to a set of quantum logic gates including a plurality of quantum programs, each of the basic quantum logic gates corresponds to a unique first tag code, and the first standard signal is implemented State the signals of basic quantum logic gate operations;
  • the target quantum program refers to a quantum program that can be realized by a combination of basic quantum logic gates in the quantum logic gate set, the target tag code is the first tag code of the basic quantum logic gate in the target quantum program, and the target time The code is the execution timing of the basic quantum logic gate in the target quantum program.
  • the host computer 1 is used to send the first tag code and the first standard signal corresponding to each basic quantum logic gate in the quantum logic gate set, and the target tag code corresponding to each basic quantum logic gate of the corresponding target quantum program and Target time code to the main control module 2;
  • the main control module 2 is configured to receive and store the first tag code and the first standard signal, and set a first address code corresponding to each of the first standard signals one-to-one, and receive the The target tag code and the target time code are combined with the first address code, the target tag code and the target time code to call the first standard signal to generate a signal to be processed.
  • the control signal generating module 3 is configured to receive the signal to be processed and process the signal to be processed to generate a qubit control signal.
  • the present invention provides a qubit control signal generation system.
  • the main control module controls the control signal generation module to generate qubit control according to the target tag code and target time code issued by the host computer.
  • Signal because the control signal corresponding to the quantum logic gate is pre-stored in the main control module in the form of the first standard signal, and the target tag code and the first address code corresponding to the first standard signal are stored in the main control module.
  • Generate the signal to be processed which greatly reduces the capacity storage requirements of the main control module in order to achieve any target quantum program at the source.
  • This embodiment realizes the set of basic quantum logic gates of any quantum program through combination, and can output any target quantum
  • the qubit control signal required for program execution greatly improves the response speed of the control signal generation module and ensures the speed of the subsequent quantum operation.
  • the qubit control signal generation system includes a host computer 1, a main control module 2 and a control signal generation module 3, wherein:
  • the upper computer 1 stores a set of quantum logic gates and a target quantum program.
  • the quantum logic gate set refers to a set including a plurality of basic quantum logic gates, each of the basic quantum logic gates corresponds to a unique first tag code, and the first standard signal is for realizing the basic Signals for quantum logic gate operations;
  • the target quantum program refers to a quantum program that can be realized by a combination of basic quantum logic gates in the quantum logic gate set.
  • the first tag code of the basic quantum logic gate in the target quantum program is recorded as the target tag code, and the target quantum
  • the execution timing of the basic quantum logic gates in the program is recorded as the target time code.
  • the host computer 1 is used to send the first tag code and the first standard signal corresponding to each basic quantum logic gate in the quantum logic gate set, and the target tag code and target time code corresponding to each basic quantum logic gate of the target quantum program To the main control module 2.
  • the set of quantum logic gates refers to a set of basic quantum logic gates that can realize arbitrary target quantum programs through combination.
  • the setting of the set of quantum logic gates can be specifically described as:
  • the set of quantum logic gates is:
  • the set of quantum logic gates is:
  • the set of quantum logic gates is:
  • the X gate, Y gate, and Z gate are single-qubit logic gates
  • CZ is a double-qubit logic gate.
  • the number in the upper right corner of the single-qubit logic gate represents the qubit label on the quantum chip
  • the angle in the lower right corner of the single-qubit logic gate represents the angle at which the logical state of the qubit changes due to the operation of the single-qubit logic gate.
  • the numbers in the lower right corner of the dual-qubit logic gate indicate the master qubit and the controlled qubit.
  • Single-qubit logic gates X gates, Y gates, Z gates, and double-qubit logic gates CZ are basic quantum logic gates. Basic quantum logic gates can realize arbitrary quantum logic gates through combination.
  • any complex quantum logic gate can be decomposed into a combination of a single-qubit logic gate and a double-qubit logic gate.
  • single-qubit logic gates X gates, Y gates, Z gates, and double-qubit logic gates CZ are called basic quantum logic gates.
  • a corresponding first tag code is set for any basic quantum logic gate in the quantum logic gate set, the first tag code is used to identify the basic quantum logic gate, and one basic quantum logic gate has a fixed first A label code.
  • a corresponding first standard signal is set for any basic quantum logic gate in the quantum logic gate set, and the first standard signal is a signal used to implement the operation of the corresponding basic quantum logic gate.
  • the host computer 1 is responsible for sending the set of quantum logic gates to the setting main control module 2 in the format of "first tag code + first standard signal".
  • the host computer 1 is also responsible for sending the target tag code and target time code corresponding to each basic quantum logic gate of the target quantum program to the main control module 2.
  • the host computer 1 is also configured with a A decomposition module 11, a first acquisition module 12 and a first determination module 13, wherein:
  • the first decomposition module 11 is used to decompose the target quantum program to generate the combination of the basic quantum logic gates;
  • the first obtaining module 12 is configured to obtain the first tag code corresponding to each of the basic quantum logic gates in the target quantum program, and record it as a target tag code;
  • the first determining module 13 is configured to determine the target time code corresponding to each basic quantum logic gate according to the execution timing of each basic quantum logic gate in the target quantum program.
  • the target quantum program is a quantum computing application to be run, which is realized by one or a combination of a single quantum logic gate, two quantum logic gates, and multiple quantum logic gates. Any multi-quantum logic gate can be decomposed into a combination of a single quantum logic gate and two quantum logic gates. Therefore, the target quantum program can be decomposed into a combination of basic quantum logic gates. Since a basic quantum logic gate has a fixed first tag code, at the same time, the position of each basic quantum logic gate in the target quantum program represents the execution timing of each basic quantum logic gate. Specifically, the time code is determined by the quantum operation. The precise execution time of the corresponding operation step in the application is converted. For example, the time code of the operation step executed 40ns after the start of the operation can be recorded as 40.
  • the target quantum program can be transformed into an instruction expressed by the first tag code and the time code.
  • the first decomposition module 11 decomposes the target quantum program into a combination of the basic quantum logic gates, so The first obtaining module 12 obtains the first tag code corresponding to each of the basic quantum logic gates in the target quantum program, and records it as the target tag code; the first determining module 13, according to the target quantum program The execution timing of each of the basic quantum logic gates determines the target time code corresponding to each of the basic quantum logic gates.
  • the main control module 2 includes:
  • the second determining module 201 is configured to determine the clock code according to the time code and the clock period, wherein the clock code is equal to the ratio of the time code to the clock period, and the clock period is the master control module 2 Clock cycle;
  • the first processing module 202 is used to form the clock trigger signal according to the clock code
  • the first receiving module 203 is configured to receive the clock trigger signal
  • the second obtaining module 204 is configured to obtain a clock code corresponding to the clock trigger signal
  • the third obtaining module 205 is configured to obtain the target time code corresponding to the clock code
  • the fourth obtaining module 206 is configured to obtain a target tag code corresponding to the target time code
  • the fifth obtaining module 207 is configured to obtain the first address code corresponding to the target tag code
  • the second processing module 208 is configured to obtain the stored first standard signal corresponding to the first address code as a signal to be processed.
  • the signal to be processed according to the target tag code and the target time code which not only considers the object to be processed (ie the signal to be processed), but also considers the processing time of the signal to be processed. That is, the clock trigger signal finally determined according to the time code and the clock code is used as the basis for the signal to be processed to be triggered.
  • the above-mentioned modules can be integrated with a clock management module.
  • the clock trigger signal of the clock management module is set according to a clock code, where the clock code is set according to the time code and can be specifically described as: the clock code is equal to the time code and the clock
  • the ratio of the cycles, the clock cycle is the clock cycle of the set signal processing device.
  • the clock code must be an integer, and this condition can be ensured from the design of the quantum operation application (that is, the target quantum program).
  • the control signal generating module 3 includes a first conversion sub-module 31, which is used to perform digital-to-analog conversion on the signal to be processed to generate the qubit control analog signal, specifically referring to The processed signal performs high-speed digital-analog conversion to obtain the qubit control analog signal.
  • the high-speed digital-analog conversion can be realized by a high-speed DAC chip.
  • the sampling rate of the DAC chip can be selected according to the speed of loading the first standard signal from the storage module.
  • multiple parallel storage modules can be set to ensure the processing efficiency of the first standard signal.
  • the method for generating a qubit control signal by using the qubit control signal production module of embodiment 3 includes the following steps:
  • Step S201 The first tag code and the first standard signal corresponding to each basic quantum logic gate in the quantum logic gate set sent by the host computer 2 are sent to the main control module 2; wherein: the quantum logic gate set can be realized by combination A set of basic quantum logic gates of any quantum program, the basic quantum logic gates include single quantum logic gates and/or double quantum logic gates, the first tag code is used to identify the basic quantum logic gates, one of the basic quantum logic gates The quantum logic gate has a fixed first tag code, and the first standard signal is a signal for realizing the operation of the basic quantum logic gate.
  • Step S202 The main control module 2 stores the first standard signal, and obtains a first address code that identifies the storage location of the first standard signal; wherein: the first address code corresponds to the first tag code one-to-one ;
  • the main control module 2 stores the first standard signal and obtains a first address code that identifies the storage location of the first standard signal; specifically, the main control module 2 adopts an FPGA chip and a storage module, and the main The control module 2 communicates with the host computer 1, receives the "first label code + first standard signal" format information sent by the host computer 1, and controls the first standard signal to be stored in the storage module.
  • the storage module can be a high-speed cache DDR3 or DDR4.
  • the storage module stores the first standard signal and returns the storage address to the control module. For example: the storage module can directly return the address (ie address code) of the first binary number storing the first standard signal to the control module. After the control module uses the address code, it can transfer the corresponding address in the cache module (ie storage module) The first standard signal of the code is loaded out for subsequent use.
  • Step S203 The main control module 2 receives the target tag code and target time code corresponding to each basic quantum logic gate in the target quantum program sent by the host computer 1; wherein: the target tag code is corresponding to the basic quantum logic gate
  • the first tag code and the target time code are used to identify the execution timing of the basic quantum logic gate in the target quantum program.
  • the target quantum program is a quantum computing application to be run, which is realized by one or a combination of single quantum logic gates, two quantum logic gates, multiple quantum logic gates, and any multiple quantum logic gates can be decomposed into single quantum logic
  • the combination of gate and two quantum logic gates therefore, the target quantum program can be decomposed into the combination of basic quantum logic gates.
  • a basic quantum logic gate has a fixed first label code
  • each basic quantum logic gate is in the target quantum program
  • the position that appears in represents the execution timing of each basic quantum logic gate, specifically the time code is converted from the precise execution time of the corresponding operation step in the quantum operation application (ie the target quantum program), for example, 40ns after the operation starts
  • the time code of the first operation step can be recorded as 40.
  • the target quantum program can be converted into an instruction expressed by the first tag code and the time code, specifically, the first tag code corresponding to each of the basic quantum logic gates in the target quantum program is obtained, It is recorded as the target tag code; the target time code corresponding to each basic quantum logic gate is determined according to the execution timing of each basic quantum logic gate in the target quantum program.
  • the upper computer is responsible for sending a target quantum program to the setting signal processing device in the format of "target tag code + target address code", that is, setting the signal processing device to receive each basic quantum logic in the corresponding target quantum program sent by the upper computer
  • target tag code and target time code of the gate are responsible for sending a target quantum program to the setting signal processing device in the format of "target tag code + target address code", that is, setting the signal processing device to receive each basic quantum logic in the corresponding target quantum program sent by the upper computer.
  • the signal processing device is set to be an FPGA chip, and the FPGA chip can be divided into a control module and a storage module by function
  • the signal processing device is set to receive each of the corresponding target quantum programs sent by the host computer.
  • the target tag code and target time code of the basic quantum logic gate that is, the control module receives the target tag code and target time code of each basic quantum logic gate corresponding to the target quantum program sent by the host computer.
  • Step S204 The control signal production module 3 obtains the corresponding first standard signal of the basic quantum logic gate in the target quantum program as the signal to be processed according to the target tag code and the target time code, and processes the The signal to be processed obtains the qubit control signal.
  • the main control module 2 when the main control module 2 receives the target tag code and the target time code again, it can use the tag code (target tag Code and first tag code) this bridge, quickly find the first address code corresponding to the target time code, then call the first standard signal stored at the location of the first address code as the signal to be processed, and then process the signal to be processed to obtain Qubit control signal.
  • tag code target tag Code and first tag code
  • the quantum logic gate set According to the distribution of qubits on the quantum chip to be measured, set the quantum logic gate set, and set the first tag code and the first standard signal corresponding to the basic quantum logic gate in the quantum logic gate set,
  • the first tag code and the first standard signal are stored in the main control module 2 for later use.
  • the setting of the quantum logic gate set needs to ensure that the basic quantum logic gates in the quantum logic gate set can realize arbitrary quantum programs through combination.
  • the basic quantum logic gates in the quantum logic gate set can realize arbitrary complex quantum logic gates through combination. It provides a reference and basis for the later convenient call.
  • the signal processing equipment uses the tag code (target tag code and the first tag code) as a bridge to quickly find the target time code corresponding Then call the first standard signal stored at the location of the first address code as the signal to be processed, and then process the signal to be processed to obtain the qubit control signal, which makes full use of the storage space of the host computer 1, greatly Reduce the capacity and storage requirements of the set signal processing equipment.
  • the preset set of basic quantum logic gates ie, the set of quantum logic gates
  • any target quantum program can be accurately realized. Provides qubit control signals required for multi-qubit testing to meet the needs of multi-qubit testing.
  • this embodiment revolves around the convolution correction processing of the signal to be processed.
  • the difference from Embodiment 3 is that the main control module 2 is optimized and improved in order to optimize the convolution correction processing of the signal to be processed.
  • the main control module 2 further includes a first creation module 209 and a first convolution module 210, and the qubit control signal generation method stores the first standard signal in the storage and obtains the connection with the first tag After the first address code corresponding to the code, it further includes the first creation module 209 to create a convolver code corresponding to the first address code, where the convolver code corresponds to the first convolution module 210,
  • the first convolution module 210 is configured to perform convolution correction processing on the first standard signal.
  • the convolution code created by the first creation module 209 corresponds to the first convolution module 210, and the number of settings for both Consistent with the number of stored first standard signals.
  • the first convolution module 210 is a module in which the convolution function is embedded, and the specific form of the convolution function can be set as required. In this embodiment, when convolution processing is performed on the discrete digital signal to be processed, the order of the convolution function determines the time length of the convolution processing.
  • the main control module 2 After setting the convolver code and the first convolution module 210, the main control module 2 obtains the corresponding first standard of the basic quantum logic gate in the target quantum program according to the target tag code and the target time code
  • the signal is used as a signal to be processed, and the signal to be processed is processed to obtain a qubit control signal, specifically:
  • the main control module 2 further includes:
  • the first setting module 211 is configured to set a clock code and a clock trigger signal according to the target time code, and the clock code and the clock trigger signal have a one-to-one correspondence;
  • the second receiving module 212 is configured to receive the clock trigger signal
  • the sixth obtaining module 213 is configured to obtain a clock code corresponding to the clock trigger signal
  • the seventh obtaining module 214 is configured to obtain a target time code corresponding to the clock code
  • An eighth obtaining module 215, configured to obtain a target tag code corresponding to the target time code
  • the ninth obtaining module 216 is configured to obtain the first address code corresponding to the target tag code, and record it as the address code to be called;
  • the tenth obtaining module 217 is configured to obtain the convolution code mark corresponding to the address code to be called, and it is the convolver code to be called;
  • the second conversion module 219 is configured to perform digital-to-analog conversion processing on the convolution processing signal to generate the qubit control signal.
  • the process of generating corresponding qubit control signals according to the execution order of the quantum logic gates in the target quantum program is realized.
  • the convolver module is controlled by the trigger clock signal, and the trigger clock signal corresponds to the execution timing of the basic quantum logic gate in the target quantum program, which improves the effectiveness of realizing the qubit control signal.
  • the clock code in order to avoid the difference in processing delays of different convolution processing modules and digital-to-analog conversion modules, the clock code can be compensated in advance according to the convolution function order in the convolution processing module to correct the final process
  • the running time of the signal generated by the digital-to-analog conversion module is disordered. For example, if the maximum order of the convolution function in all convolution processing modules is 10, then it takes 10 clock cycles to perform convolution correction in this convolution processing module.
  • control signal generation module 3 further includes a second convolution sub-module 32 configured to perform convolution correction processing on the signal to be processed.
  • the first tag code of the quantum logic gate set in the host computer will be converted into a combination of the first tag code, the first address code, and the first convolver code in the instruction demodulation module, and sent to The method of parallel convolution processing module for processing operation will not cause conflicts.
  • the convolution processing can effectively reduce the system error rate of quantum chips performing quantum computing applications by providing corrections to the qubit control signal.

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Abstract

本发明公开了一种量子比特控制信号生成方法、系统，该方法包括：接收上位机发送的对应基准量子门集中的每一个基本量子逻辑门的第一标签码和第一标准信号；存储所述第一标准信号，并获得标识所述第一标准信号存储位置的第一地址码；接收上位机发送的对应目标量子程序中的每一个基本量子逻辑门的目标标签码和目标时间码；根据所述目标标签码和所述目标时间码获得所述目标量子程序中的基本量子逻辑门的对应的所述第一标准信号作为待处理信号，并处理所述待处理信号获得量子比特控制信号。本发明能够满足多位量子比特测试需求，提供多位量子比特测试所需的量子比特控制信号需求，大大提高了控制信号生成模块的响应速度，保证后级量子运算的速度。

Description

一种量子比特控制信号生成方法、系统
相关申请的交叉引用
本申请要求于2019年1月30日提交中国专利局、申请号为201910094220.8、发明名称为“一种量子比特控制信号生成方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
本申请还要求于2019年1月30日提交中国专利局、申请号为201910093469.7、发明名称为“一种量子比特控制信号生成系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于信号处理技术领域，特别是一种量子比特控制信号生成方法、系统。
背景技术
量子芯片是量子计算机中的核心结构，量子比特是量子芯片的基本运算单元。量子芯片运行时，需要给量子芯片上的量子比特提供可靠的控制信号实现量子芯片测试及量子计算等。量子比特控制信号作用在量子芯片的量子比特上，能够使目标量子比特的量子态发生可控的指定变化，以实现量子逻辑门操作。在实际的运算过程中，需要对量子比特实施一系列量子逻辑门操作，因此量子比特控制信号的数量和长度会因量子逻辑门操作的种类和操作次数大幅增加。
现有技术的量子比特控制信号的生成方法一种是依赖于任意波形发生器等商用信号源。通常，需要将待生成的控制信号预先写好并暂存到任意波形发生器内，然后通过控制信号控制任意波形发生器使预先存储的信号逐点输出到DAC进行播放进而得到模拟波形，从而实现量子比特控制信号的输出。
传统的量子比特控制信号生成系统依赖任意波形发生器的存储容量，当面对多位量子比特需要的量子比特控制信号时，传统的量子比特控制信号生成方法因依赖任意波形发生器的存储容量而具有很大的局限性，因此无法满足多位量子比特测试需求。具体地，以量子芯片测试中的一的五位量子比特的的量子状态断层扫描(QuantumStateTomography)为例，需要完成(2 5) 2＝1024种不同的量子比特投影测量过程，每种过程都需要不同的量子比特控制信号。为了保证系统的运行效率，需要预先设计好所有的量子比特控制信号，并将预先设计好 的所有的量子比特控制信号全部存储到任意波形发生器的存储容量，这对任意波形发生器的存储容量是极大的挑战，甚至是难易实现的。
发明内容
本发明的第一个目的是提供一种量子比特控制信号的生成方法，以解决现有技术中的不足，它能够避免传统的量子比特控制信号生成方法的局限性，能够满足多位量子比特测试需求，提供多位量子比特测试所需的量子比特控制信号需求。
本发明的第二个目的是提供一种量子比特控制信号生成系统。
为达到上述目的，本发明第一方面实施例提出的一种量子比特控制信号的生成方法，所述量子比特控制信号的生成方法包括：
接收上位机发送的对应基准量子门集中每一个基本量子逻辑门的第一标签码和第一标准信号，其中，所述基准量子门集包括多个基本量子逻辑门，所述基本量子逻辑门包括单量子逻辑门和/或双量子逻辑门，所述第一标签码用于标识所述基本量子逻辑门，每个所述基本量子逻辑门具有固定的所述第一标签码，所述第一标准信号为实现所述基本量子逻辑门操作的信号；
存储所述第一标准信号，并获得标识所述第一标准信号存储位置的第一地址码；其中：所述第一地址码与所述第一标签码一一对应；
接收所述上位机发送的对应目标量子程序中每一个基本量子逻辑门的目标标签码和目标时间码，其中，所述目标标签码为所述目标量子程序中所述基本量子逻辑门对应的所述第一标签码，所述目标时间码用于标识所述目标量子程序中所述基本量子逻辑门在所述目标量子程序中的执行时序；
根据所述目标标签码和所述目标时间码获得所述目标量子程序中基本量子逻辑门的对应的所述第一标准信号，并将其作为待处理信号；以及处理所述待处理信号以生成量子比特控制信号。
如上所述的量子比特控制信号生成方法，其中，优选的是，所述接收上位机发送的对应目标量子程序中的每一个基本量子逻辑门的目标标签码和目标时间码，包括：
分解所述目标量子程序以生成所述基本量子逻辑门的组合；
获取所述目标量子程序中的每个所述基本量子逻辑门对应的第一标签码，并记为所述目标标签码；以及
根据所述目标量子程序中的每个所述基本量子逻辑门的执行时序确定每个所述基本量 子逻辑门对应的所述目标时间码。
如上所述的量子比特控制信号生成方法，其中，优选的是，所述根据所述目标标签码和所述目标时间码获得所述目标量子程序中的基本量子逻辑门的对应的所述第一标准信号作为待处理信号，包括：
根据所述目标时间码设置时钟码和时钟触发信号，其中，所述时钟码和所述时钟触发信号一一对应；
接收所述时钟触发信号；
获得与所述时钟触发信号对应的时钟码；
获得与所述时钟码对应的目标时间码；
获得与所述目标时间码对应的目标标签码；
获得与所述目标标签码对应的第一地址码；以及
获得与所述第一地址码对应的存储的所述第一标准信号作为待处理信号。
如上所述的量子比特控制信号生成方法，其中，优选的是，所述根据所述目标时间码设置时钟码和时钟触发信号，包括：
根据所述时间码和时钟周期确定所述时钟码，其中，所述时钟码等于所述时间码与所述时钟周期的比值，所述时钟周期为处理设备的时钟周期；以及
根据所述时钟码形成所述时钟触发信号。
如上所述的量子比特控制信号生成方法，其中，优选的是，所述处理所述待处理信号获得量子比特控制信号，包括：
对所述待处理信号进行数字模拟转化，得到量子比特控制模拟信号。
如上所述的量子比特控制信号生成方法，其中，优选的是，在所述对待处理信号进行数字模拟转化，得到量子比特控制模拟信号之前，还包括：
对所述待处理信号进行卷积修正处理。
如上所述的量子比特控制信号生成方法，其中，优选的是，在所述存储所述第一标准信号，并获得与所述第一标签码对应的第一地址码之后，还包括:
创建与所述第一地址码对应的卷积器码，其中，所述卷积器码与预设卷积器模块对应，所述预设卷积器模块用于对所述第一标准信号进行卷积修正处理。
如上所述的量子比特控制信号生成方法，其中，优选的是，所述根据所述目标标签码和所述目标时间码获得所述目标量子程序中的基本量子逻辑门的对应的所述第一标准信号作为待处理信号，并处理所述待处理信号获得量子比特控制信号号，包括：
根据所述目标时间码设置时钟码和时钟触发信号，其中，所述时钟码和所述时钟触发信号一一对应；
接收所述时钟触发信号；
获得与所述时钟触发信号对应的时钟码；
获得与所述时钟码对应的目标时间码；
获得与所述目标时间码对应的目标标签码；
获得与所述目标标签码对应的第一地址码，并记为待调用地址码；
获得与所述待调用地址码对应的卷积器码，并记为待调用卷积器码；
将所述待调用地址码对应的第一标准信号加载到所述待调用卷积器码所对应的所述卷积器模块中，并通过所述卷积器模块对加载的所述第一标准信号进行卷积修正处理以得到卷积处理信号；以及
对所述卷积处理信号进行数模转化处理以生成所述量子比特控制信号。
如上所述的量子比特控制信号生成方法，其中，优选的是，所述卷积器模块对加载的所述第一标准信号进行卷积修正处理得到卷积处理信号，包括：
所述卷积器模块通过内嵌的卷积函数对所述第一标准信号进行卷积修正处理以得到消失真信号。
如上所述的量子比特控制信号生成方法，其中，优选的是，在所述卷积器模块对加载的所述第一标准信号进行卷积处理得到消失真信号之前，还包括:
根据所述卷积函数的阶数调整所述卷积器模块对应的时钟码。
与现有技术相比，本发明通过在上位机中设置可以通过组合实现任意量子程序的基本量子逻辑门的集合的基准量子门集，然后上位机发送对应基准量子门集中的每一个基本量子逻辑门的第一标签码和第一标准信号给设定信号处理设备，即设定信号处理设备接收上位机发送的对应基准量子门集中的每一个基本量子逻辑门的第一标签码和第一标准信号，设定信号处理设备存储所述第一标准信号，并获得标识所述第一标准信号存储位置的第一地址码，然后在上位机中设置由基本量子逻辑门组成的目标量子程序，并记录目标量子程序中的每一个基本量子逻辑门的目标标签码和目标时间码，然后由上位机发送的对应目标量子程序中的每一个基本量子逻辑门的目标标签码和目标时间码给设定信号处理设备，设定信号处理设备只需要按照目标标签码和所述目标时间码获得所述目标量子程序中的基本量子逻辑门的对应的所述第一标准信号作为待处理信号，并处理所述待处理信号即可获得量子比特控制信号，充分利用了上位机的存储空间，大大减少了设定信号处理设备的容量存储要求，另外，通过 预设的可以通过组合实现任意量子程序的基本量子逻辑门的集合(即基准量子门集)，可以实现任意目标量子程序，能够提供多位量子比特测试所需的量子比特控制信号，满足多位量子比特测试需求。
为达到上述目的，本发明第二方面实施例提出的一种量子比特控制信号生成系统，所述量子比特控制信号生成系统包括上位机、主控模块和控制信号生成模块，其中：
所述上位机，用于获得并存储量子逻辑门集合和目标量子程序、发送对应量子逻辑门集合中的每一个基本量子逻辑门的第一标签码及第一标准信号至所述主控模块，以及发送对应目标量子程序的每一个基本量子逻辑门对应的目标标签码和目标时间码至所述主控模块，其中，所述量子逻辑门集合指包括多个量子程序的量子逻辑门的集合，每个所述基本量子逻辑门对应有一个唯一的所述第一标签码，所述第一标准信号为实现所述基本量子逻辑门操作的信号，其中，所述目标标签码为所述目标量子程序中的所述基本量子逻辑门对应的第一标签码，所述目标时间码用于标识基本量子逻辑门在所述目标量子程序中的执行时序；
所述主控模块，用于接收并存储所述第一标签码和所述第一标准信号，并设置与每个所述第一标准信号一一对应的第一地址码，并接收所述目标标签码和所述目标时间码，以及结合所述第一地址码、所述目标标签码和所述目标时间码生成待处理信号；以及
所述控制信号生成模块，用于接收所述待处理信号并处理所述待处理信号以生成量子比特控制信号。
进一步的，所述上位机包括第一分解模块、第一获取模块和第一确定模块，其中：
所述第一分解模块，用于分解所述目标量子程序以生成所述基本量子逻辑门的组合；
所述第一获取模块，用于获取所述目标量子程序中每个所述基本量子逻辑门对应的所述第一标签码，并记为所述目标标签码；以及
所述第一确定模块，用于根据所述目标量子程序中的每个所述基本量子逻辑门的执行时序确定每个所述基本量子逻辑门对应的所述目标时间码。
进一步的，所述主控模块中包括：
第二确定模块，用于根据所述时间码和时钟周期确定所述时钟码，其中，所述时钟码等于所述时间码与所述时钟周期的比值，所述时钟周期为处理设备的时钟周期；
第一处理模块，用于根据所述时钟码形成所述时钟触发信号；
第一接收模块，用于接收所述时钟触发信号；
第二获取模块，用于获取与所述时钟触发信号对应的时钟码；
第三获取模块，用于获取与所述时钟码对应的目标时间码；
第四获取模块，用于获取与所述目标时间码对应的目标标签码；
第五获取模块，用于获取与所述目标标签码对应的第一地址码；以及
第二处理模块，用于获取与所述第一地址码对应的存储的所述第一标准信号作为待处理信号。
进一步的，所述主控模块包括第一创建模块和第一卷积模块，其中：
所述第一创建模块，用于创建与所述第一地址码对应的卷积器码，其中，所述卷积器码与预设卷积器模块对应；以及
所述第一卷积模块，用于对所述第一标准信号进行卷积修正处理。
进一步的，所述主控模块还包括：
第一设置模块，用于根据所述目标时间码设置时钟码和时钟触发信号，所述时钟码和所述时钟触发信号一一对应；
第二接收模块，用于接收所述时钟触发信号；
第六获取模块，用于获得与所述时钟触发信号对应的时钟码；
第七获取模块，用于获得与所述时钟码对应的目标时间码；
第八获取模块，用于获得与所述目标时间码对应的目标标签码；
第九获取模块，用于获得与所述目标标签码对应的第一地址码，并记为待调用地址码；
第十获取模块，用于获得与所述待调用地址码对应的卷积器码记，并为待调用卷积器码；
第一加载模块，用于将所述待调用地址码对应的第一标准信号加载到所述待调用卷积器码对应的所述卷积器模块中，所述卷积器模块对加载的所述第一标准信号进行卷积修正处理得到卷积处理信号；
第二转化模块，用于对所述卷积处理信号经数模转化处理以生成所述量子比特控制信号。
进一步的，所述控制信号生成模块包括：
第一转化子模块，所述第一转化子模块用于对所述待处理信号进行数字模拟转化，以生成所述量子比特控制模拟信号。
进一步的，所述控制信号生成模块还包括：
第二卷积子模块，所述第二卷积子模块用于对所述待处理信号进行卷积修正处理。
与现有技术相比，本发明通过提供了一种量子比特控制信号生成系统，通过主控模块通过上位机下发的目标标签码和目标时间码，控制所述控制信号生成模块生成量子比特控制信号，由于将对应量子逻辑门的控制信号以第一标准信号的形式预存在主控模块中，并采用目 标标签码和在主控模块存储与第一标准信号对应的第一地址码的形式来生成待处理信号，在源头上大大减少了对于主控模块的容量存储要求，并可以通过组合实现任意量子程序的基本量子逻辑门的集合，并输出量子比特控制信号，以实现任意目标量子程序，本发明能够快速提供量子比特控制信号，大大提高了控制信号生成模块的响应速度，保证后级量子运算的速度。
附图说明
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1是本发明实施例1提供的量子比特控制信号生成方法的流程示意图。
图2是本发明具体实施例3中量子比特控制信号生成系统的硬件结构框图；
图3是本发明具体实施例4中的量子比特控制信号生成系统的硬件结构框图硬件结构框图。
具体实施方式
下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
在量子运算应用中，取决于运算应用的复杂程度，需要数百步甚至数万步运算步骤，但是在所有的运算步骤中所使用的基本运算操作数量是有限的。类比经典计算机中，所有的运算应用都可以使用与非门、异或门这两种基本逻辑门操作的组合来实现。在量子计算机中，所有的量子运算应用都可以使用单量子逻辑门操作和双量子逻辑门操作的组合来实现，例如在两位量子芯片中，所有的量子运算应用都能够使用量子逻辑门操作组合
Figure PCTCN2019086169-appb-000001
来实现；在三位量子芯片中，所有的量子运算应用都能够使用量子逻辑门操作组合
Figure PCTCN2019086169-appb-000002
来实现；在四位量子芯片中，所有的量子运算应用都能够使用量子逻辑门操作组合
Figure PCTCN2019086169-appb-000003
来实现；五位量子芯片中所有的量子运算应用都能够使用量子逻辑门操作组合
Figure PCTCN2019086169-appb-000004
实现，依次类推。
实施例1：
图1为本申请实施例1的量子比特控制信号的生成方法的流程示意图，如图1所示，本实施例提供了一种量子比特控制信号的生成方法，用于将量子运算应用转化为基本量子比特控制信号，并最终发送给量子芯片执行运算。需要说明的是，这里所述的基本量子比特控制信号并不是用于完成整个量子芯片运算应用的控制信号，而是完成一个运算步骤(即一个目标量子程序)的基本信号。
所述量子比特控制信号的生成方法包括：
步骤S1：接收上位机发送的对应基准量子门集中每一个基本量子逻辑门的第一标签码和第一标准信号，其中，所述基准量子门集包括多个基本量子逻辑门，所述基本量子逻辑门包括单量子逻辑门和/或双量子逻辑门，所述第一标签码用于标识所述基本量子逻辑门，一个所述基本量子逻辑门具有一个固定的所述第一标签码，所述第一标准信号为实现所述基本量子逻辑门操作的信号。
具体而言，对两位量子芯片而言，基准量子门集合为：
Figure PCTCN2019086169-appb-000005
对三位量子芯片而言，量子逻辑门集合为：
Figure PCTCN2019086169-appb-000006
对四位量子芯片而言，量子逻辑门集合为：
Figure PCTCN2019086169-appb-000007
其中，X门、Y门、Z门是单量子比特逻辑门，CZ是双量子比特逻辑门。单量子比特逻辑门右上角的数字表示量子芯片上的量子比特标号，单量子比特逻辑门右下角的角度表示该单量子逻辑门操作导致的量子比特逻辑状态改变的角度。双量子比特逻辑门右下角的数字表示主控量子比特和受控量子比特。单量子比特逻辑门X门、Y门、Z门、双量子比特逻辑门CZ通过组合可以实现任意的量子逻辑门。因此，任意复杂量子逻辑门均可以分解为单量子比特逻辑门和双量子比特逻辑门的组合。在本发明的实施例中，单量子比特逻辑门X门、Y门、Z门、双量子比特逻辑门CZ称为基本量子逻辑门。
对基准量子门集中的任一基本量子逻辑门均设置对应的第一标签码，第一标签码用于标识所述基本量子逻辑门，一个所述基本量子逻辑门具有一个固定的所述第一标签码。对基准量子门集中的任一基本量子逻辑门均设置对应的第一标准信号，第一标准信号为用于实现对 应基本量子逻辑门操作的信号。
上位机负责将一基准量子门集以“第一标签码+第一标准信号”的格式发送给设定信号处理设备，即设定信号处理设备接收上位机发送的对应基准量子门集中的每一个基本量子逻辑门的第一标签码和第一标准信号。
需要说明的是，设定信号处理设备可以为FPGA芯片。
步骤S2：存储所述第一标准信号，并获得标识所述第一标准信号存储位置的第一地址码，其中，所述第一地址码与所述第一标签码一一对应。
具体而言，即设定信号处理设备存储所述第一标准信号，并获得标识所述第一标准信号存储位置的第一地址码；设定信号处理设备为FPGA芯片，FPGA芯片按功能内部可以划分具体区域为控制模块和存储模块。控制模块和上位机通信，接收上位机发送的“第一标签码+第一标准信号”格式信息，并控制第一标准信号存储到存储模块中，存储模块可以为高速缓存器DDR3或DDR4。存储模块存储第一标准信号，并将存储地址返回给控制模块。例如：存储模块可以直接将存储第一标准信号的第一个二进制数的地址(即地址码)返回给控制模块，控制模块使用地址码后，能够将高速缓存模块(即存储模块)中对应地址码的第一标准信号加载出来，供后续使用。
步骤S3：接收所述上位机发送的对应目标量子程序中每一个基本量子逻辑门的目标标签码和目标时间码，其中，所述目标标签码为所述目标量子程序中所述基本量子逻辑门对应的所述第一标签码，所述目标时间码用于标识所述目标量子程序中所述基本量子逻辑门在所述目标量子程序中的执行时序。
具体而言，目标量子程序为待运行的量子运算应用，是单量子逻辑门、两量子逻辑门、多量子逻辑门之一或者组合实现的，任意的多量子逻辑门均可以分解为单量子逻辑门和两量子逻辑门的组合，因此，可以把目标量子程序分解基本量子逻辑门的组合，由于一基本量子逻辑门具有一固定的第一标签码，同时，各基本量子逻辑门在目标量子程序中出现的位置代表了各基本量子逻辑门的被执行时序，具体为时间码由量子运算应用(即目标量子程序)中对应运算步骤的精确执行时刻转化而来，例如，在运算开始后第40ns起执行的运算步骤的时间码可以记为40。
基于此，可以将目标量子程序转化为一条由第一标签码和时间码表达的指令，具体而言，获取所述目标量子程序中的每一个所述基本量子逻辑门对应的第一标签码，记为目标标签码；根据所述目标量子程序中的每一个所述基本量子逻辑门的执行时序确定每一个所述基本量子逻辑门对应的目标时间码。
上位机负责将一目标量子程序以“目标标签码+目标地址码”的格式发送给设定信号处理设备，即设定信号处理设备接收上位机发送的对应目标量子程序中的每一个基本量子逻辑门的目标标签码和目标时间码。
具体而言，在设定信号处理设备为FPGA芯片，且FPGA芯片按功能可以划分为控制模块和存储模块的硬件设备下，设定信号处理设备接收上位机发送的对应目标量子程序中的每一个基本量子逻辑门的目标标签码和目标时间码，即控制模块接收上位机发送的对应目标量子程序中的每一个基本量子逻辑门的目标标签码和目标时间码。
步骤S4：根据所述目标标签码和所述目标时间码获得所述目标量子程序中基本量子逻辑门的对应的所述第一标准信号，并将其作为待处理信号；以及处理所述待处理信号以生成量子比特控制信号。
具体而言，由于控制模块中存储有一一对应的第一标签码和第一地址码，所以当控制模块重新接收到目标标签码和目标时间码时，可以通过借助标签码(目标标签码及第一标签码)这个桥梁，迅速找到目标时间码对应的第一地址码，然后调用第一地址码位置处的存储的第一标准信号作为待处理信号，然后处理所述待处理信号以生成量子比特控制信号。
整个过程中，根据待测量量子芯片上的量子比特分布情况，设置基准量子门集，并设置与基准量子门集内的基本量子逻辑门的一一对应的第一标签码和第一标准信号，将第一标签码和第一标准信号存储在设定信号处理设备中，以备后用。基准量子门集的设置时，需要保证基准量子门集内的基本量子逻辑门可以通过组合实现任意量子程序，本质上即基准量子门集内的基本量子逻辑门可以通过组合实现任意复杂的量子逻辑门，为后期的方便调用提供了参考和基础。然后在针对上位机发送的代表目标量子程序中基本量子逻辑门的目标标签码和目标时间码，信号处理设备借助标签码(目标标签码及第一标签码)这个桥梁，迅速找到目标时间码对应的第一地址码，然后调用第一地址码位置处的存储的第一标准信号作为待处理信号，然后处理所述待处理信号获得量子比特控制信号，充分利用了上位机的存储空间，大大减少了设定信号处理设备的容量存储要求，另外，通过预设的可以通过组合实现任意量子程序的基本量子逻辑门的集合(即基准量子门集)，可以准确的实现任意目标量子程序，能够提供多位量子比特测试所需的量子比特控制信号，满足多位量子比特测试需求。
作为本实施例的一种具体实施方案，步骤S4中所述的根据所述目标标签码和所述目标时间码获得所述目标量子程序中的基本量子逻辑门的对应的所述第一标准信号作为待处理信号，包括：
步骤S41：根据所述目标时间码设置时钟码和时钟触发信号，其中，所述时钟码和所述 时钟触发信号一一对应；
步骤S42：接收所述时钟触发信号；
步骤S43：获得与所述时钟触发信号对应的时钟码；
步骤S44：获得与所述时钟码对应的目标时间码；
步骤S45：获得与所述目标时间码对应的目标标签码；
步骤S46：获得与所述目标标签码对应的第一地址码；
步骤S47：获得与所述第一地址码对应的存储的所述第一标准信号作为待处理信号。
通过步骤S41至步骤S47描述了根据所述目标标签码和所述目标时间码获得待处理信号的过程，不仅考虑了待处理对象(即待处理信号)，还考虑了待处理信号的被执行处理时间的问题，即根据时间码、时钟码最终确定的时钟触发信号作为待处理信号被触发处理的依据。
在具体实施的时候，FPGA芯片内设置钟管理模块，时钟管理模块的时钟触发信号根据时钟码设置，其中时钟码根据时间码设置可以具体描述为，所述时钟码等于所述时间码与所述时钟周期的比值；其中：所述时钟周期为设定信号处理设备的时钟周期。例如：对XilinxV7FPGA芯片，其时钟主频为200MHz，一个时钟周期为5ns，则时间码到时钟码的转化关系为时钟码＝时间码/5。需要说明的是，时钟码一定是整数，可以从量子运算应用(即目标量子程序)的设计中确保该条件满足。
同时，步骤S4中所述的对所述待处理信号进行数字模拟转化，得到量子比特控制模拟信号。具体而言是指对待处理信号进行高速数字模拟转化，得到量子比特控制模拟信号，高速数字模拟转化可以采用高速DAC芯片实现，在具体设置时，可以根据从存储模块加载第一标准信号的速度选择DAC芯片的采样率。而且，为了保证信号的高速生成，可以设置多个并行的存储模块来确保第一标准信号的处理效率。
另外，在对信号进行数模转化之前，作为优选，可以对所述待处理信号进行卷积修正处理来补偿因电路瑕疵带来的信号失真。
实施例2:
围绕着对所述待处理信号的卷积修正处理，本申请基于实施例1提供了一种量子比特控制信号生成方法的具体实施方案，本实施例与实施例1的区别在于，明确了对所述待处理信号进行卷积修正处理的准备工作以及具体进行过程。
具体而言，量子比特控制信号生成方法在所述存储所述第一标准信号，并获得与所述第一标签码对应的第一地址码之后，还包括：创建与所述第一地址码对应的卷积器码，其中， 所述卷积器码与预设卷积器模块对应，所述预设卷积器模块用于对所述第一标准信号进行卷积修正处理。
即在控制模块内部创建卷积器码和卷积器模块，两者对应，两者的设置数量与保存的第一标准信号的数量一致。卷积器模块即内嵌卷积函数的模块，卷积函数的的具体形式根据需要进行设置即可。在本实施例中，针对待处理的离散数字信号进行卷积处理时，卷积函数的阶数决定了卷积处理的用时长度。
设置卷积器码和卷积器模块之后，步骤S4所述的根据所述目标标签码和所述目标时间码获得所述目标量子程序中的基本量子逻辑门的对应的所述第一标准信号作为待处理信号，并处理所述待处理信号获得量子比特控制信号，包括：
步骤S51：根据所述目标时间码设置时钟码和时钟触发信号，其中，所述时钟码和所述时钟触发信号一一对应；
步骤S52：接收所述时钟触发信号；
步骤S53：获得与所述时钟触发信号对应的时钟码；获得与所述时钟码对应的目标时间码；获得与所述目标时间码对应的目标标签码；
步骤S54：获得与所述目标标签码对应的第一地址码，并记为待调用地址码；
步骤S55：获得与所述待调用地址码对应的卷积器码，并记为待调用卷积器码；
步骤S56：将所述待调用地址码对应的第一标准信号加载到所述待调用卷积器码所对应的所述卷积器模块中，并通过所述卷积器模块对加载的所述第一标准信号进行卷积修正处理以得到卷积处理信号；
步骤S57：对所述卷积处理信号进行数模转化处理以生成所述量子比特控制信号。
通过步骤S51至步骤S57，实现了按照目标量子程序中的量子逻辑门的执行顺序生成对应的量子比特控制信号的过程。该过程中，卷积器模块受触发时钟信号控制，触发时钟信号对应目标量子程序中的基本量子逻辑门的执行时序，提高了实现量子比特控制信号的有效性。
在具体实施的时候，为了避免不同的卷积处理模块、数模转换模块的处理延时差异，我们可以预先根据卷积处理模块中的卷积函数阶数，进行时钟码的补偿，以校正最终经过数模转换模块生成的信号的运行时刻错乱。例如，所有卷积处理模块中的卷积函数最大阶数为10阶，则在该卷积处理模块中执行卷积修正需要耗占10个时钟周期。设置卷积处理模块的时钟码补偿值为10-N，其中N为卷积处理模块中的卷积函数的阶数，则该卷积处理模块将在时钟码+10-N时刻处理对应的第一标准信号，而不是在时钟码时刻开始处理对应的第一标 准信号。
需要说明的是，在上位机执行对量子运算应用的翻译时，即上位机在解析量子程序时，实际上有可能存在同时在不同的量子比特上执行不同的运算步骤(量子逻辑门操作)的情况。换句话说，可能存在多个第一标准信号的第一标签码对应同一个第一时间码的情况。但是，首先，由于FPGA内存在多个并行的卷积处理模块，其次，每个第一标准信号仅对应一个卷积处理模块，最后，同一时刻不可能存在两个完全一样的第一标准信号，因此，将上位机中的基准量子门集的第一标签码将在指令解调模块中转化为第一标签码、第一地址码、第一卷积器码三者的组合，并分别送入并行的卷积处理模块进行处理运算的方法是不会引起冲突的。同时，卷积处理通过提供对量子比特控制信号的修正，它能够有效降低量子芯片执行量子运算应用的系统错误率。
综上，本申请提供的量子比特控制信号的生成方法，它能够将任意量子运算应用(即目标量子程序)自动转化为量子比特控制信号，输送给量子芯片完成测试或运算过程。
举例来说，在五位量子芯片中，所有的量子运算应用都能够使用如下基准量子门集来实现。
Figure PCTCN2019086169-appb-000008
由于通常情况下，每个基本量子逻辑门的平均操作时间为50ns，因此，在此基准量子门集中，第一标准信号总共占用的可播放容量仅为19×50ns＝950ns，同时，使用这19种第一标准信号可以生成的量子运算应用数量是没有上限的。因此本发明可以极大地缓解在量子计算领域硬件资源短缺的问题。
结合附图2，本实施例提供了一种量子比特控制信号生成系统，所述量子比特控制信号生成系统包括上位机1、主控模块2和控制信号生成模块3，其中：
所述上位机1用于获得并存储量子逻辑门集合和目标量子程序。
其中，所述量子逻辑门集合指包括多个量子程序的量子逻辑门的集合，每个所述基本量子逻辑门对应有一个唯一的所述第一标签码，所述第一标准信号为实现所述基本量子逻辑门操作的信号；
所述目标量子程序是指可以通过所述量子逻辑门集合中的基本量子逻辑门组合实现的量子程序，目标标签码为目标量子程序中的基本量子逻辑门具有的第一标签码记，目标时间码为目标量子程序中的基本量子逻辑门的执行时序。
所述上位机1用于发送对应量子逻辑门集合中的每个基本量子逻辑门的第一标签码及 第一标准信号、及对应目标量子程序的每个基本量子逻辑门对应的目标标签码和目标时间码至所述主控模块2；
所述主控模块2，用于接收并存储所述第一标签码和所述第一标准信号，并设置与每个所述第一标准信号一一对应的第一地址码，并接收所述目标标签码和所述目标时间码，以及结合所述第一地址码、所述目标标签码和所述目标时间码调用所述第一标准信号以生成待处理信号。
所述控制信号生成模块3，用于接收所述待处理信号并处理所述待处理信号以生成量子比特控制信号。
与现有技术相比，本发明通过提供了一种量子比特控制信号生成系统，通过主控模块根据上位机下发的目标标签码和目标时间码，控制所述控制信号生成模块生成量子比特控制信号，由于将对应量子逻辑门的控制信号以第一标准信号的形式预存在主控模块中，并采用目标标签码和在主控模块存储与第一标准信号对应的第一地址码的形式来生成待处理信号，在源头上大大减少了为实现任意目标量子程序时对于主控模块的容量存储要求，本实施例通过组合实现任意量子程序的基本量子逻辑门的集合，并可以输出任意目标量子程序执行时所需要的量子比特控制信号，大大提高了控制信号生成模块的响应速度，保证后级量子运算的速度。
实施例3
结合附图2，本实施例提供了一种量子比特控制信号生成系统，所述量子比特控制信号生成系统包括上位机1、主控模块2和控制信号生成模块3，其中：
所述上位机1内存储有量子逻辑门集合和目标量子程序。
其中，所述量子逻辑门集合指包括多个基本量子逻辑门的集合，每个所述基本量子逻辑门对应有一个唯一的所述第一标签码，所述第一标准信号为实现所述基本量子逻辑门操作的信号；
所述目标量子程序是指可以通过所述量子逻辑门集合中的基本量子逻辑门组合实现的量子程序，目标量子程序中的基本量子逻辑门具有的第一标签码记为目标标签码，目标量子程序中的基本量子逻辑门的执行时序记为目标时间码。
上位机1用于发送对应量子逻辑门集合中的每个基本量子逻辑门的第一标签码及第一标准信号、及对应目标量子程序的每个基本量子逻辑门对应目标标签码和目标时间码至所述主控模块2。
所述量子逻辑门集合指可以通过组合实现任意目标量子程序的基本量子逻辑门的集合，关于量子逻辑门集合的设置具体可以描述为：
对两位量子芯片而言，量子逻辑门集合为：
Figure PCTCN2019086169-appb-000009
对三位量子芯片而言，量子逻辑门集合为：
Figure PCTCN2019086169-appb-000010
对四位量子芯片而言，量子逻辑门集合为：
Figure PCTCN2019086169-appb-000011
其中，X门、Y门、Z门是单量子比特逻辑门，CZ是双量子比特逻辑门。单量子比特逻辑门右上角的数字表示量子芯片上的量子比特标号，单量子比特逻辑门右下角的角度表示该单量子逻辑门操作导致的量子比特逻辑状态改变的角度。双量子比特逻辑门右下角的数字表示主控量子比特和受控量子比特。单量子比特逻辑门X门、Y门、Z门、双量子比特逻辑门CZ即基本量子逻辑门，基本量子逻辑门通过组合可以实现任意的量子逻辑门。因此，任意复杂量子逻辑门均可以分解为单量子比特逻辑门和双量子比特逻辑门的组合。在本发明的实施例中，单量子比特逻辑门X门、Y门、Z门、双量子比特逻辑门CZ称为基本量子逻辑门。
对量子逻辑门集合中的任一基本量子逻辑门均设置对应的第一标签码，第一标签码用于标识所述基本量子逻辑门，一个所述基本量子逻辑门具有一个固定的所述第一标签码。对量子逻辑门集合中的任一基本量子逻辑门均设置对应的第一标准信号，第一标准信号为用于实现对应基本量子逻辑门操作的信号。
上位机1负责将量子逻辑门集合以“第一标签码+第一标准信号”的格式发送给设定主控模块2。
进一步的，所述上位机1还负责将对应目标量子程序的每一个基本量子逻辑门对应目标标签码和目标时间码发送至所述主控模块2，对应的，上位机1内还配置有第一分解模块11、第一获取模块12和第一确定模块13，其中：
所述第一分解模块11用于分解所述目标量子程序以生成所述基本量子逻辑门的组合；
所述第一获取模块12用于获取所述目标量子程序中每个所述基本量子逻辑门对应的所述第一标签码，并记为目标标签码；
所述第一确定模块13用于根据所述目标量子程序中的每个所述基本量子逻辑门的执行时序确定每个所述基本量子逻辑门对应的所述目标时间码。
具体的，目标量子程序为待运行的量子运算应用，是单量子逻辑门、两量子逻辑门、多量子逻辑门之一或者组合实现的。任意的多量子逻辑门均可以分解为单量子逻辑门和两量子逻辑门的组合，因此，可以把目标量子程序分解基本量子逻辑门的组合。而由于一基本量子逻辑门具有一固定的第一标签码，同时，各基本量子逻辑门在目标量子程序中出现的位置代表了各基本量子逻辑门的被执行时序，具体为时间码由量子运算应用中对应运算步骤的精确执行时刻转化而来，例如，在运算开始后第40ns起执行的运算步骤的时间码可以记为40。
基于此，可以将目标量子程序转化为一条由第一标签码和时间码表达的指令，具体而言，第一分解模块11将所述目标量子程序分解为所述基本量子逻辑门的组合，所述第一获取模块12获取所述目标量子程序中的每一个所述基本量子逻辑门对应的第一标签码，记为目标标签码；所述第一确定模块13，根据所述目标量子程序中的每一个所述基本量子逻辑门的执行时序确定每一个所述基本量子逻辑门对应的目标时间码。
所述主控模块2包括：
第二确定模块201，用于根据所述时间码和时钟周期确定所述时钟码，其中，所述时钟码等于所述时间码与所述时钟周期的比值，所述时钟周期为主控模块2的时钟周期；
第一处理模块202，用于其根据所述时钟码形成所述时钟触发信号；
第一接收模块203，用于接收所述时钟触发信号；
第二获取模块204，用于获取与所述时钟触发信号对应的时钟码；
第三获取模块205，用于获取与所述时钟码对应的目标时间码；
第四获取模块206，用于获取与所述目标时间码对应的目标标签码；
第五获取模块207，用于获取与所述目标标签码对应的第一地址码；
第二处理模块208，用于获取与所述第一地址码对应的存储的所述第一标准信号作为待处理信号。
通过上述模块，可以实现根据所述目标标签码和所述目标时间码获得待处理信号，不仅考虑了待处理对象(即待处理信号)，还考虑了待处理信号的被执行处理时间的问题，即根据时间码、时钟码最终确定的时钟触发信号作为待处理信号被触发处理的依据。
具体的，上述模块中可以使用时钟管理模块整合，时钟管理模块的时钟触发信号根据时钟码设置，其中时钟码根据时间码设置可以具体描述为，所述时钟码等于所述时间码与所述时钟周期的比值，所述时钟周期为设定信号处理设备的时钟周期。例如：对XilinxV7FPGA芯片，其时钟主频为200MHz，一个时钟周期为5ns，则时间码到时钟码的转化关系为时钟码 ＝时间码/5。需要说明的是，时钟码一定是整数，可以从量子运算应用(即目标量子程序)的设计中确保该条件满足。
所述控制信号生成模块3包括第一转化子模块31，所述第一转化子模块31用于对所述待处理信号进行数字模拟转化，以生成所述量子比特控制模拟信号，具体是指对待处理信号进行高速数字模拟转化，得到量子比特控制模拟信号，高速数字模拟转化可以采用高速DAC芯片实现，在具体设置时，可以根据从存储模块加载第一标准信号的速度选择DAC芯片的采样率。而且，为了保证信号的高速生成，可以设置多个并行的存储模块来确保第一标准信号的处理效率。
采用实施例3的量子比特控制信号生产模块进行量子比特控制信号生成的方法，包括以下步骤：
步骤S201：上位机2发送的对应量子逻辑门集合中的每一个基本量子逻辑门的第一标签码和第一标准信号至主控模块2；其中：所述量子逻辑门集合指可以通过组合实现任意量子程序的基本量子逻辑门的集合，所述基本量子逻辑门包括单量子逻辑门和/或双量子逻辑门，所述第一标签码用于标识所述基本量子逻辑门，一个所述基本量子逻辑门具有一个固定的所述第一标签码，所述第一标准信号为实现所述基本量子逻辑门操作的信号。
步骤S202：主控模块2存储所述第一标准信号，并获得标识所述第一标准信号存储位置的第一地址码；其中：所述第一地址码与所述第一标签码一一对应；
具体而言，即主控模块2存储所述第一标准信号，并获得标识所述第一标准信号存储位置的第一地址码；具体的，主控模块2中采用FPGA芯片和存储模块，主控模块2和上位机1通信，接收上位机1发送的“第一标签码+第一标准信号”格式信息，并控制第一标准信号存储到存储模块中，存储模块可以为高速缓存器DDR3或DDR4。存储模块存储第一标准信号，并将存储地址返回给控制模块。例如：存储模块可以直接将存储第一标准信号的第一个二进制数的地址(即地址码)返回给控制模块，控制模块使用地址码后，能够将高速缓存模块(即存储模块)中对应地址码的第一标准信号加载出来，供后续使用。
步骤S203：主控模块2接收上位机1发送的对应目标量子程序中的每一个基本量子逻辑门的目标标签码和目标时间码；其中：所述目标标签码为所述基本量子逻辑门对应的所述第一标签码，所述目标时间码用于标识基本量子逻辑门在所述目标量子程序中的执行时序。
具体而言，目标量子程序为待运行的量子运算应用，是单量子逻辑门、两量子逻辑门、多量子逻辑门之一或者组合实现的，任意的多量子逻辑门均可以分解为单量子逻辑门和两量 子逻辑门的组合，因此，可以把目标量子程序分解基本量子逻辑门的组合，由于一基本量子逻辑门具有一固定的第一标签码，同时，各基本量子逻辑门在目标量子程序中出现的位置代表了各基本量子逻辑门的被执行时序，具体为时间码由量子运算应用(即目标量子程序)中对应运算步骤的精确执行时刻转化而来，例如，在运算开始后第40ns起执行的运算步骤的时间码可以记为40。
基于此，可以将目标量子程序转化为一条由第一标签码和时间码表达的指令，具体而言，获取所述目标量子程序中的每一个所述基本量子逻辑门对应的第一标签码，记为目标标签码；根据所述目标量子程序中的每一个所述基本量子逻辑门的执行时序确定每一个所述基本量子逻辑门对应的目标时间码。
上位机负责将一目标量子程序以“目标标签码+目标地址码”的格式发送给设定信号处理设备，即设定信号处理设备接收上位机发送的对应目标量子程序中的每一个基本量子逻辑门的目标标签码和目标时间码。
具体而言，在设定信号处理设备为FPGA芯片，且FPGA芯片按功能可以划分为控制模块和存储模块的硬件设备下，设定信号处理设备接收上位机发送的对应目标量子程序中的每一个基本量子逻辑门的目标标签码和目标时间码，即控制模块接收上位机发送的对应目标量子程序中的每一个基本量子逻辑门的目标标签码和目标时间码。
步骤S204：控制信号生产模块3根据所述目标标签码和所述目标时间码获得所述目标量子程序中的基本量子逻辑门的对应的所述第一标准信号作为待处理信号，并处理所述待处理信号获得量子比特控制信号。
具体而言，由于主控模块2中存储有对应的第一标签码和第一地址码，所以当主控模块2重新接收到目标标签码和目标时间码时，可以通过借助标签码(目标标签码及第一标签码)这个桥梁，迅速找到目标时间码对应的第一地址码，然后调用第一地址码位置处的存储的第一标准信号作为待处理信号，然后处理所述待处理信号获得量子比特控制信号。
在上述整个过程中，根据待测量量子芯片上的量子比特分布情况，设置量子逻辑门集合，并设置与量子逻辑门集合内的基本量子逻辑门的对应的第一标签码和第一标准信号，将第一标签码和第一标准信号存储在主控模块2中，以备后用。量子逻辑门集合的设置需要保证量子逻辑门集合内的基本量子逻辑门可以通过组合实现任意量子程序，本质上即量子逻辑门集合内的基本量子逻辑门可以通过组合实现任意复杂的量子逻辑门，为后期的方便调用提供了参考和基础。然后在针对上位机发送的代表目标量子程序中基本量子逻辑门的目标标签码和目标时间码，信号处理设备借助标签码(目标标签码及第一标签码)这个桥梁，迅速找到目 标时间码对应的第一地址码，然后调用第一地址码位置处的存储的第一标准信号作为待处理信号，然后处理所述待处理信号获得量子比特控制信号，充分利用了上位机1的存储空间，大大减少了设定信号处理设备的容量存储要求，另外，通过预设的可以通过组合实现任意量子程序的基本量子逻辑门的集合(即量子逻辑门集合)，可以准确的实现任意目标量子程序，能够提供多位量子比特测试所需的量子比特控制信号，满足多位量子比特测试需求。
实施例4
结合附图3，本实施例围绕着对所述待处理信号的卷积修正处理，与实施例3的区别在于，为了对所述待处理信号进行卷积修正处理优化改进了主控模块2。
具体而言，所述主控模块2还包括第一创建模块209和第一卷积模块210,量子比特控制信号生成方法在所述存储所述第一标准信号，并获得与所述第一标签码对应的第一地址码之后，还包括所述第一创建模块209创建与所述第一地址码对应的卷积器码，其中，所述卷积器码与第一卷积模块210对应，所述第一卷积模块210用于对所述第一标准信号进行卷积修正处理。
即在主控模块2内部创建第一创建模块209和第一卷积模块210，所述第一创建模块209创建的卷积器码和第一卷积模块210两者对应，两者的设置数量与保存的第一标准信号的数量一致。第一卷积模块210即内嵌卷积函数的模块，卷积函数的具体形式根据需要进行设置即可。在本实施例中，针对待处理的离散数字信号进行卷积处理时，卷积函数的阶数决定了卷积处理的用时长度。
设置卷积器码和第一卷积模块210之后，主控模块2根据所述目标标签码和所述目标时间码获得所述目标量子程序中的基本量子逻辑门的对应的所述第一标准信号作为待处理信号，并处理所述待处理信号获得量子比特控制信号，具体的：
所述主控模块2还包括：
第一设置模块211，用于根据所述目标时间码设置时钟码和时钟触发信号，所述时钟码和所述时钟触发信号一一对应；
第二接收模块212，用于接收所述时钟触发信号；
第六获取模块213，用于获得与所述时钟触发信号对应的时钟码；
第七获取模块214，用于获得与所述时钟码对应的目标时间码；
第八获取模块215，用于获得与所述目标时间码对应的目标标签码；
第九获取模块216，用于获得与所述目标标签码对应的第一地址码，并记为待调用地址 码；
第十获取模块217，用于获得与所述待调用地址码对应的卷积器码记，并为待调用卷积器码；
第一加载模块218，用于将所述待调用地址码对应的第一标准信号加载到所述待调用卷积器码对应的所述卷积器模块中，所述卷积器模块对加载的所述第一标准信号进行卷积修正处理得到卷积处理信号；
第二转化模块219，用于对所述卷积处理信号经数模转化处理以生成所述量子比特控制信号。
依据上述模块，实现了按照目标量子程序中的量子逻辑门的执行顺序生成对应的量子比特控制信号的过程。该过程中，卷积器模块受触发时钟信号控制，触发时钟信号对应目标量子程序中的基本量子逻辑门的执行时序，提高了实现量子比特控制信号的有效性。
在具体实施的时候，为了避免不同的卷积处理模块、数模转换模块的处理延时差异，可以预先根据卷积处理模块中的卷积函数阶数，进行时钟码的补偿，以校正最终经过数模转换模块生成的信号的运行时刻错乱。例如，所有卷积处理模块中的卷积函数最大阶数为10阶，则在该卷积处理模块中执行卷积修正需要耗占10个时钟周期。设置卷积处理模块的时钟码补偿值为10-N，其中N为卷积处理模块中的卷积函数的阶数，则该卷积处理模块将在时钟码+10-N时刻处理对应的第一标准信号，而不是在时钟码时刻开始处理对应的第一标准信号。
更进一步的，所述控制信号生成模块3还包括第二卷积子模块32，所述第二卷积子模块32用于对所述待处理信号进行卷积修正处理。
需要说明的是，在上位机执行对量子运算应用的翻译时，实际上有可能存在同时在不同的量子比特上执行不同的运算步骤(量子逻辑门操作)的情况。换句话说，可能存在多个第一标准信号的第一标签码对应同一个第一时间码的情况。但是，首先，由于FPGA内存在多个并行的卷积处理模块，其次，每个第一标准信号仅对应一个卷积处理模块，最后，同一时刻不可能存在两个完全一样的第一标准信号，因此，将上位机中的量子逻辑门集合的第一标签码将在指令解调模块中转化为第一标签码、第一地址码、第一卷积器码三者的组合，并分别送入并行的卷积处理模块进行处理运算的方法是不会引起冲突的。同时，卷积处理通过提供对量子比特控制信号的修正，它能够有效降低量子芯片执行量子运算应用的系统错误率。
以上依据图式所示的实施例详细说明了本发明的构造、特征及作用效果，以上所述仅为本发明的较佳实施例，但本发明不以图面所示限定实施范围，凡是依照本发明的构想所作的改变，或修改为等同变化的等效实施例，仍未超出说明书与图示所涵盖的精神时，均应在本 发明的保护范围内。

Claims (17)

  1. 一种量子比特控制信号的生成方法，其特征在于，包括：
    接收上位机发送的对应基准量子门集中每一个基本量子逻辑门的第一标签码和第一标准信号，其中，所述基准量子门集包括多个基本量子逻辑门，所述基本量子逻辑门包括单量子逻辑门和/或双量子逻辑门，所述第一标签码用于标识所述基本量子逻辑门，每个所述基本量子逻辑门具有固定的所述第一标签码，所述第一标准信号为实现所述基本量子逻辑门操作的信号；
    存储所述第一标准信号，并获得标识所述第一标准信号存储位置的第一地址码，其中，所述第一地址码与所述第一标签码一一对应；
    接收所述上位机发送的对应目标量子程序中每一个基本量子逻辑门的目标标签码和目标时间码，其中，所述目标标签码为所述目标量子程序中所述基本量子逻辑门对应的所述第一标签码，所述目标时间码用于标识所述目标量子程序中所述基本量子逻辑门在所述目标量子程序中的执行时序；
    根据所述目标标签码和所述目标时间码获得所述目标量子程序中基本量子逻辑门的对应的所述第一标准信号，并将其作为待处理信号；以及
    处理所述待处理信号以生成量子比特控制信号。
  2. 根据权利要求1所述的量子比特控制信号的生成方法，其特征在于，所述接收上位机发送的对应目标量子程序中的每一个基本量子逻辑门的目标标签码和目标时间码，包括：
    分解所述目标量子程序以生成所述基本量子逻辑门的组合；
    获取所述目标量子程序中的每个所述基本量子逻辑门对应的第一标签码，并记为所述目标标签码；以及
    根据所述目标量子程序中的每个所述基本量子逻辑门的执行时序确定每个所述基本量子逻辑门对应的所述目标时间码。
  3. 根据权利要求1所述的量子比特控制信号的生成方法，其特征在于，所述根据所述目标标签码和所述目标时间码获得所述目标量子程序中的基本量子逻辑门对应的所述第一标准信号作为待处理信号，包括：
    根据所述目标时间码设置时钟码和时钟触发信号，其中，所述时钟码和所述时钟触发信号一一对应；
    接收所述时钟触发信号；
    获得与所述时钟触发信号对应的时钟码；
    获得与所述时钟码对应的目标时间码；
    获得与所述目标时间码对应的目标标签码；
    获得与所述目标标签码对应的第一地址码；以及
    获得与所述第一地址码对应的存储的所述第一标准信号作为待处理信号。
  4. 根据权利要求3所述的量子比特控制信号的生成方法，其特征在于，所述根据所述目标时间码设置时钟码和时钟触发信号，包括：
    根据所述时间码和时钟周期确定所述时钟码，其中，所述时钟码等于所述时间码与所述时钟周期的比值，所述时钟周期为处理设备的时钟周期；以及
    根据所述时钟码形成所述时钟触发信号。
  5. 根据权利要求3所述的量子比特控制信号的生成方法，其特征在于，所述处理所述待处理信号获得量子比特控制信号，包括：
    对所述待处理信号进行数字模拟转化，得到量子比特控制模拟信号。
  6. 根据权利要求5所述的量子比特控制信号的生成方法，其特征在于，在所述对待处理信号进行数字模拟转化，得到量子比特控制模拟信号之前，还包括：
    对所述待处理信号进行卷积修正处理。
  7. 根据权利要求1所述的量子比特控制信号的生成方法，其特征在于，在所述存储所述第一标准信号，并获得与所述第一标签码对应的第一地址码之后，还包括：
    创建与所述第一地址码对应的卷积器码，其中，所述卷积器码与预设卷积器模块对应，所述预设卷积器模块用于对所述第一标准信号进行卷积修正处理。
  8. 根据权利要求7所述的量子比特控制信号的生成方法，其特征在于，所述根据所述目标标签码和所述目标时间码获得所述目标量子程序中的基本量子逻辑门的对应的所述第一标准信号作为待处理信号，并处理所述待处理信号获得量子比特控制信号号，包括：
    根据所述目标时间码设置时钟码和时钟触发信号，其中，所述时钟码和所述时钟触发信号一一对应；
    接收所述时钟触发信号；
    获得与所述时钟触发信号对应的时钟码；
    获得与所述时钟码对应的目标时间码；
    获得与所述目标时间码对应的目标标签码；
    获得与所述目标标签码对应的第一地址码，并记为待调用地址码；
    获得与所述待调用地址码对应的卷积器码，并记为待调用卷积器码；
    将所述待调用地址码对应的第一标准信号加载到所述待调用卷积器码所对应的所述卷积器模块中，并通过所述卷积器模块对加载的所述第一标准信号进行卷积修正处理以得到卷积处理信号；以及
    对所述卷积处理信号进行数模转化处理以生成所述量子比特控制信号。
  9. 根据权利要求8所述的量子比特控制信号的生成方法，其特征在于，所述卷积器模块对加载的所述第一标准信号进行卷积修正处理得到卷积处理信号，包括：
    所述卷积器模块通过内嵌的卷积函数对所述第一标准信号进行卷积修正处理以得到消失真信号。
  10. 根据权利要求9所述的量子比特控制信号的生成方法，其特征在于，在所述卷积器模块对加载的所述第一标准信号进行卷积处理得到消失真信号之前，还包括：
    根据所述卷积函数的阶数调整所述卷积器模块对应的时钟码。
  11. 一种量子比特控制信号生成系统，其特征在于，包括上位机、主控模块和控制信号生成模块，其中：
    所述上位机，用于获得并存储量子逻辑门集合和目标量子程序、发送对应量子逻辑门集合中的每一个基本量子逻辑门的第一标签码及第一标准信号至所述主控模块，以及发送对应目标量子程序的每一个基本量子逻辑门对应的目标标签码和目标时间码至所述主控模块，其中，所述量子逻辑门集合指包括多个量子程序的量子逻辑门的集合，每个所述基本量子逻辑门对应有一个唯一的所述第一标签码，所述第一标准信号为实现所述基本量子逻辑门操作的信号，其中，所述目标标签码为所述目标量子程序中的所述基本量子逻辑门对应的第一标签码，所述目标时间码用于标识基本量子逻辑门在所述目标量子程序中的执行时序；
    所述主控模块，用于接收并存储所述第一标签码和所述第一标准信号，并设置与每个所述第一标准信号一一对应的第一地址码，并接收所述目标标签码和所述目标时间码，以及结合所述第一地址码、所述目标标签码和所述目标时间码生成待处理信号；以及
    所述控制信号生成模块，用于接收所述待处理信号并处理所述待处理信号以生成量子比特控制信号。
  12. 根据权利要求11所述的量子比特控制信号生成系统，其特征在于，所述上位机包括第一分解模块、第一获取模块和第一确定模块，其中：
    所述第一分解模块，用于分解所述目标量子程序以生成所述基本量子逻辑门的组合；
    所述第一获取模块，用于获取所述目标量子程序中每个所述基本量子逻辑门对应的所述 第一标签码，并记为所述目标标签码；以及
    所述第一确定模块，用于根据所述目标量子程序中的每个所述基本量子逻辑门的执行时序确定每个所述基本量子逻辑门对应的所述目标时间码。
  13. 根据权利要求11所述的量子比特控制信号生成系统，其特征在于，所述主控模块中包括：
    第二确定模块，用于根据所述时间码和时钟周期确定所述时钟码，其中，所述时钟码等于所述时间码与所述时钟周期的比值，所述时钟周期为处理设备的时钟周期；
    第一处理模块，用于根据所述时钟码形成所述时钟触发信号；
    第一接收模块，用于接收所述时钟触发信号；
    第二获取模块，用于获取与所述时钟触发信号对应的时钟码；
    第三获取模块，用于获取与所述时钟码对应的目标时间码；
    第四获取模块，用于获取与所述目标时间码对应的目标标签码；
    第五获取模块，用于获取与所述目标标签码对应的第一地址码；以及
    第二处理模块，用于获取与所述第一地址码对应的存储的所述第一标准信号作为待处理信号。
  14. 根据权利要求11所述的量子比特控制信号生成系统，其特征在于，所述主控模块包括第一创建模块和第一卷积模块，其中：
    所述第一创建模块，用于创建与所述第一地址码对应的卷积器码，其中，所述卷积器码与预设卷积器模块对应；以及
    所述第一卷积模块，用于对所述第一标准信号进行卷积修正处理。
  15. 根据权利要求14所述的量子比特控制信号生成系统，其特征在于，所述主控模块还包括：
    第一设置模块，用于根据所述目标时间码设置时钟码和时钟触发信号，所述时钟码和所述时钟触发信号一一对应；
    第二接收模块，用于接收所述时钟触发信号；
    第六获取模块，用于获得与所述时钟触发信号对应的时钟码；
    第七获取模块，用于获得与所述时钟码对应的目标时间码；
    第八获取模块，用于获得与所述目标时间码对应的目标标签码；
    第九获取模块，用于获得与所述目标标签码对应的第一地址码，并记为待调用地址码；
    第十获取模块，用于获得与所述待调用地址码对应的卷积器码记，并为待调用卷积器码；
    第一加载模块，用于将所述待调用地址码对应的第一标准信号加载到所述待调用卷积器码对应的所述卷积器模块中，所述卷积器模块对加载的所述第一标准信号进行卷积修正处理得到卷积处理信号；
    第二转化模块，用于对所述卷积处理信号经数模转化处理以生成所述量子比特控制信号。
  16. 根据权利要求11所述的量子比特控制信号生成系统，其特征在于，所述控制信号生成模块包括：
    第一转化子模块，所述第一转化子模块用于对所述待处理信号进行数字模拟转化，以生成所述量子比特控制模拟信号。
  17. 根据权利要求16所述的量子比特控制信号生成系统，其特征在于，所述控制信号生成模块还包括：
    第二卷积子模块，所述第二卷积子模块用于对所述待处理信号进行卷积修正处理。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220156619A1 (en) * 2020-11-17 2022-05-19 International Business Machines Corporation Optically Multiplexed Quantum Control Interface
CN115438790A (zh) * 2021-06-04 2022-12-06 合肥本源量子计算科技有限责任公司 量子态信息处理系统、量子测控系统、量子计算机
CN115902571A (zh) * 2021-08-31 2023-04-04 合肥本源量子计算科技有限责任公司 量子测控系统以及量子计算机

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115220373B (zh) * 2021-04-19 2024-04-05 本源量子计算科技（合肥）股份有限公司 一种量子测控系统、方法以及量子计算机
US11294797B1 (en) * 2021-06-22 2022-04-05 Classiq Technologies LTD. Debugger for quantum computers
WO2023020487A1 (zh) * 2021-08-17 2023-02-23 合肥本源量子计算科技有限责任公司 量子程序与量子芯片的映射方法和量子操作系统及计算机
CN115729753B (zh) * 2021-08-31 2024-04-05 本源量子计算科技（合肥）股份有限公司 一种信号采集装置、测控系统以及量子计算机

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090322374A1 (en) * 2008-05-29 2009-12-31 John Xavier Przybysz Method and apparatus for controlling qubits with singel flux quantum logic
US20150186791A1 (en) * 2010-12-16 2015-07-02 Northrop Grumman Systems Corporation Methods of increasing fidelity of quantum operations
CN105281886A (zh) * 2015-11-19 2016-01-27 中国科学院武汉物理与数学研究所 冷离子量子信息处理器的时序控制信号产生方法及装置
CN109165744A (zh) * 2018-08-15 2019-01-08 合肥本源量子计算科技有限责任公司 一种量子逻辑门操作优化方法
CN109615079A (zh) * 2019-01-30 2019-04-12 合肥本源量子计算科技有限责任公司 一种量子比特控制信号生成系统
CN109683086A (zh) * 2019-01-30 2019-04-26 合肥本源量子计算科技有限责任公司 一种量子比特控制信号生成方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1959708A (zh) 2005-11-01 2007-05-09 沈诗昊 高效量子线路仿真方法与系统
US20090015317A1 (en) 2007-07-13 2009-01-15 Divincenzo David Peter Methods and systems for controlling qubits
US8111083B1 (en) * 2010-12-01 2012-02-07 Northrop Grumman Systems Corporation Quantum processor
CN106301769B (zh) 2015-06-08 2020-04-10 阿里巴巴集团控股有限公司 量子密钥输出方法、存储一致性验证方法、装置及系统
CN109416764B (zh) 2015-11-06 2022-06-03 谷歌有限责任公司 单独量子比特激励控制的设备及方法
EP3414583A4 (en) 2016-02-12 2019-10-30 Yale University METHOD FOR CONTROLLING QUANTUM SYSTEMS AND RELATED SYSTEMS AND METHODS
US10325218B1 (en) * 2016-03-10 2019-06-18 Rigetti & Co, Inc. Constructing quantum process for quantum processors
US10255555B2 (en) 2016-11-10 2019-04-09 Rigetti & Co, Inc. Generating quantum logic control sequences for quantum information processing hardware
WO2018165607A1 (en) * 2017-03-10 2018-09-13 Rigetti & Co, Inc. Event scheduling in a hybrid computing system
CN108154240B (zh) 2017-12-29 2020-07-07 合肥本源量子计算科技有限责任公司 一种低复杂度的量子线路模拟系统

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090322374A1 (en) * 2008-05-29 2009-12-31 John Xavier Przybysz Method and apparatus for controlling qubits with singel flux quantum logic
US20150186791A1 (en) * 2010-12-16 2015-07-02 Northrop Grumman Systems Corporation Methods of increasing fidelity of quantum operations
CN105281886A (zh) * 2015-11-19 2016-01-27 中国科学院武汉物理与数学研究所 冷离子量子信息处理器的时序控制信号产生方法及装置
CN109165744A (zh) * 2018-08-15 2019-01-08 合肥本源量子计算科技有限责任公司 一种量子逻辑门操作优化方法
CN109615079A (zh) * 2019-01-30 2019-04-12 合肥本源量子计算科技有限责任公司 一种量子比特控制信号生成系统
CN109683086A (zh) * 2019-01-30 2019-04-26 合肥本源量子计算科技有限责任公司 一种量子比特控制信号生成方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
YU, XUAN; LU, XIN; XI, ON JUN; SHAO, PEINAN: "Progress Overview of Superconducting Quantum Chip Based on Josephson Junction", COMPUTER ENGINEERING, vol. 44, no. 12, 31 December 2018 (2018-12-31), CN, pages 33 - 38,45, XP009522434 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220156619A1 (en) * 2020-11-17 2022-05-19 International Business Machines Corporation Optically Multiplexed Quantum Control Interface
CN115438790A (zh) * 2021-06-04 2022-12-06 合肥本源量子计算科技有限责任公司 量子态信息处理系统、量子测控系统、量子计算机
CN115438790B (zh) * 2021-06-04 2024-05-07 本源量子计算科技（合肥）股份有限公司 量子态信息处理系统、量子测控系统、量子计算机
CN115902571A (zh) * 2021-08-31 2023-04-04 合肥本源量子计算科技有限责任公司 量子测控系统以及量子计算机
CN115902571B (zh) * 2021-08-31 2024-04-05 本源量子计算科技（合肥）股份有限公司 量子测控系统以及量子计算机

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