WO2020155262A1 - 显示面板的驱动装置、驱动方法及显示设备 - Google Patents

显示面板的驱动装置、驱动方法及显示设备 Download PDF

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Publication number
WO2020155262A1
WO2020155262A1 PCT/CN2019/076212 CN2019076212W WO2020155262A1 WO 2020155262 A1 WO2020155262 A1 WO 2020155262A1 CN 2019076212 W CN2019076212 W CN 2019076212W WO 2020155262 A1 WO2020155262 A1 WO 2020155262A1
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Prior art keywords
sub
pixels
voltage
driving
pixel
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English (en)
French (fr)
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单剑锋
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HKC Co Ltd
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HKC Co Ltd
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Priority to US16/981,689 priority Critical patent/US11132970B2/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • This application relates to the field of liquid crystal panel display, and in particular to a driving device, a driving method and a display device of a display panel.
  • VA-type liquid crystal technology has the advantages of higher production efficiency and lower manufacturing cost.
  • IPS liquid crystal technology it has obvious defects in optical properties. For example, VA-type The LCD panel will have color shift.
  • the brightness of the pixel should ideally change linearly with the change of the voltage, so that the driving voltage of the pixel can accurately represent the gray scale of the pixel, which is reflected by the brightness.
  • VA-type liquid crystal technology when viewing the display surface with a smaller viewing angle (such as front view), the brightness of the pixel can meet the ideal situation, that is, it changes linearly with the voltage; but when viewing the display surface with a larger viewing angle (such as with The display surface is above 160 degrees). Due to the limitation of the VA-type liquid crystal technology principle, the brightness of the pixel shows a rapid saturation with the voltage, and then slowly changes. In this way, under a large viewing angle, the gray scale that the driving voltage should originally present is seriously deviated, that is, color shift appears.
  • An exemplary technique for improving color shift is to subdivide each sub-pixel into a main pixel and a sub-pixel, and then use a relatively high driving voltage to drive the main pixel, and a relatively low driving voltage to drive the sub-pixels. Pixels and sub-pixels display one sub-pixel together. In addition, when the relatively high driving voltage and the relatively low driving voltage drive the main pixel and the sub-pixel, the relationship between the brightness and the corresponding gray scale under the front viewing angle can be maintained unchanged. Generally, in the first half of the grayscale, the main pixel uses a relatively high driving voltage to drive the display, and the sub-pixels do not display.
  • the brightness of the entire sub-pixel is half of the brightness of the main pixel; in the second half of the grayscale, the main pixel uses a relatively high
  • the driving voltage of the sub-pixel drives the display, and the sub-pixels are driven with a relatively low driving voltage.
  • the brightness of the entire sub-pixel is half of the sum of the brightness of the main pixel and the brightness of the sub-pixel.
  • the problem with the above method is that it is necessary to double the number of metal traces and driving devices to drive the sub-pixels, so that the transparent opening area is sacrificed, the light transmittance of the panel is affected, and the cost is also higher.
  • the main purpose of the present application is to provide a driving method, a driving device, a display device, and a storage medium for a display panel, so as to achieve the purpose of improving the visual bias of the current display panel.
  • the present application provides a driving device for a display panel, the display panel includes a display array, and the display array includes pixels arranged in an array, A single pixel includes three sub-pixels arranged in sequence in the row direction. The odd-numbered column pixels and the even-numbered column pixels in the row direction use different gate drive signals.
  • the different gate drive signals are divided into main gate drive signals and main gates.
  • the high-voltage sub-pixel uses a main gate driving signal
  • the low-voltage sub-pixel uses a combined signal of a main gate driving signal and a sub-gate driving signal.
  • the device includes a gate drive element and a source drive element;
  • the gate driving element sends a sub-gate driving signal to the low-voltage sub-pixels arranged in the row direction, and turns on the scanned low-voltage when the sub-gate driving signal scans the low-voltage sub-pixels
  • the sub-gate switch unit corresponding to the sub-pixel, so that the source driving element applies a first source driving signal to the low-voltage sub-pixel; the first source driving signal is the same as the low-voltage sub-pixel
  • the source drive signal of the adjacent previous high-voltage sub-pixel wherein the drive timing of the secondary gate drive signal is the corresponding gate drive timing and source drive timing of the adjacent previous high-voltage sub-pixel ;
  • the gate driving element sends the main gate driving signal to the low-voltage sub-pixels arranged in the row direction, and turns on the low-voltage when the main gate driving signal scans the low-voltage sub-pixels
  • the main gate switch unit corresponding to the sub-pixel, so that the source driving element applies a second source driving signal to the low-voltage sub-pixel, wherein the driving timing of the main gate driving signal is the low.
  • the gate driving element is further configured to simultaneously send a secondary gate driving signal and the main gate driving signal in the row direction to scan the low-voltage sub-pixels.
  • the odd-numbered rows of sub-pixels in the i-th column and the even-numbered rows of sub-pixels in the (i+1)th column share one source line, i is an odd number, and one source line corresponds to one source driving signal; wherein, the i-th column The odd-numbered rows of sub-pixels and the even-numbered rows of sub-pixels in the i+1th column share one source line, i is an odd number, and one source line corresponds to one source driving signal;
  • the gate driving element is further arranged to simultaneously send a secondary gate driving signal and the main gate driving signal in the row direction to scan the low-voltage sub-pixels.
  • the polarity of the driving voltage of the first source driving signal is opposite to the polarity of the driving voltage of the second source driving signal.
  • the polarities of the sub-pixels in each row are the same, and the polarities of the sub-pixels in two adjacent rows are opposite.
  • the present application also proposes a method for driving a display panel, wherein the display panel includes a display array, and the display array includes pixels arranged in an array,
  • a single pixel includes three sub-pixels arranged in sequence in the row direction.
  • the odd-numbered column pixels and the even-numbered column pixels in the row direction use different gate drive signals.
  • the different gate drive signals are divided into main gate drive signals and main gates.
  • the driving method includes:
  • the sub-gate drive signal is sent to the low-voltage sub-pixels set to be in the row direction.
  • the sub-gate drive signal scans the low-voltage sub-pixels in the row direction, the sub-gate corresponding to the scanned low-voltage sub-pixels is turned on.
  • a gate switch unit for applying a first source driving signal to the low-voltage sub-pixel, where the first source driving signal is the source of the previous high-voltage sub-pixel adjacent to the low-voltage sub-pixel
  • a driving signal, wherein the driving timing of the secondary gate driving signal is the gate driving timing and the source driving timing of the adjacent previous high-voltage sub-pixel;
  • the main gate driving signal is sent to the low-voltage sub-pixel in the row direction, and when the main gate driving signal scans to the low-voltage sub-pixel, the main gate corresponding to the low-voltage sub-pixel is turned on
  • the switch unit applies a second source driving signal to the low-voltage sub-pixels, so that adjacent pixels are arranged alternately with high and low voltage intensities, wherein the driving timing of the main gate driving signal is the low-voltage sub-pixel.
  • the sequence of driving the corresponding original gates in the pixel row direction sequentially.
  • the driving method further includes: driving two adjacent sub-pixels in the same column using the preset data driving signal, where the preset data driving signal is the historical driving signal of the two adjacent sub-pixels average of.
  • this embodiment also provides a display device, wherein the display device includes a display panel and a display device of the display panel;
  • the display panel includes a display array, and the display array includes pixels arranged in an array, A single pixel includes three sub-pixels arranged in sequence in the row direction.
  • the odd-numbered column pixels and the even-numbered column pixels in the row direction use different gate drive signals.
  • the different gate drive signals are divided into main gate drive signals and main gates. The combined signal of the driving signal and the sub-gate driving signal;
  • the driving device of the display panel includes a processor and a memory, the memory stores executable instructions, the processor executes the executable instructions, and the executable instructions include:
  • the sub-gate drive signal is sent to the low-voltage sub-pixels set to be in the row direction.
  • the sub-gate drive signal scans the low-voltage sub-pixels in the row direction, the sub-gate corresponding to the scanned low-voltage sub-pixels is turned on.
  • a gate switch unit for applying a first source driving signal to the low-voltage sub-pixel, where the first source driving signal is the source of the previous high-voltage sub-pixel adjacent to the low-voltage sub-pixel
  • a driving signal, wherein the driving timing of the secondary gate driving signal is the gate driving timing and the source driving timing of the adjacent previous high-voltage sub-pixel;
  • the main gate driving signal is sent to the low-voltage sub-pixel in the row direction, and when the main gate driving signal scans to the low-voltage sub-pixel, the main gate corresponding to the low-voltage sub-pixel is turned on
  • the switch unit applies a second source driving signal to the low-voltage sub-pixels, so that adjacent pixels are arranged alternately with high and low voltage intensities, wherein the driving timing of the main gate driving signal is the low-voltage sub-pixel.
  • the sequence of driving the corresponding original gates in the pixel row direction sequentially.
  • the display array of the display panel of the present application has two gate driving circuits for the same row of sub-pixels.
  • the odd-numbered column pixels and the even-numbered columns in the row direction adopt different gate driving signals, and the driving timing of the main gate driving signal is as described above
  • the driving timing of the sub-gate driving signal is the gate driving timing and source driving timing of the adjacent previous high-voltage sub-pixel, which realizes the
  • the sub-pixels on the adjacent two rows of gate drive circuits have different charging capabilities for the same driving voltage, so that adjacent pixels are arranged with high and low voltage intensities interleaved with each other.
  • the human eye will not clearly see the difference between the high-voltage sub-pixels and the low-voltage sub-pixels. Differences, to avoid a decrease in resolution.
  • FIG. 1 is a schematic diagram of an embodiment of a driving device for a display panel of this application
  • FIG. 2 is a schematic flowchart of an embodiment of a method for driving a display panel according to the present application
  • 3a is a schematic diagram of the structure of the first frame of the display array in an embodiment of the application.
  • 3b is a schematic diagram of the structure of the second frame of the display array in an embodiment of the application.
  • FIG. 4 is a schematic diagram of a driving sequence corresponding to the first frame in an embodiment of the application.
  • FIG. 5 is a schematic diagram of a driving sequence corresponding to the second frame in an embodiment of the application.
  • FIG. 1 is a schematic diagram of an embodiment of a driving device for a display panel of this application
  • the display panel includes a display array 100.
  • the display array 100 includes pixels 001 arranged in an array.
  • a single pixel 001 includes three sub-pixels sequentially arranged in the row direction.
  • the odd-numbered columns and even-numbered pixels in the row direction Columns of pixels use different gate drive signals, the different gate drive signals are divided into a main gate drive signal and a combined signal of the main gate drive signal and the sub-gate drive signal, and the drive device includes a gate drive element 300 and source driving element 200;
  • one pixel includes R sub-pixels (red), G sub-pixels (green), and B sub-pixels (blue) that are sequentially arranged in the row direction.
  • the gate driving element 300 sends a sub-gate driving signal to the low-voltage sub-pixels arranged in the row direction, and when the sub-gate driving signal scans to the low-voltage sub-pixels, turns on the scanned sub-pixels.
  • the gate driving element 300 sends the main gate driving signal to the low-voltage sub-pixels arranged in the row direction, and turns on the low-voltage sub-pixels when the main gate driving signal scans the low-voltage sub-pixels.
  • the main gate switch unit corresponding to the voltage sub-pixel, so that the source driving element 200 applies a second source driving signal to the low-voltage sub-pixel, so that the voltage intensities of adjacent pixels in the display array are different , That is, adjacent pixels are arranged alternately with high and low voltage intensity.
  • the driving timing of the main gate driving signal is the timing of sequentially driving the corresponding original gates in the row direction of the low-voltage sub-pixels.
  • the voltage intensity of sub-pixels can be divided into low voltage (such as the sub-pixel marked with L in FIG. 1) and high voltage (such as the sub-pixel marked with H in FIG. 1).
  • the display gray scale of the high-voltage unit sub-pixel is relatively bright, while the display gray scale of the low-voltage unit sub-pixel is relatively dark. As shown in FIG. 1, adjacent pixels are arranged alternately with high and low voltage intensities.
  • the gate driving element 300 of this embodiment simultaneously sends a secondary gate driving signal and the main gate driving signal in the row direction to scan the low-voltage sub-pixels.
  • two gate drive circuits are designed for the same row of sub-pixels.
  • One of the gate drive signals is Vg1_1, which is as shown in Figure 3a/4b.
  • the odd-numbered columns of a row of sub-pixels share the gate driving circuit and driving signal, and the other gate driving signal is Vg2_1, which is the even-numbered row of sub-pixels in the first row.
  • FIG. 4 shows the timing of the first frame Frame1 of the display array.
  • dot inversion (dot inversion)
  • the polarity of the driving voltage of the first source driving signal is opposite to the polarity of the driving voltage of the second source driving signal.
  • the VGd_1 sub-pixel is a high-voltage positive driving signal VG1
  • the corresponding gate driving signal of this sub-pixel is Vg2_1
  • the source charging signal is VG1.
  • the VGd_2 sub-pixel is a low-voltage negative driving signal.
  • the sub-pixel charging is divided into two timings.
  • the sub-pixel is pre-charged with a positive polarity voltage
  • the polarity of VG1’ is opposite to VG1, that is, VG1’ is less than the common electrode voltage Vcom, VG1 is greater than the common electrode voltage Vcom, and
  • the target negative polarity charging signal VG1' becomes VG1". Since the source charging signal changes from positive polarity to positive and negative polarity, the charging is limited by the capacity of the component, and the load limit of pixel voltage polarity switching is very important.
  • the pixel charging affects the low-voltage sub-pixel VGd_2 at the end of the second charging time. The charging voltage at the end of the second charging time cannot completely reach the negative polarity voltage VG1'.
  • the gate driving voltage Vg1_2'switch T2' that controls the positive polarity charging is smaller than the negative polarity charging gate.
  • the electrode driving voltage Vg1_2 switches T2, so that the final negative charging signal VG1" of the low-voltage sub-pixel is relative to the common electrode voltage Vcom
  • VG1 negative charging signal
  • low-voltage sub-pixel charging equivalent voltage
  • the source polarity of the low-voltage sub-pixel is opposite to the source driving polarity of the high-voltage sub-pixel.
  • the charging charge of the low-voltage sub-pixels is equivalently reduced compared to the high-voltage sub-pixels (the driving of the sub-pixels is based on the charge storage amount formed by the difference between the driving voltage and the common electrode voltage).
  • the sub-pixels on the two rows of gate driving circuits have different charging capabilities for the same driving voltage, and the interleaved arrangement of high-voltage pixels and low-voltage pixels on a display array is realized to achieve the purpose of improving the visual bias driving.
  • the timing gate scanning drive signal switching (exchange) of the display arrays of adjacent frames can realize different display array timings with different high and low voltage signal sub-pixels. The naked eye will not clearly see the high-voltage sub-pixels and low-voltage sub-pixels. Difference, there will be no defect of resolution drop. Adjacent pixels in the same row can form high and low equivalent voltage drives to achieve the difference between high-voltage sub-pixel charging and low-voltage sub-pixel charging, thereby achieving the effect of improving color shift.
  • the odd-numbered rows of sub-pixels in the i-th column and the even-numbered rows of sub-pixels in the (i+1)th column share one source line, i is an odd number, and one source line corresponds to one source driving signal.
  • the driving method of the sub-pixel G on the top and the sub-pixel G on the sixth column is described, that is, the driving method is described by taking the pixel on the second column as an example.
  • Vd1, Vd2, and Vd3 represent source lines respectively, and one source line corresponds to one source driving signal.
  • the Vd1 source line in Figure 3a drives the sub-pixel G on the second column and the sub-pixel R on the first column in the second column of pixels, which in turn are the positive polarity subpixel VGd_1, the negative polarity subpixel VRd_2, and the positive polarity.
  • the corresponding gate drive voltage of the pixel VBd_5 and the negative polarity sub-pixel VGd_6 is Vg2_1 , Vg1_2, Vg2_3, Vg1_4, Vg2_5, Vg1_6 Vietnamese, among which Vg2_1, Vg2_3, Vg2_5.
  • the gate switching timing for the source driving signal charging time is T1, Vg1_2, Vg1_4, Vg1_6.
  • the gate switching timing is two periods, one period corresponds to the previous adjacent sub-pixel gate voltage Vg2_1 , Vg2_3, Vg2_5.... Time periods, which are Vg1_2’, Vg1_4’, Vg1_6’...
  • the gate charging voltage time is T2', where T2' is less than the T1/T2 charging period.
  • the other period is Vg1_2, Vg1_4, Vg1_6....
  • the charging time of the gate charging voltage to the source driving signal is T2 and Vg2_1 , Vg2_3, Vg2_5....
  • the gate switching timing can be the same for the source driving signal charging time T1, or the gate switching time of T2 not equal to T1 can be adjusted, which can be adjusted according to the charging capacity of the device.
  • the gate switch is switched to the source driving signal charging timing, that is, Vg2_1 , Vg2_3, Vg2_5.
  • the gate precharge voltage time is T2', where T2' is less than the T1/T2 charging period.
  • the other period is Vg2_1, Vg2_3, Vg2_5...
  • the charging time of the gate voltage to the source drive signal is T2 and Vg1_2, Vg1_4, Vg1_6...
  • the gate switching timing for the source driving signal charging time can be the same as T1, and the gate switching time when T2 is not equal to T1 can be adjusted, and it can be adjusted according to the charging capability of the device.
  • the display arrays of different frames can have different high and low voltage signal sub-pixels with different timings, and the difference between the high-voltage sub-pixels and the low-voltage sub-pixels will not be obvious to the naked eye, and there will be no defects of reduced resolution.
  • Two adjacent sub-pixels in the same column are driven by using the preset data driving signal, and the preset data driving signal is an average value of the historical driving signals of the two adjacent sub-pixels.
  • the time sequence in FIG. 4 can illustrate the positive polarity driving signals VG1, VG2, VG3... and the negative polarity driving signals VG1', VG2', VG3'... of the G row.
  • the timing description of the first frame Frame1 in Figure 4 the source driving signals are sub-pixels VGd_1, VGd_2, VGd_3..., the sub-pixel voltage driving signals are VG1, VG1', VG2, VG2'..., and the gate voltages are sequentially The sub-pixels VGd_1, VGd_2, VGd_3... are turned on and charged by applying voltages.
  • the gate voltage of the high-voltage sub-pixel VGd_1 is Vg2_1
  • the gate voltage of the low-voltage sub-pixel VGd_2 is Vg1_2 and Vg1_2'.
  • the gate voltage is set to: Vg2_1 is turned on and the gate voltage of the low-voltage sub-pixel VGd_2 is Vg1_2' and also turned on at the same time.
  • the gate voltage of the low-voltage sub-pixel VGd_2 is set to: Vg1_2 and Vg1_2' have different gate voltage turn-on times; the gate voltage of the low-voltage sub-pixel VGd_2 is set to: Vg1_2 turn-on time T2 can be the same as the gate of the high-voltage sub-pixel VGd_1
  • the gate precharge voltage of the low-voltage sub-pixel VGd_2 is set to: Vg1_2' when T2 is turned on, is less than the gate voltage Vg2_1 turn-on time T1 of the high-voltage sub-pixel VGd_1, and the gate voltage of the low-voltage sub-pixel VGd_2 is set to Vg1_2 turn-on time T2, that is, T2' ⁇ T1 and T2’ ⁇ T2.
  • the gate switching timing T1 charges the high-voltage sub-pixel VGd_1; the next adjacent low-voltage sub-pixel VGd_2 is charged in two periods, the first is The charging period is the same as the charging gate turn-on timing T1 of the high-voltage sub-pixel VBd_1.
  • the source driving signal is the high-voltage sub-pixel VBd_1.
  • the voltage Vg1_2' precharges the sub-pixel VGd_2.
  • the gate driving voltage Vg1_2' and the gate driving voltage Vg2_1 corresponding to the high-voltage sub-pixel VBd_1 are turned on simultaneously to charge the sub-pixel VBd_1 and pre-charge the sub-pixel VGd_2 At the same time, it is designed that the turn-on time T2' of the gate driving voltage Vg1_2' is smaller than the turn-on time T1/T2 of the gate driving voltage Vg2_1/Vg1_2.
  • the charging voltage of the low-voltage sub-pixel VGd_2 during the first charging time is the positive polarity voltage VB1, and the control gate voltage Vg1_2's charging time T2' is less than the gate voltage Vg1_2 charging time T2, and the low-voltage sub-pixel VGd_2 is charged during the second charging time
  • the voltage is the negative voltage VG1', due to the positive voltage of the precharge VG", the charge control gate voltage Vg1_2 of the second charge time, charge time T2, the sub-pixel VGd_2 is precharged by the positive polarity voltage VB1 is switched to the negative voltage VG1'.
  • the load limit of the pixel voltage polarity switching affects the pixel charging, so that the low-voltage sub-pixel VGd_2 cannot fully reach the negative polarity at the end of the second charging time.
  • the voltage VG1' makes the equivalent charging voltage of the final low-voltage sub-pixel VGd_2 smaller than
  • Adjacent sub-pixels in the same row can form high and low equivalent voltage drives to achieve the difference between high-voltage sub-pixel charging and low-voltage sub-pixel charging, thereby achieving the effect of improving color shift.
  • the timing sequence shown in Fig. 5 can illustrate when the display array sub-pixel polarity and high-low voltage switching timing drive, the sub-pixel positive polarity driving signal VG1, VG2, VG3..., the sub-pixel negative polarity driving signal in G row VG1', VG2', VG3'...
  • Figure 5 Frame 2 The display array timing description of 2, the source driving signals are sub-pixels VGd_1, VGd_2, VGd_3..., and the sub-pixel voltage driving signals are VG1', VG1, VG2', VG2.
  • the gate voltage sequentially changes the sub-pixels VGd_1 , VGd_2, VGd_3...
  • the applied voltage is turned on and charged.
  • the gate voltage of the low-voltage sub-pixel VGd_3 is Vg2_3 and Vg2_3', and the gate voltage of the high-voltage sub-pixel VGd_2 is Vg1_2.
  • the gate voltage of the low voltage sub-pixel VGd_3 is Vg2_3 and the gate voltage of Vg2_3' has a different turn-on time.
  • the gate voltage of the low-voltage sub-pixel VGd_3 is Vg2_3.
  • the gate voltage of the low voltage sub-pixel VGd_3 is Vg2_3’ when T2’ is turned on It is less than the turn-on time T1 of the gate voltage Vg1_2 of the high-voltage sub-pixel VGd_2, that is, T2' ⁇ T1.
  • the gate voltage of the low-voltage sub-pixel VGd_3 is turned on at Vg2_3' and the gate voltage of the high-voltage sub-pixel VGd_2 is turned on at Vg1_2.
  • the next charging step of the adjacent low-voltage sub-pixel VGd_3 is divided into two periods.
  • the first charging period is the same as the previous high-voltage sub-pixel VGd_2 charging gate turn-on timing T1.
  • the source driving signal is the high-voltage sub-pixel VRd_2.
  • the sub-pixel VGd_3 turns on the gate driving voltage Vg2_3' to pre-charge the sub-pixel VGd_3, and the gate driving voltage Vg2_3' corresponds to the high-voltage sub-pixel VRd_2 gate driving voltage Vg1_2 At the same time, turn on to charge the sub-pixel VRd_2 and pre-charge the sub-pixel VGd_3 At the same time, it is designed that the turn-on time T2' of the gate driving voltage Vg2_3' is smaller than the turn-on time T1/T2 of the gate driving voltage Vg1_2/Vg2_3.
  • the charging voltage of the low-voltage sub-pixel VGd_3 during the first charging time is the positive polarity voltage VR1, and the control gate voltage Vg2_3's charging time T2' is less than the gate voltage Vg2_3 charging time T2; the low-voltage sub-pixel VGd_3 is charged during the second charging time
  • the voltage is the negative voltage VG2', Due to the pre-charged positive polarity voltage VG", the charge control gate voltage Vg2_3 of the second charging time is charged for the charging time T2, and the sub-pixel VGd_3 is precharged by the positive polarity voltage VG” is switched to the negative voltage VG2'.
  • the load limitation of the pixel voltage polarity switching affects the pixel charging, so that the low-voltage sub-pixel VGd_3 at the end of the second charging time cannot fully reach the negative electrode.
  • the voltage VG2' makes the equivalent charging voltage of the final low-voltage sub-pixel VGd_3 less than
  • the same row Adjacent sub-pixels can form high and low equivalent voltage drives to achieve the difference between high-voltage sub-pixel charging and low-voltage sub-pixel charging, thereby achieving the effect of improving color shift.
  • FIG. 2 is a schematic flowchart of an embodiment of the method for driving a display panel of the present application.
  • the display panel includes a display array, and the display array includes pixels arranged in an array, A single pixel includes three sub-pixels arranged in sequence in the row direction.
  • the odd-numbered column pixels and the even-numbered column pixels in the row direction use different gate drive signals.
  • the different gate drive signals are divided into main gate drive signals and main gates. The combined signal of the driving signal and the sub-gate driving signal;
  • the driving method includes:
  • Step S10 Send a sub-gate drive signal to the sub-pixels set to be low-voltage in the row direction.
  • the sub-gate drive signal scans to the low-voltage sub-pixels in the row direction, turn on the scanned low-voltage sub-pixels.
  • the corresponding sub-gate switch unit applies a first source driving signal to the low-voltage sub-pixel, and the first source driving signal is the previous high-voltage sub-pixel adjacent to the low-voltage sub-pixel
  • the driving timing of the secondary gate driving signal is the gate driving timing and the source driving timing of the adjacent previous high-voltage sub-pixel;
  • Step S20 Send the main gate drive signal to the low-voltage sub-pixel set in the row direction, and turn on the corresponding low-voltage sub-pixel when the main gate drive signal scans the low-voltage sub-pixel.
  • the main gate switch unit applies a second source driving signal to the low-voltage sub-pixels, so that adjacent pixels are arranged alternately with high and low voltage intensities, wherein the driving timing of the main gate driving signal is the The corresponding original gates in the row direction of the low-voltage sub-pixels are sequentially driven.
  • step S10 and step S20 in this embodiment are performed at the same time, that is, the driving device simultaneously turns on the sub-gate driving signal and the main gate driving signal to perform the operation on the low-voltage sub-pixel. scanning.
  • the polarity of the driving voltage of the first source driving signal is opposite to the polarity of the driving voltage of the second source driving signal.
  • the polarities of the sub-pixels in each row are the same, and the polarities of the sub-pixels in two adjacent rows are opposite.
  • the odd-numbered rows of sub-pixels in the i-th column and the even-numbered rows of sub-pixels in the i+1th column share one source line, i is an odd number, and one source line corresponds to one source. Drive signal.
  • the display array of the display panel of this embodiment has two gate driving circuits for the same row of sub-pixels.
  • the odd-numbered column and the even-numbered column of pixels in the row direction use different gate driving signals, and the driving timing of the main gate driving signal is different.
  • the sequence of driving the original gates corresponding to the row direction of the low-voltage sub-pixels in sequence, and the driving timing of the sub-gate driving signal is the gate driving timing and source driving timing of the adjacent previous high-voltage sub-pixel, which realizes
  • the sub-pixels on two adjacent rows of gate drive circuits have different charging capabilities for the same driving voltage, so that adjacent pixels are arranged with high and low voltage intensities interleaved with each other, so that the human eye will not clearly see the high-voltage sub-pixels and low-voltage sub-pixels To avoid the decrease in resolution.
  • the present application also proposes a display device, which includes the above-mentioned display panel and the above-mentioned driving device;
  • the display panel includes a display array, and the display array includes pixels arranged in an array, A single pixel includes three sub-pixels arranged in sequence in the row direction.
  • the odd-numbered column pixels and the even-numbered column pixels in the row direction use different gate drive signals.
  • the different gate drive signals are divided into main gate drive signals and main gates. The combined signal of the driving signal and the sub-gate driving signal;
  • the display device is provided with a processor, a memory, and a driver program of a display panel that is stored on the memory and can run on the processor, and the driver program of the display panel is configured to implement the display panel as described above.
  • the steps of the driving method are provided with a processor, a memory, and a driver program of a display panel that is stored on the memory and can run on the processor, and the driver program of the display panel is configured to implement the display panel as described above.

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Abstract

本申请公开一种显示面板的驱动装置、驱动方法及显示设备，同一行子像素有两种栅极驱动线路，在行方向上的奇数列像素与偶数列像素采用不同的栅极驱动信号，主栅极驱动信号的驱动时序是所述低电压子像素行方向上对应的原始栅极依序驱动的时序，次栅极驱动信号的驱动时序是相邻的上一高电压子像素对应的栅极驱动时序以及源极驱动时序，实现了相邻两行栅极驱动线路上的子像素对于相同驱动电压的充电能力不同。

Description

显示面板的驱动装置、驱动方法及显示设备
本申请要求于2019年1月30日提交中国专利局、申请号为201910098356.6、发明名称为“显示面板的驱动装置、驱动方法及显示设备”的中国专利申请的优先权，其全部内容通过引用结合在申请中。
技术领域
本申请涉及液晶面板显示领域，尤其涉及一种显示面板的驱动装置、驱动方法及显示设备。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
大尺寸液晶显示面板大多采用负型垂直配向(Vertical Alignment，VA)式或者共平面切换(In Panel Switching，IPS)式。VA型液晶技术相较于IPS液晶技术存在较高的生产效率及低制造成本的优势，但相较于IPS液晶技术，则存在较明显的光学性质缺陷，例如在大视角图像呈现时，VA型液晶显示面板会存在色偏。
在进行图像显示时，像素的亮度在理想情况下应该是随着电压的变化呈现线性的变化，这样像素的驱动电压就能够准确表示像素的灰阶，并通过亮度体现出来。采用VA型液晶技术时，以较小的视角观看显示面时(例如正视)，像素的亮度可以符合理想情况，即随电压呈现线性变化；但当以较大的视角观看显示面时(例如与显示面呈160度以上)，由于VA型液晶技术原理所限，像素的亮度随着电压呈现出快速饱和，然后缓慢变化的情况。这样一来，大视角下，驱动电压原本应该呈现的灰阶，出现了严重的偏离，即出现色偏。
示例性技术用于改善色偏的方式是将每一个子像素都再细分为一个主像素和次像素，然后用相对高的驱动电压驱动主像素，用相对低的驱动电压驱动次像素，主像素和次像素一起显示一个子像素。并且所述相对高的驱动电压和相对低的驱动电压在驱动主像素和次像素时，能够维持正视视角下的亮度与对应灰阶的关系不变。一般地，灰阶的前半段，主像素用相对高的驱动电压驱动显示、次像素不显示，整个子像素的亮度就是主像素亮度的一半；在灰阶的后半段，主像素用相对高的驱动电压驱动显示、次像素用相对低的驱动电压驱动显示，整个子像素的亮度就是主像素的亮度加上次像素的亮度的和的一半。这样合成后，大视角下的亮度曲线更接近理想曲线，因此大视角下的色偏情况有所改善。
但上述方法存在的问题是，需要增加一倍的金属走线和驱动器件来驱动次像素，使可透光开口区牺牲，影响面板透光率，同时成本也更高。
申请内容
本申请的主要目的在于提供一种显示面板的驱动方法、驱动装置、显示设备以及存储介质，旨在实现改善目前显示面板视角色偏的目的。
为实现上述目的， 本申请提出一种显示面板的驱动装置，所述显示面板包括显示阵列，所述显示阵列包括呈阵列排布的像素， 单个像素包括行方向上依次排列的三个子像素，在行方向上的奇数列像素与偶数列像素采用不同的栅极驱动信号，所述不同的栅极驱动信号分为主栅极驱动信号及主栅极驱动信号与次栅极驱动信号的组合信号，所述高电压子像素采用主栅极驱动信号，所述低电压子像素采用主栅极驱动信号与次栅极驱动信号的组合信号，所述驱动装置包括栅极驱动元件和源极驱动元件；
所述栅极驱动元件，对设置为在行方向为低电压子像素发送次栅极驱动信号，在所述次栅极驱动信号扫描到低电压子像素时，打开被扫描到的所述低电压子像素对应的次栅极开关单元，以使得所述源极驱动元件对所述低电压子像素施予第一源极驱动信号；所述第一源极驱动信号为与所述低电压子像素相邻的上一高电压子像素的源极驱动信号，其中，所述次栅极驱动信号的驱动时序是所述相邻的上一高电压子像素对应的栅极驱动时序以及源极驱动时序；
所述栅极驱动元件，对设置为在行方向为低电压子像素发送所述主栅极驱动信号，在所述主栅极驱动信号扫描到所述低电压子像素时，打开所述低电压子像素对应的主栅极开关单元，以使得所述源极驱动元件对所述低电压子像素施予第二源极驱动信号，其中，所述主栅极驱动信号的驱动时序是所述低电压子像素行方向上对应的原始栅极依序驱动的时序。
一实施例中，所述栅极驱动元件，还设置在行方向上同时发送次栅极驱动信号和所述主栅极驱动信号对所述低电压子像素进行扫描。
一实施例中，第i列的子像素奇数行和第i+1列的偶数行子像素公用一条源极线，i为奇数，一条源极线对应一条源极驱动信号；其中，第i列的子像素奇数行和第i+1列的偶数行子像素公用一条源极线，i为奇数，一条源极线对应一条源极驱动信号；
所述栅极驱动元件，还设置在行方向上同时发送次栅极驱动信号和所述主栅极驱动信号对所述低电压子像素进行扫描。
一实施例中，所述第一源极驱动信号的驱动电压的极性与所述第二源极驱动信号的驱动电压的极性相反。
一实施例中，每一行子像素的极性相同，相邻两行子像素的极性相反。
此外，为实现上述目的，本申请还提出一种显示面板的驱动方法，其中，所述显示面板包括显示阵列，所述显示阵列包括呈阵列排布的像素，
单个像素包括行方向上依次排列的三个子像素，在行方向上的奇数列像素与偶数列像素采用不同的栅极驱动信号，所述不同的栅极驱动信号分为主栅极驱动信号及主栅极驱动信号与次栅极驱动信号的组合信号；
所述驱动方法包括:
对设置为在行方向为低电压子像素发送次栅极驱动信号，所述次栅极驱动信号在行方向上扫描到低电压子像素时，打开被扫描到的所述低电压子像素对应的次栅极开关单元，以对所述低电压子像素施予第一源极驱动信号，所述第一源极驱动信号为与所述低电压子像素相邻的上一高电压子像素的源极驱动信号，其中，所述次栅极驱动信号的驱动时序是所述相邻的上一高电压子像素对应的栅极驱动时序以及源极驱动时序；
对设置为在行方向为低电压子像素发送所述主栅极驱动信号，在所述主栅极驱动信号扫描到所述低电压子像素时，打开所述低电压子像素对应的主栅极开关单元，对所述低电压子像素施予第二源极驱动信号，以使得相邻像素互为高低电压强度穿插排列，其中，所述主栅极驱动信号的驱动时序是所述低电压子像素行方向上对应的原始栅极依序驱动的时序。
一实施例中，所述驱动方法还包括：对同列的两个相邻子像素采用所述预设数据驱动信号进行驱动，所述预设数据驱动信号为相邻的两个子像素的历史驱动信号的平均值。
此外，为实现上述目的，本实施例还提出一种显示设备，其中，所述显示设备包括显示面板、以及所述显示面板的显示装置；
所述显示面板包括显示阵列，所述显示阵列包括呈阵列排布的像素， 单个像素包括行方向上依次排列的三个子像素，在行方向上的奇数列像素与偶数列像素采用不同的栅极驱动信号，所述不同的栅极驱动信号分为主栅极驱动信号及主栅极驱动信号与次栅极驱动信号的组合信号；
所述显示面板的驱动装置包括处理器和存储器，所述存储器存储可执行指令，所述处理器执行所述可执行指令，所述可执行指令包括:
对设置为在行方向为低电压子像素发送次栅极驱动信号，所述次栅极驱动信号在行方向上扫描到低电压子像素时，打开被扫描到的所述低电压子像素对应的次栅极开关单元，以对所述低电压子像素施予第一源极驱动信号，所述第一源极驱动信号为与所述低电压子像素相邻的上一高电压子像素的源极驱动信号，其中，所述次栅极驱动信号的驱动时序是所述相邻的上一高电压子像素对应的栅极驱动时序以及源极驱动时序；
对设置为在行方向为低电压子像素发送所述主栅极驱动信号，在所述主栅极驱动信号扫描到所述低电压子像素时，打开所述低电压子像素对应的主栅极开关单元，对所述低电压子像素施予第二源极驱动信号，以使得相邻像素互为高低电压强度穿插排列，其中，所述主栅极驱动信号的驱动时序是所述低电压子像素行方向上对应的原始栅极依序驱动的时序。
本申请的显示面板的显示阵列同一行子像素有两种栅极驱动线路，在行方向上的奇数列像素与偶数列像素采用不同的栅极驱动信号，主栅极驱动信号的驱动时序是所述低电压子像素行方向上对应的原始栅极依序驱动的时序，次栅极驱动信号的驱动时序是相邻的上一高电压子像素对应的栅极驱动时序以及源极驱动时序，实现了相邻两行栅极驱动线路上的子像素对于相同驱动电压的充电能力不同，以使得相邻像素互为高低电压强度穿插排列，人肉眼不会明显看到高电压子像素与低电压子像素的差异，避免解析度下降。
附图说明
图1为本申请一种显示面板的驱动装置的一实施例示意图；
图2为本申请显示面板的驱动方法一实施例的流程示意图；
图3a为本申请一实施例中的显示阵列第一帧的结构示意图；
图3b为本申请一实施例中的显示阵列第二帧的结构示意图；
图4为本申请一实施例中所述第一帧对应的驱动时序示意图；
图5为本申请一实施例中所述第二帧对应的驱动时序示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
下面结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。作为制造技术和 / 或公差的结果，可以预期图示形状的变化。因此，本申请的实施例不应解释为限于在此所示区域的特定形状，而是包括例如制造所致的形状上的偏差。因此，如图所示的区域本质上是示意性的，并且它们的形状不旨在示出区域的精确形状，并且不旨在限制实施例的范围。
在本申请的描述中，需要理解的是，术语 “ 竖向”、 “ 横向”、 “ 上”、 “ 下”、 “ 左”、 “ 右”、“ 水平”、 “ 两侧”、 “ 底”、 “中”“ 内”、等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，术语 “ 第一”、 “ 第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。本申请的描述中，除非另有说明， “ 多条”、“ 多个”的含义是两个（两条）或两个（两条）以上。
另外，术语 “ 包括”及其任何变形，意图在于覆盖不排他的包含。
参考图1，图1为本申请一种显示面板的驱动装置的一实施例示意图；,
本实施例中，所述显示面板包括显示阵列100，所述显示阵列100包括呈阵列排布的像素001，单个像素001包括行方向上依次排列的三个子像素，在行方向上的奇数列像素与偶数列像素采用不同的栅极驱动信号，所述不同的栅极驱动信号分为主栅极驱动信号及主栅极驱动信号与次栅极驱动信号的组合信号，所述驱动装置包括栅极驱动元件300和源极驱动元件200；
具体地，如图1所示，在一个像素中包括行方向上依次排列的R子像素（红）、G子像素（绿）、B子像素（蓝）。
相应地，所述栅极驱动元件300，对设置为在行方向为低电压子像素发送次栅极驱动信号，在所述次栅极驱动信号扫描到低电压子像素时，打开被扫描到的所述低电压子像素对应的次栅极开关单元，以使得所述源极驱动元件200对所述低电压子像素施予第一源极驱动信号，所述第一源极驱动信号为与所述低电压子像素相邻的上一高电压子像素的源极驱动信号，其中，所述次栅极驱动信号的驱动时序是所述相邻的上一高电压子像素对应的栅极驱动时序以及源极驱动时序；
所述栅极驱动元件300，对设置为在行方向为低电压子像素发送所述主栅极驱动信号，在所述主栅极驱动信号扫描到所述低电压子像素时，打开所述低电压子像素对应的主栅极开关单元，以使得所述源极驱动元件200对所述低电压子像素施予第二源极驱动信号，进而使得所述显示阵列中相邻像素的电压强度不同，即相邻像素互为高低电压强度穿插排列。其中，所述主栅极驱动信号的驱动时序是所述低电压子像素行方向上对应的原始栅极依序驱动的时序。
需要说明的是，子像素的电压强度可分为低电压（如图1中带有L标识的子像素）、以及高电压（如图1中带有H标识的子像素）。
可理解的是，高电压单位子像素的显示灰阶比较亮，而低电压单位子像素的显示灰阶比较暗，如图1所示，相邻像素互为高低电压强度穿插排列。
在具体实现中，本实施例的栅极驱动元件300在行方向上同时发送次栅极驱动信号和所述主栅极驱动信号对所述低电压子像素进行扫描。
考图3a所示，为了实现图1中像素高低电压穿插驱动排列方式，同一行子像素同时设计两种栅极驱动电路，其中一栅极驱动信号为Vg1_1即为如附图3a/4b中第一行子像素的奇数列像素共栅极驱动线路与驱动信号，另一栅极驱动信号为Vg2_1即为第一行子像素的偶数行像素共栅极驱动线路与驱动信号。
同时，参考图4，图4为显示阵列第一帧Frame1的时序，本实施例为采用点反转（dot inversion）的源极驱动方式，所述第一源极驱动信号的驱动电压的极性与所述第二源极驱动信号的驱动电压的极性相反。VGd_1子像素为高电压正极性驱动信号VG1，该子像素对应栅极驱动信号为Vg2_1，源极充电信号为VG1。VGd_2子像素为低电压负极性驱动信号，该子像素充电分成两个时序，首先一个时序对应栅极驱动信号为Vg1_2’，源极充电信号则为上一子像素VBd_1正极性充电电压Vd2=VB1，该子像素预先充电正极性电压，次一个时序对应栅极驱动信号为Vg1_2，源极充电信号则为该低电压子像素VGd_2的负极性充电电压Vd2=VG1’ ，其中VG1’的极性与VG1相反，即VG1’小于共电极电压Vcom， VG1大于共电极电压Vcom，且|VG1-Vcom|=|VG1’-Vcom|。透过预先正极性充电，让目标负极性充电信号VG1’变成VG1”，由于源极充电信号由正极性变成正负性，由于充电受到元件能力限制，画素电压极性切换的负载限制对于画素充电造成影响，使得低电压子像素VGd_2于第二充电时间最后的充电电压无法完全达到负极性电压VG1’，控制该正极性充电的栅极驱动电压Vg1_2’开关T2’小于负极性充电的栅极驱动电压Vg1_2开关T2，使得该低电压子像素最后的负极性充电信号VG1”相对共电极电压Vcom 有一个差值，即|VG1”-Vcom|小于|VG1’-Vcom|，即该低电压子像素充电等效电压|VG1”-Vcom|小于高电压子像素充电等效电压|VG1-Vcom|。该低电压子像素的源极极性与高电压子像素源极驱动的极性相反。使得低电压子像素的充电电荷相较于高电压子像素等效下降（子像素的驱动是看驱动电压与共电极电压压差所形成的充电电荷储存量）。两行栅极驱动线路上得子像素对于相同驱动电压得充电能力不同，实现了一阵显示阵列上高电压像素及低电压像素穿插排列得驱动达到改善视角色偏驱动的目的。相邻帧的显示阵列的时序栅极扫描驱动信号切换(互换)，可以实现不同显示阵列时序不同高低电压信号子像素，肉眼就不会明显可以见到高电压子像素与低电压子像素的差异，不会有解析度下降的缺陷。同一行相邻像素便能形成高低等效电压驱动，来达到高电压子像素充电与低电压子像素充电的差异，进而达成色偏改善的效果。
可选地，在一实施例中，第i列的子像素奇数行和第i+1列的偶数行子像素公用一条源极线，i为奇数，一条源极线对应一条源极驱动信号。
需要说明的是，第i列的子像素和第i+1列的子像素互为相邻的两列子像素，本实施例设i=1，对第4列上的子像素R、第5列上的子像素G、以及第6列上的子像素G的驱动方法进行表述，即以第二列上的像素为例来描述驱动方法。
在具体实现中，在图3a或图3b中，Vd1、Vd2、Vd3分别表示源极线，一条源极线对应一条源极驱动信号。以图3a为例，图3a中的Vd1源极线驱动第二列像素中第二列上的子像素G和第一列子上像素R，依序为正极性子像素VGd_1、负极性子像素VRd_2、正极性子像素VGd_3、负极性子像素VRd_4、正极性子像素VGd_5、负极性子像素VRd_6，对应的栅极驱动电压分别对应为Vg2_1 、Vg1_2、 Vg2_3 、Vg1_4、 Vg2_5 、Vg1_6…..；Vd2源极线驱动第二列上的子像素G及第三列子上像素B子像素正极性子像素VBd_1、负极性子像素VGd_2、正极性子像素VBd_3、负极性子像素VGd_4、正极性子像素VBd_5、负极性子像素VGd_6对应的栅极驱动电压为Vg2_1 、Vg1_2、 Vg2_3 、Vg1_4、 Vg2_5 、Vg1_6…..，其中Vg2_1 、Vg2_3、 Vg2_5…..
栅极开关时序对于源极驱动信号充电时间为T1，Vg1_2、Vg1_4、Vg1_6…..，栅极开关时序两时段，一时段为对应于上一相邻子像素栅极电压Vg2_1 、Vg2_3、 Vg2_5….时段，该时段Vg1_2’、Vg1_4’、Vg1_6’……。
栅极充电电压时间为T2’，其中T2’小于T1/T2充电周期。另一个时段为Vg1_2、Vg1_4、Vg1_6…..栅极充电电压对于源极驱动信号充电时间为T2与Vg2_1 、Vg2_3、 Vg2_5….栅极开关时序对于源极驱动信号充电时间为T1可以相同，亦可以调整T2不等于T1的栅极开关时间，可以依照元件充电能力作调整。
可选地，参考图5，随着相邻两帧显示阵列对应的图像Frame1和Frame2的驱动信号的反转，栅极开关对于源极驱动信号充电时序切换，亦即Vg2_1 、Vg2_3、 Vg2_5…..栅极开关时序两时段，一个时段为对应于上一相邻子像素源极驱动信号时段，该时段Vg2_1’ 、Vg2_3’、 Vg2_5’…栅极预充电电压时间为T2’，其中T2’小于T1/T2充电周期。另一时段个为Vg2_1 、Vg2_3、 Vg2_5…栅极电压对于源极驱动信号充电时间为T2与Vg1_2、Vg1_4、Vg1_6…
栅极开关时序对于源极驱动信号充电时间可以与T1可以相同，可以调整T2不等于T1的栅极开关时间，可以依照元件充电能力作调整。这样可以实现不同帧的显示阵列的时序不同高低电压信号子像素，肉眼就不会明显可以见到高电压子像素与低电压子像素的差异，不会有解析度下降的缺陷。
对同列的两个相邻子像素采用所述预设数据驱动信号进行驱动，所述预设数据驱动信号为相邻的两个子像素的历史驱动信号的平均值。
其中G行的子像素VGd_1与VGd_2等效电压分别以正极性驱动电压Vd1=VG1与负极性驱动电压Vd2=VG1’ 驱动， 正极性驱动电压VG1与负极性驱动电压VG1’则可选为原显示阵列像素信号Gd1与Gd2信号的平均信号(以 8 bit驱动信号来说为0~255信号)，亦即G1=( Gd1+Gd2)/2，G1信号对应的正极性驱动电压VG1及负极性驱动电压VG1’。VGd_3与VGd_4等效电压分别以正极性驱动电压Vd1=VG2与负极性驱动电压Vd2=VG2’驱动，则可选为原显示阵列像素信号Gd3与Gd4信号的平均信号(以 8 bit驱动信号来说为0~255信号)，亦即G2=( Gd3+Gd4)/2，G2信号对应的正极性驱动电压VG2及负极性驱动电压VG2’。
进一步的，图4中的时序可以说明G行的子像素正极性驱动信号VG1、VG2、VG3…..，子像素负极性动信号VG1’、VG2’、VG3’…。图4中第一帧Frame1的时序说明，源极驱动信号依序为子像素VGd_1、VGd_2、VGd_3…，子像素电压驱动信号为VG1、VG1’、VG2、VG2’…..，栅极电压依次将子像素VGd_1、VGd_2、VGd_3…施予电压开启并充电，高电压子像素VGd_1的栅极电压为Vg2_1，低电压子像素VGd_2的栅极电压为Vg1_2与Vg1_2’，其中高电压子像素VGd_1的栅极电压设置为：Vg2_1开启同时低电压子像素VGd_2的栅极电压为Vg1_2’亦同时开启。低电压子像素VGd_2的栅极电压设置为：Vg1_2与Vg1_2’的栅极电压开启时间不同；低电压子像素VGd_2的栅极电压设置为：Vg1_2开启时间T2可以同高电压子像素VGd_1的栅极电压Vg1开启时间T1，亦即T1=T2，亦可以调整T2不等于T1的栅极开关时间，可以依照元件充电能力作调整。低电压子像素VGd_2的栅极预充电电压设置为：Vg1_2’开启时T2’小于高电压子像素VGd_1的栅极电压Vg2_1开启时间T1，以及低电压子像素VGd_2的栅极电压设置为Vg1_2开启时间T2，亦即T2’<T1且 T2’<T2。
高电压子像素VGd_1充电为正极性源极驱动信号Vd1=VG1与Vg2_1栅极开关时序T1对于高电压子像素VGd_1充电；次一相邻低电压子像素VGd_2充电步骤分两个时段，第一个充电时段为同上一高电压子像素VBd_1充电栅极开启时序T1，此时的源极驱动信号为高电压子像素VBd_1充电为正极性源极驱动信号Vd2=VB1时，子像素VGd_2开启栅极驱动电压Vg1_2’对子像素VGd_2进行预充电，该栅极驱动电压Vg1_2’与相应于高电压子像素VBd_1栅极驱动电压Vg2_1同时开启对对子像素VBd_1进行充电，并对子像素VGd_2进行预充电 ，同时设计栅极驱动电压Vg1_2’的开启时T2’ 小于栅极驱动电压Vg2_1/Vg1_2开启时间T1/T2。
第二个充电时段则是负极性驱动电压Vd2=VG1’与Vg1_2的栅极开关时序T2对子像素VGd_2进行充电。低电压子像素VGd_2于第一充电时间的充电电压为正极性电压VB1，控制栅极电压Vg1_2’充电时间T2’小于栅极电压Vg1_2充电时间T2，低电压子像素VGd_2于第二充电时间的充电电压为负极性电压VG1’，由于预充电正极性电压 VG”，再第二充电时间的充电控制栅极电压Vg1_2充电时间T2，子像素VGd_2由预充电正极性电压 VB1切换成负极性电压VG1’，由于充电受到元件能力限制，画素电压极性切换的负载限制对于画素充电造成影响，使得低电压子像素VGd_2于第二充电时间最后的充电电压无法完全达到负极性电压VG1’，使得最后低电压子像素VGd_2的等效充电电压小于|VG1’-Vcom|，确保低电压子像素VGd_2充电电压为小于子像素VGd_1高电压子像素|VG1-Vcom|。同一行相邻子像素便能形成高低等效电压驱动，来达到高电压子像素充电与低电压子像素充电的差异，进而达成色偏改善的效果。
可理解的是，附图5时序能够说明当显示阵列子像素极性以及高低电压切换的时序驱动，G行的子像素正极性驱动信号VG1、VG2、VG3…..，子像素负极性动信号VG1’、VG2’、VG3’…。附图5 第二帧Frame 2的显示阵列时序说明，源极驱动信号依序为子像素VGd_1、VGd_2、VGd_3…，子像素电压驱动信号为VG1’、VG1、VG2’、VG2…..，栅极电压依次将子像素VGd_1、VGd_2、VGd_3…施予电压开启并充电，低电压子像素VGd_3的栅极电压为Vg2_3与Vg2_3’，高电压子像素VGd_2的栅极电压为Vg1_2。低电压子像素VGd_3的栅极电压为Vg2_3与Vg2_3’的栅极电压开启时间不同，低电压子像素VGd_3的栅极电压为Vg2_3开启时间T2同高电压子像素VGd_2的栅极电压Vg1_2开启时间T1，亦即T1=T2，亦可以调整T2不等于T1的栅极开关时间，可以依照元件充电能力作调整。低电压子像素VGd_3的栅极电压为Vg2_3’开启时T2’ 则小于高电压子像素VGd_2的栅极电压Vg1_2开启时间T1，亦即T2’<T1。其中低电压子像素VGd_3的栅极电压为Vg2_3’开启同时高电压子像素VGd_2的栅极电压为Vg1_2开启。
相应地，高电压子像素VGd_2充电为正极性源极驱动信号Vd2=VG1与Vg1_2栅极开关时序T1对于高电压子像素VGd_2充电。次一相邻低电压子像素VGd_3充电步骤分两个时段，第一个充电时段为同上一高电压子像素VGd_2充电栅极开启时序T1，此时的源极驱动信号为高电压子像素VRd_2充电为正極性源极驱动信号Vd1=VR1时，子像素VGd_3开启栅极驱动电压Vg2_3’对子像素VGd_3进行预充电,该栅极驱动电压Vg2_3’与相应于高电压子像素VRd_2栅极驱动电压Vg1_2同时开启对对子像素VRd_2进行充电，并对子像素VGd_3进行预充电 ，同时设计栅极驱动电压Vg2_3’的开启时T2’ 小于栅极驱动电压Vg1_2/Vg2_3开启时间T1/T2。
第二个充电时段则是负极性驱动电压Vd1=VG2’与Vg2_3的栅极开关时序T2对子像素VGd_3进行充电。低电压子像素VGd_3于第一充电时间的充电电压为正极性电压VR1，控制栅极电压Vg2_3’充电时间T2’小于栅极电压Vg2_3充电时间T2;低电压子像素VGd_3于第二充电时间的充电电压为负极性电压VG2’， 由于预充电正极性电压 VG”，再第二充电时间的充电控制栅极电压Vg2_3充电时间T2，子像素VGd_3由预充电正极性电压 VG”切换成负极性电压VG2’，由于充电受到元件能力限制，画素电压极性切换的负载限制对于画素充电造成影响，使得低电压子像素VGd_3于第二充电时间最后的充电电压无法完全达到负极性电压VG2’，使得最后低电压子像素VGd_3的等效充电电压小于|VG2’-Vcom|，确保低电压子像素VGd_3充电电压为小于子像素VGd_4高电压子像素|VG2-Vcom|。同一行相邻子像素便能形成高低等效电压驱动，来达到高电压子像素充电与低电压子像素充电的差异，进而达成色偏改善的效果。
此外，参考图2，本申请还提出一种显示面板的驱动方法，图2为本申请显示面板的驱动方法一实施例的流程示意图。
本实施例中，所述显示面板包括显示阵列，所述显示阵列包括呈阵列排布的像素， 单个像素包括行方向上依次排列的三个子像素，在行方向上的奇数列像素与偶数列像素采用不同的栅极驱动信号，所述不同的栅极驱动信号分为主栅极驱动信号及主栅极驱动信号与次栅极驱动信号的组合信号；
相应地，所述驱动方法包括:
步骤S10：对设置为在行方向为低电压子像素发送次栅极驱动信号,所述次栅极驱动信号在行方向上扫描到低电压子像素时，打开被扫描到的所述低电压子像素对应的次栅极开关单元，以对所述低电压子像素施予第一源极驱动信号，所述第一源极驱动信号为与所述低电压子像素相邻的上一高电压子像素的源极驱动信号，其中，所述次栅极驱动信号的驱动时序是所述相邻的上一高电压子像素对应的栅极驱动时序以及源极驱动时序；
步骤S20：对设置为在行方向为低电压子像素发送所述主栅极驱动信号，在所述主栅极驱动信号扫描到所述低电压子像素时，打开所述低电压子像素对应的主栅极开关单元，对所述低电压子像素施予第二源极驱动信号，以使得相邻像素互为高低电压强度穿插排列，其中，所述主栅极驱动信号的驱动时序是所述低电压子像素行方向上对应的原始栅极依序驱动的时序。
需要说明的是，本实施例中的步骤S10和步骤S20是同时进行的，即所述驱动装置同时开启所述次栅极驱动信号和所述主栅极驱动信号对所述低电压子像素进行扫描。所述第一源极驱动信号的驱动电压的极性与所述第二源极驱动信号的驱动电压的极性相反。如图3a或图3b所示，每一行子像素的极性相同，相邻两行子像素的极性相反。
在一实施例中，参考图3a或图3b，第i列的子像素奇数行和第i+1列的偶数行子像素公用一条源极线，i为奇数，一条源极线对应一条源极驱动信号。
本实施例的显示面板的驱动方法具体实施方式请参照上述显示面板的驱动装置的实施例，本实施例在此不予赘述。
本实施例的显示面板的显示阵列同一行子像素有两种栅极驱动线路，在行方向上的奇数列像素与偶数列像素采用不同的栅极驱动信号，主栅极驱动信号的驱动时序是所述低电压子像素行方向上对应的原始栅极依序驱动的时序，次栅极驱动信号的驱动时序是相邻的上一高电压子像素对应的栅极驱动时序以及源极驱动时序，实现了相邻两行栅极驱动线路上的子像素对于相同驱动电压的充电能力不同，以使得相邻像素互为高低电压强度穿插排列，人肉眼不会明显看到高电压子像素与低电压子像素的差异，避免解析度下降。
此外，本申请还提出一种显示设备，所述显示设备包括如上所述的显示面板、以及如上所述的驱动装置；
所述显示面板包括显示阵列，所述显示阵列包括呈阵列排布的像素， 单个像素包括行方向上依次排列的三个子像素，在行方向上的奇数列像素与偶数列像素采用不同的栅极驱动信号，所述不同的栅极驱动信号分为主栅极驱动信号及主栅极驱动信号与次栅极驱动信号的组合信号；
所述显示装置设有处理器、存储器以及存储在所述存储器上并可在所述处理器上运行的显示面板的驱动程序，所述显示面板的驱动程序配置为实现如上所述的显示面板的驱动方法的步骤。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的构思下，利用本申请说明书及附图内容所作的等效结构变化，或直接/间接运用在其他相关技术领域均包括在本申请的专利保护范围内。

Claims (20)

  1. 一种显示面板的驱动装置，其中，所述显示面板包括显示阵列，所述显示阵列包括呈阵列排布的像素， 单个像素包括行方向上依次排列的三个子像素，在行方向上的奇数列像素与偶数列像素采用不同的栅极驱动信号，所述不同的栅极驱动信号分为主栅极驱动信号及主栅极驱动信号与次栅极驱动信号的组合信号，所述高电压子像素采用主栅极驱动信号，所述低电压子像素采用主栅极驱动信号与次栅极驱动信号的组合信号，所述驱动装置包括栅极驱动元件和源极驱动元件；
    所述栅极驱动元件，对设置为在行方向为低电压子像素发送次栅极驱动信号，在所述次栅极驱动信号扫描到低电压子像素时，打开被扫描到的所述低电压子像素对应的次栅极开关单元，以使得所述源极驱动元件对所述低电压子像素施予第一源极驱动信号；所述第一源极驱动信号为与所述低电压子像素相邻的上一高电压子像素的源极驱动信号，其中，所述次栅极驱动信号的驱动时序是所述相邻的上一高电压子像素对应的栅极驱动时序以及源极驱动时序；以及
    所述栅极驱动元件，对设置为在行方向为低电压子像素发送所述主栅极驱动信号，在所述主栅极驱动信号扫描到所述低电压子像素时，打开所述低电压子像素对应的主栅极开关单元，以使得所述源极驱动元件对所述低电压子像素施予第二源极驱动信号，其中，所述主栅极驱动信号的驱动时序是所述低电压子像素行方向上对应的原始栅极依序驱动的时序。
  2. 根据权利要求1的所述驱动装置，其中，
    所述栅极驱动元件，还设置在行方向上同时发送次栅极驱动信号和所述主栅极驱动信号对所述低电压子像素进行扫描。
  3. 根据权利要求1所述的驱动装置，其中，第i列的子像素奇数行和第i+1列的偶数行子像素公用一条源极线，i为奇数，一条源极线对应一条源极驱动信号。
  4. 根据权利要求1的所述驱动装置，其中，第i列的子像素奇数行和第i+1列的偶数行子像素公用一条源极线，i为奇数，一条源极线对应一条源极驱动信号；
    所述栅极驱动元件，还设置在行方向上同时发送次栅极驱动信号和所述主栅极驱动信号对所述低电压子像素进行扫描。
  5. 根据权利要求4所述的驱动装置，其中，所述第一源极驱动信号的驱动电压的极性与所述第二源极驱动信号的驱动电压的极性相反。
  6. 根据权利要求5所述的驱动装置，其中，每一行子像素的极性相同，相邻两行子像素的极性相反。
  7. 一种显示面板的驱动方法，其中，所述显示面板包括显示阵列，所述显示阵列包括呈阵列排布的像素，
    单个像素包括行方向上依次排列的三个子像素，在行方向上的奇数列像素与偶数列像素采用不同的栅极驱动信号，所述不同的栅极驱动信号分为主栅极驱动信号及主栅极驱动信号与次栅极驱动信号的组合信号；
    所述驱动方法包括:
    对设置为在行方向为低电压子像素发送次栅极驱动信号，所述次栅极驱动信号在行方向上扫描到低电压子像素时，打开被扫描到的所述低电压子像素对应的次栅极开关单元，以对所述低电压子像素施予第一源极驱动信号，所述第一源极驱动信号为与所述低电压子像素相邻的上一高电压子像素的源极驱动信号，其中，所述次栅极驱动信号的驱动时序是所述相邻的上一高电压子像素对应的栅极驱动时序以及源极驱动时序；以及
    对设置为在行方向为低电压子像素发送所述主栅极驱动信号，在所述主栅极驱动信号扫描到所述低电压子像素时，打开所述低电压子像素对应的主栅极开关单元，对所述低电压子像素施予第二源极驱动信号，以使得相邻像素互为高低电压强度穿插排列，其中，所述主栅极驱动信号的驱动时序是所述低电压子像素行方向上对应的原始栅极依序驱动的时序。
  8. 根据权利要求7所述的方法，其中，同时开启所述次栅极驱动信号和所述主栅极驱动信号对所述低电压子像素进行扫描。
  9. 根据权利要求8所述的驱动方法，其中，第i列的子像素奇数行和第i+1列的偶数行子像素公用一条源极线，i为奇数，一条源极线对应一条源极驱动信号。
  10. 根据权利要求7所述的驱动方法，其中，同时开启所述次栅极驱动信号和所述主栅极驱动信号对所述低电压子像素进行扫描；第i列的子像素奇数行和第i+1列的偶数行子像素公用一条源极线，i为奇数，一条源极线对应一条源极驱动信号。
  11. 根据权利要求10所述的驱动方法，其中，所述第一源极驱动信号的驱动电压的极性与所述第二源极驱动信号的驱动电压的极性相反。
  12. 根据权利要求11所述的驱动方法，其中，每一行子像素的极性相同，相邻两行子像素的极性相反。
  13. 根据权利要求7所述的驱动方法，其中，所述驱动方法还包括：
    对同列的两个相邻子像素采用所述预设数据驱动信号进行驱动，所述预设数据驱动信号为相邻的两个子像素的历史驱动信号的平均值。
  14. 一种显示设备，其中，所述显示设备包括显示面板、以及所述显示面板的显示装置；
    所述显示面板包括显示阵列，所述显示阵列包括呈阵列排布的像素， 单个像素包括行方向上依次排列的三个子像素，在行方向上的奇数列像素与偶数列像素采用不同的栅极驱动信号，所述不同的栅极驱动信号分为主栅极驱动信号及主栅极驱动信号与次栅极驱动信号的组合信号。
  15. 根据权利要求14的显示设备，其中，所述显示面板的驱动装置包括处理器和存储器，所述存储器存储可执行指令，所述处理器执行所述可执行指令，所述可执行指令包括:
    对设置为在行方向为低电压子像素发送次栅极驱动信号，所述次栅极驱动信号在行方向上扫描到低电压子像素时，打开被扫描到的所述低电压子像素对应的次栅极开关单元，以对所述低电压子像素施予第一源极驱动信号，所述第一源极驱动信号为与所述低电压子像素相邻的上一高电压子像素的源极驱动信号，其中，所述次栅极驱动信号的驱动时序是所述相邻的上一高电压子像素对应的栅极驱动时序以及源极驱动时序；
    对设置为在行方向为低电压子像素发送所述主栅极驱动信号，在所述主栅极驱动信号扫描到所述低电压子像素时，打开所述低电压子像素对应的主栅极开关单元，对所述低电压子像素施予第二源极驱动信号，以使得相邻像素互为高低电压强度穿插排列，其中，所述主栅极驱动信号的驱动时序是所述低电压子像素行方向上对应的原始栅极依序驱动的时序。
  16. 根据权利要求15的显示设备，其中，所述可执行指令包括:
    在行方向上同时发送次栅极驱动信号和所述主栅极驱动信号对所述低电压子像素进行扫描。
  17. 根据权利要求116的显示设备，其中，第i列的子像素奇数行和第i+1列的偶数行子像素公用一条源极线，i为奇数，一条源极线对应一条源极驱动信号。
  18. 根据权利要求17的显示设备，其中，所述第一源极驱动信号的驱动电压的极性与所述第二源极驱动信号的驱动电压的极性相反
  19. 根据权利要求18的显示设备，其中，每一行子像素的极性相同，相邻两行子像素的极性相反。
  20. 根据权利要求15所述的显示设备，其中，所述可执行指令包括:
    对同列的两个相邻子像素采用所述预设数据驱动信号进行驱动，所述预设数据驱动信号为相邻的两个子像素的历史驱动信号的平均值。
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