WO2020155095A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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WO2020155095A1
WO2020155095A1 PCT/CN2019/074394 CN2019074394W WO2020155095A1 WO 2020155095 A1 WO2020155095 A1 WO 2020155095A1 CN 2019074394 W CN2019074394 W CN 2019074394W WO 2020155095 A1 WO2020155095 A1 WO 2020155095A1
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buffer layer
transition metal
doping concentration
doping
concentration
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PCT/CN2019/074394
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English (en)
French (fr)
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程凯
刘凯
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苏州晶湛半导体有限公司
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Priority to CN201980090928.4A priority Critical patent/CN113424326B/zh
Priority to PCT/CN2019/074394 priority patent/WO2020155095A1/zh
Publication of WO2020155095A1 publication Critical patent/WO2020155095A1/zh
Priority to US17/143,902 priority patent/US11848205B2/en

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Definitions

  • the invention relates to the field of microelectronics technology, in particular to a semiconductor structure and a manufacturing method thereof.
  • High Electron Mobility Transistor is a heterojunction field effect transistor. Take the AlGaN/GaN HEMT structure as an example. The band gap of AlGaN is larger than that of GaN. When they form a heterojunction, A two-dimensional electron gas (2DEG) is formed at the interface of AlGaN and GaN, so HEMT is also called 2DEG field effect transistor.
  • 2DEG two-dimensional electron gas
  • doping transition metals such as iron or other impurities into the region located below the 2DEG can improve the pinch-off characteristics or increase the cut-off voltage, but the electrons trapped by the charge traps composed of impurities hinder the formation of 2DEG, especially Prone to current collapse.
  • reducing the impurity doping concentration is beneficial to suppress the current collapse, the thickness of the buffer layer is not adjusted accurately to eliminate the current collapse.
  • a semiconductor structure which is characterized by including:
  • the first buffer layer is co-doped with transition metal, C, and n-type impurities, the doping concentration of the transition metal remains constant, the doping concentration of C is not greater than the doping concentration of the transition metal, and the n
  • the doping concentration of the n-type impurity is not more than the sum of the doping concentration of C and the doping concentration of the transition metal; preferably, the doping concentration of the C is less than the doping concentration of the transition metal, and the doping concentration of the n-type impurity Doping concentration less than C;
  • the n-type impurity is an impurity that converts a GaN-based semiconductor into an n-type semiconductor
  • the doping thickness of the n-type impurities in the first buffer layer is not greater than the doping thickness of C, and the doping thickness of C is not greater than the doping thickness of the transition metal;
  • the second buffer layer is doped with transition metal, and the concentration of the transition metal in the second buffer layer is less than the concentration of the transition metal in the first buffer layer.
  • the concentration of the transition metal doped in the second buffer layer may decrease in a direction away from the substrate.
  • the semiconductor structure further includes: the second buffer layer is co-doped with transition metal, C, and n-type impurities, and the doping concentration of C is not greater than that of the transition metal.
  • the doping concentration of the n-type impurity is not greater than the sum of the doping concentration of C and the doping concentration of the transition metal; preferably, the doping concentration of the C is less than the doping concentration of the transition metal, and the n-type impurity
  • the doping concentration of impurities is less than the C doping concentration.
  • the semiconductor structure further includes a nucleation layer disposed between the substrate and the buffer layer.
  • a method for preparing a semiconductor structure including:
  • the buffer layer includes a first buffer layer and a second buffer layer in order from the substrate upward;
  • the first buffer layer is co-doped with transition metal, C, and n-type impurities, the doping concentration of the transition metal remains constant, the doping concentration of C is not greater than the doping concentration of the transition metal, The doping concentration of the n-type impurity is not greater than the sum of the doping concentration of C and the doping concentration of the transition metal; preferably, the doping concentration of the C is less than the doping concentration of the transition metal, and the doping of the n-type impurity Doping concentration with a concentration less than C;
  • the n-type impurity is the impurity that transforms the GaN semiconductor into an n-type semiconductor
  • the doping thickness of n-type impurities in the first buffer layer is not greater than the doping thickness of C, and the doping thickness of C is not greater than the doping thickness of the transition metal;
  • the second buffer layer is doped with a transition metal, and the concentration of the transition metal in the second buffer layer is less than the concentration of the transition metal in the first buffer layer;
  • the concentration of the transition metal doped in the second buffer layer can be reduced in a direction away from the substrate.
  • the method for preparing a semiconductor structure further includes: co-doping transition metal, C, and n-type impurities in the second buffer layer, and the doping concentration of C is not greater than that of the transition metal.
  • Impurity concentration, the doping concentration of the n-type impurity is not greater than the sum of the doping concentration of C and the doping concentration of transition metal; preferably, the doping concentration of C is less than the doping concentration of transition metal, and the n The doping concentration of the type impurity is less than the C doping concentration.
  • the method for preparing a semiconductor structure further includes: disposing a nucleation layer between the substrate and the buffer layer.
  • a buffer layer is provided on the substrate layer.
  • the buffer layer includes a first buffer layer and a second buffer layer.
  • the first buffer layer is doped with a transition metal to form a deep level Traps, capture background electrons, and can effectively avoid the diffusion of free electrons to the substrate; reduce the transition metal concentration in the second buffer layer or do not deliberately dope transition metals to avoid metal tailing effects and prevent current collapse; in the buffer C is doped in the layer to make C act as an acceptor impurity to compensate for background electrons and reduce background concentration; at the same time, the choice of n-type impurity and transition metal and C co-doping is mainly to compensate/neutralize deep-level defects introduced by dislocations , So as to obtain a high crystal quality semiconductor structure.
  • FIG. 1 is a schematic diagram of the semiconductor structure involved in the present invention.
  • Figures 2a-2f show the doping modes of transition metal concentration, C and n-type impurity concentration with respect to depth in the semiconductor structure of the present invention.
  • FIG. 3 is a semiconductor structure related to another embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the semiconductor structure of the present invention applied to a HEMT device.
  • the manufacturing method of the semiconductor structure includes:
  • a substrate 1 is provided, and a buffer layer 3 is prepared on the substrate 1, wherein the buffer layer 3 includes a first buffer layer 31 and a second buffer layer 32 from the substrate 1 upwards. ;
  • the substrate 1 includes semiconductor materials, ceramic materials, and polymer materials, preferably sapphire, silicon carbide, silicon, lithium niobate, silicon insulator (SOI), gallium nitride, aluminum nitride .
  • the first buffer layer 31 is co-doped with transition metal, C, and n-type impurities, the doping concentration of the transition metal remains constant, and the doping concentration of C is not greater than that of the transition metal.
  • the doping concentration of the n-type impurity is not greater than the sum of the doping concentration of C and the doping concentration of the transition metal.
  • the doping concentration of the C is less than the doping concentration of the transition metal.
  • the doping concentration of impurities is less than the C doping concentration.
  • the n-type impurity is an impurity that converts a GaN-based semiconductor into an n-type semiconductor, such as Si, Ge, O, etc.
  • the second buffer layer 32 is doped with a transition metal, and the concentration of the transition metal in the second buffer layer 32 is less than the concentration of the transition metal in the first buffer layer;
  • the concentration of the transition metal doped in the second buffer layer 32 may decrease in a direction away from the substrate.
  • the doping concentration of the transition metal in the first buffer layer 31 is 1E17cm -3 to 1E19cm -3 , preferably, the doping concentration is 5E17cm -3 to 5E18cm -3 , and the transition metal is in the buffer Deep-level traps are formed in the layer to capture background electrons.
  • the doping concentration in the 31 C of the first buffer layer is 5E15cm -3 ⁇ 5E18cm -3, it is preferable that the doping concentration of 1E16cm -3 ⁇ 1E18cm -3, C 31 in the first buffer layer As an acceptor impurity to compensate for the background electrons introduced by other impurities, the C concentration cannot be too high, otherwise large dislocations will be introduced in the buffer layer.
  • the doping concentration of n-type impurities in the first buffer layer 31 is 1E15cm -3 ⁇ 2E18cm -3 , preferably, the doping concentration is 5E15cm -3 ⁇ 5E17cm -3 , which is mainly compensation/medium And due to the deep energy levels introduced by defects such as dislocations, a semiconductor structure with high crystal quality can be obtained.
  • the transition metal is at least one of Ti, Cr, Mn, Fe, Co, Ni, Cu, Zn, Mo, Ag, and Cd, preferably Fe.
  • the thickness of the first buffer layer 31 is 0.01 ⁇ m to 5 ⁇ m
  • the thickness of the second buffer layer 32 is 0.05 ⁇ m to 5 ⁇ m.
  • the abscissa represents the thickness of the buffer layer 3. Taking the upper surface of the second buffer layer 32 as 0 nm, the thickness of the abscissa increases toward the direction of the substrate; the ordinate represents the doping The concentration of atoms.
  • the thickness of the first buffer layer 31 is 300nm (600nm-900nm), doped with Fe, C, Si, wherein the doping thickness of Si is not greater than the doping thickness of C, and the doping thickness of C doping is not greater than that of Fe doping Thickness; the doping concentration of Si is 1.1E18cm -3 , and the doping stops at 750nm, so the doping thickness of Si is 150nm, and the doped region is 750nm-900nm; the doping concentration of C is 5E17cm -3 at 650nm Stop doping, the doping area is 650nm-900nm, so the doping thickness of C is 250nm; the doping concentration of Fe is 1E18cm -3 , and the doping area is 600nm-900nm.
  • the thickness of the second buffer layer 31 is 600nm (0nm-600nm), Si and C are not doped, and the doping concentration of Fe gradually decreases to 2E16cm -3 .
  • the deep-level traps formed by the excessive transition metal concentration will form impurity scattering , Reduce mobility.
  • the doping concentration of Si in the first buffer layer is greater than the doping concentration of Fe, but less than the sum of the doping concentrations of Fe and C. In other embodiments, the doping concentration of Si in the first buffer layer may be less than the doping concentration of Fe and greater than the doping concentration of C.
  • the doping concentration of Si in the first buffer layer 31 is 7E17cm ⁇ 3.
  • the doping area is 750nm-900nm; the doping concentration of C is 5E17cm -3 and the doping area is 650nm-900nm; the doping concentration of Fe is 1E18cm -3 and the doping area is 600nm-900nm.
  • the second buffer layer is not deliberately doped with Si and C, and the doping concentration of Fe gradually decreases to 2E16cm -3 .
  • the doping concentration of Si in the first buffer layer is less than the doping concentration of C, and the doping concentration of Fe is less than the doping concentration of C.
  • the doping concentration of Si in the first buffer layer 31 The impurity concentration is 1E17cm -3 , and the doping area is 750nm-900nm; the doping concentration of C is 5E17cm -3 , and the doping area is 650nm-900nm; the doping concentration of Fe is 1E18cm -3 , and the doping area is 600nm-900nm .
  • the second buffer layer is not deliberately doped with Si and C, and the doping concentration of Fe gradually decreases to 2E16cm -3 .
  • the semiconductor structure further includes: 32 co-doped transition metal, C, and n-type impurities in the second buffer layer, the doping concentration of C is not greater than the doping concentration of the transition metal, and the n-type impurities
  • the doping concentration of is not greater than the sum of the doping concentration of C and the doping concentration of transition metal.
  • the doping concentration of C is less than the doping concentration of transition metal, and the doping concentration of n-type impurities is less than C The doping concentration.
  • the second buffer layer 32 is co-doped with transition metal, C, and n-type impurities.
  • the thickness of the first buffer layer 31 is 300nm (600nm-900nm), and the thickness of the second buffer layer 31 a thickness of 600nm (0nm-600nm), Si doping concentration in the region of 750nm 900nm-1E17cm -3, the doping concentration in the region is 0nm-750nm 1E15cm -3; C doping concentration of 650nm-900nm 5E17cm - 3 , the doping concentration in the 0nm-650nm region is 1E16cm -3 ; the doping concentration of Fe in the first buffer layer 31 is 1E18cm -3 , and the doping concentration in the second buffer layer 32 gradually decreases to 2E16cm -3 .
  • the doping concentration of Si in the second buffer layer 32 may also be greater than the doping concentration of Fe, as long as the doping concentration of Si is less than the sum of the doping concentration of Fe and the doping concentration of C.
  • the Si, C and Fe are doped at the same time. In other embodiments, the Si, C and Fe may not be doped at the same time.
  • the doping concentration of Si is 1E17cm -3 , and the doping starts at 800nm, and the doping area is 650nm-800nm; the doping concentration of C is 5E17cm -3 , and the doping starts at 850nm, and the doping area is 600nm-850nm; the doping concentration of transition metal Fe is constant at 1E18cm -3 .
  • the doping concentration of transition metal Fe gradually decreases to 2E16 cm -3 .
  • the second buffer layer 32 is not intentionally doped with Si and C, but in the actual epitaxial growth process, due to various growth Environmental influences may cause a small amount of Si and C residues in the second buffer layer 32, and the concentration of residual Si/C in the second buffer layer 32 is less than 2E16 cm ⁇ 3 .
  • the n-type impurities in the first buffer layer 31 gradually decrease. As shown in FIG. 2f, the doping concentration of Si in the first buffer layer decreases from 1E17cm -3 to 1E15cm -3 .
  • the doping concentration of Si in the second buffer layer is constant at 1E15 cm -3 .
  • the doping thickness of the n-type impurities in the first buffer layer is not greater than The doping thickness of C, the doping thickness of C is not greater than the doping thickness of the transition metal.
  • this case does not limit the falling slope of the n-type impurity and the falling slope of the transition metal.
  • the temperature of the preparation environment, the thickness of the buffer layer, the bond energy of the doped transition metal, and the doped buffer are not limited.
  • the diffusion activation energy in the layer, the doping method of the metal, and the dislocation density between the buffer layer and the substrate layer all affect the drop slope and the minimum concentration of the dopant.
  • the preparation method may be through atomic layer deposition (ALD, Atomic layer deposition), or chemical vapor deposition (CVD, Chemical Vapor Deposition), or molecular beam epitaxy (MBE, Molecular Beam Epitaxy), or plasma Enhanced chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), or low pressure chemical vapor deposition (LPCVD, Low Pressure Chemical Vapor Deposition), or physical vapor deposition (PVD, Physical Vapor Deposition), or metal organic source molecular beam epitaxy ( MOMBE, metal-organic molecular beam epitaxy, or metal-organic chemical vapor deposition (MOCVD, Metal-Organic Chemical Vapor Deposition), or a combination thereof.
  • ALD Atomic layer deposition
  • CVD Chemical Vapor Deposition
  • MBE molecular beam epitaxy
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • the method for preparing a semiconductor structure further includes:
  • a nucleation layer 2 is provided between the substrate 1 and the buffer layer 3, and the nucleation layer 2 includes AlN, GaN, and AlGaN.
  • an embodiment of the present application provides a schematic diagram of a semiconductor structure.
  • the semiconductor structure includes: a substrate 1, a buffer layer 3 provided on the substrate 1, wherein the buffer layer 3 extends from the substrate 1
  • the bottom up includes a first buffer layer 31 and a second buffer layer 32 in sequence.
  • the first buffer layer 31 is co-doped with transition metal, C, and n-type impurities, the doping concentration of the transition metal remains constant, and the doping concentration of C is not greater than the doping concentration of the transition metal.
  • the doping concentration of n-type impurities is not greater than the sum of the doping concentration of C and the doping concentration of transition metal; preferably, the doping concentration of C is less than the doping concentration of transition metal, and the doping of the n-type impurities Doping concentration with a concentration less than C;
  • the n-type impurity is the impurity that transforms the GaN semiconductor into an n-type semiconductor
  • the doping thickness of n-type impurities in the first buffer layer is not greater than the doping thickness of C, and the doping thickness of C is not greater than the doping thickness of the transition metal;
  • the second buffer layer 32 is doped with transition metal, and the concentration of the transition metal in the second buffer layer is less than the concentration of the transition metal in the first buffer layer 31;
  • the concentration of the transition metal doped in the second buffer layer 32 may decrease toward a direction away from the substrate 1.
  • the semiconductor structure further includes: the second buffer layer 32 is co-doped with transition metal, C, and n-type impurities, the doping concentration of C is not greater than the doping concentration of the transition metal, and the doping concentration of the n-type impurities
  • the doping concentration is not greater than the sum of the doping concentration of C and the doping concentration of transition metal; preferably, the doping concentration of C is less than the doping concentration of transition metal, and the doping concentration of n-type impurities is less than that of C. Doping concentration.
  • the doping concentration of the transition metal in the first buffer layer 31 is 1E17cm -3 to 1E19cm -3 , preferably, the doping concentration is 5E17cm -3 to 5E18cm -3 .
  • the doping concentration of the first buffer layer 31 is C 5E15cm -3 ⁇ 5E18cm -3, it is preferable that the doping concentration of 1E16cm -3 ⁇ 1E18cm -3.
  • the doping concentration of the n-type impurities in the first buffer layer 31 is 1E15cm -3 to 2E18cm -3 , preferably, the doping concentration is 5E15cm -3 to 5E17cm -3 .
  • the transition metal is at least one of Ti, Cr, Mn, Fe, Co, Ni, Cu, Zn, Mo, Ag, Cd, and the n-type impurity is Si, Ge, O, wherein The transition metal is preferably Fe, and the n-type impurity is preferably Si.
  • the thickness of the first buffer layer 31 is 0.01 ⁇ m to 5 ⁇ m
  • the thickness of the second buffer layer 32 is 0.05 ⁇ m to 5 ⁇ m.
  • the substrate is semiconductor material, ceramic material, polymer material, preferably sapphire, silicon carbide, silicon, lithium niobate, silicon on insulating substrate (SOI), gallium nitride, aluminum nitride.
  • the semiconductor structure may further include a nucleation layer 2 arranged between the substrate 1 and the buffer layer 3.
  • the semiconductor structure can be applied to a variety of device structures, such as high electron mobility transistors, high electron mobility transistors made of aluminum gallium indium nitride/gallium nitride heterostructures, and aluminum nitride/gallium nitride heterostructures.
  • High mobility triode, gallium nitride MOSFET, LED, photodetector, hydrogen generator or solar cell when applied to an LED device, a light-emitting structure can be prepared on the semiconductor structure; when applied to a HEMT device, a heterojunction structure can be epitaxially grown on the semiconductor structure, as shown in FIG. 4.
  • Figure 4 shows a schematic diagram of the semiconductor structure applied to the HEMT device structure, where the HEMT device includes: a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer 4, a barrier layer 5, and a passivation layer 6. , The gate 7, the source 8, and the drain 9, wherein the buffer layer 3 includes a first buffer layer 31 and a second buffer layer 32.
  • the substrate 1 may be a Si substrate, and in other embodiments, the substrate 1 may also be a sapphire substrate or a SiC substrate;
  • the nucleation layer 2 can be AlN; the buffer layer 3 can be AlGaN; the channel layer 4 can be GaN; the barrier layer 5 is AlGaN, and the channel layer 4 and the barrier layer 5 interface 2DEG is formed at the place.
  • the passivation layer 630 may include silicon nitride, silicon dioxide, aluminum nitride, aluminum oxide, aluminum oxynitride, and the like.
  • the source 8 and the drain 9 form an ohmic contact with the barrier layer 5, and the gate 7 forms a Schottky contact with the passivation layer 6.
  • a buffer layer is provided on the substrate layer.
  • the buffer layer includes a first buffer layer and a second buffer layer.
  • the first buffer layer is doped with a transition metal to form a deep level Traps, capture background electrons, and can effectively avoid the diffusion of free electrons to the substrate; reduce the transition metal concentration in the second buffer layer or do not deliberately dope transition metals to avoid metal tailing effects and prevent current collapse;
  • in the buffer C is doped in the layer to make C act as an acceptor impurity to compensate for background electrons and reduce background concentration; at the same time, the choice of n-type impurities and transition metal and C co-doping is mainly to compensate/neutralize the deep energy introduced by defects such as dislocations Grade, thereby obtaining a semiconductor structure of high crystal quality.

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Abstract

本发明所提供的半导体结构及其制备方法，在衬底层之上设置缓冲层，所述缓冲层包括第一缓冲层和第二缓冲层，在第一缓冲层掺杂过渡金属可以形成深能级陷阱，捕获背景电子，此外还可以有效避免自由电子向衬底方向的扩散；第二缓冲层中降低过渡金属浓度或者不故意掺杂过渡金属，避免金属的拖尾效应，防止电流崩塌；在缓冲层中掺杂C，使得C作为受主杂质，补偿背景电子，减小背景浓度；同时选择n型杂质与过渡金属和C共掺杂主要是补偿/中和由于位错等缺陷引入的深能级，从而获得高晶体质量的半导体结构。

Description

一种半导体结构及其制造方法 技术领域
本发明涉及微电子技术领域，具体涉及一种半导体结构及其制造方法。
发明背景
高电子迁移率晶体管(HEMT，High Electron Mobility Transistor)是一种异质结场效应晶体管，以AlGaN/GaN HEMT结构为例，AlGaN的禁带宽度比GaN的大，它们形成异质结时，在AlGaN和GaN界面处形成二维电子气(2DEG)，因此HEMT又被称为2DEG场效应晶体管。
对于GaN类的HEMT来说，将铁等过渡金属或其它杂质向位于2DEG下部的区域掺杂可以改善夹断特性或提高截止电压，但是由杂质构成的电荷陷阱捕获的电子妨碍2DEG的形成，特别容易产生电流崩塌。虽然降低杂质掺杂浓度有利于抑制电流崩塌，但是调控不准缓冲层的厚度依然不能够消除电流崩塌。
发明内容
有鉴于此，急需提出一种半导体结构及其制备方法，可以在抑制泄漏电流、提升器件夹断特性的同时避免电流崩塌，使得应用该半导体结构的器件在动态特性时漏电流保持平衡。
本发明在一实施例中提供了一种半导体结构，其特征在于，包括：
衬底；
设于所述衬底上的缓冲层，所述缓冲层从衬底向上依次包括第一缓冲层、第二缓冲层；
其中，所述第一缓冲层共掺杂过渡金属、C、n型杂质，所述过渡金属的掺杂浓度保持恒定，所述C的掺杂浓度不大于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度不大于C的掺杂浓度和过渡金属掺杂浓度之和；优选的是，所述C的掺 杂浓度小于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度小于C的掺杂浓度；
其中所述n型杂质是使GaN类半导体转变为n型半导体的杂质；
其中所述第一缓冲层中n型杂质的掺杂厚度不大于C的掺杂厚度，C的掺杂厚度不大于过渡金属的掺杂厚度；
其中，所述第二缓冲层中掺杂过渡金属，所述第二缓冲层中过渡金属的浓度小于第一缓冲层中过渡金属的浓度。
进一步的，在本发明一实施例中，在所述第二缓冲层掺杂的过渡金属浓度可向远离衬底的方向降低。
进一步的，在本发明一实施例中，所述半导体结构还包括：所述第二缓冲层中共掺杂过渡金属、C、n型杂质，所述C的掺杂浓度不大于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度不大于C的掺杂浓度和过渡金属掺杂浓度之和；优选的是，所述C的掺杂浓度小于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度小于C的掺杂浓度。
进一步的，在本发明一实施例中，所述的半导体结构还包括成核层，设于衬底与缓冲层之间。
本发明在一实施例中提供了一种制备半导体结构的方法，包括：
提供一衬底；
在所述衬底上制备缓冲层，其中所述缓冲层从衬底向上依次包括第一缓冲层、第二缓冲层；
其中，所述第一缓冲层中共掺杂过渡金属、C、n型杂质，所述的过渡金属的掺杂浓度保持恒定，所述C的掺杂浓度不大于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度不大于C的掺杂浓度和过渡金属掺杂浓度之和；优选的是，所述C的掺杂浓度小于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度小于C的掺杂浓度；
其中所述的n型杂质是使GaN类半导体转变为n型半导体的杂质；
其中，所述的第一缓冲层中n型杂质的掺杂厚度不大于C的掺杂厚度，C的掺杂厚度不大于过渡金属的掺杂厚度；
其中所述第二缓冲层中掺杂过渡金属，所述第二缓冲层中过渡金属的浓度小于第一缓冲层中过渡金属的浓度；
进一步的，在本发明一实施例中，所述第二缓冲层掺杂的过渡金属浓度可向远离衬底的方向降低。
进一步的，在本发明一实施例中，所述制备半导体结构的方法还包括：第二缓冲层中共掺杂过渡金属、C、n型杂质，所述C的掺杂浓度不大于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度不大于C的掺杂浓度和过渡金属掺杂浓度之和；优选的是，所述C的掺杂浓度小于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度小于C的掺杂浓度。
进一步的，在本发明一实施例中，所述制备半导体结构的方法还包括：在衬底与缓冲层之间设置成核层。
本发明所提供的半导体结构及其制备方法，在衬底层之上设置缓冲层，所述缓冲层包括第一缓冲层和第二缓冲层，在第一缓冲层掺杂过渡金属可以形成深能级陷阱，捕获背景电子，此外还可以有效避免自由电子向衬底方向的扩散；第二缓冲层中降低过渡金属浓度或者不故意掺杂过渡金属，避免金属的拖尾效应，防止电流崩塌；在缓冲层中掺杂C，使得C作为受主杂质，补偿背景电子，减小背景浓度；同时选择n型杂质与过渡金属和C共掺杂主要是补偿/中和因位错引入的深能级缺陷，从而获得高晶体质量的半导体结构。
附图简要说明
图1为本发明涉及的半导体结构示意图。
图2a-2f为本发明半导体结构中过渡金属浓度、C、n型杂质浓度相对于深度变化的掺杂方式。
图3为本发明另一实施例涉及的半导体结构。
图4为本发明半导体结构应用于HEMT器件的示意图。
具体实施方式
以下将结合附图所示的具体实施方式对本发明进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
此外，在不同的实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例和/或结构之间具有任何关联性。
所述半导体结构的制备方法包括：
如图1所示，提供一衬底1，在所述衬底1上制备缓冲层3，其中所述缓冲层3从所述衬底1向上依次包括第一缓冲层31、第二缓冲层32；
本实施例中，所述衬底1包括半导体材料、陶瓷材料、高分子材料，优选的是蓝宝石、碳化硅、硅、铌酸锂、绝缘衬底硅(SOI)、氮化镓、氮化铝。
本实施例中，所述第一缓冲层31中共掺杂过渡金属、C、n型杂质，所述的过渡金属的掺杂浓度保持恒定，所述C的掺杂浓度不大于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度不大于C的掺杂浓度和过渡金属掺杂浓度之和，优选的是，所述C的掺杂浓度小于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度小于C的掺杂浓度。
其中，所述的n型杂质是使GaN类半导体转变为n型半导体的杂质，如Si、Ge、O等。
本实施例中，所述第二缓冲层32中掺杂过渡金属，所述第二缓冲层32中过渡金属的浓度小于第一缓冲层中过渡金属的浓度；
本实施例中，所述第二缓冲层32掺杂的过渡金属浓度可向远离衬底的方向降低。
进一步的，所述第一缓冲层31中过渡金属的掺杂浓度为1E17cm -3～1E19cm -3，优选的是，所述掺杂浓度为5E17cm -3～5E18cm -3，所述过渡金属在缓冲层内形成深能级陷阱，俘获背景电子。
进一步的，所述第一缓冲层31中C的掺杂浓度为5E15cm -3～5E18cm -3，优选的是，所述掺杂浓度为1E16cm -3～1E18cm -3，C在第一缓冲层31中作为受主杂质，补偿其它部分杂质引入的背景电子，所述C浓度不能过高，否则会在缓冲层中引入较大的位错。
进一步的，所述第一缓冲层31中n型杂质的掺杂浓度为1E15cm -3～2E18cm -3，优选的是，所述掺杂浓度为5E15cm -3～5E17cm -3,主要是补偿/中和由于位错等缺陷引入的深能级，从而获得高晶体质量的半导体结构。
进一步的，所述的过渡金属为Ti、Cr、Mn、Fe、Co、Ni、Cu、Zn、Mo、Ag、Cd中的至少一种，优选为Fe。
进一步的，所述的第一缓冲层31的厚度为0.01μm～5μm，所述的第二缓冲层32的厚度为0.05μm～5μm。
具体的，如图2a所示，横坐标表示缓冲层3的厚度，以第二缓冲层32的上表面为0nm，越向衬底的方向，横坐标的厚度值越大；纵坐标为掺杂原子的浓度。第一缓冲层31的厚度为300nm(600nm-900nm)，掺杂Fe、C、Si，其中Si的掺杂厚度不大于C的掺杂厚度，C掺杂的掺杂厚度不大于Fe的掺杂厚度；Si的掺杂浓度为1.1E18cm -3，在750nm处停止掺杂，因此Si的掺杂厚度为150nm，掺杂区域为750nm-900nm；C的掺杂浓度为5E17cm -3，在650nm处停止掺杂，掺杂区域为650nm-900nm，因此C的掺杂厚度为250nm；Fe的掺杂浓度为1E18cm -3，掺杂区域为600nm-900nm。第二缓冲层31的厚度为600nm(0nm-600nm)，不掺杂Si和C，Fe的掺杂浓度逐渐下降至2E16cm -3，过大的过渡金属浓度形成的深能级陷阱会形成杂质散射，降低迁移率。
本实施例中，第一缓冲层中Si的掺杂浓度大于Fe的掺杂浓度，但是小于Fe与C的掺杂浓度之和。其它实施例中，第一缓冲层中Si的掺杂浓度可小于Fe的掺杂浓度并且大于C的掺杂浓度，如图2b所示，第一缓冲层31中Si的掺杂浓度为7E17cm -3，掺杂区域为750nm-900nm；C的掺杂浓度为5E17cm -3，掺杂区域为650nm-900nm；Fe的掺杂浓度为1E18cm -3，掺杂区域为600nm-900nm。第二缓冲层中不故意掺杂Si和C，Fe的掺杂浓度逐渐下降至2E16cm -3。
优选的是，所述第一缓冲层中Si的掺杂浓度小于C的掺杂浓度，Fe的掺杂浓度小于C的掺杂浓度，如图2c所示，第一缓冲层31中Si的掺杂浓度为1E17cm -3，掺杂区域为750nm-900nm；C的掺杂浓度为5E17cm -3，掺杂区域为650nm-900nm；Fe的掺杂浓度为1E18cm -3，掺杂区域为600nm-900nm。第二缓冲层中不故意掺杂Si和C，Fe的掺杂浓度逐渐下降至2E16cm -3。
进一步的，所述的半导体结构还包括：第二缓冲层中32共掺杂过渡金属、C、n型杂质，所述C的掺杂浓度不大于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度不大于C的掺杂浓度和过渡金属掺杂浓度之和,优选的是，所述C的掺杂浓度小于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度小于C的掺杂浓度。
本实施例第二缓冲层中32共掺杂过渡金属、C、n型杂质，具体的如图2d所示，第一缓冲层31的厚度为300nm(600nm-900nm)，第二缓冲层31的厚度为600nm(0nm-600nm)，Si在750nm-900nm区域的掺杂浓度为1E17cm -3，在0nm-750nm区域的掺杂浓度为1E15cm -3；C在650nm-900nm的掺杂浓度为5E17cm -3，在0nm-650nm区域的掺杂浓度为1E16cm -3；Fe在第一缓冲层31中的掺杂浓度为1E18cm -3，在第二缓冲层32中的掺杂浓度逐渐下降至2E16cm -3。
可以理解的是，在第二缓冲层32中Si的掺杂浓度也可以大于Fe的掺杂浓度，只要保证Si的掺杂浓度小于Fe的掺杂浓度和C的掺杂浓度之和即可。
上述实施例中，所述Si、C与Fe是同时开始掺杂的，在其他实施例中，所述Si、C与Fe可以不是同时开始掺杂的，如图2e所示，在第一缓冲层31中，Si的掺杂浓度为1E17cm -3，在800nm处开始掺杂，掺杂区域为650nm-800nm；C的掺杂浓度为5E17cm -3，在850nm处开始掺杂，掺杂区域为600nm-850nm；过渡金属Fe的掺杂浓度恒定为1E18cm -3。第二缓冲层32中，过渡金属Fe的掺杂浓度逐渐下降至2E16cm -3。
可以理解的是，图2a、2b、2c、2e所示的实施例中，所述第二缓冲层32中是不故意掺杂Si和C的，但是在实际外延生长过程中，由于各种生长环境影响导致第二缓冲层32中可能会存在少量的Si和C残留，所述第二缓冲层32中残留Si/C的浓度小于2E16cm -3。
其它实施例中，所述的n型杂质在第一缓冲层31中是逐渐下降的，如图2f所示，Si在第一缓冲层的掺杂浓度从1E17cm -3下降至1E15cm -3，在第二缓冲层Si的掺杂浓度恒定为1E15cm -3。只要保证第一缓冲层中所述n型杂质的掺杂浓度不大于C的掺杂浓度和过渡金属掺杂浓度之和，以及所述的第一缓冲层中n型杂质的掺杂厚度不大于C的掺杂厚度，C的掺杂厚度不大于过渡金属的掺杂厚度即可。
可以理解的是，本案对所述n型杂质的下降斜率和过渡金属的下降斜率是不做限定的，制备环境的温度、缓冲层的厚度、所掺杂过渡金属的键能、所掺杂缓冲层中的扩散激活能、金属的掺杂方式、以及缓冲层与衬底层之间的位错密度都会影响所述下降斜率以及掺杂物质的最低浓度。
进一步的，所述的制备方法可以是通过原子层沉积(ALD,Atomic layer deposition)、或化学气相沉积(CVD，Chemical Vapor Deposition)、或分子束外延生长(MBE，Molecular Beam Epitaxy)、或等离子体增强化学气相沉积法(PECVD，Plasma Enhanced Chemical Vapor Deposition)、或低压化学蒸发沉积(LPCVD，Low Pressure Chemical Vapor Deposition)，或物理气相沉积(PVD，Physical Vapor Deposition)，或金属有机源分子束外延(MOMBE，metal-organic molecular beam epitaxy)，或金属有机化合物化学气相沉积(MOCVD，Metal-Organic Chemical Vapor Deposition)、或其组合方式制得。
进一步的，所述制备半导体结构的方法还包括：
如图3所示，在所述衬底1与所述缓冲层3之间设置成核层2，所述成核层2包括AlN，GaN，AlGaN。
如图3所示，本申请实施例提供了一种半导体结构的示意图，该半导体结构包括：衬底1，设于所述衬底1上的缓冲层3，其中所述的缓冲层3从衬底向上依次包括第一缓冲层31和第二缓冲层32。
所述的第一缓冲层31中共掺杂过渡金属、C、n型杂质，所述的过渡金属的掺杂浓度保持恒定，所述C的掺杂浓度不大于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度不大于C的掺杂浓度和过渡金属掺杂浓度之和；优选的是，所述C 的掺杂浓度小于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度小于C的掺杂浓度；
其中所述的n型杂质是使GaN类半导体转变为n型半导体的杂质；
其中，所述的第一缓冲层中n型杂质的掺杂厚度不大于C的掺杂厚度，C的掺杂厚度不大于过渡金属的掺杂厚度；
其中所述第二缓冲层32中掺杂过渡金属，所述第二缓冲层中过渡金属的浓度小于第一缓冲层31中过渡金属的浓度；
进一步的，所述第二缓冲层32掺杂的过渡金属浓度可向远离衬底1的方向降低。
进一步的，所述的半导体结构还包括：第二缓冲层32中共掺杂过渡金属、C、n型杂质，所述C的掺杂浓度不大于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度不大于C的掺杂浓度和过渡金属掺杂浓度之和；优选的是，所述C的掺杂浓度小于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度小于C的掺杂浓度。
进一步的，所述第一缓冲层31中过渡金属的掺杂浓度为1E17cm -3～1E19cm -3，优选的是，所述掺杂浓度为5E17cm -3～5E18cm -3。
进一步的，所述第一缓冲层31中C的掺杂浓度为5E15cm -3～5E18cm -3，优选的是，所述掺杂浓度为1E16cm -3～1E18cm -3。
进一步的，所述第一缓冲层31中n型杂质的掺杂浓度为1E15cm -3～2E18cm -3，优选的是，所述掺杂浓度为5E15cm -3～5E17cm -3。
进一步的，所述的过渡金属为Ti、Cr、Mn、Fe、Co、Ni、Cu、Zn、Mo、Ag、Cd中的至少一种，所述的n型杂质为Si、Ge、O，其中过渡金属优选为Fe，n型杂质优选为Si。
进一步的，所述的第一缓冲层31的厚度为0.01μm～5μm，所述的第二缓冲层32的厚度为0.05μm～5μm。
进一步的，所述的衬底为半导体材料、陶瓷材料、高分子材料，优选的是蓝宝石、碳化硅、硅、铌酸锂、绝缘衬底硅(SOI)、氮化镓、氮化铝。
本实施例中，为了降低位错密度和缺陷密度，防止回熔，该半导体结构还 可以进一步包括设置于衬底1和缓冲层3之间的成核层2。
该半导体结构可应用于多种器件结构当中，例如高电子迁移率晶体管、铝镓铟氮/氮化镓异质结构成的高电子迁移率晶体管、氮化铝/氮化镓异质结构成的高迁移率三极管、氮化镓MOSFET、LED、光电探测器、氢气产生器或太阳能电池。例如应用于LED器件时，可在该半导体结构上制备发光结构；而应用于HEMT器件时，可在该半导体结构上外延生长异质结结构，如图4。
图4给出了在该半导体结构应用于HEMT器件结构的示意图，其中该HEMT器包括：衬底1、成核层2、缓冲层3、沟道层4、势垒层5、钝化层6、栅极7、源极8、漏极9，其中缓冲层3包括第一缓冲层31和第二缓冲层32。
本实施例中，所述的衬底1可以为Si衬底，在其他实施例中，所述的衬底1也可以是蓝宝石衬底或者SiC衬底；
本实施例中，所述的成核层2可以是AlN；缓冲层3可以是AlGaN；沟道层4可以是GaN；势垒层5为AlGaN，所述沟道层4与势垒层5界面处形成2DEG。
本实施例中，所述钝化层630可以包括氮化硅、二氧化硅、氮化铝、氧化铝、氧氮铝等。
本实施例中，所述的源极8、漏极9与势垒层5形成欧姆接触，所述的栅极7与钝化层6形成肖特基接触。
本发明所提供的半导体结构及其制备方法，在衬底层之上设置缓冲层，所述缓冲层包括第一缓冲层和第二缓冲层，在第一缓冲层掺杂过渡金属可以形成深能级陷阱，捕获背景电子，此外还可以有效避免自由电子向衬底方向的扩散；第二缓冲层中降低过渡金属浓度或者不故意掺杂过渡金属，避免金属的拖尾效应，防止电流崩塌；在缓冲层中掺杂C，使得C作为受主杂质，补偿背景电子，减小背景浓度；同时选择n型杂质与过渡金属和C共掺杂主要是补偿/中和由于位错等缺陷引入的深能级，从而获得高晶体质量的半导体结构。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当 组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，它们并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (16)

  1. 一种半导体器件，其特征在于，包括：
    衬底；
    设于所述衬底上的缓冲层，其中所述缓冲层从衬底向上依次包括第一缓冲层、第二缓冲层；
    其中，所述的第一缓冲层中共掺杂过渡金属、C、n型杂质，所述的过渡金属的掺杂浓度保持恒定，所述C的掺杂浓度不大于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度不大于C的掺杂浓度和过渡金属掺杂浓度之和；
    其中，所述的第一缓冲层中n型杂质的掺杂厚度不大于C的掺杂厚度，C的掺杂厚度不大于过渡金属的掺杂厚度；
    其中所述第二缓冲层中掺杂过渡金属，所述第二缓冲层中过渡金属的浓度小于第一缓冲层中过渡金属的浓度。
  2. 根据权利要求1所述的半导体器件，其特征在于：所述第二缓冲层中共掺杂过渡金属、C、n型杂质，所述C的掺杂浓度不大于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度不大于C的掺杂浓度和过渡金属掺杂浓度之和。
  3. 根据权利要求1或2所述的半导体器件，其特征在于：所述第二缓冲层掺杂的过渡金属浓度向远离衬底的方向降低。
  4. 根据权利要求1或2所述的半导体器件，其特征在于：所述第一缓冲层中过渡金属的掺杂浓度为1E17cm -3～1E19cm -3。
  5. 根据权利要求1或2所述的半导体器件，其特征在于：所述第一缓冲层中C的掺杂浓度为5E15cm -33～5E18cm -3。
  6. 根据权利要求1或2所述的半导体器件，其特征在于：所述第一缓冲层中n型杂质的掺杂浓度为1E15cm -3～2E18cm -3。
  7. 根据权利要求1或2所述的半导体器件，其特征在于：所述的过渡金属为Ti、Cr、Mn、Fe、Co、Ni、Cu、Zn、Mo、Ag、Cd中的至少一种。
  8. 根据权利要求1或2所述的半导体器件，其特征在于：所述的n型杂质包 括Si、Ge、O。
  9. 根据权利要求1或2所述的半导体器件，其特征在于：所述的第一缓冲层的厚度为0.01μm～5μm，所述的第二缓冲层的厚度为0.05μm～5μm。
  10. 根据权利要求1或2所述的半导体器件，其特征在于：所述的衬底为半导体材料、陶瓷材料、高分子材料，包括蓝宝石、碳化硅、硅、铌酸锂、绝缘衬底硅(SOI)、氮化镓、氮化铝。
  11. 一种制备半导体结构的方法，包括：
    提供一衬底；
    在所述衬底上制备缓冲层，其中所述缓冲层从衬底向上依次包括第一缓冲层、第二缓冲层；
    其中，所述的第一缓冲层中共掺杂过渡金属、C、n型杂质，所述的过渡金属的掺杂浓度保持恒定，所述C的掺杂浓度不大于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度不大于C的掺杂浓度和过渡金属掺杂浓度之和；
    其中，所述的第一缓冲层中n型杂质的掺杂厚度不大于C的掺杂厚度，C的掺杂厚度不大于过渡金属的掺杂厚度；
    其中所述第二缓冲层中掺杂过渡金属，所述第二缓冲层中过渡金属的浓度小于第一缓冲层中过渡金属的浓度。
  12. 根据权利要求11所述的制备半导体结构的方法，其特征在于：第二缓冲层中共掺杂过渡金属、C、n型杂质，所述C的掺杂浓度不大于过渡金属的掺杂浓度，所述n型杂质的掺杂浓度不大于C的掺杂浓度和过渡金属掺杂浓度之和。
  13. 根据权利要求11或12所述的制备半导体结构的方法，其特征在于：所述第二缓冲层掺杂的过渡金属浓度向远离衬底的方向降低。
  14. 根据权利要求11或12所述的制备半导体结构的方法，其特征在于：所述第一缓冲层中过渡金属的掺杂浓度为1E17cm -3～1E19cm -3。
  15. 根据权利要求11或12所述的制备半导体结构的方法，其特征在于：所述第一缓冲层中C的掺杂浓度为5E15cm -3～5E18cm -3。
  16. 根据权利要求11或12所述的制备半导体结构的方法，其特征在于：所述第一缓冲层中n型杂质的掺杂浓度为1E15cm -3～2E18cm -3。
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