WO2020151458A1 - 通信方法和光模块 - Google Patents

通信方法和光模块 Download PDF

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Publication number
WO2020151458A1
WO2020151458A1 PCT/CN2019/129697 CN2019129697W WO2020151458A1 WO 2020151458 A1 WO2020151458 A1 WO 2020151458A1 CN 2019129697 W CN2019129697 W CN 2019129697W WO 2020151458 A1 WO2020151458 A1 WO 2020151458A1
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Prior art keywords
delay
optical module
optical
data stream
circuit
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Ceased
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PCT/CN2019/129697
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English (en)
French (fr)
Chinese (zh)
Inventor
祁云磊
李春荣
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to JP2021542439A priority Critical patent/JP7482884B2/ja
Priority to MX2021008729A priority patent/MX2021008729A/es
Priority to EP19911499.2A priority patent/EP3902165A4/en
Publication of WO2020151458A1 publication Critical patent/WO2020151458A1/zh
Priority to US17/368,986 priority patent/US11876884B2/en
Anticipated expiration legal-status Critical
Priority to JP2023115753A priority patent/JP7637724B2/ja
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0075—Arrangements for synchronising receiver with transmitter with photonic or optical means
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/66—Non-coherent receivers, e.g. using direct detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/40—Transceivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0691—Synchronisation in a TDM node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H04Q2011/0037—Operation
    • H04Q2011/0045—Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1336—Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/36—Synchronisation

Definitions

  • the embodiments of the present application relate to the field of communication technologies, and in particular, to a communication method and an optical module.
  • base stations based on the Time Division Duplex (TDD) system need to meet strict time synchronization requirements, otherwise the wireless signals sent by the base station will interfere with other base stations, causing base stations in adjacent areas to fail to work normally .
  • TDD Time Division Duplex
  • time synchronization between different base stations can be achieved through clock protocols.
  • IEEE Institute of Electrical and Electronics Engineers
  • 1588V2 protocol is a precision clock synchronization protocol standard for network measurement and control systems.
  • the 1588V2 protocol is also called Precision Time Protocol (PTP). Realize the time synchronization of multiple network devices, and the accuracy can reach the microsecond level.
  • PTP Precision Time Protocol
  • the master-slave clock method is adopted.
  • the master-slave time is realized through the two-way interaction of message messages by encoding time information, using network symmetry and delay measurement technology Synchronization. Specifically, the master and slave clocks respectively stamp the message when sending and receiving a message, thereby calculating the time difference between the master and slave clocks, and the slave clock calibrates the local time according to the calculated time difference.
  • the embodiments of the present application provide a communication method and an optical module, which can report the delay of the optical module to an interface chip, so as to improve the accuracy of time synchronization between the master and slave clocks, thereby further improving the clock accuracy of the network device.
  • the first aspect of this application provides a communication method, including:
  • the first optical module determines the first time delay
  • the first optical module sends the first delay to the interface chip.
  • the first optical module can report the first delay to the interface chip through the delay reporting register access interface, so that the second optical module can report the first delay to the interface chip.
  • a time delay is compensated to the time stamp of the message recorded by the interface chip to improve the accuracy of time synchronization between the master and slave clocks, thereby further improving the clock accuracy of the network device.
  • the first optical module is a gray optical module
  • the first optical module includes an optical transmitter
  • the optical transmitter includes an input interface and an output interface
  • the first optical module determines the first time Extension, including:
  • the first optical module receives the first data stream through the ingress interface
  • the first optical module sends the first data stream to the second network device through the outgoing interface
  • the first optical module determines that the transmission delay of the first data stream in the optical transmitter is the first delay.
  • the first delay may be the delay of the first data stream being transmitted in the optical transmitter in the first optical module.
  • the above-mentioned first delay may also be the delay caused by different processing circuits in the optical transmitter when processing the first data stream.
  • the above-mentioned first delay may be the delay of the first data stream being transmitted from the inbound interface of the optical transmitter to the outbound interface of the optical transmitter, or it may be the delay of at least one processing circuit included in the optical transmitter on the first data stream.
  • the delay caused by the processing of the data stream can also be the delay caused by the processing of the first data stream by at least one processing circuit included in the optical transmitter plus the default value or the design value The sum.
  • the first optical module is a color light optical module in a first network device, and the first optical module includes an optical transmitter and a first optical receiver;
  • the method further includes:
  • the first optical module receives a first data stream through the optical transmitter, and the transmission delay of the first data stream in the optical transmitter is a second delay;
  • the first optical module sends the first data stream to the second optical receiver of the second optical module in the second network device through the optical transmitter.
  • the first data stream is transmitted in the second optical receiver Delay for the third time delay;
  • the sum of the second delay and the third delay is the first delay
  • the first optical module receives a second data stream sent by the second network device through the first optical receiver, and the second data stream carries indication information;
  • the determining of the first time delay by the first optical module includes:
  • the first optical module determines the first delay according to the instruction information.
  • the first optical module is the color light optical module in the first network device
  • the second optical module is the color light optical module in the second network device.
  • the first optical module includes an optical transmitter and a first optical receiver. After the first optical module receives the first data stream through the optical transmitter, it transmits the optical transmitter to the second optical module in the second network device. The second optical receiver sends the first data stream. In this way, according to the first data stream, the second delay of the transmission of the first data stream in the first optical module and the third delay of the transmission in the second optical module can be measured.
  • the second delay is carried in the first data stream and sent to the second optical module.
  • the optical module determines the third delay of the first data stream in the second optical module, the sum obtained by adding the second delay and the third delay is determined as the first delay.
  • the second optical module sends a second data stream to the first optical module.
  • the second data stream carries indication information. In this way, the first optical module can determine the first optical module according to the indication information. A time delay.
  • the indication information includes the first delay.
  • the first delay is a design value.
  • the above-mentioned first time delay can be a preset design value, or a simulation value obtained through simulation, of course, it can also be a Defaults.
  • the method further includes:
  • the first optical module extracts the first indication signal carried in the first data stream when the first data stream is transmitted to the first circuit
  • the first optical module extracts the second indication signal carried in the first data stream when the first data stream is transmitted to the second circuit
  • the first optical module determines the first time delay according to the first indication signal and the second indication signal.
  • the determining the first time delay according to the first indication signal and the second indication signal includes:
  • both the first indication signal and the second indication signal may be alignment mark AM indication signals, or the first indication signal may be an AM indication signal, and the second indication signal may be a digital signal processing DSP frame header signal.
  • the first indication signal carried in the first data stream is extracted, and when the first data stream is transmitted to the second circuit, the first indication signal carried in the first data stream is extracted The second indication signal. Then, by measuring the phase difference between the first indicator signal and the second indicator signal through a high-precision phase detection algorithm, the first time delay can be determined, which can improve the accuracy of the determined time delay.
  • first circuit and the second circuit may be any two different circuits in the first optical module.
  • first indicator signal and the second indicator signal may be an AM indicator signal, or the first indicator signal is an AM indicator signal, and the second indicator signal is a digital signal processing DSP frame header signal.
  • first indication signal and second indication signal may also be other signals that are convenient for identification, such as an identifier inserted in the first data stream.
  • the interface chip includes at least one of a physical layer PHY chip and a media access control layer MAC chip.
  • a second aspect of the present application provides an optical module used as a first optical module, including:
  • the processor is also used to send the first delay to the interface chip.
  • the first optical module is a gray light optical module
  • the first optical module includes an optical transmitter
  • the optical transmitter includes the processor, an inbound interface, and an outbound interface, wherein:
  • the optical transmitter is used to receive the first data stream through the inbound interface
  • the optical transmitter is also used to send the first data stream to the second network device through the outgoing interface
  • the processor is further configured to determine that the transmission delay of the first data stream in the optical transmitter is the first delay.
  • the first optical module is a colored light optical module in a first network device, the first optical module includes an optical transmitter and a first optical receiver, and the first optical receiver includes the processor;
  • the optical transmitter is configured to receive a first data stream, and the transmission delay of the first data stream in the optical transmitter is a second delay;
  • the optical transmitter is also used to send the first data stream to the second optical receiver of the second optical module in the second network device.
  • the transmission delay of the first data stream in the second optical receiver Is the third time delay;
  • the sum of the second delay and the third delay is the first delay
  • the first optical receiver is configured to receive a second data stream sent by the second network device, where the second data stream carries indication information;
  • the processor is specifically configured to determine the first delay according to the instruction information.
  • the indication information includes the first delay.
  • the first delay is a design value.
  • the optical transmitter includes a first circuit and a second circuit; the processor is further used for:
  • the first time delay is determined according to the first indication signal and the second indication signal.
  • the processor is also used for:
  • first indicator signal and the second indicator signal are both alignment mark AM indicator signals, or the first indicator signal is an AM indicator signal, and the second indicator signal is a digital signal processing DSP frame header signal.
  • the interface chip includes at least one of a physical layer PHY chip and a media access control layer MAC chip.
  • the first optical module determines the first delay, it will send the determined first delay to the interface chip. Since the delay reporting register access interface is defined in the first optical module, the first optical module can report the first delay to the interface chip through the delay reporting register access interface to compensate the first delay to the MAC In the time stamp of the message recorded by the layer or the PHY layer, the accuracy of time synchronization between the master and slave clocks can be improved, and the clock accuracy of the network device can be further improved.
  • FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the application
  • Figure 2 is a schematic diagram of calculating the time difference between the master and slave clocks
  • FIG. 3 is a schematic flowchart of a communication method provided by an embodiment of this application.
  • Figure 4 is a schematic diagram of the composition of an optical module
  • Figure 5 is a schematic diagram of the structure of a gray light optical module
  • Fig. 6 is a schematic diagram of the structure of the color light optical module
  • Figure 7 is a schematic diagram of the structure of the oDSP chip in the gray light optical module
  • Figure 8 is a schematic diagram of the structure of the oDSP chip in the color light optical module
  • FIG. 9 is a schematic structural diagram of an optical module provided by an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of another optical module provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of yet another optical module provided by an embodiment of the application.
  • Optical module mainly composed of photoelectric conversion devices and electrical signal processing devices.
  • the optical module includes two parts: an optical transmitter and an optical receiver.
  • the electrical signal processing device includes a clock and data recovery (clock and data recovery; CDR) chip or an optical digital signal processing (optical digital signal processing; oDSP) chip.
  • Optical modules usually perform photoelectric conversion and/or electro-optical conversion. For example, the optical module at the transmitting end converts the electrical signal into an optical signal, and after the converted optical signal is transmitted to the optical module at the receiving end through an optical fiber, the optical module at the receiving end then converts the optical signal into an electrical signal to compare the converted electrical signal. Signal processing.
  • Network equipment which can be equipment used to communicate with mobile devices.
  • Network equipment can be routers, switches, packet transport network (PTN) equipment, optical transport network (OTN) equipment, passive Optical network (passive optical network; PON) equipment or synchronous digital hierarchy (synchronous digital hierarchy; SDH) equipment, etc.
  • PTN packet transport network
  • OTN optical transport network
  • PON passive Optical network
  • synchronous digital hierarchy synchronous digital hierarchy; SDH
  • AP access points
  • base transceiver stations in GSM or CDMA , BTS base transceiver stations
  • BTS base transceiver stations
  • AP access points
  • base transceiver stations in GSM or CDMA , BTS
  • AP access points
  • base transceiver stations in GSM or CDMA , BTS
  • AP access points
  • base transceiver stations in GSM or CDMA , BTS
  • AP access points
  • base transceiver stations in GSM or CDMA , BTS
  • AP access points
  • the delay report register access interface which can also be called the register access interface or the delay report interface. It is used to report the transmission delay of the message in the optical transmitter or optical receiver of the first optical module to the interface chip, or is used to report the message to the interface chip in the optical transmitter of the first optical module, and the message The transmission delay in the optical receiver of the second optical module.
  • At least one can refer to one or more, and “multiple” refers to two or more.
  • “And/or” describes the association relationship of the associated object, indicating that there can be three relationships, for example, A and/or B, which can mean: A alone exists, both A and B exist, and B exists alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the associated objects are in an "or” relationship.
  • "The following at least one item (a)” or similar expressions refers to any combination of these items, including any combination of a single item (a) or a plurality of items (a).
  • At least one item (a) of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple .
  • the range described as “above” or “below” includes boundary points.
  • the unit in this application refers to a functional unit or a logical unit. It can be in the form of software, and its function is realized by the processor executing the program code; it can also be in the form of hardware.
  • the communication method provided in the embodiments of this application can be applied to the application scenario where the optical module reports the time delay to the interface chip, where the interface chip includes a physical layer (PHY) chip and media access control At least one of the layer (media access control; MAC) chips.
  • PHY physical layer
  • MAC media access control
  • the interface chip can realize the function of PHY layer.
  • base stations based on the Time Division Duplex (TDD) system need to meet strict time synchronization requirements, otherwise the wireless signals sent by the base station will interfere with other base stations, causing base stations in adjacent areas to fail to work normally .
  • TDD Time Division Duplex
  • the 1588V2 protocol is enabled to transmit time information as an example for description.
  • other protocols can also be used to transmit time information.
  • the clock level information can be represented by synchronization status information (synchronous status message, SSM) information in the SDH protocol.
  • FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the application.
  • a time source device is usually deployed at the core layer of the wireless network, and satellite time is received through the Global Positioning System (GPS) or Beidou As a reference source, it then transmits time information to the transmission device 101 through external time auxiliary interfaces such as pulse per second and time of day (1Pulse per Second and Time of Day; 1PPS+TOD) or PTP interface (Ethernet interface with 1588V2 protocol enabled),
  • the transmission device 101 hops down from the core layer through the PTP interface, passing time information to the convergence layer device 102, and the convergence layer device 102 hops down again, passing the time information to the access layer device 103, and the access layer device 103
  • the time information is transmitted to the connected base station 104 through the external time auxiliary interface such as 1PPS+TOD or the PTP interface, so as to realize the time synchronization of the base stations of the whole network.
  • the transmission device 101, the convergence layer device 102, and the access layer device 103 may be network devices such as routers, switches, PTN devices, OTN devices, or PON devices.
  • the transmission device 101, the convergence layer device 102, and the access layer device 103 may also perform time synchronization through the solution described in the embodiment of the present application.
  • the 1588V2 protocol also referred to as PTP, is a precise time synchronization protocol that can synchronize the time of multiple network devices.
  • the core idea is to use the master-slave clock mode to encode time information, use the symmetry of the network and delay measurement technology to realize master-slave time synchronization through the two-way interaction of messages.
  • the master and slave clocks respectively stamp the message when sending and receiving a message, thereby calculating the time difference between the master and slave clocks, and the slave clock calibrates the local time according to the calculated time difference.
  • Figure 2 is a schematic diagram of calculating the time difference between the master and slave clocks.
  • the master node (Master) sends a synchronization message (Sync) to the slave node (Slave), and records the sending timestamp t1 in the register. After the node (Slave) receives the synchronization message, it will record the received timestamp t2.
  • the master node (Master) sends a follow message (Follow_Up) to the slave node (Slave), and carries the timestamp t1 to the follow message.
  • the text is sent to the slave node (Slave), and the slave node (Slave) sends a delay request message (Delay_Req) to the master node (Master), where the delay request message carries a timestamp t3.
  • the master node (Master) After receiving the delay request message, the master node (Master) records the reception timestamp t4, and the master node (Master) carries t4 in the delay response message (Delay_Resp) and sends it to the slave node (Slave).
  • the clock in the master node is the master clock
  • the clock in the slave node is the slave clock.
  • the slave clock can calculate the delay and time difference (Offset) between the slave clock and the master clock according to the following formula (1) and formula (2), and the slave clock passes the delay (Delay) and time difference (Offset), the local time stamp can be calibrated to achieve synchronization between master and slave clocks.
  • the stamping reference plane of the master and slave clocks is at the physical medium-dependent interface (MDI) of the PTP port.
  • MDI physical medium-dependent interface
  • the MDI layer cannot complete the PTP message header identification, and thus the stamping cannot be completed. Therefore, in the specific implementation, the media access control (MAC) layer or the physical layer (PHY) layer is often stamped to record the time stamp of the message, and the MAC layer or PHY layer The time delay between the 1588 message stamping point and the MDI layer of the optical module is measured and compensated to the time stamp recorded in the MAC layer or the PHY layer, thereby realizing the function of stamping at the MDI layer.
  • the MDI layer of the optical module is the port of the photoelectric conversion device in the optical module.
  • the current Ethernet protocol IEEE 802.3 only defines the register interface for reporting the PHY layer delay, and uses the above message transmission delay in the PHY layer.
  • the PHY layer is jointly implemented by the interface chip and the optical module, that is, the PHY layer delay includes two parts, the PHY layer delay of the interface chip, and the PHY layer delay of the optical module.
  • the protocol only the PHY layer delay of the interface chip is reported.
  • the delay compensated in the recorded time stamp only includes the PHY layer delay of the interface chip, and the PHY layer delay of the optical module is not recorded, so that the compensated The time stamp is inaccurate, resulting in low accuracy of the master-slave clock time synchronization, resulting in low accuracy of the clock of the network device.
  • the reporting delay function of the PHY layer currently defined by the IEEE 802.3 protocol has low accuracy, which also leads to inaccurate 1588 timestamps, which results in low accuracy of network equipment clocks.
  • the reasons for the low accuracy of IEEE 802.3 report delay include several points: 1) The accuracy of the report delay is 1 ns; 2) The PHY layer includes multiple sub-layers (eg, PCS, PMA, PMD, etc.), and each sub-layer has a report delay. Accuracy will introduce a loss of 1ns, so that N sublayers report delays respectively, resulting in a total delay accuracy of N ns.
  • the embodiment of the present application takes the above problem into consideration and proposes a communication method, in which, after determining the first delay, the first optical module sends the determined first delay to the interface chip. Since the delay reporting register access interface is defined in the first optical module, the first optical module can report the first delay to the interface chip through the delay reporting register access interface, so that the message can be transmitted in the optical module. The generated time delay is compensated to the time stamp of the recorded message, so that the accuracy of time synchronization between the master and slave clocks can be improved, and the clock accuracy of the network device can be further improved.
  • FIG. 3 is a schematic flowchart of a communication method provided by an embodiment of this application. As shown in FIG. 3, the method of this embodiment may include:
  • Step 301 The first optical module determines a first delay.
  • the PTP time stamp before correction is the same as the corrected offset calculation result.
  • delay reporting and correction may not be performed. Therefore, in practical applications, it is only necessary to perform delay reporting and correction on optical modules with asymmetric delays in the receiving and transmitting directions. Therefore, before introducing how the first optical module determines the first delay, the structure of the existing optical module and the delay symmetry of the optical module are introduced first.
  • FIG. 4 is a schematic diagram of the composition of the optical module.
  • the optical module 100 includes an optical transmitter 110 and an optical receiver 120.
  • the optical module 100 can generally be divided into two parts, the "digital domain” and the “analog domain”.
  • the "digital domain” is composed of CDR or oDSP chips, which mainly implement analog and digital signal processing.
  • the "analog domain” includes the optical transmit sub-module (transmitter optical subassembly; TOSA) and the optical receive sub-module (receiver optical subassembly; ROSA), including gold fingers and printed circuits Board (printed circuit board; PCB) traces and photoelectric conversion devices are generally designed according to the symmetry of receiving and sending, and the delay of receiving and sending is relatively fixed and symmetric, which basically has no effect on the accuracy of clock synchronization. Therefore, when determining the time delay in the optical module, usually only the time delay in the "digital domain" is considered.
  • the optical module uses a CDR chip, since the CDR chip processes the data stream through a pure analog signal circuit, at this time, the transmission and reception delays in the optical module are symmetrical, so there is no need to determine and delay the delay. Reported.
  • the delay of the optical module may also be determined using the method in the embodiment of the present application, or the delay of the optical module may also be designed as a default value or a design value.
  • the oDSP chip will cause asymmetry and uncertainty in the transmission and reception delay. At this time, the delay of the message transmission in the optical module will affect the accuracy of the clock of the network device. Therefore, it is necessary to determine the delay of the message transmission in the optical module, and report the delay to the interface chip to improve the accuracy of the clock of the network device.
  • a specific example is used for description.
  • FIG. 5 is a schematic diagram of the structure of the gray light optical module.
  • the gray light optical module includes an optical transmitter 170 and an optical receiver 180.
  • the optical transmitter 170 includes an oDSP chip 130 and a TOSA 25, an optical receiver 180 includes oDSP chip 140 and ROSA 26.
  • TOSA 25 and ROSA 26 connect optical fibers.
  • the oDSP chip 130 includes serializing/deserializing circuits (Serializing/deserializing circuitry; Serial) 11, channel alignment circuit 12, first in first out (first in first out; FIFO) circuit 13, mapping circuit 14, digital A signal processing (digital signal processing; DSP) circuit 15, a FIFO circuit 16, and a digital analog converter (digital analog converter; DAC) 17.
  • oDSP chip 140 includes serial/parallel circuit (Serdes) 18, channel distribution circuit 19, FIFO circuit 20, demapping circuit 21, DSP circuit 22, FIFO circuit 23, and analog digital converter (analog digital converter) connected in sequence; ADC) 24.
  • the mapping circuit 14 may be implemented by a four-level pulse amplitude modulation (PAM4) circuit or a bit interleaving (BitMux) circuit.
  • the demapping circuit 21 can be implemented by a PAM4 circuit or a bit deinterleaving (BitDeMux) circuit.
  • the circuits in the oDSP chip 130 and the oDSP chip 140 mentioned above will cause asymmetry and uncertainty in the transmission and reception delays. About 10NS (nanosecond) delays may be introduced, which will cause the accuracy of clock synchronization between base stations to be low. , Thereby affecting the clock accuracy of network equipment. Therefore, the gray optical module determines the delay of the message transmission in the gray optical module, and reports the delay to the interface chip, which can further improve the clock accuracy of the network device.
  • FIG. 6 is a schematic diagram of the structure of the color light optical module.
  • the color light optical module includes an optical transmitter 190 and an optical receiver 200.
  • the optical transmitter 190 includes an oDSP chip 150 and an integrated adjustable laser array (integrable tunable laser assembly; ITLA) 49.
  • the optical receiver 200 includes an oDSP chip 160 and a dual filter switch 50. ITLA 49 and the dual filter switch 50 are connected to the optical fiber.
  • the oDSP chip 150 includes serializing/deserializing circuits (Serializing/deserializing circuitry; Serial) 31, channel alignment circuit 32, FIFO circuit 33, mapping circuit 34, FIFO circuit 35, and forward error correction (forward error correction) connected in sequence. correction; FEC) circuit 36, DSP circuit 37, FIFO circuit 38, and DAC 39.
  • oDSP chip 160 includes serial/parallel circuit (Serdes) 40, channel distribution circuit 41, FIFO circuit 42, demapping circuit 43, FIFO circuit 44, FEC circuit 45, DSP circuit 46, FIFO circuit 47, and ADC connected in sequence. 48.
  • mapping circuit 34 may be implemented by a framer (Framer) or a bit interleaving (BitMux) circuit.
  • demapping circuit 43 can be implemented by a deframer (DeFramer) or a bit deinterleaving (BitDeMux) circuit.
  • the oDSP chip 150 and oDSP chip 160 of the color light optical module add FEC circuits to the gray optical module, there are more uncertain factors in the transmission and reception delay, and the impact on the synchronization accuracy is about 10NS. Therefore, the above The color light optical module determines the delay of the message transmission in the color light optical module, and reports the delay to the interface chip, which can further improve the clock accuracy of the network device.
  • the following uses the gray light module and the color light module as an example for the first optical module to respectively introduce the process of determining the first delay by the first optical module.
  • the first optical module when the first optical module is a gray optical module, the first optical module includes an optical transmitter 170, and the optical transmitter 170 includes an input interface and an output interface, and the first optical module can receive the first optical module through the input interface.
  • a data stream is sent to the second network device through the outgoing interface, and the first optical module determines that the transmission delay of the first data stream in the optical transmitter is the first delay.
  • the first delay may be the delay of the first data stream being transmitted in the optical transmitter 170 in the first optical module. It can be understood that, referring to FIG. 5, since the optical transmitter 170 includes different processing Therefore, the aforementioned first delay may also be the delay caused by different processing circuits in the optical transmitter when processing the first data stream.
  • the above-mentioned first delay may be the delay of the first data stream being transmitted from the inbound interface of the optical transmitter 170 to the outbound interface of the optical transmitter 170.
  • the first delay may also be a delay caused by at least one processing circuit included in the optical transmitter 170 when processing the first data stream.
  • the first delay may also be the sum of the delay caused by at least one processing circuit included in the optical transmitter 170 when processing the first data stream and the default value or design value.
  • the first delay may be the delay of the first data stream being transmitted from the serial/parallel circuit 11 to the optical TOSA module 25, or it may be the processing circuit in the oDSP chip 130 performing the processing of the first data stream.
  • the time delay caused during processing can also be the time delay caused when the channel alignment circuit 12, FIFO circuit 13, mapping circuit 14, DSP circuit 15 and FIFO circuit 16 in the oDSP chip 130 process the first data stream. The sum obtained by adding the default value or design value.
  • the first optical module extracts the first indication signal carried in the first data stream when the first data stream is transmitted to the first circuit, and extracts the first data stream when the first data stream is transmitted to the second circuit
  • the second indication signal carried in the, and the first time delay is determined according to the first indication signal and the second indication signal.
  • the first time delay can be measured based on the alignment marker (AM) indicator signal, that is, the first indicator signal and the second indicator signal can be AM indicator signals.
  • the first indicator signal and the second indicator signal can also be other signals that are easy to identify, such as an identifier inserted in the first data stream.
  • the specific form of the signal is not limited in the embodiment of the present application, as long as the first indicator signal and the second indicator signal can be identified in the inbound interface and the outbound interface.
  • the phase difference between the first indicator signal and the second indicator signal can be measured, and the first time delay can be determined according to the above phase difference.
  • the first circuit and the second circuit can be any two different circuits in the oDSP chip.
  • the first circuit can be the channel alignment circuit 12 shown in FIG. 5, and the second circuit can be the FIFO circuit 16.
  • the transmission delay of the first data stream from the channel alignment circuit 12 to the FIFO circuit 16 can be determined.
  • the default value or Design value the first circuit may also be the FIFO circuit 13
  • the second circuit may also be the FIFO circuit 16, etc.
  • the transmission delay of the FIFO circuit 13 to the FIFO circuit 16 is similarly, for the delay of other circuits, the default value or the designed value can be used.
  • the first circuit is the channel alignment circuit 12
  • the second circuit is the DAC 17, and both the first indicator signal and the second indicator signal are AM indicator signals.
  • Fig. 7 is a schematic diagram of the structure of the oDSP chip in the gray light optical module.
  • Serdes11 and DAC 17, or Serdes18 and ADC 24 mainly realize the conversion between serial data and parallel data
  • the first optical module After each power-on and the link status is stable, the delays of Serdes11 and DAC17, or Serdes18 and ADC24 are relatively fixed, and will not be affected by factors such as plugging and unplugging optical fibers, plugging and unplugging modules.
  • Serdes11 and DAC17, or The delays corresponding to Serdes18 and ADC 24 can be preset design values, or simulation values obtained through simulation, of course, it can be Is a default value.
  • mapping circuit 14 and the demapping circuit 21 mainly implement the mapping and demapping processing from multiple low-speed channels to high-speed channels. Since the mapping adopts a bit interleaving method, the structure of the first data stream and the delay of each bit of data will not be changed. Will be the same. However, under the influence of factors such as fiber insertion and removal, module insertion and removal, PVT (process, voltage, temperature, voltage, temperature) changes, etc., it will cause the phase of the read and write clocks of the synchronous processing FIFO circuits 13, 16 or FIFO circuits 20, 23 to occur The change makes the delay of each level of FIFO circuit not fixed, which introduces delay asymmetry.
  • PVT process, voltage, temperature, voltage, temperature
  • the description is made by taking an example that the first indicator signal and the second indicator signal are AM indicator signals.
  • the first data stream reaches the channel alignment circuit 12 through multiple channels.
  • the channel selection module 55 will transfer the data from the multiple channels.
  • One of the channels is selected, the AM indicator signal 1 carried in the first data stream is detected from the selected channel, and the detected AM indicator signal 1 is sent to the TX delay measurement module 56.
  • the AM indicator signal needs to be identified, and the identified AM indicator signal will be carried in the first data stream for transmission.
  • the AM extraction module 53 When it is detected that the first data stream is output from the FIFO circuit 16, that is, after it is transmitted to the DAC 17, the AM extraction module 53 will extract the AM indication carried in the first data stream from the channel for detecting the AM indication signal 1 according to the aforementioned identifier. Signal 2 and send the detected AM indicator signal 2 to the TX delay measurement module 56.
  • the TX delay measurement module 56 measures the phase difference between the AM indicator signal 1 and the AM indicator signal 2 by adopting a high-precision phase discrimination algorithm, so as to determine the delay of the first data stream in the path B.
  • the measurement accuracy depends on the accuracy of the phase detection algorithm. Under normal circumstances, the accuracy of the measured time delay can reach a hundred ps level.
  • AM indicator signal 1 and AM indicator signal 2 are the same AM indicator signal.
  • the first data stream can be selected to arrive at the channel at the latest Align the channel of the module to extract the AM indicator signal.
  • the transmission delay of the first data stream in the optical receiver of the optical module of the first optical module may be a value obtained by adding the respective delays of path D, path E, and path F.
  • the delays of path D and path F are similar to the delays of path C and path A in the optical transmitter, which can be a preset design value or a simulated value obtained through simulation, of course, it can also be A default value.
  • the delay of path E is similar to the determination of the delay of path B in the sending direction, that is, when the first data stream is transmitted to the first circuit, the AM detection module 54 extracts the AM indication signal 3 carried by the first data stream, And when the first data stream is transmitted to the second circuit, the AM extraction module extracts the AM indicator signal 4 carried by the first data stream, and the RX delay measurement module 57 measures the phase difference between the AM indicator signal 3 and the AM indicator signal 4, namely The time delay of path E can be determined.
  • the first circuit may be a FIFO circuit
  • the second circuit may be a serial/parallel circuit 18.
  • the channel selection process and the AM indicator signal extraction process please refer to the description in the optical transmitter, which will not be repeated here.
  • the delay of path B and path E can also be preset design values, or The simulation value obtained through simulation, of course, may also be a default value.
  • the preset design value, simulation value or default value will be changed. Not precise enough.
  • the first optical module is a color light optical module
  • the color light optical module has overhead processing circuits such as a framer (Framer) and FEC
  • the overhead processing will change the structure of the original data stream, resulting in
  • the processing delay of each bit of data in the process of adding overhead (transmitting end) and deleting overhead (receiving end) is different. Since every bit of data received by the first optical module may be a PTP packet stamping signal, this non-fixed delay makes it impossible to measure the delay when the first optical module is used as the transmitter alone, or the first optical module is used as The delay at the receiving end.
  • the delay change introduced by the data mapping at the transmitting end and the delay change introduced by the data demapping at the receiving end are opposite processes, that is, the same bit of data is processed at the transmitting end and the receiving end.
  • the sum of the extension is fixed.
  • the first optical module and the second optical module may be paired to measure the delay.
  • the first optical module is the color light optical module in the first network device
  • the second optical module is the color light optical module in the second network device
  • the first optical module includes an optical transmitter and a first optical receiver.
  • An optical module receives the first data stream through the optical transmitter, where the transmission delay of the first data stream in the optical transmitter is the second delay, and then the first optical module transmits the first data stream to the second network device through the optical transmitter.
  • the second optical receiver of the second optical module sends the first data stream, and the transmission delay of the first data stream in the second optical receiver is the third delay; where the second delay and the third delay The sum obtained by the addition is the aforementioned first delay; the first optical module receives the second data stream sent by the second network device through the first optical receiver, and the second data stream carries indication information; correspondingly, the first optical module The module determines the first time delay, which can be determined according to the indication information carried in the second data stream.
  • FIG. 8 is a schematic diagram of the structure of the oDSP chip in the color light optical module.
  • the first optical module 67 is the color light optical module in the first network device, and the first optical module includes the optical transmitter 210 and the optical module.
  • the receiver 220 wherein, after the first optical module 67 receives the first data stream through the optical transmitter 210, it will send to the second optical receiver 230 of the second optical module 96 in the second network device through the optical transmitter 210 The first data stream.
  • the second delay of the first data stream transmitted in the optical transmitter 210 of the first optical module 67 and the second optical reception of the first data stream in the second optical module 96 can be measured.
  • the second optical module 96 includes an optical transmitter 240 and an optical receiver 230.
  • the optical transmitter 240 includes an oDSP chip 97 and ITLA 82
  • the optical receiver 230 includes an oDSP chip 95 and a dual filter switch. 70.
  • the ITLA 82 and the double filter switch 70 are connected to optical fibers.
  • the oDSP chip 97 includes serializing/deserializing circuits (Serializing/deserializing circuitry; Serial) 93, a channel alignment circuit 91, a FIFO circuit 90, a mapping circuit 89, a FIFO circuit 88, and a forward error correction FEC circuit 87, which are sequentially connected. , DSP circuit 86, FIFO circuit 85 and DAC 83.
  • oDSP chip 95 includes ADC 71, FIFO circuit 73, DSP circuit 74, FEC circuit 75, FIFO circuit 76, demapping circuit 77, FIFO circuit 78, channel distribution circuit 79, and serial/parallel circuit (Serdes) connected in sequence. 81.
  • mapping circuit 89 may be implemented by a framer (Framer) or a bit interleaving (BitMux) circuit.
  • demapping circuit 77 can be implemented by a deframer (DeFramer) or a bit deinterleaving (BitDeMux) circuit.
  • the above-mentioned second time delay can be caused by different processing circuits in the transmitter 210 when processing the first data stream.
  • the optical receiver 230 in the second optical module also includes different processing circuits. Therefore, the aforementioned third time delay may be caused by different processing circuits in the optical receiver 230 in the process of processing the first data stream. Time delay.
  • the foregoing second delay may be the delay of the first data stream being transmitted from the inbound interface of the optical transmitter 210 to the outbound interface of the optical transmitter 210, or may be the delay included in the optical transmitter 210
  • the time delay caused by at least one processing circuit processing the first data stream can also be the time delay caused by at least one processing circuit included in the optical transmitter 210 when processing the first data stream.
  • the second delay may be the delay of the first data stream being transmitted from the serial/parallel circuit 31 to the TOSA module 49, or it may be the processing circuit in the oDSP chip 190 processing the first data stream.
  • the delay caused by time can also be the channel alignment circuit 32, FIFO circuit 33, mapping circuit 34, FIFO circuit 35, FEC circuit 36, DSP circuit 37, and FIFO circuit 38 in the oDSP chip 190 for processing the first data stream.
  • the time delay caused by the time is the sum of the default value or the design value.
  • the above-mentioned third delay may be the delay of the first data stream being transmitted from the inbound interface of the second optical receiver 230 to the outbound interface of the second optical receiver 230, or may be at least one included in the second optical receiver 230
  • the delay caused by the processing circuit when processing the first data stream can also be the delay caused by at least one processing circuit included in the second optical receiver 230 when processing the first data stream.
  • the third time delay may be the time delay of the first data stream being transmitted from the dual filter switch 70 to the serial/parallel circuit 81, or it may be the time delay of each processing circuit in the oDSP chip 95 in the first data stream.
  • the time delay caused by the data stream processing can also be the DAC71, FIFO circuit 73, DSP circuit 74, FEC circuit 75, FIFO circuit 76, demapping circuit 77, FIFO circuit 78 and channel distribution circuit 79 in the oDSP chip 95.
  • the time delay caused when processing the first data stream is the sum obtained by adding the default value or the design value.
  • the first optical module when the first data stream is transmitted in the first optical module, when the first data stream is transmitted to the first circuit, the first optical module extracts the first indication signal carried in the first data stream, and sends it to the first data stream.
  • the second indication signal carried in the first data stream is extracted, and then according to the first indication signal and the second indication signal, it can be determined that the first data stream is in the first optical module 67 by the optical transmitter 210 The second delay in the transmission.
  • the second optical module extracts the third indication signal carried in the first data stream when the first data stream is transmitted to the third circuit, and sends it to the first data stream.
  • the fourth indicator signal carried in the first data stream is extracted, and then according to the third indicator signal and the fourth indicator signal, it can be determined that the first data stream receives the second light in the second optical module 96
  • the third time delay transmitted in the device 230 is transmitted.
  • the first circuit and the second circuit can be any two different circuits in the oDSP chip 190.
  • the first circuit can be the channel alignment circuit 32 shown in FIG. 8 and the second circuit can be the FIFO circuit 38.
  • the transmission delay of the first data stream from the channel alignment circuit 32 to the FIFO circuit 38 can be determined.
  • the default value can be used.
  • the first circuit may also be the FIFO circuit 33, the second circuit may also be the FIFO circuit 38, etc.
  • the first data stream is from The transmission delay of the FIFO circuit 33 to the FIFO circuit 38.
  • a default value or a design value can be used for the delay of other circuits.
  • the third circuit and the fourth circuit can be any two different circuits in the oDSP chip 95.
  • the third circuit can be the FIFO circuit 73 shown in FIG. 8, and the fourth circuit can be a serial/parallel circuit. 81.
  • the delay of the first data stream from the FIFO circuit 73 to the serial/parallel circuit 81 can be determined. , You can use the default value or design value.
  • the third circuit may also be a signal processing circuit 74, and the fourth circuit may also be a serial/parallel circuit 81, etc.
  • the first indicator signal can be determined The delay of a data stream from the signal processing circuit 74 to the serial/parallel circuit 81. Similarly, for the delay of other circuits, a default value or a design value can be used.
  • the delays of the path A1 and the path C1 in the first optical module 67, and the second optical module 67 are similar to those of Serdes11 and DAC17, or Serdes18 and ADC 24 in gray optical modules. They can be preset design values or can be obtained through simulation. The simulation value of, of course, can also be a default value.
  • the first circuit is the channel alignment circuit 32
  • the second circuit is the DAC 39
  • the first indicator signal is the AM indicator signal
  • the second indicator signal is the DSP frame header indicator signal. Examples are explained.
  • the first data stream reaches the channel alignment circuit 32 in the first optical module 67 through multiple channels.
  • the channel selection module 64 will select one of the multiple channels.
  • the AM detection module 60 detects the AM indicator signal 1 carried in the first data stream from the selected channel, and will The detected AM indicator signal 1 is sent to the TX delay measurement module 65.
  • the AM indicator signal needs to be identified.
  • the identified AM indicator signal will be carried in the first Transmission continues in the data stream.
  • the outgoing interface of the optical transmitter 210 of the first optical module 67 will periodically extract the DSP frame header indication signal 1.
  • the DSP frame header extraction module 61 will extract the first data.
  • the DSP frame header indicator signal 1 carried in the stream, and the extracted DSP frame header indicator signal 1 is sent to the TX delay measurement module 65.
  • the TX delay measurement module 65 uses a high-precision phase detection algorithm to measure AM
  • the phase difference between the indicator signal 1 and the DSP frame header indicator signal 1 can determine the time delay of the first data stream in the path B1.
  • the measurement accuracy depends on the accuracy of the phase detection algorithm. Under normal circumstances, the accuracy of the measured time delay can reach a hundred ps level.
  • the AM indicator needs to be The signal and DSP frame header indicate that two adjacent signals are selected for measurement. For example, if the period of the AM indicator signal is 3ms and the period of the DSP frame header indicator signal is 1.2ms, it is possible that only one AM indicator signal will appear in the first data stream after two DSP frame header indicator signals appear. At this time, you can select the AM indicator signal and the DSP frame header indicator signal adjacent to the AM indicator signal for measurement. For example, you can select the AM indicator signal and the second DSP frame header indicator signal, and measure one of these two signals. The phase difference between.
  • the third circuit is the FIFO circuit 73
  • the fourth circuit is the serial/parallel circuit 81
  • the third indicator signal is the DSP frame header indicator signal
  • the fourth indicator signal is AM
  • the indication signal is described as an example. As shown in FIG.
  • the first data stream passes through the ADC in the second optical module 96 71, and transmitted to the FIFO circuit 73, according to the identification information added to the DSP frame header indicator signal in the optical transmitter 210 of the first optical module 67, the DSP frame header indicator signal 2 is extracted through the DSP frame header pre-detection module 72 , And send the extracted DSP frame header indication signal 2 to the RX delay measurement module 94. At this time, the first data stream will continue to be transmitted.
  • the AM extraction module 80 After detecting that the first data stream is transmitted to the serial/parallel circuit 81, the AM extraction module 80 will use the AM extraction module 80 according to the optical transmitter 210 of the first optical module 67.
  • the added identification information extracts the AM indicator signal 2 carried in the first data stream from the channel, and sends the extracted AM indicator signal 2 to the RX delay measurement module 94.
  • the RX delay measurement module 94 adopts high
  • the accurate phase detection algorithm measures the phase difference between the DSP frame header indicator signal 2 and the AM indicator signal 2 to determine the time delay of the first data stream in the path E2. Among them, the measurement accuracy depends on the accuracy of the phase detection algorithm. Under normal circumstances, the accuracy of the measured time delay can reach a hundred ps level.
  • the aforementioned AM indicator signal 1 and AM indicator signal 2 are the same AM indicator signal
  • the DSP frame header indicator signal 1 and the DSP frame header indicator signal 2 are the same indicator signal.
  • the second indication information and the fourth indication information may also use other data identifiers that are easy to identify, such as inserting an identifier into the first data stream.
  • the second indication information and the fourth indication information this The application examples are not limited here.
  • the first optical module after determining the second delay of the first data stream in the optical transmitter 210, the first optical module will carry the second delay in the first data stream and send it to the second optical module.
  • the second optical module determines the third delay of the first data stream in the second receiver 230, the sum obtained by adding the second delay and the third delay , Determined as the first delay.
  • the second optical receiver 230 of the second optical module sends the second data stream to the first optical receiver 220 of the first optical module 67 after determining the first time delay.
  • the second data stream carries indication information, so that the first optical module can determine the first delay according to the indication information.
  • the indication information includes the first time delay. After the first optical module 67 receives the indication information in the second data stream through the first optical receiver 220, it can directly determine The first delay.
  • the delay of path B1 and path E2 can also be preset design values. Or the simulation value obtained through simulation, of course, it can also be a default value.
  • the first delay may be that the first data stream is in the second
  • the transmission delay of the optical transmitter 240 of the optical module 96 is the sum of the transmission delay of the first data stream in the first optical receiver 220 of the first optical module 67.
  • the transmission delay of the first data stream at the optical transmitter 240 of the second optical module 96 is the sum of the corresponding delays of path A2, path B2, and path C2, and the first data stream at the first optical module 67
  • the time delay in the first optical receiver 220 is the sum of the respective delays corresponding to the path D1, the path E1, and the path F1.
  • the respective delays of path A2, path C2, path D1, and path F1 are similar to the aforementioned delays of path A1, path C1, path D2, and path F2, and can be preset design values or pass through
  • the simulated value obtained by the simulation can also be a default value.
  • the time delay of the path B2 in the optical transmitter 240 of the second optical module 96 and the path E1 in the first optical receiver 220 of the first optical module 67 is the same as that of the aforementioned optical transmitter 210 of the first optical module 67.
  • the path B1 of the second optical module 96 and the path E2 of the second optical receiver 230 of the second optical module 96 are determined in a similar manner for determining the delay, which will not be repeated here.
  • Step 202 The first optical module sends a first delay to the interface chip.
  • the first optical module since the first optical module defines the delay reporting register access interface, after determining the first delay, the first optical module will report to the register access interface through the delay reporting register of the first optical module.
  • the interface chip sends the first time delay so that the interface chip compensates the first time delay to the recording time stamp.
  • the time stamp recorded by the MDI layer includes the time delay of the message transmission in the optical module, so that the MDI The time stamp recorded by the layer is more accurate, which can make the master-slave clock time synchronization accuracy higher, thereby further improving the clock accuracy of the network device.
  • the interface chip includes at least one of a PHY chip and a MAC chip.
  • the delay reporting register access interface of the first optical module can be defined in the manner in the following table:
  • the interface bit width is used to indicate the number of bits of the interface signal.
  • the reported value of the delay reporting register access interface is a fixed value of 0.
  • Optical modules that support delay reporting can be divided into two types: optical modules that do not support delay measurement and optical modules that support delay measurement.
  • the first reported delay is It is the design value of the oDSP chip.
  • the first delay reported is the measured value obtained through the indication information.
  • the first optical module is a gray optical module
  • the interface chip can compensate the first delay and the delay of the message transmission in the MAC layer or PHY layer to the time stamp recorded by the MAC layer or PHY layer.
  • the asymmetry error introduced by the optical module is reduced, and the time stamp recorded by the MDI layer is more accurate, which can make the master-slave clock time synchronization accuracy higher, thereby further improving the clock accuracy of the network device. .
  • the first delay is the delay of the transmission of the first data stream in the optical transmitter of the first optical module and the second optical reception of the first data stream in the second optical module The sum of the transmission delays in the device.
  • the first optical module can report the register through the delay defined in the first optical module The access interface reports the first delay to the interface chip.
  • the second optical module can report the first delay to the interface chip through the delay report register access interface defined in the second optical module, or report 0 or report a special identifier.
  • the second optical module can also report the first delay. None can be reported.
  • the first optical module can pass through the first optical module.
  • the delay reporting register access interface defined in the interface chip reports the first delay to the interface chip. It can also report 0 or report a special identifier. Of course, the first optical module can also report nothing.
  • the first optical module and the second optical module may divide the first delay into two parts according to a preset rule, where the first part is defined by the first optical module through the first optical module
  • the delay reporting register access interface reports to the interface chip, and the second part is reported by the second optical module to the interface chip through the delay reporting register access interface defined in the second optical module.
  • the first optical module after determining the first delay, sends the determined first delay to the interface chip. Since the delay reporting register access interface is defined in the first optical module, the first optical module can report the first delay to the MAC layer or the PHY layer through the delay reporting register access interface, so that the first delay It is compensated to the time stamp of the message recorded by the MAC layer or the PHY layer, thereby improving the accuracy of time synchronization between the master and slave clocks, thereby further improving the clock accuracy of the network device.
  • the optical module provided in the embodiment of the present application is used as the first optical module and can be used to perform actions related to the first optical module in the foregoing method embodiment.
  • the optical module includes a processor 101.
  • the processor 101 is configured to determine the first time delay
  • the processor 101 is further configured to send the first delay to the interface chip.
  • the optical module After the optical module provided in the embodiment of the present application determines the first delay, it will send the determined first delay to the interface chip. Since the delay reporting register access interface is defined in the optical module, the optical module can report the first delay to the MAC layer or the PHY layer through the delay reporting register access interface, and the first delay can be compensated to the MAC layer Or in the time stamp of the message recorded by the PHY layer, which can improve the accuracy of master-slave clock time synchronization, thereby further improving the clock accuracy of the network device.
  • FIG. 9 is a schematic structural diagram of an optical module provided by an embodiment of the application.
  • the first optical module 10 is a gray light optical module, and the first optical module 10 includes: an optical transmitter 102.
  • the transmitter 102 includes the processor 101, an inbound interface 1021, and an outbound interface 1022, where:
  • the optical transmitter 102 is configured to receive the first data stream through the inbound interface 1021;
  • the optical transmitter 102 is further configured to send the first data stream to a second network device through the outgoing interface 1022;
  • the processor 101 is further configured to determine that the transmission delay of the first data stream in the optical transmitter 102 is the first delay.
  • FIG. 10 is a schematic structural diagram of another optical module provided by an embodiment of the application.
  • the first optical module 20 is a color light optical module in a first network device, and the first optical module 20 includes: The transmitter 103 and the first optical receiver 104, the first optical receiver 104 includes the processor 101, wherein:
  • the optical transmitter 103 is configured to receive a first data stream, and the transmission delay of the first data stream in the optical transmitter 103 is a second delay;
  • the optical transmitter 103 is also configured to send the first data stream to the second optical receiver of the second optical module in the second network device, and the first data stream is in the second optical receiver.
  • the transmission delay in the middle is the third delay;
  • the sum obtained by adding the second delay and the third delay is the first delay
  • the first optical receiver 104 is configured to receive a second data stream sent by the second network device, where the second data stream carries indication information;
  • the processor 101 is specifically configured to determine the first delay according to the instruction information.
  • the indication information includes the first time delay.
  • the first delay is a design value.
  • FIG. 11 is a schematic structural diagram of another optical module provided by an embodiment of this application.
  • the optical transmitter 103 includes a first circuit 1031 and a second circuit 1302,
  • the processor 101 is further configured to:
  • the processor 101 is further configured to:
  • the first indication signal and the second indication signal are both alignment mark AM indication signals, or the first indication signal is an AM indication signal, and the second indication signal is a digital signal processing DSP frame header signal .
  • the interface chip includes at least one of a physical layer PHY chip and a media access control layer MAC chip.
  • the aforementioned processor 101 may be one or more integrated circuits configured to implement the above methods, such as: oDSP, or, one or more application specific integrated circuits (ASIC), or, one or Multiple microprocessors (digital singnal processors, DSP), or, one or more field programmable gate arrays (FPGA), etc.
  • the processor may also be a central processing unit (CPU) or other processors that can call programs.
  • optical module provided in the embodiment of the present application can execute the above-mentioned corresponding method embodiment, and its implementation principles and technical effects are similar, and will not be repeated here.
  • An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, it can implement the process related to the first optical module in the communication method provided in the foregoing method embodiment.
  • various aspects or features of the embodiments of the present application may be implemented as methods, devices, or products using standard programming and/or engineering techniques.
  • article of manufacture used in this application encompasses a computer program that can be accessed from any computer-readable device, carrier, or medium.
  • computer-readable media may include, but are not limited to: magnetic storage devices (for example, hard disks, floppy disks, or tapes, etc.), optical disks (for example, compact discs (CD), digital versatile discs (DVD)) Etc.), smart cards and flash memory devices (for example, erasable programmable read-only memory (EPROM), cards, sticks or key drives, etc.).
  • various storage media described herein may represent one or more devices and/or other machine-readable media for storing information.
  • the term "machine-readable medium” may include, but is not limited to, wireless channels and various other media capable of storing, containing, and/or carrying instructions and/or data.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center integrated with one or more available media.
  • the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)).
  • the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic.
  • the implementation process of the embodiment constitutes any limitation.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solutions of the embodiments of the present application can be embodied in the form of software products in essence or parts that contribute to the prior art or parts of the technical solutions, and the computer software products are stored in a storage medium , Including several instructions to enable a computer device (which may be a personal computer, a server, or an access network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code .

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Optical Communication System (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
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MX2021008729A MX2021008729A (es) 2019-01-22 2019-12-30 Metodo de comunicacion y modulo optico.
EP19911499.2A EP3902165A4 (en) 2019-01-22 2019-12-30 Communication method and optical module
US17/368,986 US11876884B2 (en) 2019-01-22 2021-07-07 Communication method and optical module
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CN111464252B (zh) 2023-01-06
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US20210336762A1 (en) 2021-10-28
CN115913442A (zh) 2023-04-04
CN115913442B (zh) 2025-10-31
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