WO2020151458A1 - 通信方法和光模块 - Google Patents

通信方法和光模块 Download PDF

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Publication number
WO2020151458A1
WO2020151458A1 PCT/CN2019/129697 CN2019129697W WO2020151458A1 WO 2020151458 A1 WO2020151458 A1 WO 2020151458A1 CN 2019129697 W CN2019129697 W CN 2019129697W WO 2020151458 A1 WO2020151458 A1 WO 2020151458A1
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Prior art keywords
delay
optical module
optical
data stream
circuit
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PCT/CN2019/129697
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English (en)
French (fr)
Inventor
祁云磊
李春荣
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华为技术有限公司
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Priority to MX2021008729A priority Critical patent/MX2021008729A/es
Priority to EP19911499.2A priority patent/EP3902165A4/en
Priority to JP2021542439A priority patent/JP7482884B2/ja
Publication of WO2020151458A1 publication Critical patent/WO2020151458A1/zh
Priority to US17/368,986 priority patent/US11876884B2/en
Priority to JP2023115753A priority patent/JP2023130494A/ja

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0075—Arrangements for synchronising receiver with transmitter with photonic or optical means
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/66—Non-coherent receivers, e.g. using direct detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/40—Transceivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0691—Synchronisation in a TDM node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697—Synchronisation in a packet node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H04Q2011/0037—Operation
    • H04Q2011/0045—Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1336—Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/36—Synchronisation

Definitions

  • the embodiments of the present application relate to the field of communication technologies, and in particular, to a communication method and an optical module.
  • base stations based on the Time Division Duplex (TDD) system need to meet strict time synchronization requirements, otherwise the wireless signals sent by the base station will interfere with other base stations, causing base stations in adjacent areas to fail to work normally .
  • TDD Time Division Duplex
  • time synchronization between different base stations can be achieved through clock protocols.
  • IEEE Institute of Electrical and Electronics Engineers
  • 1588V2 protocol is a precision clock synchronization protocol standard for network measurement and control systems.
  • the 1588V2 protocol is also called Precision Time Protocol (PTP). Realize the time synchronization of multiple network devices, and the accuracy can reach the microsecond level.
  • PTP Precision Time Protocol
  • the master-slave clock method is adopted.
  • the master-slave time is realized through the two-way interaction of message messages by encoding time information, using network symmetry and delay measurement technology Synchronization. Specifically, the master and slave clocks respectively stamp the message when sending and receiving a message, thereby calculating the time difference between the master and slave clocks, and the slave clock calibrates the local time according to the calculated time difference.
  • the embodiments of the present application provide a communication method and an optical module, which can report the delay of the optical module to an interface chip, so as to improve the accuracy of time synchronization between the master and slave clocks, thereby further improving the clock accuracy of the network device.
  • the first aspect of this application provides a communication method, including:
  • the first optical module determines the first time delay
  • the first optical module sends the first delay to the interface chip.
  • the first optical module can report the first delay to the interface chip through the delay reporting register access interface, so that the second optical module can report the first delay to the interface chip.
  • a time delay is compensated to the time stamp of the message recorded by the interface chip to improve the accuracy of time synchronization between the master and slave clocks, thereby further improving the clock accuracy of the network device.
  • the first optical module is a gray optical module
  • the first optical module includes an optical transmitter
  • the optical transmitter includes an input interface and an output interface
  • the first optical module determines the first time Extension, including:
  • the first optical module receives the first data stream through the ingress interface
  • the first optical module sends the first data stream to the second network device through the outgoing interface
  • the first optical module determines that the transmission delay of the first data stream in the optical transmitter is the first delay.
  • the first delay may be the delay of the first data stream being transmitted in the optical transmitter in the first optical module.
  • the above-mentioned first delay may also be the delay caused by different processing circuits in the optical transmitter when processing the first data stream.
  • the above-mentioned first delay may be the delay of the first data stream being transmitted from the inbound interface of the optical transmitter to the outbound interface of the optical transmitter, or it may be the delay of at least one processing circuit included in the optical transmitter on the first data stream.
  • the delay caused by the processing of the data stream can also be the delay caused by the processing of the first data stream by at least one processing circuit included in the optical transmitter plus the default value or the design value The sum.
  • the first optical module is a color light optical module in a first network device, and the first optical module includes an optical transmitter and a first optical receiver;
  • the method further includes:
  • the first optical module receives a first data stream through the optical transmitter, and the transmission delay of the first data stream in the optical transmitter is a second delay;
  • the first optical module sends the first data stream to the second optical receiver of the second optical module in the second network device through the optical transmitter.
  • the first data stream is transmitted in the second optical receiver Delay for the third time delay;
  • the sum of the second delay and the third delay is the first delay
  • the first optical module receives a second data stream sent by the second network device through the first optical receiver, and the second data stream carries indication information;
  • the determining of the first time delay by the first optical module includes:
  • the first optical module determines the first delay according to the instruction information.
  • the first optical module is the color light optical module in the first network device
  • the second optical module is the color light optical module in the second network device.
  • the first optical module includes an optical transmitter and a first optical receiver. After the first optical module receives the first data stream through the optical transmitter, it transmits the optical transmitter to the second optical module in the second network device. The second optical receiver sends the first data stream. In this way, according to the first data stream, the second delay of the transmission of the first data stream in the first optical module and the third delay of the transmission in the second optical module can be measured.
  • the second delay is carried in the first data stream and sent to the second optical module.
  • the optical module determines the third delay of the first data stream in the second optical module, the sum obtained by adding the second delay and the third delay is determined as the first delay.
  • the second optical module sends a second data stream to the first optical module.
  • the second data stream carries indication information. In this way, the first optical module can determine the first optical module according to the indication information. A time delay.
  • the indication information includes the first delay.
  • the first delay is a design value.
  • the above-mentioned first time delay can be a preset design value, or a simulation value obtained through simulation, of course, it can also be a Defaults.
  • the method further includes:
  • the first optical module extracts the first indication signal carried in the first data stream when the first data stream is transmitted to the first circuit
  • the first optical module extracts the second indication signal carried in the first data stream when the first data stream is transmitted to the second circuit
  • the first optical module determines the first time delay according to the first indication signal and the second indication signal.
  • the determining the first time delay according to the first indication signal and the second indication signal includes:
  • both the first indication signal and the second indication signal may be alignment mark AM indication signals, or the first indication signal may be an AM indication signal, and the second indication signal may be a digital signal processing DSP frame header signal.
  • the first indication signal carried in the first data stream is extracted, and when the first data stream is transmitted to the second circuit, the first indication signal carried in the first data stream is extracted The second indication signal. Then, by measuring the phase difference between the first indicator signal and the second indicator signal through a high-precision phase detection algorithm, the first time delay can be determined, which can improve the accuracy of the determined time delay.
  • first circuit and the second circuit may be any two different circuits in the first optical module.
  • first indicator signal and the second indicator signal may be an AM indicator signal, or the first indicator signal is an AM indicator signal, and the second indicator signal is a digital signal processing DSP frame header signal.
  • first indication signal and second indication signal may also be other signals that are convenient for identification, such as an identifier inserted in the first data stream.
  • the interface chip includes at least one of a physical layer PHY chip and a media access control layer MAC chip.
  • a second aspect of the present application provides an optical module used as a first optical module, including:
  • the processor is also used to send the first delay to the interface chip.
  • the first optical module is a gray light optical module
  • the first optical module includes an optical transmitter
  • the optical transmitter includes the processor, an inbound interface, and an outbound interface, wherein:
  • the optical transmitter is used to receive the first data stream through the inbound interface
  • the optical transmitter is also used to send the first data stream to the second network device through the outgoing interface
  • the processor is further configured to determine that the transmission delay of the first data stream in the optical transmitter is the first delay.
  • the first optical module is a colored light optical module in a first network device, the first optical module includes an optical transmitter and a first optical receiver, and the first optical receiver includes the processor;
  • the optical transmitter is configured to receive a first data stream, and the transmission delay of the first data stream in the optical transmitter is a second delay;
  • the optical transmitter is also used to send the first data stream to the second optical receiver of the second optical module in the second network device.
  • the transmission delay of the first data stream in the second optical receiver Is the third time delay;
  • the sum of the second delay and the third delay is the first delay
  • the first optical receiver is configured to receive a second data stream sent by the second network device, where the second data stream carries indication information;
  • the processor is specifically configured to determine the first delay according to the instruction information.
  • the indication information includes the first delay.
  • the first delay is a design value.
  • the optical transmitter includes a first circuit and a second circuit; the processor is further used for:
  • the first time delay is determined according to the first indication signal and the second indication signal.
  • the processor is also used for:
  • first indicator signal and the second indicator signal are both alignment mark AM indicator signals, or the first indicator signal is an AM indicator signal, and the second indicator signal is a digital signal processing DSP frame header signal.
  • the interface chip includes at least one of a physical layer PHY chip and a media access control layer MAC chip.
  • the first optical module determines the first delay, it will send the determined first delay to the interface chip. Since the delay reporting register access interface is defined in the first optical module, the first optical module can report the first delay to the interface chip through the delay reporting register access interface to compensate the first delay to the MAC In the time stamp of the message recorded by the layer or the PHY layer, the accuracy of time synchronization between the master and slave clocks can be improved, and the clock accuracy of the network device can be further improved.
  • FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the application
  • Figure 2 is a schematic diagram of calculating the time difference between the master and slave clocks
  • FIG. 3 is a schematic flowchart of a communication method provided by an embodiment of this application.
  • Figure 4 is a schematic diagram of the composition of an optical module
  • Figure 5 is a schematic diagram of the structure of a gray light optical module
  • Fig. 6 is a schematic diagram of the structure of the color light optical module
  • Figure 7 is a schematic diagram of the structure of the oDSP chip in the gray light optical module
  • Figure 8 is a schematic diagram of the structure of the oDSP chip in the color light optical module
  • FIG. 9 is a schematic structural diagram of an optical module provided by an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of another optical module provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of yet another optical module provided by an embodiment of the application.
  • Optical module mainly composed of photoelectric conversion devices and electrical signal processing devices.
  • the optical module includes two parts: an optical transmitter and an optical receiver.
  • the electrical signal processing device includes a clock and data recovery (clock and data recovery; CDR) chip or an optical digital signal processing (optical digital signal processing; oDSP) chip.
  • Optical modules usually perform photoelectric conversion and/or electro-optical conversion. For example, the optical module at the transmitting end converts the electrical signal into an optical signal, and after the converted optical signal is transmitted to the optical module at the receiving end through an optical fiber, the optical module at the receiving end then converts the optical signal into an electrical signal to compare the converted electrical signal. Signal processing.
  • Network equipment which can be equipment used to communicate with mobile devices.
  • Network equipment can be routers, switches, packet transport network (PTN) equipment, optical transport network (OTN) equipment, passive Optical network (passive optical network; PON) equipment or synchronous digital hierarchy (synchronous digital hierarchy; SDH) equipment, etc.
  • PTN packet transport network
  • OTN optical transport network
  • PON passive Optical network
  • synchronous digital hierarchy synchronous digital hierarchy; SDH
  • AP access points
  • base transceiver stations in GSM or CDMA , BTS base transceiver stations
  • BTS base transceiver stations
  • AP access points
  • base transceiver stations in GSM or CDMA , BTS
  • AP access points
  • base transceiver stations in GSM or CDMA , BTS
  • AP access points
  • base transceiver stations in GSM or CDMA , BTS
  • AP access points
  • base transceiver stations in GSM or CDMA , BTS
  • AP access points
  • the delay report register access interface which can also be called the register access interface or the delay report interface. It is used to report the transmission delay of the message in the optical transmitter or optical receiver of the first optical module to the interface chip, or is used to report the message to the interface chip in the optical transmitter of the first optical module, and the message The transmission delay in the optical receiver of the second optical module.
  • At least one can refer to one or more, and “multiple” refers to two or more.
  • “And/or” describes the association relationship of the associated object, indicating that there can be three relationships, for example, A and/or B, which can mean: A alone exists, both A and B exist, and B exists alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the associated objects are in an "or” relationship.
  • "The following at least one item (a)” or similar expressions refers to any combination of these items, including any combination of a single item (a) or a plurality of items (a).
  • At least one item (a) of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple .
  • the range described as “above” or “below” includes boundary points.
  • the unit in this application refers to a functional unit or a logical unit. It can be in the form of software, and its function is realized by the processor executing the program code; it can also be in the form of hardware.
  • the communication method provided in the embodiments of this application can be applied to the application scenario where the optical module reports the time delay to the interface chip, where the interface chip includes a physical layer (PHY) chip and media access control At least one of the layer (media access control; MAC) chips.
  • PHY physical layer
  • MAC media access control
  • the interface chip can realize the function of PHY layer.
  • base stations based on the Time Division Duplex (TDD) system need to meet strict time synchronization requirements, otherwise the wireless signals sent by the base station will interfere with other base stations, causing base stations in adjacent areas to fail to work normally .
  • TDD Time Division Duplex
  • the 1588V2 protocol is enabled to transmit time information as an example for description.
  • other protocols can also be used to transmit time information.
  • the clock level information can be represented by synchronization status information (synchronous status message, SSM) information in the SDH protocol.
  • FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the application.
  • a time source device is usually deployed at the core layer of the wireless network, and satellite time is received through the Global Positioning System (GPS) or Beidou As a reference source, it then transmits time information to the transmission device 101 through external time auxiliary interfaces such as pulse per second and time of day (1Pulse per Second and Time of Day; 1PPS+TOD) or PTP interface (Ethernet interface with 1588V2 protocol enabled),
  • the transmission device 101 hops down from the core layer through the PTP interface, passing time information to the convergence layer device 102, and the convergence layer device 102 hops down again, passing the time information to the access layer device 103, and the access layer device 103
  • the time information is transmitted to the connected base station 104 through the external time auxiliary interface such as 1PPS+TOD or the PTP interface, so as to realize the time synchronization of the base stations of the whole network.
  • the transmission device 101, the convergence layer device 102, and the access layer device 103 may be network devices such as routers, switches, PTN devices, OTN devices, or PON devices.
  • the transmission device 101, the convergence layer device 102, and the access layer device 103 may also perform time synchronization through the solution described in the embodiment of the present application.
  • the 1588V2 protocol also referred to as PTP, is a precise time synchronization protocol that can synchronize the time of multiple network devices.
  • the core idea is to use the master-slave clock mode to encode time information, use the symmetry of the network and delay measurement technology to realize master-slave time synchronization through the two-way interaction of messages.
  • the master and slave clocks respectively stamp the message when sending and receiving a message, thereby calculating the time difference between the master and slave clocks, and the slave clock calibrates the local time according to the calculated time difference.
  • Figure 2 is a schematic diagram of calculating the time difference between the master and slave clocks.
  • the master node (Master) sends a synchronization message (Sync) to the slave node (Slave), and records the sending timestamp t1 in the register. After the node (Slave) receives the synchronization message, it will record the received timestamp t2.
  • the master node (Master) sends a follow message (Follow_Up) to the slave node (Slave), and carries the timestamp t1 to the follow message.
  • the text is sent to the slave node (Slave), and the slave node (Slave) sends a delay request message (Delay_Req) to the master node (Master), where the delay request message carries a timestamp t3.
  • the master node (Master) After receiving the delay request message, the master node (Master) records the reception timestamp t4, and the master node (Master) carries t4 in the delay response message (Delay_Resp) and sends it to the slave node (Slave).
  • the clock in the master node is the master clock
  • the clock in the slave node is the slave clock.
  • the slave clock can calculate the delay and time difference (Offset) between the slave clock and the master clock according to the following formula (1) and formula (2), and the slave clock passes the delay (Delay) and time difference (Offset), the local time stamp can be calibrated to achieve synchronization between master and slave clocks.
  • the stamping reference plane of the master and slave clocks is at the physical medium-dependent interface (MDI) of the PTP port.
  • MDI physical medium-dependent interface
  • the MDI layer cannot complete the PTP message header identification, and thus the stamping cannot be completed. Therefore, in the specific implementation, the media access control (MAC) layer or the physical layer (PHY) layer is often stamped to record the time stamp of the message, and the MAC layer or PHY layer The time delay between the 1588 message stamping point and the MDI layer of the optical module is measured and compensated to the time stamp recorded in the MAC layer or the PHY layer, thereby realizing the function of stamping at the MDI layer.
  • the MDI layer of the optical module is the port of the photoelectric conversion device in the optical module.
  • the current Ethernet protocol IEEE 802.3 only defines the register interface for reporting the PHY layer delay, and uses the above message transmission delay in the PHY layer.
  • the PHY layer is jointly implemented by the interface chip and the optical module, that is, the PHY layer delay includes two parts, the PHY layer delay of the interface chip, and the PHY layer delay of the optical module.
  • the protocol only the PHY layer delay of the interface chip is reported.
  • the delay compensated in the recorded time stamp only includes the PHY layer delay of the interface chip, and the PHY layer delay of the optical module is not recorded, so that the compensated The time stamp is inaccurate, resulting in low accuracy of the master-slave clock time synchronization, resulting in low accuracy of the clock of the network device.
  • the reporting delay function of the PHY layer currently defined by the IEEE 802.3 protocol has low accuracy, which also leads to inaccurate 1588 timestamps, which results in low accuracy of network equipment clocks.
  • the reasons for the low accuracy of IEEE 802.3 report delay include several points: 1) The accuracy of the report delay is 1 ns; 2) The PHY layer includes multiple sub-layers (eg, PCS, PMA, PMD, etc.), and each sub-layer has a report delay. Accuracy will introduce a loss of 1ns, so that N sublayers report delays respectively, resulting in a total delay accuracy of N ns.
  • the embodiment of the present application takes the above problem into consideration and proposes a communication method, in which, after determining the first delay, the first optical module sends the determined first delay to the interface chip. Since the delay reporting register access interface is defined in the first optical module, the first optical module can report the first delay to the interface chip through the delay reporting register access interface, so that the message can be transmitted in the optical module. The generated time delay is compensated to the time stamp of the recorded message, so that the accuracy of time synchronization between the master and slave clocks can be improved, and the clock accuracy of the network device can be further improved.
  • FIG. 3 is a schematic flowchart of a communication method provided by an embodiment of this application. As shown in FIG. 3, the method of this embodiment may include:
  • Step 301 The first optical module determines a first delay.
  • the PTP time stamp before correction is the same as the corrected offset calculation result.
  • delay reporting and correction may not be performed. Therefore, in practical applications, it is only necessary to perform delay reporting and correction on optical modules with asymmetric delays in the receiving and transmitting directions. Therefore, before introducing how the first optical module determines the first delay, the structure of the existing optical module and the delay symmetry of the optical module are introduced first.
  • FIG. 4 is a schematic diagram of the composition of the optical module.
  • the optical module 100 includes an optical transmitter 110 and an optical receiver 120.
  • the optical module 100 can generally be divided into two parts, the "digital domain” and the “analog domain”.
  • the "digital domain” is composed of CDR or oDSP chips, which mainly implement analog and digital signal processing.
  • the "analog domain” includes the optical transmit sub-module (transmitter optical subassembly; TOSA) and the optical receive sub-module (receiver optical subassembly; ROSA), including gold fingers and printed circuits Board (printed circuit board; PCB) traces and photoelectric conversion devices are generally designed according to the symmetry of receiving and sending, and the delay of receiving and sending is relatively fixed and symmetric, which basically has no effect on the accuracy of clock synchronization. Therefore, when determining the time delay in the optical module, usually only the time delay in the "digital domain" is considered.
  • the optical module uses a CDR chip, since the CDR chip processes the data stream through a pure analog signal circuit, at this time, the transmission and reception delays in the optical module are symmetrical, so there is no need to determine and delay the delay. Reported.
  • the delay of the optical module may also be determined using the method in the embodiment of the present application, or the delay of the optical module may also be designed as a default value or a design value.
  • the oDSP chip will cause asymmetry and uncertainty in the transmission and reception delay. At this time, the delay of the message transmission in the optical module will affect the accuracy of the clock of the network device. Therefore, it is necessary to determine the delay of the message transmission in the optical module, and report the delay to the interface chip to improve the accuracy of the clock of the network device.
  • a specific example is used for description.
  • FIG. 5 is a schematic diagram of the structure of the gray light optical module.
  • the gray light optical module includes an optical transmitter 170 and an optical receiver 180.
  • the optical transmitter 170 includes an oDSP chip 130 and a TOSA 25, an optical receiver 180 includes oDSP chip 140 and ROSA 26.
  • TOSA 25 and ROSA 26 connect optical fibers.
  • the oDSP chip 130 includes serializing/deserializing circuits (Serializing/deserializing circuitry; Serial) 11, channel alignment circuit 12, first in first out (first in first out; FIFO) circuit 13, mapping circuit 14, digital A signal processing (digital signal processing; DSP) circuit 15, a FIFO circuit 16, and a digital analog converter (digital analog converter; DAC) 17.
  • oDSP chip 140 includes serial/parallel circuit (Serdes) 18, channel distribution circuit 19, FIFO circuit 20, demapping circuit 21, DSP circuit 22, FIFO circuit 23, and analog digital converter (analog digital converter) connected in sequence; ADC) 24.
  • the mapping circuit 14 may be implemented by a four-level pulse amplitude modulation (PAM4) circuit or a bit interleaving (BitMux) circuit.
  • the demapping circuit 21 can be implemented by a PAM4 circuit or a bit deinterleaving (BitDeMux) circuit.
  • the circuits in the oDSP chip 130 and the oDSP chip 140 mentioned above will cause asymmetry and uncertainty in the transmission and reception delays. About 10NS (nanosecond) delays may be introduced, which will cause the accuracy of clock synchronization between base stations to be low. , Thereby affecting the clock accuracy of network equipment. Therefore, the gray optical module determines the delay of the message transmission in the gray optical module, and reports the delay to the interface chip, which can further improve the clock accuracy of the network device.
  • FIG. 6 is a schematic diagram of the structure of the color light optical module.
  • the color light optical module includes an optical transmitter 190 and an optical receiver 200.
  • the optical transmitter 190 includes an oDSP chip 150 and an integrated adjustable laser array (integrable tunable laser assembly; ITLA) 49.
  • the optical receiver 200 includes an oDSP chip 160 and a dual filter switch 50. ITLA 49 and the dual filter switch 50 are connected to the optical fiber.
  • the oDSP chip 150 includes serializing/deserializing circuits (Serializing/deserializing circuitry; Serial) 31, channel alignment circuit 32, FIFO circuit 33, mapping circuit 34, FIFO circuit 35, and forward error correction (forward error correction) connected in sequence. correction; FEC) circuit 36, DSP circuit 37, FIFO circuit 38, and DAC 39.
  • oDSP chip 160 includes serial/parallel circuit (Serdes) 40, channel distribution circuit 41, FIFO circuit 42, demapping circuit 43, FIFO circuit 44, FEC circuit 45, DSP circuit 46, FIFO circuit 47, and ADC connected in sequence. 48.
  • mapping circuit 34 may be implemented by a framer (Framer) or a bit interleaving (BitMux) circuit.
  • demapping circuit 43 can be implemented by a deframer (DeFramer) or a bit deinterleaving (BitDeMux) circuit.
  • the oDSP chip 150 and oDSP chip 160 of the color light optical module add FEC circuits to the gray optical module, there are more uncertain factors in the transmission and reception delay, and the impact on the synchronization accuracy is about 10NS. Therefore, the above The color light optical module determines the delay of the message transmission in the color light optical module, and reports the delay to the interface chip, which can further improve the clock accuracy of the network device.
  • the following uses the gray light module and the color light module as an example for the first optical module to respectively introduce the process of determining the first delay by the first optical module.
  • the first optical module when the first optical module is a gray optical module, the first optical module includes an optical transmitter 170, and the optical transmitter 170 includes an input interface and an output interface, and the first optical module can receive the first optical module through the input interface.
  • a data stream is sent to the second network device through the outgoing interface, and the first optical module determines that the transmission delay of the first data stream in the optical transmitter is the first delay.
  • the first delay may be the delay of the first data stream being transmitted in the optical transmitter 170 in the first optical module. It can be understood that, referring to FIG. 5, since the optical transmitter 170 includes different processing Therefore, the aforementioned first delay may also be the delay caused by different processing circuits in the optical transmitter when processing the first data stream.
  • the above-mentioned first delay may be the delay of the first data stream being transmitted from the inbound interface of the optical transmitter 170 to the outbound interface of the optical transmitter 170.
  • the first delay may also be a delay caused by at least one processing circuit included in the optical transmitter 170 when processing the first data stream.
  • the first delay may also be the sum of the delay caused by at least one processing circuit included in the optical transmitter 170 when processing the first data stream and the default value or design value.
  • the first delay may be the delay of the first data stream being transmitted from the serial/parallel circuit 11 to the optical TOSA module 25, or it may be the processing circuit in the oDSP chip 130 performing the processing of the first data stream.
  • the time delay caused during processing can also be the time delay caused when the channel alignment circuit 12, FIFO circuit 13, mapping circuit 14, DSP circuit 15 and FIFO circuit 16 in the oDSP chip 130 process the first data stream. The sum obtained by adding the default value or design value.
  • the first optical module extracts the first indication signal carried in the first data stream when the first data stream is transmitted to the first circuit, and extracts the first data stream when the first data stream is transmitted to the second circuit
  • the second indication signal carried in the, and the first time delay is determined according to the first indication signal and the second indication signal.
  • the first time delay can be measured based on the alignment marker (AM) indicator signal, that is, the first indicator signal and the second indicator signal can be AM indicator signals.
  • the first indicator signal and the second indicator signal can also be other signals that are easy to identify, such as an identifier inserted in the first data stream.
  • the specific form of the signal is not limited in the embodiment of the present application, as long as the first indicator signal and the second indicator signal can be identified in the inbound interface and the outbound interface.
  • the phase difference between the first indicator signal and the second indicator signal can be measured, and the first time delay can be determined according to the above phase difference.
  • the first circuit and the second circuit can be any two different circuits in the oDSP chip.
  • the first circuit can be the channel alignment circuit 12 shown in FIG. 5, and the second circuit can be the FIFO circuit 16.
  • the transmission delay of the first data stream from the channel alignment circuit 12 to the FIFO circuit 16 can be determined.
  • the default value or Design value the first circuit may also be the FIFO circuit 13
  • the second circuit may also be the FIFO circuit 16, etc.
  • the transmission delay of the FIFO circuit 13 to the FIFO circuit 16 is similarly, for the delay of other circuits, the default value or the designed value can be used.
  • the first circuit is the channel alignment circuit 12
  • the second circuit is the DAC 17, and both the first indicator signal and the second indicator signal are AM indicator signals.
  • Fig. 7 is a schematic diagram of the structure of the oDSP chip in the gray light optical module.
  • Serdes11 and DAC 17, or Serdes18 and ADC 24 mainly realize the conversion between serial data and parallel data
  • the first optical module After each power-on and the link status is stable, the delays of Serdes11 and DAC17, or Serdes18 and ADC24 are relatively fixed, and will not be affected by factors such as plugging and unplugging optical fibers, plugging and unplugging modules.
  • Serdes11 and DAC17, or The delays corresponding to Serdes18 and ADC 24 can be preset design values, or simulation values obtained through simulation, of course, it can be Is a default value.
  • mapping circuit 14 and the demapping circuit 21 mainly implement the mapping and demapping processing from multiple low-speed channels to high-speed channels. Since the mapping adopts a bit interleaving method, the structure of the first data stream and the delay of each bit of data will not be changed. Will be the same. However, under the influence of factors such as fiber insertion and removal, module insertion and removal, PVT (process, voltage, temperature, voltage, temperature) changes, etc., it will cause the phase of the read and write clocks of the synchronous processing FIFO circuits 13, 16 or FIFO circuits 20, 23 to occur The change makes the delay of each level of FIFO circuit not fixed, which introduces delay asymmetry.
  • PVT process, voltage, temperature, voltage, temperature
  • the description is made by taking an example that the first indicator signal and the second indicator signal are AM indicator signals.
  • the first data stream reaches the channel alignment circuit 12 through multiple channels.
  • the channel selection module 55 will transfer the data from the multiple channels.
  • One of the channels is selected, the AM indicator signal 1 carried in the first data stream is detected from the selected channel, and the detected AM indicator signal 1 is sent to the TX delay measurement module 56.
  • the AM indicator signal needs to be identified, and the identified AM indicator signal will be carried in the first data stream for transmission.
  • the AM extraction module 53 When it is detected that the first data stream is output from the FIFO circuit 16, that is, after it is transmitted to the DAC 17, the AM extraction module 53 will extract the AM indication carried in the first data stream from the channel for detecting the AM indication signal 1 according to the aforementioned identifier. Signal 2 and send the detected AM indicator signal 2 to the TX delay measurement module 56.
  • the TX delay measurement module 56 measures the phase difference between the AM indicator signal 1 and the AM indicator signal 2 by adopting a high-precision phase discrimination algorithm, so as to determine the delay of the first data stream in the path B.
  • the measurement accuracy depends on the accuracy of the phase detection algorithm. Under normal circumstances, the accuracy of the measured time delay can reach a hundred ps level.
  • AM indicator signal 1 and AM indicator signal 2 are the same AM indicator signal.
  • the first data stream can be selected to arrive at the channel at the latest Align the channel of the module to extract the AM indicator signal.
  • the transmission delay of the first data stream in the optical receiver of the optical module of the first optical module may be a value obtained by adding the respective delays of path D, path E, and path F.
  • the delays of path D and path F are similar to the delays of path C and path A in the optical transmitter, which can be a preset design value or a simulated value obtained through simulation, of course, it can also be A default value.
  • the delay of path E is similar to the determination of the delay of path B in the sending direction, that is, when the first data stream is transmitted to the first circuit, the AM detection module 54 extracts the AM indication signal 3 carried by the first data stream, And when the first data stream is transmitted to the second circuit, the AM extraction module extracts the AM indicator signal 4 carried by the first data stream, and the RX delay measurement module 57 measures the phase difference between the AM indicator signal 3 and the AM indicator signal 4, namely The time delay of path E can be determined.
  • the first circuit may be a FIFO circuit
  • the second circuit may be a serial/parallel circuit 18.
  • the channel selection process and the AM indicator signal extraction process please refer to the description in the optical transmitter, which will not be repeated here.
  • the delay of path B and path E can also be preset design values, or The simulation value obtained through simulation, of course, may also be a default value.
  • the preset design value, simulation value or default value will be changed. Not precise enough.
  • the first optical module is a color light optical module
  • the color light optical module has overhead processing circuits such as a framer (Framer) and FEC
  • the overhead processing will change the structure of the original data stream, resulting in
  • the processing delay of each bit of data in the process of adding overhead (transmitting end) and deleting overhead (receiving end) is different. Since every bit of data received by the first optical module may be a PTP packet stamping signal, this non-fixed delay makes it impossible to measure the delay when the first optical module is used as the transmitter alone, or the first optical module is used as The delay at the receiving end.
  • the delay change introduced by the data mapping at the transmitting end and the delay change introduced by the data demapping at the receiving end are opposite processes, that is, the same bit of data is processed at the transmitting end and the receiving end.
  • the sum of the extension is fixed.
  • the first optical module and the second optical module may be paired to measure the delay.
  • the first optical module is the color light optical module in the first network device
  • the second optical module is the color light optical module in the second network device
  • the first optical module includes an optical transmitter and a first optical receiver.
  • An optical module receives the first data stream through the optical transmitter, where the transmission delay of the first data stream in the optical transmitter is the second delay, and then the first optical module transmits the first data stream to the second network device through the optical transmitter.
  • the second optical receiver of the second optical module sends the first data stream, and the transmission delay of the first data stream in the second optical receiver is the third delay; where the second delay and the third delay The sum obtained by the addition is the aforementioned first delay; the first optical module receives the second data stream sent by the second network device through the first optical receiver, and the second data stream carries indication information; correspondingly, the first optical module The module determines the first time delay, which can be determined according to the indication information carried in the second data stream.
  • FIG. 8 is a schematic diagram of the structure of the oDSP chip in the color light optical module.
  • the first optical module 67 is the color light optical module in the first network device, and the first optical module includes the optical transmitter 210 and the optical module.
  • the receiver 220 wherein, after the first optical module 67 receives the first data stream through the optical transmitter 210, it will send to the second optical receiver 230 of the second optical module 96 in the second network device through the optical transmitter 210 The first data stream.
  • the second delay of the first data stream transmitted in the optical transmitter 210 of the first optical module 67 and the second optical reception of the first data stream in the second optical module 96 can be measured.
  • the second optical module 96 includes an optical transmitter 240 and an optical receiver 230.
  • the optical transmitter 240 includes an oDSP chip 97 and ITLA 82
  • the optical receiver 230 includes an oDSP chip 95 and a dual filter switch. 70.
  • the ITLA 82 and the double filter switch 70 are connected to optical fibers.
  • the oDSP chip 97 includes serializing/deserializing circuits (Serializing/deserializing circuitry; Serial) 93, a channel alignment circuit 91, a FIFO circuit 90, a mapping circuit 89, a FIFO circuit 88, and a forward error correction FEC circuit 87, which are sequentially connected. , DSP circuit 86, FIFO circuit 85 and DAC 83.
  • oDSP chip 95 includes ADC 71, FIFO circuit 73, DSP circuit 74, FEC circuit 75, FIFO circuit 76, demapping circuit 77, FIFO circuit 78, channel distribution circuit 79, and serial/parallel circuit (Serdes) connected in sequence. 81.
  • mapping circuit 89 may be implemented by a framer (Framer) or a bit interleaving (BitMux) circuit.
  • demapping circuit 77 can be implemented by a deframer (DeFramer) or a bit deinterleaving (BitDeMux) circuit.
  • the above-mentioned second time delay can be caused by different processing circuits in the transmitter 210 when processing the first data stream.
  • the optical receiver 230 in the second optical module also includes different processing circuits. Therefore, the aforementioned third time delay may be caused by different processing circuits in the optical receiver 230 in the process of processing the first data stream. Time delay.
  • the foregoing second delay may be the delay of the first data stream being transmitted from the inbound interface of the optical transmitter 210 to the outbound interface of the optical transmitter 210, or may be the delay included in the optical transmitter 210
  • the time delay caused by at least one processing circuit processing the first data stream can also be the time delay caused by at least one processing circuit included in the optical transmitter 210 when processing the first data stream.
  • the second delay may be the delay of the first data stream being transmitted from the serial/parallel circuit 31 to the TOSA module 49, or it may be the processing circuit in the oDSP chip 190 processing the first data stream.
  • the delay caused by time can also be the channel alignment circuit 32, FIFO circuit 33, mapping circuit 34, FIFO circuit 35, FEC circuit 36, DSP circuit 37, and FIFO circuit 38 in the oDSP chip 190 for processing the first data stream.
  • the time delay caused by the time is the sum of the default value or the design value.
  • the above-mentioned third delay may be the delay of the first data stream being transmitted from the inbound interface of the second optical receiver 230 to the outbound interface of the second optical receiver 230, or may be at least one included in the second optical receiver 230
  • the delay caused by the processing circuit when processing the first data stream can also be the delay caused by at least one processing circuit included in the second optical receiver 230 when processing the first data stream.
  • the third time delay may be the time delay of the first data stream being transmitted from the dual filter switch 70 to the serial/parallel circuit 81, or it may be the time delay of each processing circuit in the oDSP chip 95 in the first data stream.
  • the time delay caused by the data stream processing can also be the DAC71, FIFO circuit 73, DSP circuit 74, FEC circuit 75, FIFO circuit 76, demapping circuit 77, FIFO circuit 78 and channel distribution circuit 79 in the oDSP chip 95.
  • the time delay caused when processing the first data stream is the sum obtained by adding the default value or the design value.
  • the first optical module when the first data stream is transmitted in the first optical module, when the first data stream is transmitted to the first circuit, the first optical module extracts the first indication signal carried in the first data stream, and sends it to the first data stream.
  • the second indication signal carried in the first data stream is extracted, and then according to the first indication signal and the second indication signal, it can be determined that the first data stream is in the first optical module 67 by the optical transmitter 210 The second delay in the transmission.
  • the second optical module extracts the third indication signal carried in the first data stream when the first data stream is transmitted to the third circuit, and sends it to the first data stream.
  • the fourth indicator signal carried in the first data stream is extracted, and then according to the third indicator signal and the fourth indicator signal, it can be determined that the first data stream receives the second light in the second optical module 96
  • the third time delay transmitted in the device 230 is transmitted.
  • the first circuit and the second circuit can be any two different circuits in the oDSP chip 190.
  • the first circuit can be the channel alignment circuit 32 shown in FIG. 8 and the second circuit can be the FIFO circuit 38.
  • the transmission delay of the first data stream from the channel alignment circuit 32 to the FIFO circuit 38 can be determined.
  • the default value can be used.
  • the first circuit may also be the FIFO circuit 33, the second circuit may also be the FIFO circuit 38, etc.
  • the first data stream is from The transmission delay of the FIFO circuit 33 to the FIFO circuit 38.
  • a default value or a design value can be used for the delay of other circuits.
  • the third circuit and the fourth circuit can be any two different circuits in the oDSP chip 95.
  • the third circuit can be the FIFO circuit 73 shown in FIG. 8, and the fourth circuit can be a serial/parallel circuit. 81.
  • the delay of the first data stream from the FIFO circuit 73 to the serial/parallel circuit 81 can be determined. , You can use the default value or design value.
  • the third circuit may also be a signal processing circuit 74, and the fourth circuit may also be a serial/parallel circuit 81, etc.
  • the first indicator signal can be determined The delay of a data stream from the signal processing circuit 74 to the serial/parallel circuit 81. Similarly, for the delay of other circuits, a default value or a design value can be used.
  • the delays of the path A1 and the path C1 in the first optical module 67, and the second optical module 67 are similar to those of Serdes11 and DAC17, or Serdes18 and ADC 24 in gray optical modules. They can be preset design values or can be obtained through simulation. The simulation value of, of course, can also be a default value.
  • the first circuit is the channel alignment circuit 32
  • the second circuit is the DAC 39
  • the first indicator signal is the AM indicator signal
  • the second indicator signal is the DSP frame header indicator signal. Examples are explained.
  • the first data stream reaches the channel alignment circuit 32 in the first optical module 67 through multiple channels.
  • the channel selection module 64 will select one of the multiple channels.
  • the AM detection module 60 detects the AM indicator signal 1 carried in the first data stream from the selected channel, and will The detected AM indicator signal 1 is sent to the TX delay measurement module 65.
  • the AM indicator signal needs to be identified.
  • the identified AM indicator signal will be carried in the first Transmission continues in the data stream.
  • the outgoing interface of the optical transmitter 210 of the first optical module 67 will periodically extract the DSP frame header indication signal 1.
  • the DSP frame header extraction module 61 will extract the first data.
  • the DSP frame header indicator signal 1 carried in the stream, and the extracted DSP frame header indicator signal 1 is sent to the TX delay measurement module 65.
  • the TX delay measurement module 65 uses a high-precision phase detection algorithm to measure AM
  • the phase difference between the indicator signal 1 and the DSP frame header indicator signal 1 can determine the time delay of the first data stream in the path B1.
  • the measurement accuracy depends on the accuracy of the phase detection algorithm. Under normal circumstances, the accuracy of the measured time delay can reach a hundred ps level.
  • the AM indicator needs to be The signal and DSP frame header indicate that two adjacent signals are selected for measurement. For example, if the period of the AM indicator signal is 3ms and the period of the DSP frame header indicator signal is 1.2ms, it is possible that only one AM indicator signal will appear in the first data stream after two DSP frame header indicator signals appear. At this time, you can select the AM indicator signal and the DSP frame header indicator signal adjacent to the AM indicator signal for measurement. For example, you can select the AM indicator signal and the second DSP frame header indicator signal, and measure one of these two signals. The phase difference between.
  • the third circuit is the FIFO circuit 73
  • the fourth circuit is the serial/parallel circuit 81
  • the third indicator signal is the DSP frame header indicator signal
  • the fourth indicator signal is AM
  • the indication signal is described as an example. As shown in FIG.
  • the first data stream passes through the ADC in the second optical module 96 71, and transmitted to the FIFO circuit 73, according to the identification information added to the DSP frame header indicator signal in the optical transmitter 210 of the first optical module 67, the DSP frame header indicator signal 2 is extracted through the DSP frame header pre-detection module 72 , And send the extracted DSP frame header indication signal 2 to the RX delay measurement module 94. At this time, the first data stream will continue to be transmitted.
  • the AM extraction module 80 After detecting that the first data stream is transmitted to the serial/parallel circuit 81, the AM extraction module 80 will use the AM extraction module 80 according to the optical transmitter 210 of the first optical module 67.
  • the added identification information extracts the AM indicator signal 2 carried in the first data stream from the channel, and sends the extracted AM indicator signal 2 to the RX delay measurement module 94.
  • the RX delay measurement module 94 adopts high
  • the accurate phase detection algorithm measures the phase difference between the DSP frame header indicator signal 2 and the AM indicator signal 2 to determine the time delay of the first data stream in the path E2. Among them, the measurement accuracy depends on the accuracy of the phase detection algorithm. Under normal circumstances, the accuracy of the measured time delay can reach a hundred ps level.
  • the aforementioned AM indicator signal 1 and AM indicator signal 2 are the same AM indicator signal
  • the DSP frame header indicator signal 1 and the DSP frame header indicator signal 2 are the same indicator signal.
  • the second indication information and the fourth indication information may also use other data identifiers that are easy to identify, such as inserting an identifier into the first data stream.
  • the second indication information and the fourth indication information this The application examples are not limited here.
  • the first optical module after determining the second delay of the first data stream in the optical transmitter 210, the first optical module will carry the second delay in the first data stream and send it to the second optical module.
  • the second optical module determines the third delay of the first data stream in the second receiver 230, the sum obtained by adding the second delay and the third delay , Determined as the first delay.
  • the second optical receiver 230 of the second optical module sends the second data stream to the first optical receiver 220 of the first optical module 67 after determining the first time delay.
  • the second data stream carries indication information, so that the first optical module can determine the first delay according to the indication information.
  • the indication information includes the first time delay. After the first optical module 67 receives the indication information in the second data stream through the first optical receiver 220, it can directly determine The first delay.
  • the delay of path B1 and path E2 can also be preset design values. Or the simulation value obtained through simulation, of course, it can also be a default value.
  • the first delay may be that the first data stream is in the second
  • the transmission delay of the optical transmitter 240 of the optical module 96 is the sum of the transmission delay of the first data stream in the first optical receiver 220 of the first optical module 67.
  • the transmission delay of the first data stream at the optical transmitter 240 of the second optical module 96 is the sum of the corresponding delays of path A2, path B2, and path C2, and the first data stream at the first optical module 67
  • the time delay in the first optical receiver 220 is the sum of the respective delays corresponding to the path D1, the path E1, and the path F1.
  • the respective delays of path A2, path C2, path D1, and path F1 are similar to the aforementioned delays of path A1, path C1, path D2, and path F2, and can be preset design values or pass through
  • the simulated value obtained by the simulation can also be a default value.
  • the time delay of the path B2 in the optical transmitter 240 of the second optical module 96 and the path E1 in the first optical receiver 220 of the first optical module 67 is the same as that of the aforementioned optical transmitter 210 of the first optical module 67.
  • the path B1 of the second optical module 96 and the path E2 of the second optical receiver 230 of the second optical module 96 are determined in a similar manner for determining the delay, which will not be repeated here.
  • Step 202 The first optical module sends a first delay to the interface chip.
  • the first optical module since the first optical module defines the delay reporting register access interface, after determining the first delay, the first optical module will report to the register access interface through the delay reporting register of the first optical module.
  • the interface chip sends the first time delay so that the interface chip compensates the first time delay to the recording time stamp.
  • the time stamp recorded by the MDI layer includes the time delay of the message transmission in the optical module, so that the MDI The time stamp recorded by the layer is more accurate, which can make the master-slave clock time synchronization accuracy higher, thereby further improving the clock accuracy of the network device.
  • the interface chip includes at least one of a PHY chip and a MAC chip.
  • the delay reporting register access interface of the first optical module can be defined in the manner in the following table:
  • the interface bit width is used to indicate the number of bits of the interface signal.
  • the reported value of the delay reporting register access interface is a fixed value of 0.
  • Optical modules that support delay reporting can be divided into two types: optical modules that do not support delay measurement and optical modules that support delay measurement.
  • the first reported delay is It is the design value of the oDSP chip.
  • the first delay reported is the measured value obtained through the indication information.
  • the first optical module is a gray optical module
  • the interface chip can compensate the first delay and the delay of the message transmission in the MAC layer or PHY layer to the time stamp recorded by the MAC layer or PHY layer.
  • the asymmetry error introduced by the optical module is reduced, and the time stamp recorded by the MDI layer is more accurate, which can make the master-slave clock time synchronization accuracy higher, thereby further improving the clock accuracy of the network device. .
  • the first delay is the delay of the transmission of the first data stream in the optical transmitter of the first optical module and the second optical reception of the first data stream in the second optical module The sum of the transmission delays in the device.
  • the first optical module can report the register through the delay defined in the first optical module The access interface reports the first delay to the interface chip.
  • the second optical module can report the first delay to the interface chip through the delay report register access interface defined in the second optical module, or report 0 or report a special identifier.
  • the second optical module can also report the first delay. None can be reported.
  • the first optical module can pass through the first optical module.
  • the delay reporting register access interface defined in the interface chip reports the first delay to the interface chip. It can also report 0 or report a special identifier. Of course, the first optical module can also report nothing.
  • the first optical module and the second optical module may divide the first delay into two parts according to a preset rule, where the first part is defined by the first optical module through the first optical module
  • the delay reporting register access interface reports to the interface chip, and the second part is reported by the second optical module to the interface chip through the delay reporting register access interface defined in the second optical module.
  • the first optical module after determining the first delay, sends the determined first delay to the interface chip. Since the delay reporting register access interface is defined in the first optical module, the first optical module can report the first delay to the MAC layer or the PHY layer through the delay reporting register access interface, so that the first delay It is compensated to the time stamp of the message recorded by the MAC layer or the PHY layer, thereby improving the accuracy of time synchronization between the master and slave clocks, thereby further improving the clock accuracy of the network device.
  • the optical module provided in the embodiment of the present application is used as the first optical module and can be used to perform actions related to the first optical module in the foregoing method embodiment.
  • the optical module includes a processor 101.
  • the processor 101 is configured to determine the first time delay
  • the processor 101 is further configured to send the first delay to the interface chip.
  • the optical module After the optical module provided in the embodiment of the present application determines the first delay, it will send the determined first delay to the interface chip. Since the delay reporting register access interface is defined in the optical module, the optical module can report the first delay to the MAC layer or the PHY layer through the delay reporting register access interface, and the first delay can be compensated to the MAC layer Or in the time stamp of the message recorded by the PHY layer, which can improve the accuracy of master-slave clock time synchronization, thereby further improving the clock accuracy of the network device.
  • FIG. 9 is a schematic structural diagram of an optical module provided by an embodiment of the application.
  • the first optical module 10 is a gray light optical module, and the first optical module 10 includes: an optical transmitter 102.
  • the transmitter 102 includes the processor 101, an inbound interface 1021, and an outbound interface 1022, where:
  • the optical transmitter 102 is configured to receive the first data stream through the inbound interface 1021;
  • the optical transmitter 102 is further configured to send the first data stream to a second network device through the outgoing interface 1022;
  • the processor 101 is further configured to determine that the transmission delay of the first data stream in the optical transmitter 102 is the first delay.
  • FIG. 10 is a schematic structural diagram of another optical module provided by an embodiment of the application.
  • the first optical module 20 is a color light optical module in a first network device, and the first optical module 20 includes: The transmitter 103 and the first optical receiver 104, the first optical receiver 104 includes the processor 101, wherein:
  • the optical transmitter 103 is configured to receive a first data stream, and the transmission delay of the first data stream in the optical transmitter 103 is a second delay;
  • the optical transmitter 103 is also configured to send the first data stream to the second optical receiver of the second optical module in the second network device, and the first data stream is in the second optical receiver.
  • the transmission delay in the middle is the third delay;
  • the sum obtained by adding the second delay and the third delay is the first delay
  • the first optical receiver 104 is configured to receive a second data stream sent by the second network device, where the second data stream carries indication information;
  • the processor 101 is specifically configured to determine the first delay according to the instruction information.
  • the indication information includes the first time delay.
  • the first delay is a design value.
  • FIG. 11 is a schematic structural diagram of another optical module provided by an embodiment of this application.
  • the optical transmitter 103 includes a first circuit 1031 and a second circuit 1302,
  • the processor 101 is further configured to:
  • the processor 101 is further configured to:
  • the first indication signal and the second indication signal are both alignment mark AM indication signals, or the first indication signal is an AM indication signal, and the second indication signal is a digital signal processing DSP frame header signal .
  • the interface chip includes at least one of a physical layer PHY chip and a media access control layer MAC chip.
  • the aforementioned processor 101 may be one or more integrated circuits configured to implement the above methods, such as: oDSP, or, one or more application specific integrated circuits (ASIC), or, one or Multiple microprocessors (digital singnal processors, DSP), or, one or more field programmable gate arrays (FPGA), etc.
  • the processor may also be a central processing unit (CPU) or other processors that can call programs.
  • optical module provided in the embodiment of the present application can execute the above-mentioned corresponding method embodiment, and its implementation principles and technical effects are similar, and will not be repeated here.
  • An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, it can implement the process related to the first optical module in the communication method provided in the foregoing method embodiment.
  • various aspects or features of the embodiments of the present application may be implemented as methods, devices, or products using standard programming and/or engineering techniques.
  • article of manufacture used in this application encompasses a computer program that can be accessed from any computer-readable device, carrier, or medium.
  • computer-readable media may include, but are not limited to: magnetic storage devices (for example, hard disks, floppy disks, or tapes, etc.), optical disks (for example, compact discs (CD), digital versatile discs (DVD)) Etc.), smart cards and flash memory devices (for example, erasable programmable read-only memory (EPROM), cards, sticks or key drives, etc.).
  • various storage media described herein may represent one or more devices and/or other machine-readable media for storing information.
  • the term "machine-readable medium” may include, but is not limited to, wireless channels and various other media capable of storing, containing, and/or carrying instructions and/or data.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center integrated with one or more available media.
  • the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)).
  • the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic.
  • the implementation process of the embodiment constitutes any limitation.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solutions of the embodiments of the present application can be embodied in the form of software products in essence or parts that contribute to the prior art or parts of the technical solutions, and the computer software products are stored in a storage medium , Including several instructions to enable a computer device (which may be a personal computer, a server, or an access network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code .

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Abstract

本申请提供一种通信方法和光模块，该方法包括：第一光模块确定第一时延；所述第一光模块向接口芯片发送所述第一时延。本申请提供的通信方法和光模块能够将光模块的时延上报给接口芯片，以提高主从时钟时间同步的精度，从而可以进一步提高网络设备的时钟精度。

Description

通信方法和光模块
本申请要求于2019年01月22日提交中国国家知识产权局、申请号为201910059723.1、申请名称为“通信方法和光模块”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及通信技术领域，尤其涉及一种通信方法和光模块。
背景技术
在移动通信网络中，基于时分复用(Time Division Duplex，TDD)制式的基站需要满足严格的时间同步要求，否则基站发送的无线信号将对其他基站形成干扰，导致相邻区域的基站无法正常工作。
目前可以通过时钟协议，实现不同基站之间的时间同步。例如电气和电子工程师学会(Institute of Electrical and Electronics Engineers；IEEE)1588V2协议，其是网络测量和控制系统的精密时钟同步协议标准，1588V2协议又称为精确时间协议(Precision Time Protocol；PTP)，可以实现多个网络设备的时间同步，精度可以达到微秒级。目前，1588V2协议中实现网络设备间的时间同步时，是采用主从时钟方式，通过对时间信息进行编码，利用网络的对称性和延时测量技术，通过报文消息的双向交互实现主从时间的同步。具体的，主从时钟分别在发送报文和接收到报文时，对报文进行打戳，从而计算出主从时钟之间的时间差，从时钟根据计算出的时间差校准本地时间。
目前，如何进一步提高主从时钟时间同步的精度，从而进一步提高网络设备的时钟精度，是目前亟待解决的技术问题。
发明内容
本申请实施例提供一种通信方法和光模块，能够将光模块的时延上报给接口芯片，以提高主从时钟时间同步的精度，从而可以进一步提高网络设备的时钟精度。
本申请第一方面提供一种通信方法，包括：
第一光模块确定第一时延；
该第一光模块向接口芯片发送该第一时延。
在本方案中，由于在第一光模块中定义了时延上报寄存器访问接口，这样，第一光模块可以通过该时延上报寄存器访问接口向接口芯片上报第一时延，从而可以将该第一时延补偿到接口芯片记录的报文的时戳中，以提高主从时钟时间同步的精度，从而可以进一步提高网络设备的时钟精度。
在一种可能的实现方式中，该第一光模块为灰光光模块，该第一光模块包括光发射器，该光发射器包括入接口和出接口，该第一光模块确定第一时延，该包括：
该第一光模块通过该入接口接收第一数据流；
该第一光模块通过该出接口向第二网络设备发送该第一数据流；
该第一光模块确定该第一数据流在该光发射器中传输的时延为该第一时延。
在本方案中，第一时延可以是第一数据流在第一光模块中光发射器中传输的时延。另外，由于光发射器中包括有不同的处理电路，因此，上述第一时延也可以为光发射器中不同的处理电路在对第一数据流进行处理时所引起的时延。
具体的，上述第一时延可以为第一数据流从光发射器的入接口传输到光发射器的出接口的时延，也可以为光发射器中包括的至少一个处理电路在对第一数据流进行处理时所引起的时延，当然，也可以为光发射器中包括的至少一个处理电路在对第一数据流进行处理时所引起的时延与默认值或者设计值相加所得到的和。
在一种可能的实现方式中，该第一光模块为第一网络设备中的彩光光模块，该第一光模块包括光发射器和第一光接收器；
该第一光模块确定第一时延之前，该方法还包括：
该第一光模块通过该光发射器接收第一数据流，该第一数据流在该光发射器中传输的时延为第二时延；
该第一光模块通过该光发射器向第二网络设备中的第二光模块的第二光接收器发送该第一数据流，该第一数据流在该第二光接收器中传输的时延为第三时延；
其中，该第二时延和该第三时延相加所得的和为该第一时延；
该第一光模块通过该第一光接收器接收该第二网络设备发送的第二数据流，该第二数据流携带指示信息；
该第一光模块确定第一时延，包括：
该第一光模块根据该指示信息，确定该第一时延。
在本案中，第一光模块为第一网络设备中的彩光光模块，第二光模块为第二网络设备中的彩光光模块。第一光模块包括光发射器和第一光接收器，其中，第一光模块通过光发射器接收到第一数据流后，会通过光发射器向第二网络设备中的第二光模块的第二光接收器发送该第一数据流。这样，可以根据该第一数据流，测量出第一数据流在第一光模块中传输的第二时延和在第二光模块中传输的第三时延。
进一步地，第一光模块在确定出第一数据流在第一光模块中的第二时延后，会将该第二时延携带在第一数据流中发送给第二光模块，第二光模块在确定出第一数据流在第二光模块中的第三时延后，将得到的第二时延和第三时延相加所得的和，确定为第一时延。第二光模块在确定出第一时延后，向第一光模块发送第二数据流，该第二数据流中携带有指示信息，这样，第一光模块可以根据该指示信息，确定出第一时延。
在一种可能的实现方式中，该指示信息中包括该第一时延。
在一种可能的实现方式中，该第一光模块不支持时延测量时，该第一时延为设计值。
在本方案中，若第一光模块不具备测量时延的功能时，上述的第一时延可以为预先设定的设计值，或者为通过仿真得出的仿真值，当然，还可以是一个默认值。
在一种可能的实现方式中，该方法还包括：
该第一光模块在该第一数据流传输至第一电路时，提取该第一数据流中携带的第一指示信号；
该第一光模块在该第一数据流传输至第二电路时，提取该第一数据流中携带的第二指示信号；
该第一光模块根据该第一指示信号和该第二指示信号，确定该第一时延。
在一种可能的实现方式中，该根据该第一指示信号和该第二指示信号，确定该第一时延，包括：
测量该第一指示信号和该第二指示信号之间的相位差；
根据该相位差确定该第一时延；
其中，该第一指示信号和该第二指示信号均可以为对齐标识AM指示信号，或者，该第一指示信号可以为AM指示信号，该第二指示信号可以为数字信号处理DSP帧头信号。
在上述方案中，在第一数据流传输至第一电路时，提取第一数据流中携带的第一指示信号，在第一数据流传输至第二电路时，提取第一数据流中携带的第二指示信号。然后通过高精度的鉴相算法，测量第一指示信号和第二指示信号之间的相位差，即可确定出第一时延，由此可以提高确定出的时延的精度。
其中，第一电路和第二电路可以为第一光模块中的任意两个不同的电路。
进一步地，第一指示信号和第二指示信号可以为AM指示信号，或者该第一指示信号为AM指示信号，该第二指示信号为数字信号处理DSP帧头信号。另外，上述的第一指示信号和第二指示信号也可以为其他便于识别的信号，如在第一数据流中插入的标识符等。
在一种可能的实现方式中，该接口芯片包括物理层PHY芯片和媒质接入控制层MAC芯片中的至少一个。
本申请第二方面提供一种光模块，用作第一光模块，包括：
处理器，用于确定第一时延；
该处理器，还用于向接口芯片发送该第一时延。
在一种可能的实现方式中，该第一光模块为灰光光模块，该第一光模块包括光发射器，该光发射器包括该处理器、入接口和出接口，其中：
该光发射器，用于通过该入接口接收第一数据流；
该光发射器，还用于通过该出接口向第二网络设备发送该第一数据流；
该处理器，还用于确定该第一数据流该在该光发射器中传输的时延为该第一时延。
在一种可能的实现方式中，该第一光模块为第一网络设备中的彩光光模块，该第一光模块包括光发射器和第一光接收器，该第一光接收器包括该处理器；
该光发射器，用于接收第一数据流，该第一数据流在该光发射器中传输的时延为第二时延；
该光发射器，还用于向第二网络设备中的第二光模块的该第二光接收器发送该第一数据流，该第一数据流在该第二光接收器中传输的时延为第三时延；
其中，该第二时延和该第三时延相加所得的和为该第一时延；
该第一光接收器，用于接收该第二网络设备发送的第二数据流，该第二数据流携带指示信息；
该处理器，具体用于根据该指示信息，确定该第一时延。
在一种可能的实现方式中，该指示信息中包括该第一时延。
在一种可能的实现方式中，该第一光模块不支持时延测量时，该第一时延为设计值。
在一种可能的实现方式中，该光发射器包括第一电路和第二电路；该处理器，还用于：
在该第一数据流传输至该第一电路时，提取该第一数据流中携带的第一指示信号；
在该第一数据流传输至该第二电路时，提取该第一数据流中携带的第二指示信号；
根据该第一指示信号和该第二指示信号，确定该第一时延。
在一种可能的实现方式中，该处理器，还用于：
测量该第一指示信号和该第二指示信号之间的相位差；
根据该相位差确定该第一时延；
其中，该第一指示信号和该第二指示信号均为对齐标识AM指示信号，或者，该第一指示信号为AM指示信号，该第二指示信号为数字信号处理DSP帧头信号。
在一种可能的实现方式中，该接口芯片包括物理层PHY芯片和媒质接入控制层MAC芯片中的至少一个。
本申请提供的通信方法和光模块，第一光模块在确定出第一时延后，将向接口芯片发送确定出的第一时延。由于在第一光模块中定义了时延上报寄存器访问接口，这样，第一光模块可以通过该时延上报寄存器访问接口向接口芯片上报第一时延，以将该第一时延补偿到MAC层或PHY层记录的报文的时戳中，由此可以提高主从时钟时间同步的精度，从而可以进一步提高网络设备的时钟精度。
附图说明
图1为本申请实施例提供的一种应用场景示意图；
图2为计算主从时钟之间的时间差的示意图；
图3为本申请实施例提供的通信方法的一种流程示意图；
图4为光模块的组成示意图；
图5为灰光光模块的结构示意图；
图6为彩光光模块的结构示意图；
图7为灰光光模块中oDSP芯片的结构示意图；
图8为彩光光模块中oDSP芯片的结构示意图；
图9为本申请实施例提供的一种光模块的结构示意图；
图10为本申请实施例提供的另一种光模块的结构示意图；
图11为本申请实施例提供的又一种光模块的结构示意图。
具体实施方式
以下，对本申请中的部分用语进行解释说明，以便于本领域技术人员理解。
1)光模块(optical module)，主要由光电转换器件和电信号处理器件组成。其中，光模块中包括有光发射器和光接收器两部分。电信号处理器件包括时钟和数据恢复(clock and data recovery；CDR)芯片或光数字信号处理(optical digital signal processing；oDSP) 芯片。光模块通常是进行光电转换和/或电光转换。例如，发送端的光模块把电信号转换成光信号，并通过光纤将转换后的光信号传送到接收端的光模块后，接收端的光模块再将光信号转换成电信号，以对转换后的电信号进行处理。
2)网络设备，可以是用于与移动设备通信的设备，网络设备可以是路由器、交换机、分组传送网(packet transport network；PTN)设备、光传送网(optical transport network；OTN)设备、无源光纤网络(passive optical network；PON)设备或同步数字体系(synchronous digital hierarchy；SDH)设备等，也可以是WLAN中的接入点(access point，AP)，GSM或CDMA中的基站(base transceiver station，BTS)，也可以是WCDMA中的基站(nodeB，NB)，还可以是LTE中的演进型基站(evolutional node B，eNB或eNodeB)，或者网络型中继站或网络型接入点，或者车载设备、可穿戴设备以及未来5G网络中的网络设备或者未来演进的PLMN网络中的网络设备，或NR系统中的新一代基站(new generation node B,gNodeB)等。
3)时延上报寄存器访问接口，也可以称之为寄存器访问接口或时延上报接口。用于向接口芯片上报报文在第一光模块的光发射器或者光接收器中传输的时延，或者用于向接口芯片上报报文在第一光模块的光发射器中，以及报文在第二光模块的光接收器中传输的时延。
4)本申请中，“至少一个”可以是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A,B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a,b,或c中的至少一项(个)，可以表示：a,b,c,a-b,a-c,b-c,或a-b-c，其中a,b,c可以是单个，也可以是多个。“以上”或“以下”等所描述的范围包括边界点。
5)本申请中的单元是指功能单元或逻辑单元。其可以为软件形式，通过处理器执行程序代码来实现其功能；也可以为硬件形式。
本领域技术人员可以理解，本申请实施例提供的通信方法可以应用于光模块向接口芯片上报时延的应用场景中，其中，接口芯片包括物理层(physical layer；PHY)芯片和媒质接入控制层(media access control；MAC)芯片中的至少一个。接口芯片可以实现PHY层的功能。在移动通信网络中，基于时分复用(Time Division Duplex，TDD)制式的基站需要满足严格的时间同步要求，否则基站发送的无线信号将对其他基站形成干扰，导致相邻区域的基站无法正常工作。为实现基站间的时间同步，通常需要开通网络协议来传递时间信息。本申请实施例中以开通1588V2协议传递时间信息为例进行说明，当然，也可以通过其他协议来传递时间信息。例如可以通过SDH协议中的同步状态信息(synchronous status message，SSM)信息表示时钟等级信息。
图1为本申请实施例提供的一种应用场景示意图，如图1所示，通常在无线网核心层部署有时间源设备，并通过全球定位系统(Global Positioning System；GPS)或北斗接收卫星时间作为基准源，然后通过秒脉冲和日时间(1 Pulse per Second and Time of Day；1PPS+TOD)等外时间辅助接口或PTP接口(开通1588V2协议的以太网接口)传递时间信息给传输设备101，传输设备101通过PTP接口从核心层逐跳向下，将时 间信息传递给汇聚层设备102，汇聚层设备102再逐跳向下，将时间信息传递给接入层设备103，接入层设备103通过1PPS+TOD等外时间辅助接口或PTP接口将时间信息传递给相连的基站104，从而实现全网基站的时间同步。
其中，传输设备101、汇聚层设备102和接入层设备103可以为路由器、交换机、PTN设备、OTN设备或PON设备等网络设备。
值得注意的是，传输设备101、汇聚层设备102和接入层设备103之间也可以通过本申请实施例中描述的方案进行时间同步。
下面，以1588V2协议为例，具体说明如何实现基站间的时间同步：1588V2协议又简称PTP，是一种精确的时间同步协议，可以实现多个网络设备的时间同步。其核心思想是采用主从时钟方式，对时间信息进行编码，利用网络的对称性和延时测量技术，通过报文消息的双向交互实现主从时间的同步。具体的，主从时钟分别在发送报文和接收到报文时，对报文进行打戳，从而计算出主从时钟之间的时间差，从时钟根据计算出的时间差校准本地时间。图2为计算主从时钟之间的时间差的示意图，如图2所示，主节点(Master)向从节点(Slave)发送同步报文(Sync)，并将发送时间戳t1记入寄存器，从节点(Slave)接收到同步报文后，会记录接收到的时间戳t2，另外，主节点(Master)向从节点(Slave)发送跟随报文(Follow_Up)，并将时间戳t1携带到跟随报文中发送给从节点(Slave)，从节点(Slave)向主节点(Master)发送延时请求报文(Delay_Req)，其中，延时请求报文中携带有时间戳t3。主节点(Master)接收到延时请求报文后，将记录接收时间戳t4，主节点(Master)将t4携带在延时应答报文(Delay_Resp)中发送给从节点(Slave)。其中，主节点中的时钟为主时钟，从节点中的时钟为从时钟。
通过上述时间t1、t2、t3和t4，从时钟可以根据下述公式(1)和公式(2)计算出从时钟和主时钟之间的延迟(Delay)和时间差(Offset)，从时钟通过延迟(Delay)和时间差(Offset)，可以校准本地时间戳，从而达到主从时钟的同步。
Delay＝(t2-t1+t4-t3)/2    (1)
Offset＝(t2-t1-t4+t3)/2    (2)
根据1588V2协议原理，主从时钟的打戳参考平面在PTP端口的物理介质相关子层(medium dependent interface；MDI)。但是由于打戳事件由PTP报文头触发，MDI层无法完成PTP报文头识别，也就无法完成打戳。因此，在具体实现时，往往在媒质接入控制(media access control；MAC)层或物理层(physical layer；PHY)层进行打戳，以记录报文的时戳，并将MAC层或PHY层的1588报文打戳点与光模块的MDI层之间的时延测量出来补偿到在MAC层或PHY层记录的时戳中，从而实现MDI层打戳的功能。其中，光模块的MDI层为光模块中的光电转换器件的端口。
然而，当前的以太网协议IEEE 802.3协议中仅定义了PHY层时延上报的寄存器接口，用以上报报文在PHY层中传输的时延。但是，由于一些光模块，PHY层会由接口芯片与光模块共同实现，即：PHY层的时延包括两部分，接口芯片的PHY层时延，以及光模块的PHY层时延。协议中只是上报了接口芯片的PHY层时延，补偿到记录的时戳中的时延仅包括了接口芯片的PHY层时延，没有对光模块的PHY层时延进行记录，使得补偿后的时间戳不准确，造成主从时钟时间同步精度不高，从而导致网络设备的时钟精度不高。
另外，IEEE 802.3协议当前定义的PHY层上报时延功能，精度不高，也导致1588时 间戳不准确，从而导致网络设备的时钟精度不高。IEEE 802.3上报时延的精度不高的原因包括几点：1)上报时延的精度为1ns；2)PHY层包括多个子层(如，PCS，PMA，PMD等)，每个子层上报时延精度都会引入1ns的损失，从而N个子层分别上报时延，导致总时延精度为N ns。
本申请实施例考虑到上述问题，提出一种通信方法，其中，第一光模块在确定出第一时延后，将向接口芯片发送确定出的第一时延。由于在第一光模块中定义了时延上报寄存器访问接口，这样，第一光模块可以通过该时延上报寄存器访问接口向接口芯片上报第一时延，以将报文在光模块中传输所产生的时延补偿到记录的报文的时戳中，由此可以提高主从时钟时间同步的精度，从而可以进一步提高网络设备的时钟精度。
下面以具体的实施例对本发明的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
图3为本申请实施例提供的通信方法的一种流程示意图。如图3所示，本实施例的方法可以包括：
步骤301、第一光模块确定第一时延。
其中，根据上述公式(2)可知，如果光模块的接收和发送两个方向的时延是对称的，PTP时戳修正前与修正的offset计算结果相同。对于该类光模块，可以不进行时延上报和修正，因此，在实际应用中，只需要对接收和发送两个方向的时延不对称的光模块进行时延上报和修正即可。因此，在介绍第一光模块如何确定第一时延之前，先对现有的光模块的结构以及光模块的时延对称性进行介绍。
图4为光模块的组成示意图，如图4所示，光模块100中包括有光发射器110和光接收器120两部分。另外，光模块100一般可以划分为“数字域”和“模拟域”两部分，其中“数字域”由CDR或oDSP芯片构成，主要实现模拟和数字信号处理，当接收和发送两个方向的处理电路不对称时，就会引入时延不对称；另外，“模拟域”包括光发射次模块(transmitter optical subassembly；TOSA)和光接收次模块(receiver optical subassembly；ROSA)，包括金手指、印制电路板(printed circuit board；PCB)走线和光电转换器件等，一般会按照收发对称进行设计，收发时延相对固定且对称，对时钟同步精度基本无影响。因此，在确定光模块中的时延时，通常只考虑“数字域”中的时延。
可以理解的是，若光模块采用CDR芯片，由于CDR芯片是通过纯模拟信号电路对数据流进行处理，此时，光模块中的收发时延对称，则不需要进行时延的确定和时延上报。示例性的，若光模块采用CDR芯片，也可以采用本申请实施例中的方式确定光模块的时延，或者也可以将该光模块的时延设计为一个默认值或者设计值。
若光模块采用oDSP芯片，由于oDSP芯片会导致收发时延存在不对称性以及不确定性，此时，报文在该光模块中传输的时延将会影响网络设备的时钟的精度。因此，需要确定报文在该光模块中传输的时延，并将该时延上报给接口芯片，以提高网络设备的时钟的精度。下面，以具体的示例进行说明。
图5为灰光光模块的结构示意图，如图5所示，灰光光模块中包括光发射器170和光接收器180，其中，光发射器170中包括oDSP芯片130和TOSA 25，光接收器180中包括oDSP芯片140和ROSA 26。TOSA 25和ROSA 26连接光纤。
其中，oDSP芯片130中包括有依次连接的串行/并行电路(serializing/deserializing circuitry；Serdes)11、通道对齐电路12、先入先出(first in first out；FIFO)电路13、映射电路14、数字信号处理(digital signal processing；DSP)电路15、FIFO电路16和数字模拟转换器(digital analog converter；DAC)17。oDSP芯片140中包括有依次连接的串行/并行电路(Serdes)18、通道分发电路19、FIFO电路20、解映射电路21、DSP电路22、FIFO电路23和模拟数字转换器(analog digital converter；ADC)24。
示例性的，映射电路14可以通过4级脉冲幅度调制(four-level pulse amplitude modulation；PAM4)电路或者比特交织(BitMux)电路实现。类似的，解映射电路21可以通过PAM4电路或者比特解交织(BitDeMux)电路实现。
上述oDSP芯片130和oDSP芯片140中的这些电路会导致收发时延存在不对称且不确定性，大约可能会引入10NS(纳秒)级的时延，会造成基站间的时钟同步的精度不高，从而影响网络设备的时钟精度。因此，上述灰光光模块确定报文在灰光光模块中传输的时延，并将该时延上报给接口芯片，能够进一步提高网络设备的时钟精度。
图6为彩光光模块的结构示意图，如图6所示，彩光光模块中包括光发射器190和光接收器200，其中，光发射器190中包括oDSP芯片150和可集成可调激光器阵列(integrable tunable laser assembly；ITLA)49，光接收器200中包括oDSP芯片160和和双滤光片切换器50。ITLA 49和双滤光片切换器50连接光纤。
其中，oDSP芯片150中包括有依次连接的串行/并行电路(serializing/deserializing circuitry；Serdes)31、通道对齐电路32、FIFO电路33、映射电路34、FIFO电路35、前向纠错(forward error correction；FEC)电路36、DSP电路37、FIFO电路38和DAC39。oDSP芯片160中包括有依次连接的串行/并行电路(Serdes)40、通道分发电路41、FIFO电路42、解映射电路43、FIFO电路44、FEC电路45、DSP电路46、FIFO电路47和ADC 48。
示例性的，映射电路34可以通过成帧器(Framer)或者比特交织(BitMux)电路实现。类似的，解映射电路43可以通过解帧器(DeFramer)或者比特解交织(BitDeMux)电路实现。
由于彩光光模块的oDSP芯片150和oDSP芯片160相对于灰光光模块增加了FEC电路，从而造成收发时延的不确定性因素更多，对同步精度的影响大约在10NS级，因此，上述彩光光模块确定报文在彩光光模块中传输的时延，并将该时延上报给接口芯片，能够进一步提高网络设备的时钟精度。
基于上述内容，下面以第一光模块为上述灰光光模块和彩光光模块为例，分别介绍第一光模块确定第一时延的过程。
结合图5所示，第一光模块为灰光光模块时，第一光模块包括光发射器170，该光发射器170包括入接口和出接口，则第一光模块可以通过入接口接收第一数据流，并通过出接口向第二网络设备发送第一数据流，第一光模块将确定该第一数据流在光发射器中传输的时延为第一时延。
其中，第一时延可以是第一数据流在第一光模块中光发射器170中传输的时延，可以理解的是，参考图5所示，由于光发射器170中包括有不同的处理电路，因此，上述第一时延也可以为光发射器中不同的处理电路在对第一数据流进行处理时所引起的时延。
具体的，如图5所示，上述第一时延可以为第一数据流从光发射器170的入接口传输到光发射器170的出接口的时延。该第一时延也可以为光发射器170中包括的至少一个处理电路在对第一数据流进行处理时所引起的时延。当然，该第一时延也可以为光发射器170中包括的至少一个处理电路在对第一数据流进行处理时所引起的时延与默认值或者设计值相加所得到的和。举例来说，该第一时延可以为第一数据流从串行/并行电路11传输至光TOSA模块25的时延，也可以为oDSP芯片130中的各处理电路在对第一数据流进行处理时所引起的时延，也可以为oDSP芯片130中的通道对齐电路12、FIFO电路13、映射电路14、DSP电路15和FIFO电路16对第一数据流进行处理时所引起的时延，与默认值或者设计值的相加得到的和。
示例性的，由于第一光模块中的oDSP芯片的时延存在不对称性和不确定性，故在实际应用中，在计算第一光模块的时延时，通常只需要确定oDSP芯片对应的时延即可。
下面，将详细介绍第一数据流在灰光光模块中的oDSP芯片中的时延的确定方法。具体的，第一光模块在第一数据流传输至第一电路时，提取第一数据流中携带的第一指示信号，并在第一数据流传输至第二电路时，提取第一数据流中携带的第二指示信号，并根据第一指示信号和第二指示信号，确定第一时延。其中，由于接收路径上的第一数据流在映射过程中和发送路径上的第一数据流在解映射过程中，第一数据流的结构没有发生变化，因此，在一种可能的实现方式中，可以基于对齐标识(alignment marker；AM)指示信号测量第一时延，即第一指示信号和第二指示信号可以为AM指示信号。当然，在其他可能的实现方式中，第一指示信号和第二指示信号也可以为其他便于识别的信号，如在第一数据流中插入的标识符等，对于第一指示信号和第二指示信号的具体形式，本申请实施例在此不做限制，只要第一指示信号和第二指示信号可以在入接口和出接口中可以被识别即可。
进一步地，在根据第一指示信号和第二指示信号，确定第一时延时，可以通过测量第一指示信号和第二指示信号之间的相位差，并根据上述相位差确定第一时延。
另外，第一电路和第二电路可以为oDSP芯片中的任意两个不同的电路，如第一电路可以为图5中所示的通道对齐电路12、第二电路可以为FIFO电路16，此时，根据第一指示信号和第二指示信号之间的相位差，可以确定出第一数据流从通道对齐电路12传输至FIFO电路16的时延，对于其他电路的时延，可以采用默认值或者设计值。或者，第一电路也可以为FIFO电路13、第二电路也可以为FIFO电路16等，此时，根据第一指示信号和第二指示信号之间的相位差，可以确定出第一数据流从FIFO电路13传输至FIFO电路16的时延，同样的，对于其他电路的时延，可以采用默认值或者设计值。
下面，以第一电路为通道对齐电路12、第二电路为DAC 17，第一指示信号和第二指示信号均为AM指示信号为例进行说明。
具体的，图7为灰光光模块中oDSP芯片的结构示意图，如图7所示，由于Serdes11和DAC 17、或者Serdes18和ADC 24主要实现串行数据和并行数据间的转换，第一光模块每次上电且链路状态稳定后，Serdes11和DAC 17、或者Serdes18和ADC 24的时延相对固定，并不会受插拔光纤、插拔模块等因素的影响，因此，Serdes11和DAC17、或者Serdes18和ADC 24对应的时延(如图7中的路径A、路径F、路径C和路径D)可以为预先设定的设计值，也可以为通过仿真得出的仿真值，当然，还可以是一个默认值。
另外，映射电路14和解映射电路21主要实现多路低速通道向高速通道的映射以及解映射处理，由于映射采用的是比特交织方式，不会改变第一数据流的结构，每比特数据的时延会相同。但在光纤插拔、模块插拔、PVT(process,voltage,temperature工艺、电压、温度)变化等因素影响下，会导致同步处理FIFO电路13、16或者FIFO电路20、23的读写时钟相位发生变化，使得每级FIFO电路的时延不固定，从而引入时延非对称，因此在每次第一光模块的链路建立成功以及时钟状态出现变化时，均需要对oDSP芯片的时延进行测量。在一种可能的实现方式中，在测量报文在oDSP芯片的时延时，通常仅需要测量如图7中所示的路径B或路径E对应的时延。
也就是说，以测量报文在光发射器中oDSP芯片的时延为例，在实际应用中，在测量第一数据流从光发射器的入接口传输至光发射器的出接口的第一时延时，可以仅测量第一数据流在路径B中的时延，在测量出路径B对应的时延后，将路径B对应的时延、路径A对应的时延以及路径C对应的时延相加，即可得到第一数据流在光发射器中的传输时延。
示例性的，以第一指示信号和第二指示信号为AM指示信号为例进行说明。如图7所示，第一数据流通过多个通道到达通道对齐电路12，通道对齐电路12对多个通道中的第一数据流进行通道对齐处理后，通道选择模块55会从多个通道中选择其中的一个通道，并从选择的通道中检测第一数据流中携带的AM指示信号1，并将检测出的AM指示信号1发送给TX时延测量模块56。另外，为了能够在光发射器的出接口正确的提取该AM指示信号，还需要对该AM指示信号进行标识，其中，标识后的AM指示信号将携带在第一数据流中继续进行传输。当检测到第一数据流从FIFO电路16输出，即传输至DAC 17后，会通过AM提取模块53根据前述标识，从上述检测AM指示信号1的通道中提取第一数据流中携带的AM指示信号2，并将检测出的AM指示信号2发送给TX时延测量模块56。这样，TX时延测量模块56通过采用高精度的鉴相算法，测量AM指示信号1和AM指示信号2之间的相位差，即可确定出第一数据流在路径B中的时延。其中，测量精度取决于鉴相算法的精度，通常情况下，测量出的时延的精度可以达到百ps级。
其中，上述的AM指示信号1和AM指示信号2为同一个AM指示信号。
示例性的，在确定出第一数据流在路径B中的时延后，通过获取路径A和路径C的时延，并将路径A、路径C和路径B各自的时延相加，即可得到第一数据流在光发射器中传输的时延。
另外，值得注意的是，为了提高时延确定的准确性，在通道进行对齐处理，并从多个通道中选择其中的一个通道来提取AM指示信号时，可以选择第一数据流最晚到达通道对齐模块的那一个通道，来提取AM指示信号。
本领域技术人员可以理解，第一数据流在第一光模块光模块的光接收器中的传输时延，可以是路径D、路径E和路径F各自的时延相加后得到的值。其中，路径D和路径F的时延与光发射器中路径C和路径A的时延类似，可以是预先设定的设计值，也可以为通过仿真得出的仿真值，当然，还可以是一个默认值。对于路径E的时延，与发送方向的路径B的时延的确定方式类似，即在第一数据流传输至第一电路时，AM检测模块54提取第一数据流携带的AM指示信号3，并在第一数据流传输至第二电路时，AM提 取模块提取第一数据流携带的AM指示信号4，RX时延测量模块57通过测量AM指示信号3和AM指示信号4的相位差，即可确定出路径E的时延。其中，第一电路可以为FIFO电路，第二电路可以为串行/并行电路18。对于通道的选择过程以及AM指示信号的提取过程，可以参照光发射器中的描述，此处不再赘述。
进一步地，考虑到芯片实现的差异，在灰光光模块不具备测量路径B和路径E的时延的功能时，路径B和路径E的时延也可以为预先设定的设计值，或者为通过仿真得出的仿真值，当然，还可以是一个默认值。另外，由于路径B和路径E的实际时延在每次第一光模块的链路建立成功以及时钟状态出现变化后均会发生变化，因此，预先设定的设计值、仿真值或者默认值将不够精确。为了解决这一问题，在实际应用中，以预先设定的设计值为例，可以计算设计值的平均值，并将平均值作为路径B和路径E的时延，或者确定最小的设计值和最大的设计值，并将确定出的最小的设计值和最大的设计值均作为路径B和路径E的时延，以将这两个值均上报给接口芯片。对于仿真值和默认值的确定方式，与设计值的确定方式类似，此处不再赘述。
继续参照图6所示，第一光模块为彩光光模块时，由于彩光光模块内部有成帧器(Framer)和FEC等开销处理电路，开销增删处理会改变原始数据流的结构，导致增加开销(发送端)和删除开销(接收端)过程中每比特数据的处理时延均不相同。由于第一光模块接收的每比特数据都有可能是PTP报文打戳信号，这种时延的不固定使得无法单独测量第一光模块作为发送端时的时延，或者第一光模块作为接收端时的时延。然而，本领域技术人员可以理解的是，发送端数据映射引入的时延变化和接收端数据解映射引入的时延变化是相反过程，也就是说，同一比特数据在发送端和接收端处理时延之和是固定的。基于此，本申请实施例中可以采用第一光模块和第二光模块配对来测量时延。
其中，第一光模块为第一网络设备中的彩光光模块，第二光模块为第二网络设备中的彩光光模块，第一光模块包括光发射器和第一光接收器，第一光模块通过光发射器接收第一数据流，其中，第一数据流在光发射器中传输的时延为第二时延，然后第一光模块通过光发射器向第二网络设备中的第二光模块的第二光接收器发送该第一数据流，该第一数据流在第二光接收器中传输的时延为第三时延；其中，第二时延和第三时延相加所得的和为前述的第一时延；第一光模块通过第一光接收器接收第二网络设备发送的第二数据流，该第二数据流携带指示信息；相应的，第一光模块确定第一时延时，可以根据该第二数据流中携带的指示信息进行确定。
具体的，图8为彩光光模块中oDSP芯片的结构示意图，如图8所示，第一光模块67为第一网络设备中的彩光光模块，第一光模块包括光发射器210和光接收器220，其中，第一光模块67通过光发射器210接收到第一数据流后，会通过光发射器210向第二网络设备中的第二光模块96的第二光接收器230发送该第一数据流。这样，可以根据该第一数据流，测量出第一数据流在第一光模块67的光发射器210中传输的第二时延和第一数据流在第二光模块96的第二光接收器230中传输的第三时延。
其中，第二光模块96中包括光发射器240和光接收器230，其中，光发射器240中包括oDSP芯片97和ITLA 82，光接收器230中包括oDSP芯片95和和双滤光片切换器70。ITLA 82和双滤光片切换器70连接光纤。
其中，oDSP芯片97中包括有依次连接的串行/并行电路(serializing/deserializing circuitry；Serdes)93、通道对齐电路91、FIFO电路90、映射电路89、FIFO电路88、前向纠错FEC电路87、DSP电路86、FIFO电路85和DAC 83。oDSP芯片95中包括有依次连接的ADC 71、FIFO电路73、DSP电路74、FEC电路75、FIFO电路76、解映射电路77、FIFO电路78、通道分发电路79和串行/并行电路(Serdes)81。
示例性的，映射电路89可以通过成帧器(Framer)或者比特交织(BitMux)电路实现。类似的，解映射电路77可以通过解帧器(DeFramer)或者比特解交织(BitDeMux)电路实现。
可以理解的是，参考图8所示，由于第一光模块中发射器210包括有不同的处理电路，因此，上述第二时延可以为发射器210中不同的处理电路在对第一数据流进行处理的过程中引起的时延。同样的，第二光模块中光接收器230也包括有不同的处理电路，因此，上述第三时延可以为光接收器230中不同的处理电路在对第一数据流进行处理的过程中引起的时延。
具体的，如图8所示，上述第二时延可以为第一数据流从光发射器210的入接口传输到光发射器210的出接口的时延，也可以为光发射器210中包括的至少一个处理电路在对第一数据流进行处理时所引起的时延，当然，也可以为光发射器210中包括的至少一个处理电路在对第一数据流进行处理时所引起的时延与默认值或者设计值相加所得到的和。举例来说，该第二时延可以为第一数据流从串行/并行电路31传输至TOSA模块49的时延，也可以为oDSP芯片190中的各处理电路在对第一数据流进行处理时所引起的时延，也可以为oDSP芯片190中的通道对齐电路32、FIFO电路33、映射电路34、FIFO电路35、FEC电路36、DSP电路37、FIFO电路38对第一数据流进行处理时所引起的时延，与默认值或者设计值相加所得到的和。
上述第三时延可以为第一数据流从第二光接收器230的入接口传输到第二光接收器230的出接口的时延，也可以为第二光接收器230中包括的至少一个处理电路在对第一数据流进行处理时所引起的时延，当然，也可以为第二光接收器230中包括的至少一个处理电路在对第一数据流进行处理时所引起的时延与默认值或者设计值相加所得到的和。举例来说，该第三时延可以为第一数据流从双滤光片切换器70传输至串行/并行电路81的时延，也可以为oDSP芯片95中的各处理电路在对第一数据流进行处理时所引起的时延，也可以为oDSP芯片95中的DAC71、FIFO电路73、DSP电路74、FEC电路75、FIFO电路76、解映射电路77、FIFO电路78和通道分发电路79对第一数据流进行处理时所引起的时延，与默认值或者设计值相加所得到的和。
与灰光光模块类似，由于第一光模块和第二光模块中的oDSP芯片的时延存在不对称性和不确定性，故在实际应用中，在计算第一光模块和第二光模块的时延时，通常只需要确定第一光模块和第二光模块中的oDSP芯片对应的时延即可。
下面，将详细介绍第一数据流在第一光模块中的oDSP芯片中的时延和第一数据流在第二光模块中的oDSP芯片中的时延。
具体的，第一数据流在第一光模块中传输时，第一光模块在第一数据流传输至第一电路时，提取第一数据流中携带的第一指示信号，并在第一数据流传输至第二电路时，提取第一数据流中携带的第二指示信号，然后可以根据第一指示信号和第二指示 信号，确定第一数据流在第一光模块67中光发射器210中传输的第二时延。
进一步的，第一数据流在第二光模块中传输时，第二光模块在第一数据流传输至第三电路时，提取第一数据流中携带的第三指示信号，并在第一数据流传输至第四电路时，提取第一数据流中携带的第四指示信号，然后可以根据第三指示信号和第四指示信号，确定第一数据流在第二光模块96中第二光接收器230中传输的第三时延。
其中，第一电路和第二电路可以为oDSP芯片190中的任意两个不同的电路，如第一电路可以为图8中所示的通道对齐电路32、第二电路可以为FIFO电路38，此时，根据第一指示信号和第二指示信号之间的相位差，可以确定出第一数据流从通道对齐电路32传输至FIFO电路38的时延，对于其他电路的时延，可以采用默认值或者设计值。或者，第一电路也可以为FIFO电路33、第二电路也可以为FIFO电路38等，此时，根据第一指示信号和第二指示信号之间的相位差，可以确定出第一数据流从FIFO电路33传输至FIFO电路38的时延，同样的，对于其他电路的时延，可以采用默认值或者设计值。
类似的，第三电路和第四电路可以为oDSP芯片95中的任意两个不同的电路，如第三电路可以为图8中所示的FIFO电路73、第四电路可以为串行/并行电路81，此时，根据第一指示信号和第二指示信号之间的相位差，可以确定出第一数据流从FIFO电路73传输至串行/并行电路81的时延，对于其他电路的时延，可以采用默认值或者设计值。或者，第三电路也可以为信号处理电路74、第四电路也可以为串行/并行电路81等，此时，根据第一指示信号和第二指示信号之间的相位差，可以确定出第一数据流从信号处理电路74传输至串行/并行电路81的时延，同样的，对于其他电路的时延，可以采用默认值或者设计值。
继续参照图8所示，以第一光模块67向第二光模块96发送第一数据流的发送方向为例，第一光模块67中的路径A1和路径C1的时延，以及第二光模块96中的路径D2和路径F2的时延与灰光光模块中的Serdes11和DAC17、或者Serdes18和ADC 24对应的时延类似，可以为预先设定的设计值，也可以为通过仿真得出的仿真值，当然，还可以是一个默认值。因此，在测量第一数据流在第一光模块67的光发射器210的第二时延时，只需要测量路径B1对应的时延，在测量第一数据流在第二光模块96的第二光接收器230的第三时延时，只需要测量路径E2对应的时延即可。
具体的，在测量路径B1对应的时延时，以第一电路为通道对齐电路32、第二电路为DAC 39，第一指示信号为AM指示信号，第二指示信号为DSP帧头指示信号为例进行说明。如图8所示，第一数据流通过多个通道到达第一光模块67中的通道对齐电路32，通道对齐电路32对多个通道中的第一数据流进行通道对齐处理后，通道选择模块64将从多个通道中选择其中的一个通道，AM检测模块60在第一数据流传输至通道对齐电路32时，从选择的通道中检测第一数据流中携带的AM指示信号1，并将检测出的AM指示信号1发送给TX时延测量模块65。另外，为了能够在第二光模块96的第二接收器230的出接口正确的提取该AM指示信号，还需要对该AM指示信号进行标识，其中，标识后的AM指示信号将携带在第一数据流中继续进行传输。在第一光模块67的光发射器210的出接口会周期性的提取DSP帧头指示信号1，如在第一数据流传输至DAC 39后，会通过DSP帧头提取模块61提取第一数据流中携带的DSP帧头指示信号1，并将提取出的DSP帧头指示信号1发送给TX时延测量模块65，这样，TX时延测量模块65通过采用 高精度的鉴相算法，测量AM指示信号1和DSP帧头指示信号1之间的相位差，即可确定出第一数据流在路径B1中的时延。其中，测量精度取决于鉴相算法的精度，通常情况下，测量出的时延的精度可以达到百ps级。
值得注意的是，由于AM指示信号的周期与DSP帧头指示信号的周期不相同，因此，AM指示信号和DSP帧头指示信号之间没有固定的相位关系，为便于配对测量，需要从AM指示信号和DSP帧头指示信号中选择相邻的两个信号进行测量。举例来说，若AM指示信号的周期为3ms，DSP帧头指示信号的周期为1.2ms，则第一数据流中有可能在出现两个DSP帧头指示信号后，才会出现一个AM指示信号，此时，可以选择AM指示信号，以及与AM指示信号相邻的DSP帧头指示信号进行测量，如可以选择AM指示信号，以及第二个DSP帧头指示信号，并测量这两个信号之间的相位差。
另外，为了能够在第二光模块96的第二光接收器230的入接口正确的提取该DSP帧头指示信号，还需要在该DSP帧头信号中添加标识信息，并将添加了标识信息的第一数据流通过光纤发送给第二光模块96。
同样的，在测量路径E2对应的时延时，以第三电路为FIFO电路73、第四电路为串行/并行电路81，第三指示信号为DSP帧头指示信号，第四指示信号为AM指示信号为例进行说明。如图8所示，第一光模块67通过光发射器210将第一数据流发送给第二光模块96的第二光接收器230后，第一数据流通过第二光模块96中的ADC 71，并传输至FIFO电路73后，将根据第一光模块67的光发射器210中对DSP帧头指示信号所添加的标识信息，通过DSP帧头预检测模块72提取DSP帧头指示信号2，并将提取出的DSP帧头指示信号2发送给RX时延测量模块94。此时，第一数据流将继续进行传输，在检测到第一数据流传输至串行/并行电路81后，会通过AM提取模块80根据第一光模块67的光发射器210中对AM所添加的标识信息，从通道中提取第一数据流中携带的AM指示信号2，并将提取出的AM指示信号2发送给RX时延测量模块94，这样，RX时延测量模块94通过采用高精度的鉴相算法，测量DSP帧头指示信号2和AM指示信号2之间的相位差，即可确定出第一数据流在路径E2中的时延。其中，测量精度取决于鉴相算法的精度，通常情况下，测量出的时延的精度可以达到百ps级。
其中，上述的AM指示信号1和AM指示信号2为同一个AM指示信号，DSP帧头指示信号1和DSP帧头指示信号2为同一个指示信号。
另外，第二指示信息和第四指示信息也可以采用其他便于识别的数据标识，如在第一数据流中新插入一个标识符等，对于第二指示信息和第四指示信息的具体形式，本申请实施例在此不做限制。
示例性的，在确定出第一数据流在路径B1中的时延后，通过获取路径A1和路径C1的时延，并将路径A1、路径C1和路径B1各自的时延相加，即可得到第一数据流在第一光模块的光发射器中传输的第二时延。
示例性的，在确定出第一数据流在路径E2中的时延后，通过获取路径D2和路径F2的时延，并将路径D2、路径E2和路径F2各自的时延相加，即可得到第一数据流在第二光模块的第二光接收器中传输的第三时延。
需要进行说明的是，第一光模块在确定出第一数据流在光发射器210中的第二时延后，会将该第二时延携带在第一数据流中发送给第二光模块96的第二接收器230，第二 光模块在确定出第一数据流在第二接收器230中的第三时延后，将得到的第二时延和第三时延相加所得的和，确定为第一时延。
在一种可能的实现方式中，第二光模块的第二光接收器230在确定出第一时延后，向第一光模块67的第一光接收器220发送第二数据流，该第二数据流中携带有指示信息，这样，第一光模块可以根据该指示信息，确定出第一时延。在一种可能的实现方式中，该指示信息中包括有第一时延，第一光模块67在通过第一光接收器220接收到第二数据流中的指示信息后，即可直接确定出第一时延。
值得注意的是，与灰光光模块类似，若彩光光模块不具备测量路径B1和路径E2的时延的功能时，路径B1和路径E2的时延也可以为预先设定的设计值，或者为通过仿真得出的仿真值，当然，还可以是一个默认值。
本领域技术人员可以理解，第二光模块96通过光发射器240向第一光模块67的第一光接收器220发送第一数据流时，第一时延可以为第一数据流在第二光模块96的光发射器240的传输时延，与第一数据流在第一光模块67的第一光接收器220中的传输时延的和。其中，第一数据流在第二光模块96的光发射器240的传输时延为路径A2、路径B2和路径C2各自对应的时延的加和，第一数据流在第一光模块67的第一光接收器220中的时延为路径D1、路径E1和路径F1各自对应的时延的加和。其中，路径A2、路径C2、路径D1和路径F1各自的时延，与前述的路径A1、路径C1、路径D2和路径F2的时延类似，可以是预先设定的设计值，也可以为通过仿真得出的仿真值，当然，还可以是一个默认值。对于第二光模块96的光发射器240中的路径B2和第一光模块67的第一光接收器220中的路径E1的时延，与前述的第一光模块67的光发射器210中的路径B1和第二光模块96的第二光接收器230中的路径E2的时延的确定方式类似，此处不再赘述。
步骤202、第一光模块向接口芯片发送第一时延。
在本实施例中，由于第一光模块中定义有时延上报寄存器访问接口，因此，第一光模块在确定出第一时延后，将通过第一光模块的时延上报寄存器访问接口，向接口芯片发送该第一时延，以使接口芯片将该第一时延补偿到记录时戳中，这样，MDI层记录的时戳中包括了报文在光模块中传输的时延，使得MDI层记录的时间戳更准确，由此可以使主从时钟时间同步精度更高，从而可以进一步提高网络设备的时钟精度。
在一种可能的实现方式中，接口芯片包括PHY芯片和MAC芯片中的至少一个。
在一种可能的实现方式中，第一光模块的时延上报寄存器访问接口可以按照下表中的方式进行定义：
Figure PCTCN2019129697-appb-000001
Figure PCTCN2019129697-appb-000002
其中，接口位宽用于表示接口信号的比特数。对于不支持时延上报的光模块来说，时延上报寄存器访问接口的上报值为固定值0。对于支持时延上报的光模块，又可以划分为不支持时延测量的光模块和支持时延测量的光模块两种类型，对于不支持时延测量的光模块，其上报的第一时延为oDSP芯片的设计值，对于支持时延测量的光模块，其上报的第一时延为通过指示信息得到的测量值。
进一步地，若第一光模块为灰光光模块，则第一光模块在确定出第一时延后，即可根据上述定义的接口向接口芯片上报该第一时延。接口芯片在接收到第一时延后，可以将该第一时延以及报文在MAC层或PHY层中传输的时延共同补偿到MAC层或PHY层记录的时戳中，这样，可以大大降低光模块引入的不对称误差，使得MDI层记录的时 间戳更准确，由此可以使主从时钟时间同步精度更高，从而可以进一步提高网络设备的时钟精度。。
若第一光模块为彩光光模块，该第一时延为第一数据流在第一光模块的光发射器中传输的时延和第一数据流在第二光模块的第二光接收器中传输的时延的加和。在一种实现方式中，若第二光模块通过第二数据流将测量出的第一时延发送给第一光模块，则第一光模块可以通过第一光模块中定义的时延上报寄存器访问接口向接口芯片上报该第一时延。此时，第二光模块可以通过第二光模块中定义的时延上报寄存器访问接口向接口芯片上报该第一时延，也可以上报0、或上报特殊标识符，当然，第二光模块也可以什么都不上报。
在另一种实现方式中，若第二光模块通过第二光模块中定义的时延上报寄存器访问接口向接口芯片上报该第一时延，此时，第一光模块可以通过第一光模块中定义的时延上报寄存器访问接口向接口芯片上报该第一时延，也可以上报0，或上报特殊标识符，当然，第一光模块也可以什么都不上报。
在又一种实现方式中，第一光模块和第二光模块可以按照预设的规则，将第一时延分为两部分，其中，第一部分由第一光模块通过第一光模块中定义的时延上报寄存器访问接口向接口芯片上报，第二部分由第二光模块通过第二光模块中定义的时延上报寄存器访问接口向接口芯片上报。
本申请实施例提供的通信方法，第一光模块在确定出第一时延后，将向接口芯片发送确定出的第一时延。由于在第一光模块中定义了时延上报寄存器访问接口，这样，第一光模块可以通过该时延上报寄存器访问接口向MAC层或PHY层上报第一时延，以将该第一时延补偿到MAC层或PHY层记录的报文的时戳中，由此可以提高主从时钟时间同步的精度，从而可以进一步提高网络设备的时钟精度。
上文描述了本申请实施例提供的通信方法，下文将描述本申请实施例提供的光模块。
本申请实施例提供的光模块，用作第一光模块，可以用于执行上述方法实施例中第一光模块相关的动作，该光模块包括：处理器101。
处理器101，用于确定第一时延；
所述处理器101，还用于向接口芯片发送所述第一时延。
本申请实施例提供的光模块，在确定出第一时延后，将向接口芯片发送确定出的第一时延。由于在光模块中定义了时延上报寄存器访问接口，这样，光模块可以通过该时延上报寄存器访问接口向MAC层或PHY层上报第一时延，可以将该第一时延补偿到MAC层或PHY层记录的报文的时戳中，由此可以提高主从时钟时间同步的精度，从而可以进一步提高网络设备的时钟精度。
图9为本申请实施例提供的一种光模块的结构示意图，参见图9，所述第一光模块10为灰光光模块，该第一光模块10包括：光发射器102，所述光发射器102包括所述处理器101、入接口1021和出接口1022，其中：
所述光发射器102用于通过所述入接口1021接收第一数据流；
所述光发射器102还用于通过所述出接口1022向第二网络设备发送所述第一数据 流；
所述处理器101，还用于确定所述第一数据流在所述光发射器102中传输的时延为所述第一时延。
图10为本申请实施例提供的另一种光模块的结构示意图，参见图10，所述第一光模块20为第一网络设备中的彩光光模块，该第一光模块20包括：光发射器103和第一光接收器104，所述第一光接收器104包括所述处理器101，其中：
所述光发射器103用于接收第一数据流，所述第一数据流在所述光发射器103中传输的时延为第二时延；
所述光发射器103还用于向第二网络设备中的第二光模块的所述第二光接收器发送所述第一数据流，所述第一数据流在所述第二光接收器中传输的时延为第三时延；
其中，所述第二时延和所述第三时延相加所得的和为所述第一时延；
所述第一光接收器104用于接收所述第二网络设备发送的第二数据流，所述第二数据流携带指示信息；
所述处理器101具体用于根据所述指示信息，确定所述第一时延。
作为一个实施例，所述指示信息中包括所述第一时延。
作为一个实施例，所述光模块不支持时延测量时，所述第一时延为设计值。
图11为本申请实施例提供的又一种光模块的结构示意图，参见图11，在图10所示实施例的基础上，所述光发射器103包括第一电路1031和第二电路1302，所述处理器101，还用于：
在所述第一数据流传输至所述第一电路时，提取所述第一数据流中携带的第一指示信号；
在所述第一数据流传输至第二电路时，提取所述第一数据流中携带的第二指示信号；
根据所述第一指示信号和所述第二指示信号，确定所述第一时延。
作为一个实施例，所述处理器101，还用于：
测量所述第一指示信号和所述第二指示信号之间的相位差；
根据所述相位差确定所述第一时延；
其中，所述第一指示信号和所述第二指示信号均为对齐标识AM指示信号，或者，所述第一指示信号为AM指示信号，所述第二指示信号为数字信号处理DSP帧头信号。
作为一个实施例，所述接口芯片包括物理层PHY芯片和媒质接入控制层MAC芯片中的至少一个。
其中，上述的处理器101可以为是被配置成实施以上方法的一个或多个集成电路，例如：oDSP，或，一个或多个特定集成电路(application specific integrated circuit，ASIC)，或，一个或多个微处理器(digital singnal processor，DSP)，或，一个或者多个现场可编程门阵列(field programmable gate array，FPGA)等。再如，该处理器还可以是中央处理器(central processing unit，CPU)或其它可以调用程序的处理器。
本申请实施例提供的光模块，可以执行上述对应的方法实施例，其实现原理和技术效果类似，在此不再赘述。
本申请实施例还提供一种计算机可读存储介质，其上存储有计算机程序，该程序被 处理器执行时可以实现上述方法实施例提供的通信方法中与第一光模块相关的流程。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请实施例的范围。
此外，本申请实施例的各个方面或特征可以实现成方法、装置或使用标准编程和/或工程技术的制品。本申请中使用的术语“制品”涵盖可从任何计算机可读器件、载体或介质访问的计算机程序。例如，计算机可读介质可以包括，但不限于:磁存储器件(例如，硬盘、软盘或磁带等)，光盘(例如，压缩盘(compact disc，CD)、数字通用盘(digital versatile disc，DVD)等)，智能卡和闪存器件(例如，可擦写可编程只读存储器(erasable programmable read-only memory，EPROM)、卡、棒或钥匙驱动器等)。另外，本文描述的各种存储介质可代表用于存储信息的一个或多个设备和/或其它机器可读介质。术语“机器可读介质”可包括但不限于，无线信道和能够存储、包含和/或承载指令和/或数据的各种其它介质。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
应理解，在本申请实施例的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络 单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者接入网设备等)执行本申请实施例各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (30)

  1. 一种通信方法，其特征在于，包括：
    第一网络设备中的第一光模块确定第一时延；
    所述第一光模块通过时延上报接口向所述第一网络设备中的接口芯片发送所述第一时延。
  2. 根据权利要求1所述的方法，其特征在于，所述第一光模块包括光发射器，所述光发射器包括入接口和出接口，所述第一光模块确定第一时延，包括：
    所述第一光模块通过所述入接口接收第一数据流；
    所述第一光模块通过所述出接口向第二网络设备发送所述第一数据流；
    所述第一光模块确定所述第一数据流在所述光发射器中传输的时延为所述第一时延。
  3. 根据权利1所述的方法，其特征在于，所述第一光模块包括光发射器,所述第一光模块确定第一时延,包括:
    所述光发射器接收第一数据流；
    所述第一时延包括所述光发射器中至少一个电路对所述第一数据流进行处理所引起的时延。
  4. 根据权利要求3所述的方法，其特征在于，所述光发射器包括数字信号处理模块，所述至少一个电路包括所述数字信号处理模块中的至少一个电路。
  5. 根据权利要求1所述的方法，其特征在于，所述第一光模块包括光接收器，所述第一光模块通过时延上报接口向接口芯片发送所述第一时延包括：
    所述光接收器通过所述时延上报接口向所述接口芯片发送所述第一时延。
  6. 根据权利要求5所述的方法，其特征在于，所述方法包括：
    所述光接收器接收第二网络设备的第二光模块的光发射器发送的第二数据流；
    所述第一时延包括所述光接收器中至少一个电路对所述第二数据流进行处理所引起的时延。
  7. 根据权利要求6所述的方法，其特征在于，所述光接收器包括数字信号处理模块，所述至少一个电路包括所述数字信号处理模块中的至少一个电路。
  8. 根据权利要求5-7任一项所述的方法，其特征在于，所述第二数据流在所述第二光模块的光发射器中传输时延包括第二时延，所述第二数据流在所述第一光模块的光接收器中传输的时延包括第三时延，所述第一时延包括所述第二时延和所述第三时延。
  9. 根据权利要求1所述的方法，其特征在于，所述第一光模块包括光发射器和第一光接收器；
    所述第一光模块确定第一时延之前，所述方法还包括：
    所述第一光模块通过所述光发射器接收第一数据流，所述第一数据流在所述光发射器中传输的时延包括第二时延；
    所述第一光模块通过所述光发射器向第二网络设备中的第二光模块的第二光接收器发送所述第一数据流，所述第一数据流在所述第二光接收器中传输的时延包括第三时延；
    所述第一光模块通过所述第一光接收器接收所述第二网络设备发送的第二数据流，所述第二数据流携带指示信息；
    所述第一光模块确定第一时延，包括：
    所述第一光模块根据所述指示信息，确定所述第一时延，所述第一时延包括所述第二时延和所述第三时延。
  10. 根据权利要求1-4任一项所述的方法，其特征在于，所述第一光模块包括第一电路和第二电路，所述方法还包括：
    所述第一光模块在所述第一数据流传输至所述第一电路时，提取所述第一数据流中携带的第一指示信号；
    所述第一光模块在所述第一数据流传输至所述第二电路时，提取所述第一数据流中携带的第二指示信号；
    所述第一光模块根据所述第一指示信号和所述第二指示信号，确定所述第一时延。
  11. 根据权利要10所述的方法，其特征在于，所述根据所述第一指示信号和所述第二指示信号，确定所述第一时延，包括：
    测量所述第一指示信号和所述第二指示信号之间的相位差；
    根据所述相位差确定所述第一时延。
  12. 根据权利要求10或11所述的方法，其特征在于，其中，所述第一指示信号和所述第二指示信号均为对齐标识AM指示信号，或者，所述第一指示信号为AM指示信号，所述第二指示信号为数字信号处理DSP帧头信号，或者，所述第一指示信息和所述第二指示信号为帧起始定界符SFD。
  13. 根据权利要求1-12任一项所述的方法，其特征在于，所述接口芯片包括用于实现物理层PHY功能或媒质接入控制层MAC功能的芯片。
  14. 根据权利要求1-13任一项所述的方法，其特征在于，所述第一光模块上报所述第一时延，包括：
    当所述第一光模块的时钟状态发生变化时，向所述接口芯片上报所述第一时延；或者
    在所述第一光模块的链路建立成功时，向所述接口芯片上报所述第一时延。
  15. 根据权利要求1-14任一项所述的方法，其特征在于，所述第一时延是光模块用于发送数据时的发送时延最大值或发送时延最小值；或者所述第一时延是所述光模块用于接收数据时的接收时延最大值或接收时延最小值。
  16. 一种第一网络设备中的光模块，用作第一光模块，其特征在于，包括：
    处理，用于确定第一时延；
    所述时延上报接口，还用于向所述第一网络设备中的接口芯片发送所述第一时延。
  17. 根据权利要求16所述的光模块，其特征在于，所述第一光模块包括光发射器，所述光发射器包括所述处理器、所述时延上报接口、入接口和出接口，其中：
    所述入接口用于接收第一数据流；
    所述出接口用于向第二网络设备发送所述第一数据流；
    所述处理器，用于确定所述第一数据流在所述光发射器中传输的时延为所述第一时延。
  18. 根据权利要求16所述的光模块，其特征在于，所述第一光模块包括光发射器，所述光发射器包括所述处理器、所述时延上报接口、入接口和出接口，
    所述入接口用于接收第一数据流；
    所述出接口用于向第二网络设备发送所述第一数据流；其中，
    所述第一时延包括所述光发射器中至少一个电路对所述第一数据流进行处理所引起的时延。
  19. 根据权利要求18所述的光模块，其特征在于，所述光发射器包括数字信号处理模块，所述至少一个电路包括所述数字信号处理模块中的至少一个电路。
  20. 根据权利要求16所述的光模块，其特征在于，所述第一光模块包括光接收器，所述光接收器包括所述处理器和所述时延上报接口。
  21. 根据权利要求20所述的光模块，其特征在于，所述光接收器包括入接口，
    所述入接口用于接收第二网络设备的第二光模块中光发射器发送的第二数据流；其中，所述第一时延包括所述光接收器中至少一个电路对所述第二数据流进行处理所引起的时延。
  22. 根据权利要求21所述的光模块，其特征在于，所述光接收器包括数字信号处理模块，所述至少一个电路包括所述数字信号处理模块中的至少一个电路。
  23. 根据权利要求21或22所述的光模块，其特征在于，所述第二数据流在所述第二光模块的光发射器中传输时延包括第二时延，所述第二数据流在所述第一光模块的光接收器中传输的时延包括第三时延，所述第一时延包括所述第二时延和所述第三时延。
  24. 根据权利要求16所述的光模块，其特征在于，所述第一光模块为第一网络设备中的光模块，所述第一光模块包括光发射器和第一光接收器，所述第一光接收器包括所述处理器和所述时延上报接口；
    所述光发射器，用于接收第一数据流，所述第一数据流在所述光发射器中传输的时延包括第二时延；
    所述光发射器，还用于向第二网络设备中的第二光模块的所述第二光接收器发送所述第一数据流，所述第一数据流在所述第二光接收器中传输的时延包括第三时延；
    所述第一光接收器，用于接收所述第二网络设备发送的第二数据流，所述第二数据流携带指示信息；
    所述处理器，具体用于根据所述指示信息，确定所述第一时延，所述第一时延包括所述第二时延和所述第三时延。
  25. 根据权利要求16-19所述的光模块，其特征在于，所述第一光模块包括第一电路和第二电路；所述处理器，还用于：
    在所述第一数据流传输至所述第一电路时，提取所述第一数据流中携带的第一指示信号；
    在所述第一数据流传输至第二电路时，提取所述第一数据流中携带的第二指示信号；
    根据所述第一指示信号和所述第二指示信号，确定所述第一时延。
  26. 根据权利要求25所述的光模块，其特征在于，所述处理器，还用于：
    测量所述第一指示信号和所述第二指示信号之间的相位差；
    根据所述相位差确定所述第一时延；
    其中，所述第一指示信号和所述第二指示信号均为对齐标识AM指示信号，或者，所述第一指示信号为AM指示信号，所述第二指示信号为数字信号处理DSP帧头信号，或者，所述第一指示信息和所述第二指示信号为帧起始定界符SFD。
  27. 根据权利要求16-26任一项所述的光模块，其特征在于，所述接口芯片包括用于实现物理层PHY或媒质接入控制层MAC功能的芯片。
  28. 根据权利要求16-27任一项所述的光模块，其中，
    所述时延上报接口，用于；
    在所述第一光模块的时钟状态发生变化时，向所述接口芯片上报所述第一时延；或者
    在所述第一光模块的链路建立成功时，向所述接口芯片上报所述第一时延。
  29. 根据权利要求16-28任一项所述的光模块，其中，所述第一时延是光模块用于发送数据时的发送时延最大值或发送时延最小值；或者所述第一时延是所述光模块用于接收数据时的接收时延最大值或接收时延最小值。
  30. 一种网络设备，其特征在于，包括权利要求16-29任一项所述的光模块。
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