WO2020151050A1 - Goa电路以及液晶显示装置 - Google Patents

Goa电路以及液晶显示装置 Download PDF

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Publication number
WO2020151050A1
WO2020151050A1 PCT/CN2019/076913 CN2019076913W WO2020151050A1 WO 2020151050 A1 WO2020151050 A1 WO 2020151050A1 CN 2019076913 W CN2019076913 W CN 2019076913W WO 2020151050 A1 WO2020151050 A1 WO 2020151050A1
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Prior art keywords
pull
circuit
electrically connected
goa
control circuit
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PCT/CN2019/076913
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English (en)
French (fr)
Inventor
刘全胜
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Publication of WO2020151050A1 publication Critical patent/WO2020151050A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present disclosure relates to the field of display technology, in particular to a GOA circuit and a liquid crystal display device.
  • GOA gate driver on array
  • the existing GOA circuit includes a plurality of GOA modules, and each GOA module is used to provide a scan signal to a scan line.
  • the falling time of the output waveform of the GOA module is an important factor for judging the quality of the output waveform of the GOA module. When the falling time is shorter, the GOA module can turn off the thin film transistor electrically connected to the scan line faster, and the risk of pixel mischarging is lower. However, the fall time of the output waveform of the existing GOA module is not short enough.
  • the purpose of the present disclosure is to provide a GOA circuit and a liquid crystal display device, which can solve the problem of insufficient fall time of the output waveform of the existing GOA module.
  • a GOA circuit includes a plurality of cascaded GOA modules, each of the plurality of GOA modules includes: a pull-up control circuit for precharging the precharge point of the module; A pull-up circuit, electrically connected to the pull-up control circuit and used to increase the gate output of the GOA module; a pull-down circuit, electrically connected to the pull-up control circuit and the pull-up circuit and used to The precharge point and the gate output are pulled down to a low level; a pull-down sustaining circuit is electrically connected to the pull-up control circuit, the pull-up circuit, and the pull-down circuit; the bootstrap capacitor is electrically connected to The pull-up control circuit, the pull-up circuit, the pull-down circuit, and the pull-down sustain circuit are used to raise the gate output to a first high level; and a coupling circuit electrically connected to the upper The pull-up control circuit, the pull-up circuit, the pull-down circuit, the pull-down sustain circuit, and the bootstrap
  • the coupling circuit includes: a first transistor, the gate of the first transistor is electrically connected to the precharge point, the source of the first transistor is electrically connected to a clock signal; and a first capacitor is electrically connected Connected between the drain of the first transistor and the precharge point.
  • the clock signal is different from the clock signal input to the GOA module.
  • the pull-down sustain circuit is used to maintain the precharge point and the gate output at the low level.
  • a GOA circuit includes a plurality of cascaded GOA modules, each of the plurality of GOA modules includes: a pull-up control circuit for precharging the precharge point of the module; A pull-up circuit, electrically connected to the pull-up control circuit and used to increase the gate output of the GOA module; a pull-down circuit, electrically connected to the pull-up control circuit and the pull-up circuit; a pull-down sustain circuit, Are electrically connected to the pull-up control circuit, the pull-up circuit, and the pull-down circuit; a bootstrap capacitor is electrically connected to the pull-up control circuit, the pull-up circuit, the pull-down circuit, and the A pull-down sustaining circuit and used for raising the gate output to a first high level; and a coupling circuit, electrically connected to the pull-up control circuit, the pull-up circuit, the pull-down circuit, and the pull-down sustain circuit And the bootstrap capacitor are used to raise the precharge point to a second high level, and
  • the coupling circuit includes: a first transistor, the gate of the first transistor is electrically connected to the precharge point, and the source of the first transistor is electrically connected to a clock signal; and
  • the first capacitor is electrically connected between the drain of the first transistor and the precharge point.
  • the clock signal is different from the clock signal input to the GOA module.
  • the pull-down circuit is used to pull the precharge point and the gate output to a low level.
  • the pull-down sustain circuit is used to maintain the precharge point and the gate output at the low level.
  • a liquid crystal display device includes: a plurality of source lines; a plurality of gate lines, the plurality of source lines and the plurality of gate lines define a plurality of pixels; and
  • the GOA circuit is electrically connected to the plurality of gate lines and used to provide scan signals to the plurality of gate lines
  • the GOA circuit includes a plurality of cascaded GOA modules, each of the plurality of GOA modules includes : A pull-up control circuit, used to precharge the precharge point of the module; a pull-up circuit, electrically connected to the pull-up control circuit and used to increase the gate output of the GOA module; a pull-down circuit, electrical Connected to the pull-up control circuit and the pull-up circuit; a pull-down sustaining circuit, electrically connected to the pull-up control circuit, the pull-up circuit, and the pull-down circuit; a bootstrap capacitor, electrically connected to all The pull-up control circuit, the pull-up circuit, the pull-down circuit, and
  • the coupling circuit includes: a first transistor, the gate of the first transistor is electrically connected to the precharge point, and the source of the first transistor is electrically connected to a clock signal; and
  • the first capacitor is electrically connected between the drain of the first transistor and the precharge point.
  • the clock signal is different from the clock signal input to the GOA module.
  • the pull-down circuit is used to pull the precharge point and the gate output to a low level.
  • the pull-down sustain circuit is used to maintain the precharge point and the gate output at the low level.
  • the coupling circuit can be coupled again on the basis of the precharge point (that is, the second coupling), it can reduce the The fall time of the gate output of the GOA module, thereby reducing the risk of incorrect charging of the pixel.
  • the GOA circuit and the liquid crystal display device of the present disclosure can raise the level of the precharge point again, thereby making the waveform output by the gate more ideal.
  • FIG. 1 shows a liquid crystal display device according to an embodiment of the present disclosure.
  • Figure 2 shows the circuit diagram of a GOA module in Figure 1.
  • FIG. 3 shows the voltage curve C1 of the gate output of the GOA module of the present disclosure and the voltage curve C2 of the gate output of the existing GOA module.
  • Fig. 4 shows the voltage curve C1' of the precharge point of the GOA module of the present disclosure and the voltage curve C2' of the precharge point of the existing GOA module.
  • FIG. 1 shows a liquid crystal display device according to an embodiment of the present disclosure.
  • the liquid crystal display device has a display area 10 and a non-display area 30.
  • the display device includes a plurality of source lines S1-SN, a plurality of gate lines G1-GM, at least one source driving unit 12 (one source driving unit 12 is shown in the figure), and an array substrate row driving circuit (Gate driver On Array, hereinafter referred to as GOA circuit) 14.
  • GOA circuit array driver On Array
  • the plurality of source lines S1-SN and the plurality of gate lines G1-GM are arranged on the display area 10. More specifically, the plurality of source lines S1-SN are arranged on the display area 10 and extend to the source driving unit 12. The plurality of gate lines G1-GM are arranged on the display area 10 and extend to the plurality of gate driving units 14. The plurality of source lines S1-SN are formed along a first direction. The plurality of gate lines G1-GM are formed along a second direction. The first direction is perpendicular to the second direction. The plurality of source lines S1-SN and the plurality of gate lines G1-GM define a plurality of pixels 16. Each of the pixels 16 is electrically connected to a thin film transistor 18.
  • the source driving unit 12 is disposed on the non-display area 30 and is electrically connected to the first ends of the source lines S1-SN.
  • the source driving unit 12 is used to provide data voltages to the plurality of source lines S1-SN, and the data voltages are used to write the pixels 16.
  • the GOA circuit 14 is arranged on the non-display area 30.
  • the GOA circuit 14 is electrically connected to the plurality of gate lines G1-GM and used to provide scan signals to the plurality of gate lines G1-GM.
  • the GOA circuit 14 includes a plurality of cascaded GOA modules 140. Each level of GOA module receives the corresponding clock signal.
  • FIG. 2 shows a circuit diagram of a GOA module 140 in FIG.
  • the GOA module 140 includes a pull-up control circuit 142, a pull-up circuit 144, a pull-down circuit 146, a pull-down sustain circuit 148, a bootstrap capacitor Cb, and a coupling circuit 150.
  • the pull-up control circuit 142 is used to precharge the precharge point Q of the GOA module 140.
  • the pull-up control circuit 142 is usually electrically connected to the downstream signal transmitted by the GOA module 140 at the upper level.
  • the pull-up circuit 144 is electrically connected to the pull-up control circuit 142 and is used to increase the gate output OUT of the GOA module 140 of the current stage.
  • the gate output OUT is used to turn on the thin film transistor 18 electrically connected to the scan line corresponding to the GOA module 140.
  • the pull-down circuit 146 is electrically connected to the pull-up control circuit 142 and the pull-up circuit 144 and is used to pull the precharge point Q and the gate output OUT down to a low level VSS, thereby preventing
  • the thin film transistor 18 electrically connected to the scan line corresponding to the GOA module 140 is turned on.
  • the pull-down sustain circuit 148 is electrically connected to the pull-up control circuit 142, the pull-up circuit 144, and the pull-down circuit 146, and is used to maintain the precharge point Q and the gate output OUT at the Low level VSS.
  • the bootstrap capacitor Cb is electrically connected to the pull-up control circuit 142, the pull-up circuit 144, the pull-down circuit 146, and the pull-down sustain circuit 148 and is used to output the gate of the GOA module 140 to OUT Promote to a first high level (first coupling).
  • the GOA module 140 of the present disclosure further includes the coupling circuit 150.
  • the coupling circuit 150 is electrically connected to the pull-up control circuit 142, the pull-up circuit 144, the pull-down circuit 146, the pull-down sustain circuit 148, and the bootstrap capacitor Cb and is used to precharge the Point Q is raised to a second high level.
  • the second high level is higher than the first high level.
  • the coupling circuit 150 includes a first transistor T1 and a first capacitor C1.
  • the gate of the first transistor T1 is electrically connected to the precharge point Q.
  • the source of the first transistor T1 is electrically connected to a clock signal input to the GOA module 140 of another stage.
  • the clock signal electrically connected to the source of the first transistor T1 is different from the clock signal input to the GOA module 140 of this stage.
  • the source of the first transistor T1 is electrically connected to the clock signal CK(k+1) of the GOA module 140 of the next stage.
  • the drain of the first transistor T1 is electrically connected to the precharge point Q.
  • the first capacitor C1 is electrically connected between the drain of the first transistor T1 and the precharge point Q and is used to couple the output voltage of the first transistor T1 to the precharge point Q.
  • the coupling circuit 150 can be coupled again on the basis of the precharge point Q (that is, the second coupling), the fall time of the gate output OUT of the GOA module 140 can be reduced, and the GOA module The faster 140 can turn off the thin film transistor electrically connected to the scan line, the lower the risk of incorrect charging of the pixel 16 is.
  • the coupling circuit 150 can perform coupling again on the basis of the precharge point Q (that is, the second coupling), the level of the precharge point Q can be raised again, thereby causing the gate
  • the waveform of the pole output OUT is more ideal.
  • FIG. 3 shows the voltage curve C1 of the gate output OUT of the GOA module 140 of the present disclosure and the voltage curve C2 of the gate output of the existing GOA module.
  • the fall time of the gate output OUT of the GOA module 140 of the present disclosure is shorter than the fall time of the gate output of the existing GOA module, which can be reduced by about 10%.
  • FIG. 4 shows the voltage curve C1' of the precharge point Q of the GOA module 140 of the present disclosure and the voltage curve C2' of the precharge point of the existing GOA module.
  • the final voltage (the highest voltage) of the precharge point Q of the GOA module 140 of the present disclosure is higher than the final voltage of the precharge point of the existing GOA module.
  • the coupling circuit can be coupled again on the basis of the pre-charge point (that is, the second coupling)
  • the gate output of the GOA module can be reduced The fall time, thereby reducing the risk of incorrect charging of the pixels.
  • the GOA circuit and the liquid crystal display device of the present disclosure can raise the level of the precharge point again, thereby making the waveform output by the gate more ideal.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种GOA电路(14)以及液晶显示装置，包括多个级联的GOA模块(140)，每一GOA模块(140)包括：上拉控制电路(142)，用于对GOA模块(140)的预充点Q预充电；上拉电路(144)，用于提高GOA模块(140)的栅极输出OUT；下拉电路(146)；下拉维持电路(148)；自举电容Cb用于将栅极输出OUT提升为第一高电平；以及耦合电路(150)，用于将预充点Q提升为第二高电平，第二高电平高于第一高电平。

Description

GOA电路以及液晶显示装置 技术领域
本揭示涉及显示技术领域，特别是涉及一种GOA电路以及液晶显示装置。
 背景技术
一种驱动液晶显示装置的扫描线的技术为阵列基板行驱动（Gate driver On Array，GOA）技术。GOA技术是指将栅极驱动电路直接制作于液晶显示装置之阵列基板上，因此不需要外接的栅极驱动集成电路。由于可以直接利用现有的制程将栅极驱动电路制作于阵列基板上，因此可降低制造成本且适用于窄边框及薄型化的液晶显示装置。
现有GOA电路包括多个GOA模块，每个GOA模块用于提供一扫描信号给一条扫描线。GOA模块的输出波形的下降时间（falling time）是判断GOA模块的输出波形优劣的重要因素。当下降时间越短，GOA模块可以越快将与扫描线电性连接的薄膜晶体管不导通，像素错充的风险就越低。然而现有GOA模块的输出波形的下降时间不够短的问题。
因此需要对现有技术的问题提出解决方法。
 技术问题
本揭示的目的在于提供一种GOA电路以及液晶显示装置，其能解决现有GOA模块的输出波形的下降时间不够短的问题。
 技术解决方案
为解决上述问题，本揭示提供的一种GOA电路包括多个级联的GOA模块，每一所述多个GOA模块包括：上拉控制电路，用于对所述模块的预充点预充电；上拉电路，电性连接至所述上拉控制电路并用于提高所述GOA模块的栅极输出；下拉电路，电性连接至所述上拉控制电路及所述上拉电路并用于将所述预充点及所述栅极输出拉低至低电平；下拉维持电路，电性连接至所述上拉控制电路、所述上拉电路及所述下拉电路；自举电容，电性连接至所述上拉控制电路、所述上拉电路、所述下拉电路及所述下拉维持电路并用于将所述栅极输出提升为第一高电平；以及耦合电路，电性连接至所述上拉控制电路、所述上拉电路、所述下拉电路、所述下拉维持电路及所述自举电容并用于将所述预充点提升为第二高电平，所述第二高电平高于所述第一高电平。所述耦合电路包括：第一晶体管，所述第一晶体管的栅极电性连接至所述预充点，所述第一晶体管的源极电性连接至时钟信号；以及第一电容，电性连接于所述第一晶体管的漏极与所述预充点之间。
于一实施例中，所述时钟信号与输入至所述GOA模块的时钟信号不同。
于一实施例中，所述下拉维持电路用于将所述预充点及所述栅极输出维持在所述低电平。
为解决上述问题，本揭示提供的一种GOA电路包括多个级联的GOA模块，每一所述多个GOA模块包括：上拉控制电路，用于对所述模块的预充点预充电；上拉电路，电性连接至所述上拉控制电路并用于提高所述GOA模块的栅极输出；下拉电路，电性连接至所述上拉控制电路及所述上拉电路；下拉维持电路，电性连接至所述上拉控制电路、所述上拉电路及所述下拉电路；自举电容，电性连接至所述上拉控制电路、所述上拉电路、所述下拉电路及所述下拉维持电路并用于将所述栅极输出提升为第一高电平；以及耦合电路，电性连接至所述上拉控制电路、所述上拉电路、所述下拉电路、所述下拉维持电路及所述自举电容并用于将所述预充点提升为第二高电平，所述第二高电平高于所述第一高电平。
于一实施例中，所述耦合电路包括：第一晶体管，所述第一晶体管的栅极电性连接至所述预充点，所述第一晶体管的源极电性连接至时钟信号；以及第一电容，电性连接于所述第一晶体管的漏极与所述预充点之间。
于一实施例中，所述时钟信号与输入至所述GOA模块的时钟信号不同。
于一实施例中，所述下拉电路用于将所述预充点及所述栅极输出拉低至低电平。
于一实施例中，所述下拉维持电路用于将所述预充点及所述栅极输出维持在所述低电平。
为解决上述问题，本揭示提供的一种液晶显示装置包括：多条源极线；多条栅极线，所述多条源极线及所述多条栅极线定义出多个像素；以及GOA电路，电性连接至所述多条栅极线并用于向所述多条栅极线提供扫描信号，所述GOA电路包括多个级联的GOA模块，每一所述多个GOA模块包括：上拉控制电路，用于对所述模块的预充点预充电；上拉电路，电性连接至所述上拉控制电路并用于提高所述GOA模块的栅极输出；下拉电路，电性连接至所述上拉控制电路及所述上拉电路；下拉维持电路，电性连接至所述上拉控制电路、所述上拉电路及所述下拉电路；自举电容，电性连接至所述上拉控制电路、所述上拉电路、所述下拉电路及所述下拉维持电路并用于将所述栅极输出提升为第一高电平；以及耦合电路，电性连接至所述上拉控制电路、所述上拉电路、所述下拉电路、所述下拉维持电路及所述自举电容并用于将所述预充点提升为第二高电平，所述第二高电平高于所述第一高电平。
于一实施例中，所述耦合电路包括：第一晶体管，所述第一晶体管的栅极电性连接至所述预充点，所述第一晶体管的源极电性连接至时钟信号；以及第一电容，电性连接于所述第一晶体管的漏极与所述预充点之间。
于一实施例中，所述时钟信号与输入至所述GOA模块的时钟信号不同。
于一实施例中，所述下拉电路用于将所述预充点及所述栅极输出拉低至低电平。
于一实施例中，所述下拉维持电路用于将所述预充点及所述栅极输出维持在所述低电平。
 有益效果
相较于现有技术，本揭示之GOA电路以及液晶显示装置中，由于所述耦合电路能够在所述预充点的基础上再次进行耦合（亦即第二次耦合），因此能够降低所述GOA模块的栅极输出的下降时间，进而降低所述像素错充的风险。此外，本揭示之GOA电路以及液晶显示装置能够再次提升所述预充点的电平，进而使所述栅极输出的波形更加理想。
 附图说明
图1显示根据本揭示一实施例之液晶显示装置。
图2显示图1中一个GOA模块的电路图。
图3显示本揭示之GOA模块的栅极输出的电压曲线C1与现有GOA模块的栅极输出的电压曲线C2。
图4显示本揭示之GOA模块的预充点的电压曲线C1’与现有GOA模块的预充点的电压曲线C2’。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
请参阅图1，图1显示根据本揭示一实施例之液晶显示装置。
所述液晶显示装置具有一显示区10以及一非显示区30。所述显示装置包括多条源极线S1-SN、多条栅极线G1-GM、至少一源极驱动单元12（图中显示一个源极驱动单元12）以及一阵列基板行驱动电路（Gate driver On Array，以下称GOA电路）14。
所述多条源极线S1-SN及所述多条栅极线G1-GM设置于所述显示区10上。更明确地说，所述多条源极线S1-SN设置于所述显示区10上并延伸至所述源极驱动单元12。所述多条栅极线G1-GM设置于所述显示区10上并延伸至所述多个栅极驱动单元14。所述多条源极线S1-SN沿一第一方向形成。所述多条栅极线G1-GM沿一第二方向形成。所述第一方向垂直于所述第二方向。所述多条源极线S1-SN及所述多条栅极线G1-GM定义出多个像素16。每一所述像素16电性连接至一薄膜晶体管18。
所述源极驱动单元12设置于所述非显示区30上并电性连接至所述多条源极线S1-SN的第一端。所述源极驱动单元12用于向所述多条源极线S1-SN提供数据电压，所述数据电压用于写入所述像素16。
所述GOA电路14设置于所述非显示区30上。所述GOA电路14电性连接至所述多条栅极线G1-GM并用于向所述多条栅极线G1-GM提供扫描信号。
所述GOA电路14包括多个级联的GOA模块140。每一级GOA模块接收相应的时钟信号。
请参阅图1以及图2，图2显示图1中一个GOA模块140的电路图。
所述GOA模块140包括一上拉控制电路142、一上拉电路144、一下拉电路146、一下拉维持电路148、一自举电容Cb以及一耦合电路150。
所述上拉控制电路142用于对所述GOA模块140的预充点Q实现预充电。所述上拉控制电路142通常电性连接至上一级的GOA模块140所传送的下传信号。
所述上拉电路144电性连接至所述上拉控制电路142并用于提高本级GOA模块140的栅极输出OUT。所述栅极输出OUT用于导通与该GOA模块140对应的扫描线电性连接的薄膜晶体管18。
所述下拉电路146电性连接至所述上拉控制电路142及所述上拉电路144并用于将所述预充点Q及所述栅极输出OUT拉低至一低电平VSS，进而不导通与该GOA模块140对应的扫描线电性连接的薄膜晶体管18。
所述下拉维持电路148电性连接至所述上拉控制电路142、所述上拉电路144及所述下拉电路146并用于将所述预充点Q及所述栅极输出OUT维持在所述低电平VSS。
所述自举电容Cb电性连接至所述上拉控制电路142、所述上拉电路144、所述下拉电路146及所述下拉维持电路148并用于将所述GOA模块140的栅极输出OUT提升为一第一高电平（第一次耦合）。
为了降低所述GOA模块140的栅极输出OUT的下降时间，本揭示之GOA模块140进一步包括所述耦合电路150。所述耦合电路150电性连接至所述上拉控制电路142、所述上拉电路144、所述下拉电路146、所述下拉维持电路148及所述自举电容Cb并用于将所述预充点Q提升为一第二高电平。所述第二高电平高于所述第一高电平。
所述耦合电路150包括一第一晶体管T1以及一第一电容C1。
所述第一晶体管T1的栅极电性连接至所述预充点Q。所述第一晶体管T1的源极电性连接至一输入至其他级的GOA模块140的时钟信号。也就是说，所述第一晶体管T1的源极电性连接的时钟信号与输入至本级GOA模块140的时钟信号不同。举例来说，所述第一晶体管T1的源极电性连接至下一级的GOA模块140的时钟信号CK(k+1)。所述第一晶体管T1的漏极电性连接至所述预充点Q。
所述第一电容C1电性连接于所述第一晶体管T1的漏极与所述预充点Q之间并用于将所述第一晶体管T1的输出电压耦合至所述预充点Q。
由于所述耦合电路150能够在所述预充点Q的基础上再次进行耦合（亦即第二次耦合），因此能够降低所述GOA模块140的栅极输出OUT的下降时间，所述GOA模块140可以越快将与扫描线电性连接的薄膜晶体管不导通，所述像素16错充的风险就越低。
此外，由于所述耦合电路150能够在所述预充点Q的基础上再次进行耦合（亦即第二次耦合），因此能够再次提升所述预充点Q的电平，进而使所述栅极输出OUT的波形更加理想。
请参阅图3，图3显示本揭示之GOA模块140的栅极输出OUT的电压曲线C1与现有GOA模块的栅极输出的电压曲线C2。
如图3所示，本揭示之GOA模块140的栅极输出OUT的下降时间比现有GOA模块的栅极输出的下降时间更短，能下降约10%。
请参阅图4，图4显示本揭示之GOA模块140的预充点Q的电压曲线C1’与现有GOA模块的预充点的电压曲线C2’。
如图4所示，本揭示之GOA模块140的预充点Q的最终电压（最高电压）高于现有GOA模块的预充点的最终电压。
本揭示之GOA电路以及液晶显示装置中，由于所述耦合电路能够在所述预充点的基础上再次进行耦合（亦即第二次耦合），因此能够降低所述GOA模块的栅极输出的下降时间，进而降低所述像素错充的风险。此外，本揭示之GOA电路以及液晶显示装置能够再次提升所述预充点的电平，进而使所述栅极输出的波形更加理想。
综上所述，虽然本揭示已以优选实施例揭露如上，但上述优选实施例并非用以限制本揭示，本领域的普通技术人员，在不脱离本揭示的精神和范围内，均可作各种更动与润饰，因此本揭示的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种GOA电路，包括多个级联的GOA模块，每一所述多个GOA模块包括：
    上拉控制电路，用于对所述模块的预充点预充电；
    上拉电路，电性连接至所述上拉控制电路并用于提高所述GOA模块的栅极输出；
    下拉电路，电性连接至所述上拉控制电路及所述上拉电路并用于将所述预充点及所述栅极输出拉低至低电平；
    下拉维持电路，电性连接至所述上拉控制电路、所述上拉电路及所述下拉电路；
    自举电容，电性连接至所述上拉控制电路、所述上拉电路、所述下拉电路及所述下拉维持电路并用于将所述栅极输出提升为第一高电平；以及
    耦合电路，电性连接至所述上拉控制电路、所述上拉电路、所述下拉电路、所述下拉维持电路及所述自举电容并用于将所述预充点提升为第二高电平，所述第二高电平高于所述第一高电平，
    其中所述耦合电路包括：
    第一晶体管，所述第一晶体管的栅极电性连接至所述预充点，所述第一晶体管的源极电性连接至时钟信号；以及
    第一电容，电性连接于所述第一晶体管的漏极与所述预充点之间。
  2. 根据权利要求1所述的GOA电路，其中所述时钟信号与输入至所述GOA模块的时钟信号不同。
  3. 根据权利要求1所述的GOA电路，其中所述下拉维持电路用于将所述预充点及所述栅极输出维持在所述低电平。
  4. 一种GOA电路，包括多个级联的GOA模块，每一所述多个GOA模块包括：
    上拉控制电路，用于对所述模块的预充点预充电；
    上拉电路，电性连接至所述上拉控制电路并用于提高所述GOA模块的栅极输出；
    下拉电路，电性连接至所述上拉控制电路及所述上拉电路；
    下拉维持电路，电性连接至所述上拉控制电路、所述上拉电路及所述下拉电路；
    自举电容，电性连接至所述上拉控制电路、所述上拉电路、所述下拉电路及所述下拉维持电路并用于将所述栅极输出提升为第一高电平；以及
    耦合电路，电性连接至所述上拉控制电路、所述上拉电路、所述下拉电路、所述下拉维持电路及所述自举电容并用于将所述预充点提升为第二高电平，所述第二高电平高于所述第一高电平。
  5. 根据权利要求4所述的GOA电路，其中所述耦合电路包括：
    第一晶体管，所述第一晶体管的栅极电性连接至所述预充点，所述第一晶体管的源极电性连接至时钟信号；以及
    第一电容，电性连接于所述第一晶体管的漏极与所述预充点之间。
  6. 根据权利要求5所述的GOA电路，其中所述时钟信号与输入至所述GOA模块的时钟信号不同。
  7. 根据权利要求4所述的GOA电路，其中所述下拉电路用于将所述预充点及所述栅极输出拉低至低电平。
  8. 根据权利要求7所述的GOA电路，其中所述下拉维持电路用于将所述预充点及所述栅极输出维持在所述低电平。
  9. 一种液晶显示装置，包括：
    多条源极线；
    多条栅极线，所述多条源极线及所述多条栅极线定义出多个像素；以及
    GOA电路，电性连接至所述多条栅极线并用于向所述多条栅极线提供扫描信号，所述GOA电路包括多个级联的GOA模块，每一所述多个GOA模块包括：
    上拉控制电路，用于对所述模块的预充点预充电；
    上拉电路，电性连接至所述上拉控制电路并用于提高所述GOA模块的栅极输出；
    下拉电路，电性连接至所述上拉控制电路及所述上拉电路；
    下拉维持电路，电性连接至所述上拉控制电路、所述上拉电路及所述下拉电路；
    自举电容，电性连接至所述上拉控制电路、所述上拉电路、所述下拉电路及所述下拉维持电路并用于将所述栅极输出提升为第一高电平；以及
    耦合电路，电性连接至所述上拉控制电路、所述上拉电路、所述下拉电路、所述下拉维持电路及所述自举电容并用于将所述预充点提升为第二高电平，所述第二高电平高于所述第一高电平。
  10. 根据权利要求9所述的液晶显示装置，其中所述耦合电路包括：
    第一晶体管，所述第一晶体管的栅极电性连接至所述预充点，所述第一晶体管的源极电性连接至时钟信号；以及
    第一电容，电性连接于所述第一晶体管的漏极与所述预充点之间。
  11. 根据权利要求10所述的液晶显示装置，其中所述时钟信号与输入至所述GOA模块的时钟信号不同。
  12. 根据权利要求9所述的液晶显示装置，其中所述下拉电路用于将所述预充点及所述栅极输出拉低至低电平。
  13. 根据权利要求12所述的液晶显示装置，其中所述下拉维持电路用于将所述预充点及所述栅极输出维持在所述低电平。
PCT/CN2019/076913 2019-01-22 2019-03-05 Goa电路以及液晶显示装置 Ceased WO2020151050A1 (zh)

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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
CN111243541B (zh) * 2020-02-26 2021-09-03 深圳市华星光电半导体显示技术有限公司 一种goa电路及tft基板
CN111667793B (zh) * 2020-05-28 2021-08-06 昆山国显光电有限公司 一种移位寄存器及显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110228893A1 (en) * 2010-03-18 2011-09-22 Mitsubishi Electric Corporation Shift register circuit
US20150213746A1 (en) * 2014-01-24 2015-07-30 Sumsung Display Co., Ltd. Gate driver integrated on display panel
CN106023921A (zh) * 2016-07-08 2016-10-12 深圳市华星光电技术有限公司 一种goa电路
CN106251817A (zh) * 2016-08-31 2016-12-21 深圳市华星光电技术有限公司 一种goa驱动电路
CN106486078A (zh) * 2016-12-30 2017-03-08 深圳市华星光电技术有限公司 一种扫描驱动电路、驱动电路及显示装置
CN108364622A (zh) * 2018-04-24 2018-08-03 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、驱动装置和显示装置
CN108877713A (zh) * 2018-07-17 2018-11-23 惠科股份有限公司 显示装置及移位暂存电路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2720185B1 (fr) * 1994-05-17 1996-07-05 Thomson Lcd Registre à décalage utilisant des transistors M.I.S. de même polarité.
WO2012111586A1 (ja) * 2011-02-18 2012-08-23 シャープ株式会社 半導体装置及び表示装置
CN105047127B (zh) * 2015-09-21 2017-12-22 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、行扫描驱动电路、显示装置
TWI611413B (zh) * 2016-12-30 2018-01-11 友達光電股份有限公司 移位暫存器電路
CN107993627A (zh) * 2017-12-25 2018-05-04 深圳市华星光电技术有限公司 一种goa电路

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110228893A1 (en) * 2010-03-18 2011-09-22 Mitsubishi Electric Corporation Shift register circuit
US20150213746A1 (en) * 2014-01-24 2015-07-30 Sumsung Display Co., Ltd. Gate driver integrated on display panel
CN106023921A (zh) * 2016-07-08 2016-10-12 深圳市华星光电技术有限公司 一种goa电路
CN106251817A (zh) * 2016-08-31 2016-12-21 深圳市华星光电技术有限公司 一种goa驱动电路
CN106486078A (zh) * 2016-12-30 2017-03-08 深圳市华星光电技术有限公司 一种扫描驱动电路、驱动电路及显示装置
CN108364622A (zh) * 2018-04-24 2018-08-03 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、驱动装置和显示装置
CN108877713A (zh) * 2018-07-17 2018-11-23 惠科股份有限公司 显示装置及移位暂存电路

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