WO2020147108A1 - 一种时间同步的方法及装置 - Google Patents

一种时间同步的方法及装置 Download PDF

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Publication number
WO2020147108A1
WO2020147108A1 PCT/CN2019/072324 CN2019072324W WO2020147108A1 WO 2020147108 A1 WO2020147108 A1 WO 2020147108A1 CN 2019072324 W CN2019072324 W CN 2019072324W WO 2020147108 A1 WO2020147108 A1 WO 2020147108A1
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Prior art keywords
time
signal
time value
npps
tod
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PCT/CN2019/072324
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English (en)
French (fr)
Inventor
傅健新
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华为技术有限公司
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Priority to CN201980065832.2A priority Critical patent/CN112805958B/zh
Priority to PCT/CN2019/072324 priority patent/WO2020147108A1/zh
Publication of WO2020147108A1 publication Critical patent/WO2020147108A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

Definitions

  • This application relates to the field of communication technology, and in particular to a method and device for time synchronization.
  • Time synchronization can refer to setting the time of multiple devices communicating with each other to be consistent. For example, setting the time of multiple devices communicating with each other to be the same as the time source on the network Consistently, the time source here can be provided by reliable equipment in the network, such as GPS satellites or time servers.
  • the sender device can output the corresponding time value at a certain moment through the standard time interface, and the receiver device obtains the corresponding time value through analysis, and realizes the inter-device communication based on the analyzed time value. Time synchronization.
  • a standard time interface usually includes: a pulse per second (1PPS) + time of day (TOD) interface and a DC level shift (DCLS) interface.
  • PPS pulse per second
  • TOD time of day
  • DCLS DC level shift
  • the above two time interfaces both output time information once per second, and the smallest unit of the output time information is seconds, so that time synchronization can only be performed at whole seconds.
  • these two time interfaces will have the following problems in circuit implementation: digital circuits are difficult to control the time of each output as a whole second, so there is a certain deviation between the output time and the actual time; analog circuits can Realize the output of the whole second accurately, but the cost is high, the power consumption is high, and the implementation complexity is high. Therefore, how to improve the synchronization performance of the time interface and ensure that its implementation cost, power consumption and complexity are low is a key issue.
  • the embodiments of the present application provide a time synchronization method and device, which are used to improve the synchronization performance of a time interface while ensuring low implementation cost, power consumption and complexity.
  • a time synchronization method includes: a first device generates N pulses per second NPPS signal and a time of day TOD signal, the TOD signal is used to carry the time value corresponding to the rising/falling edge of the NPPS signal, The time value corresponding to the rising/falling edge includes a time value less than a second, and N is an integer greater than 1.
  • the first device sends an NPPS signal and a TOD signal to the second device to synchronize the time of the second device with the first device.
  • the minimum time unit of the time value carried by the TOD signal can be less than seconds, so as to improve the accuracy of the time value in the time synchronization process; in addition, when the NPPS signal and TOD signal are sent through the digital circuit, although The clock of the digital circuit is not ideal, which will cause the time value corresponding to the rising/falling edge of NPPS to include the time value less than second, but because the TOD signal can carry the time value less than second, it can directly output the up/down of NPPS Along the corresponding time value, the problem of deviation between the output time and the actual time is avoided.
  • the structure of the digital circuit is relatively simple, and the implementation cost, power consumption and complexity are relatively low, so the synchronization performance of the time interface can be improved.
  • the time value less than a second includes at least one of the following: milliseconds, microseconds, nanoseconds, or nanosecond fractions.
  • time synchronization in the order of milliseconds, microseconds, nanoseconds, and/or nanoseconds is achieved, thereby improving the accuracy of the time value in the time synchronization process.
  • the time value carried by the TOD corresponds to the time value corresponding to the rising/falling edge of the NPPS in a one-to-one correspondence.
  • the flexibility of the time value carried by the TOD can be improved, so that the cost, power consumption, and complexity of the circuit implementation are relatively low.
  • the TOD signal is also used to carry a first delay
  • the first delay includes a transmission delay inside the first device or transmission between the first device and the second device
  • At least one of the delays, that is, the first device may superimpose the first delay and the time value corresponding to the rising and falling edges of the NPPS signal and then carry it on the TOD signal, so as to realize the compensation of the transmission delay.
  • a method for time synchronization includes: a second device receives N pulses per second NPPS signal and a time of day TOD signal sent by the first device, the TOD signal is used to carry the rising/falling edge of the NPPS signal Corresponding time value, the time value includes a time value less than a second, and N is an integer greater than 1.
  • the second device synchronizes the time of the second device with the first device according to the NPPS signal and the TOD signal.
  • the minimum time unit of the time value corresponding to the rising/falling edge of the NPPS signal carried by the TOD signal can be less than seconds, so as to improve the accuracy of the time value in the time synchronization process; in addition, when sending through a digital circuit
  • the clock of the digital circuit is not ideal, it will cause the time value corresponding to the rising/falling edge of NPPS to include a time value less than second, but because the TOD signal can also carry the time value less than second Therefore, the time value corresponding to the rising/falling edge of NPPS can be directly output, avoiding the problem of deviation between the output time and the actual time.
  • the structure of the digital circuit is relatively simple, and the implementation cost, power consumption and complexity are relatively low, so it can improve The synchronization performance of the time interface.
  • the time information less than a second includes at least one of the following: milliseconds, microseconds, nanoseconds, or nanosecond fractions.
  • time synchronization in the order of milliseconds, microseconds, nanoseconds, and/or nanoseconds is achieved, thereby improving the accuracy of the time value in the time synchronization process.
  • the time value carried by the TOD corresponds to the time value corresponding to the rising/falling edge of the NPPS in a one-to-one correspondence.
  • the flexibility of the time value carried by the TOD can be improved, so that the cost, power consumption, and complexity of the circuit implementation are relatively low.
  • the TOD signal is also used to carry the first delay
  • the first delay includes the transmission delay within the first device or the transmission between the first device and the second device
  • At least one of the delays that is, the first device may superimpose the first delay and the time value corresponding to the rising and falling edges of the NPPS signal and then carry it on the TOD signal, so as to realize the compensation of the transmission delay.
  • a device for time synchronization includes: a processing unit for generating N pulses per second NPPS signal and time of day TOD signal, the TOD signal is used to carry the time corresponding to the rising/falling edge of the NPPS signal
  • the time value includes a time value less than a second, and N is an integer greater than 1.
  • the sending unit is used to send an NPPS signal and a TOD signal to the second device to synchronize the time of the second device with the device.
  • the time information less than a second includes at least one of the following: milliseconds, microseconds, nanoseconds, or nanosecond fractions.
  • the time value carried by the TOD corresponds to the time value corresponding to the rising/falling edge of the NPPS in a one-to-one correspondence.
  • the TOD signal is also used to carry the first delay, and the first delay includes the transmission delay inside the device or the transmission delay between the device and the second device At least one of the delays.
  • a device for time synchronization includes: a receiving unit for receiving N pulses per second NPPS signal and time of day TOD signal sent by a first device, and the TOD signal is used to carry the NPPS signal.
  • the time value corresponding to the falling edge, the time value includes a time value less than a second, and N is an integer greater than 1.
  • the processing unit is configured to synchronize the time of the device with the first device according to the NPPS signal and the TOD signal.
  • the time information less than a second includes at least one of the following: milliseconds, microseconds, nanoseconds, or nanosecond fractions.
  • the time information carried by the TOD corresponds to the time value corresponding to the rising/falling edge of the NPPS in a one-to-one correspondence.
  • the TOD signal is also used To bear the first delay.
  • a time synchronization method includes: a first device generates a DC level conversion N-DCLS signal N times per second, and each DCLS signal includes W symbols, and the W symbols are used to carry The time value corresponding to the rising/falling edge of the first reference symbol among the W symbols, the time value corresponding to the rising/falling edge includes a time value less than a second, and N is an integer greater than 1; the first device sends the second The device sends an N-DCLS signal to synchronize the time of the second device with the first device.
  • the minimum time unit of the time value carried by the W symbols can be less than second, so as to improve the accuracy of the time value in the time synchronization process; in addition, when the N-DCLS signal is sent through a digital circuit, Although the clock of the digital circuit is not ideal, it will cause the time value corresponding to the rising/falling edge of the first reference symbol to include a time value less than a second, but because the above W symbols can carry the time value less than a second, it can Directly output the time value corresponding to the rising/falling edge of the first reference symbol, avoiding the problem of deviation between the output time and the actual time. At the same time, the structure of the digital circuit is relatively simple, and the implementation cost, power consumption and complexity are relatively low, so it can Improve the synchronization performance of the time interface.
  • W is an integer greater than 100, and the symbols before the first 100 symbols among the W symbols are used to carry the time value less than a second; optionally, W Each symbol is 100*M symbols, and M is an integer greater than 1.
  • the provided implementation manner for carrying the time value less than a second can be compatible with the existing manner of realizing time synchronization through a DCLS signal once per second.
  • the time value less than second includes at least one of the following: milliseconds, microseconds, nanoseconds, or nanosecond fractions.
  • time synchronization in the order of milliseconds, microseconds, nanoseconds, and/or nanoseconds is achieved, thereby improving the accuracy of the time value in the time synchronization process.
  • symbols other than the first reference symbol among the W symbols are used to carry the time value corresponding to the rising/falling edge of the first reference symbol.
  • the flexibility of the time value carried by the W symbols can be improved, so that the cost, power consumption, and complexity of the circuit implementation are relatively low.
  • the N-DCLS signal is also used to carry the first delay
  • the first delay includes the transmission delay within the first device or between the first device and the second device. At least one of the transmission delays, that is, the first device can superimpose the first delay with the time value corresponding to the rising and falling edges of the first reference symbol and then carry it on the N-DCLS signal to realize the transmission time. Delayed compensation.
  • a simple and effective method of compensating for delay is provided, and it does not cause the problem of high complexity in circuit implementation.
  • a time synchronization method includes: a second device receives a DC level conversion N-DCLS signal sent by a first device N times per second, and each DCLS signal includes W symbols, and the W symbols The symbol is used to carry the time value corresponding to the rising/falling edge of the first reference symbol among the W symbols, and the time value corresponding to the rising/falling edge includes a time value less than seconds, and N is an integer greater than 1.
  • the second device synchronizes the time of the second device with the first device according to the N-DCLS signal.
  • the minimum time unit of the time value carried by the W symbols can be less than second, so as to improve the accuracy of the time value in the time synchronization process; in addition, when the N-DCLS signal is sent through a digital circuit, Although the clock of the digital circuit is not ideal, it will cause the time value corresponding to the rising/falling edge of the first reference symbol to include a time value less than a second, but because the above W symbols can carry the time value less than a second, it can Directly output the time value corresponding to the rising/falling edge of the first reference symbol, avoiding the problem of deviation between the output time and the actual time. At the same time, the structure of the digital circuit is relatively simple, and the implementation cost, power consumption and complexity are relatively low, so it can Improve the synchronization performance of the time interface.
  • W is an integer greater than 100, and the symbols before the first 100 symbols among the W symbols are used to carry the time value less than a second; optionally, W Each symbol is 100*M symbols, and M is an integer greater than 1.
  • the provided implementation manner for carrying the time value less than a second can be compatible with the existing manner of realizing time synchronization through a DCLS signal once per second.
  • the time value less than second includes at least one of the following: milliseconds, microseconds, nanoseconds, or nanosecond fractions.
  • time synchronization in the order of milliseconds, microseconds, nanoseconds, and/or nanoseconds is achieved, thereby improving the accuracy of the time value in the time synchronization process.
  • symbols other than the first reference symbol among the W symbols are used to carry the time value corresponding to the rising/falling edge of the first reference symbol.
  • the flexibility of the time value carried by the W symbols can be improved, so that the cost, power consumption, and complexity of the circuit implementation are relatively low.
  • the N-DCLS signal is also used to carry the first delay
  • the first delay includes the transmission delay within the first device or between the first device and the second device. At least one of the transmission delays, that is, the first device can superimpose the first delay with the time value corresponding to the rising and falling edges of the first reference symbol and then carry it on the N-DCLS signal to realize the transmission time. Delayed compensation.
  • a simple and effective method of compensating for delay is provided, and it does not cause the problem of high complexity in circuit implementation.
  • a device for time synchronization includes: a processing unit for generating a DC level conversion N-DCLS signal N times per second, each time the DCLS signal includes W symbols, and the W symbols are used To carry the time value corresponding to the rising/falling edge of the first reference symbol among the W symbols, the time value corresponding to the rising/falling edge includes a time value less than a second, and N is an integer greater than 1; the sending unit uses Yu sends an N-DCLS signal to the second device to synchronize the time of the second device with the device.
  • W is an integer greater than 100, and the symbols before the first 100 symbols among the W symbols are used to carry the time value less than a second; optionally, W Each symbol is 100*M symbols, and M is an integer greater than 1.
  • the time value less than second includes at least one of the following: milliseconds, microseconds, nanoseconds, or nanosecond fractions.
  • symbols other than the first reference symbol among the W symbols are used to carry the time value corresponding to the rising/falling edge of the first reference symbol.
  • the N-DCLS signal is also used to carry the first delay, and the first delay includes the transmission delay within the device or the transmission between the device and the second device At least one of the delays.
  • a time synchronization device includes: a receiving unit for receiving N-DCLS signals sent by a first device N-times of DC level conversion per second, and each DCLS signal includes W symbols, and W symbols are used to carry the time value corresponding to the rising/falling edge of the first reference symbol among the W symbols, the time value corresponding to the rising/falling edge includes a time value less than a second, and N is an integer greater than 1. ; A processing unit for synchronizing the device with the time of the first device according to the N-DCLS signal.
  • W is an integer greater than 100, and the symbols before the first 100 symbols among the W symbols are used to carry the time value less than a second; optionally, W Each symbol is 100*M symbols, and M is an integer greater than 1.
  • the time value less than second includes at least one of the following: milliseconds, microseconds, nanoseconds, or nanosecond fractions.
  • symbols other than the first reference symbol among the W symbols are used to carry the time value corresponding to the rising/falling edge of the first reference symbol.
  • the N-DCLS signal is also used to carry the first delay
  • the first delay includes the transmission delay within the first device or the delay between the first device and the device. At least one of the transmission delays.
  • a time synchronization system in another aspect of the present application, includes a first device and a second device; wherein, the first device is determined by the third aspect or any one of the possible implementation manners of the third aspect.
  • the time synchronization device provided by the second device is the time synchronization device provided by the foregoing fourth aspect or any one of the possible implementation manners of the fourth aspect; or, the first device is any of the foregoing seventh aspect or the seventh aspect
  • the time synchronization device provided by a possible implementation manner is the time synchronization device provided by the second device in the eighth aspect or any one of the eighth aspect possible implementation manners.
  • any of the above-provided time synchronization methods and devices are used to implement the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the corresponding methods provided above. The beneficial effects will not be repeated here.
  • FIG. 1 is a schematic structural diagram of a communication system provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a 1PPS+TOD interface provided by an embodiment of the application
  • FIG. 3 is a schematic diagram of a DCLS interface provided by an embodiment of the application.
  • FIG. 4 is a schematic flowchart of a time synchronization method provided by an embodiment of this application.
  • FIG. 5 is a schematic diagram of a first time interface provided by an embodiment of this application.
  • FIG. 6 is a schematic diagram of a frame structure provided by an embodiment of the application.
  • FIG. 7 is a schematic flowchart of another time synchronization method provided by an embodiment of this application.
  • FIG. 8 is a first structural diagram of a time synchronization apparatus provided by an embodiment of the application.
  • FIG. 9 is a second structural diagram of a time synchronization apparatus provided by an embodiment of the application.
  • At least one refers to one or more, and “multiple” refers to two or more.
  • “And/or” describes the relationship of the related objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A exists alone, A and B exist at the same time, B exists alone, where A, B can be singular or plural.
  • “At least one of the following” or similar expressions refers to any combination of these items, including any combination of single items or plural items.
  • at least one (a) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c may be single or multiple.
  • the character "/" generally indicates that the related object is a "or” relationship.
  • words such as “first” and “second” do not limit the number and execution order.
  • FIG. 1 is a schematic structural diagram of a communication system provided by an embodiment of the application.
  • the communication system includes a first device and a second device, and the first device and the second device use a time interface for time synchronization.
  • the first device and the second device are connected in a wired manner, for example, the first device and the second device are connected by a cable.
  • the first device and the second device can be network elements in the network (for example, the first device and the second device are two terminals in the network), or can be test instruments in the time synchronization performance test (
  • the first device is a network element
  • the second device is a test instrument used to test the time synchronization performance of the first device).
  • the time interface may refer to the interface used for time synchronization.
  • the time interface may include 1 pulse per second (1PPS) + time of day (TOD) interface, and DC level shift (DCLS). ) Interface, etc.
  • 1PPS+TOD interface and the DCLS interface using the sending time value of the first device to the second device.
  • the time value is transmitted through two signal lines.
  • the two signal lines include the signal line used to send 1PPS signal) and the signal line used to send TOD signal.
  • TOD here is a timing method.
  • the 1PPS signal is a 1Hz signal, that is, one pulse is sent every second.
  • the rising edge of the 1PPS signal is used to indicate the whole second of the first device;
  • the TOD signal is used to carry the time value (unit) corresponding to the rising edge of the 1PPS signal.
  • the time value corresponding to the rising edge of the 1PPS signal is xxxx year xx month xx day xx hour xx minute xx second.
  • the TOD signal is high when there is no data transmission; when there is data transmission, each byte contains 8 bits, and each byte starts with 1 bit "0" and ends with 1 bit "1" Bit, the middle is 8 bits of data.
  • the baud rate of the TOD signal can support 9600, 19200, 38400, etc., and the level width of each bit can comply with the baud rate agreed by the transceiver device.
  • the high-level pulse width of the 1PPS signal is 20ms-200ms, and the time between the starting position of the TOD signal corresponding to the rising edge of 1PPS and the rising edge is greater than 1ms, and the time value of each transmission
  • the length is less than 500ms as an example.
  • TOD frame structure may include frame header 1, frame header 2, message type, message ID, message length field, payload field, and check field (specifically as shown in Figure 5 below), the payload field
  • the length of can be 16 bytes, and the relevant description of 16 bytes can refer to the relevant description of the first 16 bytes shown in Table 2 below, which is not repeated here in the embodiment of the application.
  • DCLS interface time information is transmitted through a signal line, which is used to transmit DCLS signals.
  • the DCLS interface can send 100 symbols per second, and the time width of each symbol is 10 ms, and each symbol represents different information with a different duty cycle.
  • 8ms: 2ms (that is, the ratio of high to low level is 4) represents the reference symbol (also called reference symbol)
  • 5ms: 5ms (that is, the ratio of high to low level is 1) represents data 1
  • the first symbol and the last symbol have a duty ratio of 8ms:2ms, that is, the first symbol and the last symbol are both reference symbols.
  • the rising edge of the first reference symbol per second represents the whole second time of the first device, and the time of the first device corresponding to this time is determined by the symbols other than the reference symbol in the second. Bearer.
  • FIG. 4 is a schematic flowchart of a time synchronization method provided by an embodiment of the application. Referring to FIG. 4, the method includes the following steps.
  • the first device generates N pulse per second (NPPS) signals and time of day (TOD) signals, and the TOD signal is used to carry the time value corresponding to the rising/falling edge of the NPPS signal ,
  • the time value corresponding to the rising/falling edge includes a time value less than seconds, and N is an integer greater than 1.
  • the NPPS signal is an N Hz signal, that is, N pulses are sent per second.
  • the value is not limited.
  • the TOD signal is used to carry the time value corresponding to the rising/falling edge of the NPPS signal, that is, the TOD signal can be used to indicate the time value corresponding to the rising edge of the NPPS signal, and it can also be used to indicate the time value corresponding to the falling edge of the NPPS signal.
  • the time value specifically indicates that the time value corresponding to the rising edge or the time value corresponding to the falling edge can be agreed in advance by the first device and the second device.
  • N can also be equal to 1, that is, one pulse is sent per second, but the interval for time synchronization can only be 1 second, and when N is an integer greater than 1, the time is performed
  • the synchronization interval is 1/N, so relative to N equal to 1, the frequency of time synchronization can be increased, thereby improving the performance of time synchronization.
  • the time value corresponding to the rising/falling edge of the NPPS signal includes a time value less than seconds, that is, the minimum time unit of the time value carried by the TOD signal can be less than seconds, for example, the minimum time unit can be milliseconds (ms), micro Seconds (us), nanoseconds (ns), or nanosecond fractions (ns fractions), etc., so the time value carried by the TOD signal can be a time value including ms, us, ns, or ns fractions, for example, the time value can be 2008 April 06, 12:00, 23, and 14 milliseconds.
  • the TOD signal is used to carry the time value corresponding to the rising/falling edge of the NPPS signal.
  • the time value carried by the TOD signal can be a whole second value , At this time, the time value less than second is 0; when the time value corresponding to the rising/falling edge of the NPPS signal is a non-integral second value (for example, including time information of ns or ns decimal), the time carried by the TOD signal
  • the value can also be a non-integral second value, in which case time information less than a second is not 0.
  • the time value carried by the TOD signal corresponds to the time value corresponding to the rising/falling edge of the NPPS signal, that is, each time value carried on the TOD signal is used to indicate different rise/fall of the NPPS signal The time value corresponding to the edge.
  • Figure 5 is a schematic diagram of an NPPS signal and a TOD signal. (a) in Figure 5 is a one-to-one correspondence between the time value carried by the TOD signal and the time value corresponding to the falling edge of the NPPS signal, and (b) in Figure 5 The time value carried by the TOD signal corresponds to the time value corresponding to the rising edge of the NPPS signal in a one-to-one correspondence.
  • the TOD signal is high when there is no data transmission; when there is data transmission, each byte contains 8 bits, and each byte starts with 1 bit "0" and 1 bit "1" as The end bit, the middle is 8-bit data.
  • the high-level pulse width of the NPPS signal, the time width between the starting position of the time value carried by the TOD signal corresponding to the rising/falling edge of the NPPS signal and the rising/falling edge, and The length of the time value sent each time is not specifically limited, as long as the implementation of the above method can be guaranteed.
  • the frame structure of the TOD signal can be as shown in Figure 6.
  • the frame structure includes frame header 1, frame header 2, message type, message ID, message length field, payload field and check field.
  • the test range can be from the message type to the payload domain.
  • the payload field can include 21 bytes.
  • the 16th to 19th bytes can be used to represent nanosecond integers
  • the 20th to 21st bytes can be used to represent nanosecond decimals.
  • the payload field can also include more or less bytes, as long as it can express time information less than a second.
  • Table 1 takes the payload field including 21 bytes as an example to explain the definition of some bytes.
  • the relevant description of the bytes with byte offsets of 5-12 in Table 1 can be found in the prior art. For related descriptions, the embodiments of this application will not elaborate on this.
  • the first device sends the NPPS signal and the TOD signal to the second device.
  • S403 The second device receives the NPPS signal and the TOD signal sent by the first device.
  • the NPPS signal and TOD signal in S403 are the same as the NPPS signal and TOD signal in S401.
  • S401 For details, refer to the description in S401, and the details of this embodiment are not repeated here.
  • the second device may analyze the NPPS signal and the TOD signal to obtain the rising/falling edge of the NPPS signal carried by the TOD signal The corresponding time value.
  • the time value parsed by the second device can be the time value corresponding to the rising edge of the NPPS signal Time value; if the first device and the second device agree in advance that the time value carried by the TOD signal indicates the time value corresponding to the falling edge of the NPPS signal, the time value analyzed by the second device may be the falling edge of the NPPS signal The time value corresponding to the edge.
  • S404 The second device synchronizes the time of the second device with the first device according to the NPPS signal and the TOD signal.
  • the second device can calibrate the local time of the second device according to the time value. For example, the second device calibrates its own local time to the The time value corresponding to the falling edge of the NPPS signal is consistent, so as to realize time synchronization between the second device and the first device.
  • the TOD signal is also used to carry the first delay That is, the time value carried by the TOD signal may be the superposition of the first time delay and the time value corresponding to the rising/falling edge of the NPPS.
  • the first delay is compensated by the first device, that is, the first device superimposes the first delay and the time value corresponding to the rising/falling edge of the NPPS signal before sending it to the first delay as the time value carried by the TOD signal.
  • the first delay is compensated by the second device, that is, the time value corresponding to the rising/falling edge of the NPPS signal is consistent with the time value carried by the TOD signal.
  • the second device analyzes and obtains the time value carried by the TOD signal, The second device superimposes the first time delay with the time value carried by the TOD signal, and uses the time value obtained after superposition for time synchronization.
  • the time value (ie, local time) corresponding to the falling edge of the NPPS signal sent by the first device is: 1 second and 100 ms
  • the TOD signal carries this "1 second and 100 milliseconds" information, if the first device and the second device
  • the transmission path delay between the two devices is 100ns (that is, the first delay is 100ns).
  • the second device When the second device performs time synchronization, the second device needs to carry the TOD signal with the time value "1 second 100 milliseconds" and the first Add the delay "100ns” and set its own local time to be consistent with the added time value "1 second 100 milliseconds 100ns", that is, when the falling edge of the NPPS signal reaches the second device, the first device's The local time is "1 second 100 milliseconds 100 ns".
  • the minimum time unit of the time value carried by the TOD signal may be less than seconds, so that the accuracy of the time value in the time synchronization process can be improved.
  • the actual timing step may deviate from the theoretical timing due to network jitter or temperature drift (for example, take a 1GHz clock as an example) ,
  • the theoretical timing step length is 1ns, the actual timing step length may be 0.95ns), which causes the time value corresponding to the rising/falling edge of the NPPS to include time values less than seconds, but because the TOD signal can carry time values less than seconds Therefore, the time value corresponding to the rising/falling edge of the NPPS can be directly output, avoiding the problem of deviation between the output time and the actual time, and the structure of the digital circuit is relatively simple, and the implementation cost, power consumption and complexity are relatively low. Therefore, the above method can improve the synchronization performance of the time interface.
  • FIG. 7 is a schematic flowchart of a time synchronization method provided by an embodiment of the application. Referring to FIG. 7, the method includes the following steps.
  • the first device generates a DCLS (N-DCLS) signal N times per second, each time the DCLS signal includes W symbols, and the W symbols are used to carry the value of the first reference symbol among the W symbols.
  • the time value corresponding to the falling edge, the time value corresponding to the rising/falling edge includes a time value less than a second, and N is an integer greater than 1.
  • W may be an integer greater than 100.
  • W symbols may be 110 symbols, 120 symbols, 200 symbols, or 300 symbols.
  • W symbols are equal to 100*M symbols, and M is a positive integer greater than 1, that is, the number of W symbols can be an integer multiple of 100. In the embodiment of this application, W symbols are equal to 100. *M symbols are taken as an example for description.
  • N DCLS signals per second means that DCLS signals are sent N times per second.
  • the specific value of N is not limited.
  • the DCLS signal sent each time may include 100*M symbols, and the time width of each symbol is 10/(M*N)ms.
  • each symbol represents different information with a different duty cycle, which is similar to the description in the above-mentioned DCLS interface.
  • a high-to-low level ratio of 4 represents a reference symbol (also called a reference symbol), and a high-to-low level ratio of 1 represents Data 1, that is, the ratio of high to low level is 1/4, which means data 0.
  • the high-low level ratio corresponding to the first symbol and the last symbol is 4, that is, the first symbol and the last symbol are both reference symbols.
  • the W symbols are used to carry the time value corresponding to the rising/falling edge of the first reference symbol (that is, the first base station symbol) among the W symbols, that is, the W symbols are used to carry the W
  • the time value corresponding to the rising edge of the first reference symbol in the symbol can also be used to carry the time value corresponding to the falling edge of the first reference symbol in the W symbols, specifically indicating the time value corresponding to the rising edge
  • the time value corresponding to the falling edge can be agreed in advance by the first device and the second device.
  • N can also be equal to 1, that is, send once per second, but the interval for time synchronization can only be 1 second, and when N is an integer greater than 1, time synchronization is performed
  • the interval of is 1/N, so relative to N equal to 1, the frequency of time synchronization can be increased, thereby improving the performance of time synchronization.
  • the time value carried by the W symbols includes a time value less than second, that is, the minimum time unit of the time value carried by the W symbols may be less than second, for example, the minimum time unit may be ms, us, ns, or ns Decimals, etc., so that the time value can be a time value including ms, us, ns, or ns decimals, for example, the time value is 12:00, 00, 23, 23, and 14 milliseconds on April 6, 2008.
  • the W symbols are used to carry the time value corresponding to the rising/falling edge of the first reference symbol among the W symbols, and when the time value corresponding to the rising/falling edge of the first reference symbol is an integral second value,
  • the time value carried by the W symbols can be a whole second value, and the time information less than a second is 0; when the time value corresponding to the rising/falling edge of the first reference symbol is a non-integral second value (for example, including When the time information is ns or ns fractional number), the time value carried by the W symbols may also be a partial second value, and the time information less than a second is not 0 at this time.
  • symbols other than the first reference symbol ie, symbols representing data
  • the 100*M symbols sent each time can be used to transmit a time value.
  • the other symbols except the first reference symbol is used to carry the time value corresponding to the rising/falling edge of the first reference symbol.
  • the symbol serial number 100-139 can be specifically used to represent nanosecond values.
  • the symbols 140-159 can be used to represent decimal values, and every 5 symbols can be a group, the first symbol in every 5 symbols can be index bits, and the last 4 in every 5 symbols Symbols can be used to represent nanosecond values or fractional nanosecond values.
  • the nanosecond value includes 32 bytes (that is, 0-31), and the nanosecond fractional value includes 16 bytes (that is, 0-15).
  • the symbol sequence number 160-199 is reserved The code element will be described as an example.
  • S702 The first device sends an N-DCLS signal to the second device.
  • S703 The second device receives the N-DCLS signal sent by the first device.
  • the N-DCLS signal in S703 is the same as the N-DCLS signal in 7401 above.
  • the second device may analyze the N-DCLS signal to obtain the first reference among the W symbols carried by the W symbols The time value corresponding to the rising/falling edge of the symbol. If the first device and the second device agree in advance that the time value carried by the W symbols indicates the time value corresponding to the rising edge of the first reference symbol, the time value parsed by the second device may be the first The time value corresponding to the rising edge of the reference symbol; if the first device and the second device agree in advance that the time value carried by the W symbols indicates the time value corresponding to the falling edge of the first reference symbol, the second device The time value parsed by the device may be the time value corresponding to the falling edge of the first reference symbol.
  • S704 The second device synchronizes the time of the second device with the first device according to the N-DCLS signal.
  • the second device When the second device parses and obtains the time value corresponding to the falling edge of the first reference symbol among the W symbols, the second device can calibrate the local time of the second device according to the time value, for example, the second device will The own local time is calibrated to be consistent with the time value corresponding to the falling edge of the first reference symbol among the W symbols, so as to achieve time synchronization between the second device and the first device.
  • the time value carried by the W symbols may be The superposition of the first time delay and the time value corresponding to the rising/falling edge of the first reference symbol.
  • the first delay is compensated by the first device, that is, the first device superimposes the first delay and the time value corresponding to the rising/falling edge of the first reference symbol in advance as the time carried by the W symbols The value is sent to the second device.
  • the first delay is compensated by the second device, that is, the time value corresponding to the rising/falling edge of the first reference symbol is consistent with the time value carried by the W symbols, and the second device analyzes and obtains the W codes After the time value carried by the element, the second device superimposes the first delay and the time value carried by the W symbols to synchronize the time.
  • the time value corresponding to the falling edge of the first symbol sent by the first device of W symbols is: 1 second and 100 ms, and the W symbols carry this "1 second 100 milliseconds" information, if the first device
  • the transmission path delay between the second device and the second device is 100ns (that is, the first delay is 100ns).
  • the second device When the second device performs time synchronization, the second device needs to carry the "1 second 100
  • the information value of milliseconds is added to the first time delay "100ns", and its own local time is set to be consistent with the added time value of "1 second 100 milliseconds 100ns", that is, the first of the W symbols
  • the local time of the first device is "1 second 100 milliseconds 100 ns”.
  • the minimum time unit of the time value carried by the above W symbols may be less than second, so that the accuracy of the time value in the time synchronization process can be improved.
  • the actual timing step may deviate from the theoretical timing due to network jitter or temperature drift (for example, take a 1GHz clock as an example)
  • the theoretical timing step size is 1ns
  • the actual timing step size may be 0.95ns), which results in the time value corresponding to the rising/falling edge of the first reference symbol being a non-full second time, but because the above W symbols can carry
  • the time value is less than seconds, so that the time value corresponding to the rising/falling edge of the first reference symbol can be directly output, avoiding the problem of deviation between the output time and the actual time.
  • the structure of the digital circuit is relatively simple, and the cost, power consumption and The complexity is relatively low. Therefore, the above method can improve the synchronization
  • the first device and the second device in order to implement the above functions, include hardware structures and/or software corresponding to each function. Module.
  • the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is performed by hardware or computer software driven hardware depends on the specific application of the technical solution and design constraints. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
  • the embodiment of the present application can divide the first device and the second device into functional modules according to the above method examples.
  • each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module.
  • the above-mentioned functional modules can be implemented in the form of hardware or software functional modules. It should be noted that the division of the modules in the embodiments of the present application is schematic, and is only a division of logical functions. In actual implementation, there may be another division manner.
  • FIG. 8 shows a possible structural schematic diagram of the time synchronization device involved in the foregoing embodiment.
  • the device may be the first device or the first device.
  • the chip or the system-on-chip may also be a circuit, module, or unit used in the first device to implement the foregoing method embodiments.
  • the device includes: a processing unit 801 and a sending unit 802.
  • the processing unit 801 is used to support the device to perform S401 in the above method embodiment, or S701 in the above method embodiment, and/or other technical processes described herein;
  • the sending unit 802 is used to support the device to perform the above method S402 in the embodiment or S702 in the foregoing method embodiment.
  • FIG. 9 shows a possible structural schematic diagram of the time synchronization device involved in the foregoing embodiment.
  • the device may be the second device or the second device.
  • the chip or the system-on-chip may also be a circuit, module, or unit used in the second device to implement the foregoing method embodiments.
  • the device includes: a receiving unit 901 and a processing unit 902.
  • the receiving unit 901 is used to support the device to perform S403 in the above method embodiment or S703 in the above method embodiment;
  • the processing unit 902 is used to support the device to perform S404 in the above method embodiment or the above method embodiment S704, and/or other technical processes described in this article.
  • An embodiment of the present application also provides a time synchronization system.
  • the time synchronization system includes a first device and a second device; wherein, the first device may be configured to execute the first device in the foregoing method embodiment as shown in FIG.
  • the steps of the device; the second device can be used to perform the steps of the second device in the foregoing method embodiment as shown in FIG. 9 above.
  • the minimum time unit of the time value sent by the first device may be less than seconds, so as to improve the accuracy of the time information in the time synchronization process; in addition, when the above solution is implemented through a digital circuit, it can avoid In order to solve the problem of deviation between the output time and the actual time, the structure of the digital circuit is relatively simple, and the implementation cost, power consumption and complexity are relatively low. Therefore, the above solution can improve the synchronization performance of the time interface.
  • the disclosed device and method may be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the module or unit is only a division of logical functions.
  • there may be another division manner for example, multiple units or components may be The combination can either be integrated into another device, or some features can be ignored, or not implemented.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may be one physical unit or multiple physical units, that is, may be located in one place, or may be distributed in multiple different places . Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or software function unit.

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Abstract

一种时间同步的方法及装置，涉及通信技术领域，用于提高时间接口的同步性能，同时保证较低的实现成本、功耗和复杂度。所述方法包括：第一设备向第二设备发送的NPPS信号和TOD信号中，该NPPS的升/降沿对应的时间值包括小于秒的时间值，该TOD信号能够承载该小于秒的时间值，从而第二设备在接收到该NPPS信号和该TOD信号时，能够基于该小于秒的时间值实现时间同步，从而提高了时间同步的精准度，同时在电路实现上也能够降低成本、功耗和复杂度。

Description

一种时间同步的方法及装置 技术领域
本申请涉及通信技术领域，尤其涉及一种时间同步的方法及装置。
背景技术
在通信技术领域，一直存在着时间同步的需求，时间同步可以是指将相互通信的多个设备的时间设置为一致，比如，将相互通信的多个设备的时间设置为与网络上的时间源一致，这里的时间源可以由网络中可靠的设备提供，比如GPS卫星或者时间服务器等。当设备间进行时间同步时，发送端设备可以通过标准的时间接口在某一时刻输出该时刻对应的时间值，接收端设备通过解析得到对应的时间值，并基于解析得到的时间值实现设备间的时间同步。
现有技术中，标准的时间接口通常包括：秒脉冲(1pulse per second，1PPS)+日时间(time of day，TOD)接口和直流电平转换(DC level shift，DCLS)接口。上述两种时间接口在协议定义上都是每秒输出一次时间信息，且输出的时间信息的最小单位为秒，从而只能在整秒时刻进行时间同步。另外，基于上述协议定义，这两种时间接口在电路实现方面会存在以下问题：数字电路很难控制每次输出的时间为整秒时刻，从而输出时间与实际时间存在一定的偏差；模拟电路能够实现准确实现整秒时刻的输出，但是成本高、功耗大且实现复杂度高。因此，如何提高时间接口的同步性能、且保证其实现成本、功耗和复杂度较低是一个关键问题。
发明内容
本申请的实施例提供一种时间同步的方法及装置，用于提高时间接口的同步性能，同时保证较低的实现成本、功耗和复杂度。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供一种时间同步的方法，该方法包括：第一设备生成每秒N次脉冲NPPS信号和日时间TOD信号，TOD信号用于承载NPPS信号的升/降沿对应的时间值，该升/降沿对应的时间值包括小于秒的时间值，N为大于1的整数；第一设备向第二设备发送NPPS信号和TOD信号，以使得第二设备与第一设备的时间同步。上述技术方案中，上述TOD信号承载的时间值的最小时间单位可以小于秒，从而能够提高时间同步过程中该时间值的精准度；此外，在通过数字电路发送该NPPS信号和TOD信号时，尽管数字电路的时钟不是理想的，会导致NPPS的升/降沿对应的时间值包括小于秒的时间值，但由于上述TOD信号能够承载该小于秒的时间值，从而可以直接输出NPPS的升/降沿对应的时间值，避免了输出时间与实际时间存在偏差问题，同时数字电路的结构比较简单，实现成本、功耗和复杂度都比较低，因此能够提高时间接口的同步性能。
在第一方面的一种可能的实现方式中，该小于秒的时间值包括以下至少一项：毫秒、微秒、纳秒、或纳秒小数。上述可能的实现方式中，使得实现毫秒、微秒、纳秒、和/或纳秒小数级的时间同步，从而提高了时间同步过程中该时间值的精准度。
在第一方面的一种可能的实现方式中，该TOD承载的时间值与该NPPS的升/降沿对应的时间值一一对应。上述可能的实现方式中，能够提高该TOD承载的时间值的灵活性，进而使得在电路实现上，成本、功耗和复杂度都比较低。
在第一方面的一种可能的实现方式中，该TOD信号还用于承载第一时延，第一时延包括第一设备内部的传输时延或者第一设备与第二设备之间的传输时延中的至少一种时延，即第一设备可以将第一时延与NPPS信号的升降沿对应的时间值叠加后承载在TOD信号上，以实现传输时延的补偿。上述可能的实现方式中，提供了一种简单有效的补偿延时的方法，且不会带来电路实现方面的复杂度较高问题。
第二方面，提供一种时间同步的方法，该方法包括：第二设备接收第一设备发送的每秒N次脉冲NPPS信号和日时间TOD信号，TOD信号用于承载NPPS信号的升/降沿对应的时间值，该时间值包括小于秒的时间值，N为大于1的整数；第二设备根据NPPS信号和TOD信号，将第二设备与第一设备的时间同步。上述技术方案中，上述TOD信号承载的NPPS信号的升/降沿对应的时间值的最小时间单位可以小于秒，从而能够提高时间同步过程中该时间值的精准度；此外，在通过数字电路发送该NPPS信号和TOD信号时，尽管数字电路的时钟不是理想的，会导致NPPS的升/降沿对应的时间值包括小于秒的时间值，但由于上述TOD信号也能够承载该小于秒的时间值，从而可以直接输出NPPS的升/降沿对应的时间值，避免了输出时间与实际时间存在偏差问题，同时数字电路的结构比较简单，实现成本、功耗和复杂度都比较低，因此能够提高时间接口的同步性能。
在第二方面的一种可能的实现方式中，该小于秒的时间信息包括以下至少一项：毫秒、微秒、纳秒、或纳秒小数。上述可能的实现方式中，使得实现毫秒、微秒、纳秒、和/或纳秒小数级的时间同步，从而提高了时间同步过程中该时间值的精准度。
在第二方面的一种可能的实现方式中，该TOD承载的时间值与该NPPS的升/降沿对应的时间值一一对应。上述可能的实现方式中，能够提高该TOD承载的时间值的灵活性，进而使得在电路实现上，成本、功耗和复杂度都比较低。
在第二方面的一种可能的实现方式中，该TOD信号还用于承载第一时延，第一时延包括第一设备内部的传输时延或者第一设备与第二设备之间的传输时延中的至少一种时延，即第一设备可以将第一时延与NPPS信号的升降沿对应的时间值叠加后承载在TOD信号上，以实现传输时延的补偿。上述可能的实现方式中，提供了一种简单有效的补偿延时的方法，且不会带来电路实现方面的复杂度较高问题。
第三方面，提供一种时间同步的装置，该装置包括：处理单元，用于生成每秒N次脉冲NPPS信号和日时间TOD信号，TOD信号用于承载NPPS信号的升/降沿对应的时间值，该时间值包括小于秒的时间值，N为大于1的整数；发送单元，用于向第二设备发送NPPS信号和TOD信号，以使得第二设备与该装置的时间同步。
在第三方面的一种可能的实现方式中，该小于秒的时间信息包括以下至少一项：毫秒、微秒、纳秒、或纳秒小数。
在第三方面的一种可能的实现方式中，该TOD承载的时间值与该NPPS的升/降沿对应的时间值一一对应。
在第三方面的一种可能的实现方式中，该TOD信号还用于承载第一时延，第一时 延包括该装置内部的传输时延或者该装置与第二设备之间的传输时延中的至少一种时延。
第四方面，提供一种时间同步的装置，该装置包括：接收单元，用于接收第一设备发送的每秒N次脉冲NPPS信号和日时间TOD信号，TOD信号用于承载NPPS信号的升/降沿对应的时间值，时间值包括小于秒的时间值，N为大于1的整数；处理单元，用于根据NPPS信号和TOD信号，将该装置与第一设备的时间同步。
在第四方面的一种可能的实现方式中，该小于秒的时间信息包括以下至少一项：毫秒、微秒、纳秒、或纳秒小数。
在第四方面的一种可能的实现方式中，该TOD承载的时间信息与该NPPS的升/降沿对应的时间值一一对应。
在第四方面的一种可能的实现方式中，若第一设备内部存在第一时延的传输时延或者第一设备与该装置之间存在第一时延的传输时延，TOD信号还用于承载第一时延。
第五方面，提供一种时间同步的方法，该方法包括：第一设备生成每秒N次直流电平转换N-DCLS信号，每次DCLS信号包括W个码元，该W个码元用于承载该W个码元中第一基准码元的升/降沿对应的时间值，该升/降沿对应的时间值包括小于秒的时间值，N为大于1的整数；第一设备向第二设备发送N-DCLS信号，以使得第二设备与第一设备的时间同步。上述技术方案中，上述W个码元承载的时间值的最小时间单位可以小于秒，从而能够提高时间同步过程中该时间值的精准度；此外，在通过数字电路发送该N-DCLS信号时，尽管数字电路的时钟不是理想的，会导致第一基准码元的升/降沿对应的时间值包括小于秒的时间值，但由于上述W个码元能够承载该小于秒的时间值，从而可以直接输出第一基准码元的升/降沿对应的时间值，避免了输出时间与实际时间存在偏差问题，同时数字电路的结构比较简单，实现成本、功耗和复杂度都比较低，因此能够提高时间接口的同步性能。
在第五方面的一种可能的实现方式中，W为大于100的整数，W个码元中除前100个码元之前的码元用于承载该小于秒的时间值；可选的，W个码元为100*M个码元，M为大于1的整数。上述可能的实现方式，提供的承载该小于秒的时间值的实现方式能够兼容现有通过每秒1次DCLS信号实现时间同步的方式。
在第五方面的一种可能的实现方式中，该小于秒的时间值包括以下至少一项：毫秒、微秒、纳秒、或纳秒小数。上述可能的实现方式中，使得实现毫秒、微秒、纳秒、和/或纳秒小数级的时间同步，从而提高了时间同步过程中该时间值的精准度。
在第五方面的一种可能的实现方式中，W个码元中除第一基准码元之外的其他码元用于承载第一基准码元的升/降沿对应的时间值。上述可能的实现方式中，能够提高W个码元承载的时间值的灵活性，进而使得在电路实现上，成本、功耗和复杂度都比较低。
在第五方面的一种可能的实现方式中，该N-DCLS信号还用于承载第一时延，第一时延包括第一设备内部的传输时延或者第一设备与第二设备之间的传输时延中的至少一种时延，即第一设备可以将第一时延与第一基准码元的升降沿对应的时间值叠加后承载在该N-DCLS信号上，以实现传输时延的补偿。上述可能的实现方式中，提供 了一种简单有效的补偿延时的方法，且不会带来电路实现方面的复杂度较高问题。
第六方面，提供一种时间同步的方法，该方法包括：第二设备接收第一设备发送的每秒N次直流电平转换N-DCLS信号，每次DCLS信号包括W个码元，该W个码元用于承载该W个码元中第一基准码元的升/降沿对应的时间值，该升/降沿对应的时间值包括小于秒的时间值，N为大于1的整数；第二设备根据N-DCLS信号将第二设备与第一设备的时间同步。上述技术方案中，上述W个码元承载的时间值的最小时间单位可以小于秒，从而能够提高时间同步过程中该时间值的精准度；此外，在通过数字电路发送该N-DCLS信号时，尽管数字电路的时钟不是理想的，会导致第一基准码元的升/降沿对应的时间值包括小于秒的时间值，但由于上述W个码元能够承载该小于秒的时间值，从而可以直接输出第一基准码元的升/降沿对应的时间值，避免了输出时间与实际时间存在偏差问题，同时数字电路的结构比较简单，实现成本、功耗和复杂度都比较低，因此能够提高时间接口的同步性能。
在第六方面的一种可能的实现方式中，W为大于100的整数，W个码元中除前100个码元之前的码元用于承载该小于秒的时间值；可选的，W个码元为100*M个码元，M为大于1的整数。上述可能的实现方式，提供的承载该小于秒的时间值的实现方式能够兼容现有通过每秒1次DCLS信号实现时间同步的方式。
在第六方面的一种可能的实现方式中，该小于秒的时间值包括以下至少一项：毫秒、微秒、纳秒、或纳秒小数。上述可能的实现方式中，使得实现毫秒、微秒、纳秒、和/或纳秒小数级的时间同步，从而提高了时间同步过程中该时间值的精准度。
在第六方面的一种可能的实现方式中，W个码元中除第一基准码元之外的其他码元用于承载第一基准码元的升/降沿对应的时间值。上述可能的实现方式中，能够提高W个码元承载的时间值的灵活性，进而使得在电路实现上，成本、功耗和复杂度都比较低。
在第六方面的一种可能的实现方式中，该N-DCLS信号还用于承载第一时延，第一时延包括第一设备内部的传输时延或者第一设备与第二设备之间的传输时延中的至少一种时延，即第一设备可以将第一时延与第一基准码元的升降沿对应的时间值叠加后承载在该N-DCLS信号上，以实现传输时延的补偿。上述可能的实现方式中，提供了一种简单有效的补偿延时的方法，且不会带来电路实现方面的复杂度较高问题。
第七方面，提供一种时间同步的装置，该装置包括：处理单元，用于生成每秒N次直流电平转换N-DCLS信号，每次DCLS信号包括W个码元，该W个码元用于承载该W个码元中第一基准码元的升/降沿对应的时间值，该升/降沿对应的时间值包括小于秒的时间值，N为大于1的整数；发送单元，用于向第二设备发送N-DCLS信号，以使得第二设备与该装置的时间同步。
在第七方面的一种可能的实现方式中，W为大于100的整数，W个码元中除前100个码元之前的码元用于承载该小于秒的时间值；可选的，W个码元为100*M个码元，M为大于1的整数。
在第七方面的一种可能的实现方式中，该小于秒的时间值包括以下至少一项：毫秒、微秒、纳秒、或纳秒小数。
在第七方面的一种可能的实现方式中，该W个码元中除第一基准码元之外的其他 码元用于承载第一基准码元的升/降沿对应的时间值。
在第七方面的一种可能的实现方式中，该N-DCLS信号还用于承载第一时延，第一时延包括该装置内部的传输时延或者该装置与第二设备之间的传输时延中的至少一种时延。
第八方面，提供一种时间同步的装置，该装置包括：接收单元，用于接收第一设备发送的每秒N次直流电平转换N-DCLS信号，每次DCLS信号包括W个码元，该W个码元用于承载该W个码元中第一基准码元的升/降沿对应的时间值，该升/降沿对应的时间值包括小于秒的时间值，N为大于1的整数；处理单元，用于根据N-DCLS信号将该装置与第一设备的时间同步。
在第八方面的一种可能的实现方式中，W为大于100的整数，W个码元中除前100个码元之前的码元用于承载该小于秒的时间值；可选的，W个码元为100*M个码元，M为大于1的整数。
在第八方面的一种可能的实现方式中，该小于秒的时间值包括以下至少一项：毫秒、微秒、纳秒、或纳秒小数。
在第八方面的一种可能的实现方式中，该W个码元中除第一基准码元之外的其他码元用于承载第一基准码元的升/降沿对应的时间值。
在第八方面的一种可能的实现方式中，该N-DCLS信号还用于承载第一时延，第一时延包括第一设备内部的传输时延或者第一设备与该装置之间的传输时延中的至少一种时延。
在本申请的又一方面，提供一种时间同步的系统，该系统包括第一设备和第二设备；其中，第一设备为上述第三方面或者第三方面的任一种可能的实现方式所提供的时间同步的装置，第二设备上述第四方面或者第四方面的任一种可能的实现方式所提供的时间同步的装置；或者，第一设备为上述第七方面或者第七方面的任一种可能的实现方式所提供的时间同步的装置，第二设备上述第八方面或者第八方面的任一种可能的实现方式所提供的时间同步的装置。
可以理解地，上述提供的任一种时间同步的方法的装置均用于执行上文所提供的对应的方法，因此，其所能达到的有益效果可参考上文所提供的对应的方法中的有益效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种通信系统的结构示意图；
图2为本申请实施例提供的一种1PPS+TOD接口的示意图；
图3为本申请实施例提供的一种DCLS接口的示意图；
图4为本申请实施例提供的一种时间同步的方法的流程示意图；
图5为本申请实施例提供的一种第一时间接口的示意图；
图6为本申请实施例提供的一种帧结构的示意图；
图7为本申请实施例提供的另一种时间同步的方法的流程示意图；
图8为本申请实施例提供的一种时间同步的装置的结构示意图一；
图9为本申请实施例提供的一种时间同步的装置的结构示意图二。
具体实施方式
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c或a-b-c，其中a、b和c可以是单个，也可以是多个。字符“/”一般表示前后关联对象是一种“或”的关系。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和执行次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
图1为本申请实施例提供的一种通信系统的结构示意图，参见图1，该通信系统包括第一设备和第二设备，第一设备与第二设备使用时间接口进行时间同步。其中，第一设备和第二设备通过有线方式连接，比如，第一设备与第二设备通过电缆连接。在实际应用中，第一设备和第二设备可以是网络中的网元(比如，第一设备和第二设备是网络中的两个终端)，也可以是时间同步性能测试中的测试仪表(比如，第一设备是网元，第二设备是用于测试第一设备的时间同步性能的测试仪表)等。
时间接口可以是指用于进行时间同步的接口，比如该时间接口可以包括秒脉冲(1pulse per second，1PPS)+日时间(time of day，TOD)接口、以及直流电平转换(DC level shift，DCLS)接口等。下面以第一设备向第二设备发送时间值为例分别对1PPS+TOD接口和DCLS接口举例说明。
1PPS+TOD接口：通过两根信号线传输时间值，两根信号线包括用于发送1PPS信号的信号线)和用于发送TOD信号的信号线，这里的TOD是一种计时方式。如图2所示，1PPS信号是1Hz信号，即每秒发送一个脉冲，1PPS信号的上升沿用于表示第一设备的整秒时刻；TOD信号用于承载1PPS信号的上升沿对应的时间值(单位为秒)，比如1PPS信号的上升沿对应的时间值为xxxx年xx月xx日xx时xx分xx秒。TOD信号在没有数据传输时信号为高电平；在有数据传输时，每个字节包含8比特，每个字节以1比特“0”为起始比特，以1比特“1”为结束比特，中间是8比特数据。TOD信号的波特率可以支持9600、19200、38400等，每比特的电平宽度可以遵从收发端设备约定的波特速率。图2中以1PPS信号的高电平脉宽为20ms-200ms，与1PPS的上升沿对应的TOD信号承载的时间信息的起始位置与该上升沿之间大于1ms，每次发送的时间值的长度小于500ms为例进行说明。
需要说明的是，上述TOD的帧结构可以包括帧头1、帧头2、消息类、消息ID、消息长度域、净负荷域和校验域(具体如下述图5所示)，净负荷域的长度可以为16个字节，且16个字节的相关描述可以参见下述表2所示的前16个字节的相关描述，本申请实施例在此不再赘述。
DCLS接口：通过一根信号线传输时间信息，该信号线用于传输DCLS信号。如图3所示，DCLS接口每秒可以发送100个码元，每个码元的时间宽度为10ms，每个 码元以不同占空比表示不同信息。其中，8ms:2ms(即高低电平比为4)表示基准码元(也叫参考码元)，5ms:5ms(即高低电平比为1)表示数据1，2ms:8ms(即高低电平比为1/4)表示数据0。其中每秒发送的100个码元中第一个码元和最后一个码元为8ms:2ms的占空比，即第一个码元和最后一个码元均为基准码元。在进行时间表示时，每秒的第一个基准码元的上升沿表示第一设备的整秒时刻，该时刻对应的第一设备的时间由该秒内除基准码元之外的其他码元承载。其中关于每秒发送的100个码元的码元定义和定义的说明可以参考现有技术中的相关描述，本申请实施例对此不作阐述。
图4为本申请实施例提供的一种时间同步的方法的流程示意图，参见图4，该方法包括以下几个步骤。
S401：第一设备生成每秒N次脉冲(N pulse per second，NPPS)信号和日时间(time of day，TOD)信号，该TOD信号用于承载该NPPS信号的升/降沿对应的时间值，该升/降沿对应的时间值包括小于秒的时间值，N为大于1的整数。
其中，NPPS信号是N Hz信号，即每秒发送N次脉冲，比如N＝2即表示每秒发送两次脉冲，N＝3即表示每秒发送3次脉冲，本申请实施例对N的具体取值不作限定。该TOD信号用于承载该NPPS信号的升/降沿对应的时间值，即该TOD信号可用于指示该NPPS信号的上升沿对应的时间值，也可以用于指示该NPPS信号的下降沿对应的时间值，具体指示的是上升沿对应的时间值或者是下降沿对应的时间值可以由第一设备与第二设备事先约定即可。
需要说明的是，在实际应用中，N的取值也可以等于1，即每秒发送1次脉冲，但是这样进行时间同步的间隔只能是1秒，而N取大于1的整数时进行时间同步的间隔为1/N，这样相对于N等于1而言，时间同步的频率能够得到提升，从而能够提高时间同步的性能。
另外，该NPPS信号的升/降沿对应的时间值包括小于秒的时间值，即该TOD信号承载的时间值的最小时间单位可以小于秒，比如，最小时间单位可以是毫秒(ms)、微秒(us)、纳秒(ns)或者纳秒小数(ns小数)等，从而该TOD信号承载的时间值可以是包括ms、us、ns或者ns小数的时间值，比如该时间值可以为2008年04月06日12时00分23秒14毫秒。
该TOD信号用于承载该NPPS信号的升/降沿对应的时间值，当该NPPS信号的升/降沿对应的时间值为整秒值时，该TOD信号承载的时间值可以是整秒值，此时小于秒的时间值即为0；当该NPPS信号的升/降沿对应的时间值为非整秒值(比如，包括ns或者ns小数的时间信息)时，该TOD信号承载的时间值也可以是非整秒值，此时小于秒的时间信息不为0。
具体的，该TOD信号承载的时间值与该NPPS信号的升/降沿对应的时间值一一对应，即该TOD信号上承载的每个时间值均用于指示该NPPS信号的不同升/降沿对应的时间值。图5为一种NPPS信号和TOD信号的示意图，图5中的(a)是该TOD信号承载的时间值与该NPPS信号的下降沿对应的时间值一一对应，图5中的(b)是该TOD信号承载的时间值与该NPPS信号的上升沿对应的时间值一一对应。该TOD信号在没有数据传输时信号为高电平；在有数据传输时，每个字节包含8比特，每个字节以1比特“0”为起始比特，以1比特“1”为结束比特，中间是8比特数据。本 申请实施例对该NPPS信号的高电平脉宽，与该NPPS信号的升/降沿对应的该TOD信号承载的时间值的起始位置与该升/降沿之间的时间宽度，以及每次发送的时间值的长度不作具体限定，只要能够保证上述方法的实现即可。
其中，该TOD信号的帧结构可以如图6所示，该帧结构包括帧头1、帧头2、消息类、消息ID、消息长度域、净负荷域和校验域，校验域的校验范围可以是消息类至净负荷域。其中，净负荷域可以包括21个字节，比如第16-第19个字节可以用于表示纳秒整数，第20-第21个字节可以用于表示纳秒小数。在实际应用时净负荷域还可以包括更多或者更少的字节，只要能够表示出小于秒的时间信息即可。下述表1以净负荷域包括21个字节为例对部分字节的定义进行解释说明，表1中字节偏移量为5-12的字节的相关描述具体可以参见现有技术中的相关描述，本申请实施例对此不作阐述。
表1
Figure PCTCN2019072324-appb-000001
需要说明的是，上述仅对净负荷域中第16-第21个字节的定义进行举例说明，并不对本申请实施例构成限定。另外，关于上述帧结构的详细描述可以参见相关技术，本申请实施例在此不再赘述。
S402：第一设备向第二设备发送该NPPS信号和该TOD信号。
S403：第二设备接收第一设备发送的NPPS信号和TOD信号。其中，S403中的NPPS信号和TOD信号与上述S401中的NPPS信号和TOD信号一致，具体参见上述S401中的描述，本申请实施例在此不再赘述。
其中，当第二设备接收到第一设备发送的NPPS信号和TOD信号时，第二设备可以对该NPPS信号和该TOD信号进行解析，以得到该TOD信号承载的该NPPS信号的升/降沿对应的时间值。若第一设备与第二设备事先约定该TOD信号承载的时间值指示的是该NPPS信号的上升沿对应的时间值，则第二设备解析得到的时间值可以为该NPPS信号的上升沿对应的时间值；若第一设备与第二设备事先约定该TOD信号承载的时间值指示的是该NPPS信号的下降沿对应的时间值，则第二设备解析得到的时间值可以为该NPPS信号的下降沿对应的时间值。
S404：第二设备根据该NPPS信号和该TOD信号，将第二设备与第一设备的时间同步。
当第二设备解析得到该NPPS信号的下降沿对应的时间值时，第二设备可以根据该时间值对第二设备的本地时间进行校准，比如，第二设备将自身的本地时间校准为与该NPPS信号的下降沿对应的时间值一致，以实现第二设备与第一设备的时间同步。
进一步地，当第一设备内部存在第一时延的传输时延、或者第一设备与第二设备之间存在第一时延的传输时延时，该TOD信号还用于承载第一时延，即TOD信号承载的时间值可以为第一时延与该NPPS的升/降沿对应的时间值的叠加。此时，第一时延由第一设备进行补偿，即第一设备提前将第一延时与该NPPS信号的升/降沿对应的时间值叠加之后作为该TOD信号承载的时间值发送给第二设备。
或者，第一时延由第二设备进行补偿，即该NPPS信号的升/降沿对应的时间值与TOD信号承载的时间值一致，当第二设备解析得到该TOD信号承载的时间值后，第二设备将第一时延与该TOD信号承载的时间值叠加，使用叠加后得到的时间值作时间同步。比如，第一设备发出该NPPS信号的下降沿对应的时间值(即本地时间)为：1秒100ms时刻，该TOD信号承载这个“1秒100毫秒”的信息，若第一设备与第二设备之间的传输路径延时为100ns(即第一时延为100ns)，则第二设备在作时间同步时，第二设备需要将该TOD信号承载的时间值“1秒100毫秒”与第一时延“100ns”相加，并将其自身的本地时间设置为与相加后的时间值“1秒100毫秒100ns”一致，即该NPPS信号的下降沿到达第二设备时，第一设备的本地时间是“1秒100毫秒100ns”。
在本申请实施例中，上述TOD信号承载的时间值的最小时间单位可以小于秒，从而能够提高时间同步过程中该时间值的精准度。另外，在通过数字电路实现该方案时，尽管数字电路的时钟不是理想的，会因为网络抖动或者温度漂移等原因导致实际计时步长与理论计时步长产生偏差(比如，以1GHz的时钟为例，理论计时步长为1ns、实际计时步长可能为0.95ns)，进而导致该NPPS的升/降沿对应的时间值包括小于秒的时间值，但由于上述TOD信号能够承载小于秒的时间值，从而可以直接输出该NPPS的升/降沿对应的时间值，避免了输出时间与实际时间存在偏差问题，同时数字电路的结构比较简单，实现成本、功耗和复杂度都比较低。因此，上述方法能够提高时间接口的同步性能。
图7为本申请实施例提供的一种时间同步的方法的流程示意图，参见图7，该方法包括以下几个步骤。
S701：第一设备生成每秒N次DCLS(N-DCLS)信号，每次DCLS信号包括W个码元，该W个码元用于承载该W个码元中第一基准码元的升/降沿对应的时间值，该升/降沿对应的时间值包括小于秒的时间值，N为大于1的整数。
示例性的，W可以为大于100的整数，比如，W个码元可以为110个码元、120个码元、200个码元、或者300个码元等。可选的，W个码元等于100*M个码元，M为大于1的正整数，即W个码元的数量可以为100的整数倍，本申请实施例中以W个码元等于100*M个码元为例进行说明。
其中，每秒N次DCLS信号，即每秒发送N次DCLS信号，比如N＝2即表示每秒发送两次DCLS信号，N＝3即表示每秒发送3次DCLS信号，本申请实施例对N的 具体取值不作限定。每次发送的DCLS信号可包括100*M个码元，每个码元的时间宽度为10/(M*N)ms，比如M＝2即表示每次发送的DCLS信号包括200个码元，M＝3即表示每次发送的DCLS信号包括300个码元，本申请实施例对M的具体取值不作限定。其中，每个码元以不同占空比表示不同信息，具体与上述DCLS接口中的描述类似，高低电平比为4表示基准码元(也叫参考码元)，高低电平比为1表示数据1，即高低电平比为1/4表示数据0。其中每次发送的100*M个码元中第一个码元和最后一个码元对应的高低电平比为4，即第一个码元和最后一个码元均为基准码元。
该W个码元用于承载该W个码元中第一基准码元(即第一个基站码元)的升/降沿对应的时间值，即该W个码元用于承载该W个码元中第一基准码元的上升沿对应的时间值，也可以用于承载该W个码元中第一基准码元的下降沿对应的时间值，具体指示的是上升沿对应的时间值或者是下降沿对应的时间值可以由第一设备与第二设备事先约定即可。
需要说明的是，在实际应用中，N的取值也可以等于1，即每秒发送1次，但是这样进行时间同步的间隔只能是1秒，而N取大于1的整数时进行时间同步的间隔为1/N，这样相对于N等于1而言，时间同步的频率能够得到提升，从而能够提高时间同步的性能。
另外，该W个码元承载的时间值包括小于秒的时间值，即该W个码元承载的时间值的最小时间单位可以小于秒，比如，最小时间单位可以是ms、us、ns或者ns小数等，从而该时间值可以是包括ms、us、ns或者ns小数的时间值，比如该时间值为2008年04月06日12时00分23秒14毫秒。
该W个码元用于承载该W个码元中第一基准码元的升/降沿对应的时间值，当第一基准码元的升/降沿对应的时间值为整秒值时，该W个码元承载的时间值可以是整秒值，此时小于秒的时间信息即为0；当第一基准码元的升/降沿对应的时间值为非整秒值(比如，包括ns或者ns小数的时间信息)时，该W个码元承载的时间值也可以是非整秒值，此时小于秒的时间信息不为0。
具体的，100*M个码元中除第一基准码元之外的其他码元(即表示数据的码元)用于承载第一基准码元的升/降沿对应的时间值。即每次发送的100*M个码元可用于传输一次时间值，在每次发送的100*M个码元中，除第一基准码元之外的其他码元(用于表示数据的码元)用于承载第一基准码元的升/降沿对应的时间值。
为便于理解，下面表2中以M＝2为例对后100个码元(码元序号为100-199)的定义和说明进行举例说明，码元序号100-139具体可用于表示纳秒值，码元140-159具体可用于表示小数值，且每5个码元可以为一组，每5个码元中的第1个码元可以为索引位，每5个码元中的后4个码元可以用于表示纳秒值或者纳秒小数值。在如下表2中，以纳秒值包括32个字节(即0—31)，纳秒小数值包括16个字节(即0—15)，码元序号为160-199的码元为保留码元为例进行说明。
表2
码元序号 定义 说明
100 索引位 置“0”
101～104 纳秒值[31:28]  
… … …
136～139 纳秒值[3:0]  
140 索引位 置“0”
141～144 纳秒小数值[15:12]  
… … …
156～159 纳秒小数值[3:0]  
… … …
196～199 保留  
需要说明的是，上述仅对码元序号为100-199的100个码元的定义进行举例说明，并不对本申请实施例构成限定。
S702：第一设备向第二设备发送N-DCLS信号。
S703：第二设备接收第一设备发送的N-DCLS信号。其中，S703中的N-DCLS信号与上述7401中的N-DCLS信号一致，具体参见上述S701中的描述，本申请实施例在此不再赘述。
其中，当第二设备接收到第一设备发送的N-DCLS信号时，第二设备可以对该N-DCLS信号进行解析，以得到该W个码元承载的该W个码元中第一基准码元的升/降沿对应的时间值。若第一设备与第二设备事先约定该W个码元承载的时间值指示的是第一个基准码元的上升沿对应的时间值，则第二设备解析得到的时间值可以为第一个基准码元的上升沿对应的时间值；若第一设备与第二设备事先约定该W个码元承载的时间值指示的是第一个基准码元的下降沿对应的时间值，则第二设备解析得到的时间值可以为第一个基准码元的下降沿对应的时间值。
S704：第二设备根据该N-DCLS信号，将第二设备与第一设备的时间同步。
当第二设备解析得到该W个码元中第一基准码元的下降沿对应的时间值时，第二设备可以根据该时间值对第二设备的本地时间进行校准，比如，第二设备将自身的本地时间校准为与该W个码元中第一基准码元的下降沿对应的时间值一致，以实现第二设备与第一设备的时间同步。
进一步地，若第一设备内部存在第一时延的传输时延、或者是第一设备与第二设备之间存在第一时延的传输时延，该W个码元承载的时间值可以为第一时延与第一基准码元的升/降沿对应的时间值的叠加。此时，第一时延由第一设备进行补偿，即第一设备提前将第一延时与第一基准码元的升/降沿对应的时间值叠加之后作为该W个码元承载的时间值发送给第二设备。
或者，第一时延由第二设备进行补偿，即第一基准码元的升/降沿对应的时间值与该W个码元承载的时间值一致，当第二设备解析得到该W个码元承载的时间值后，第二设备将第一时延与该W个码元承载的时间值叠加后作时间同步。比如，第一设备发出W个码元中第一个码元的下降沿对应的时间值为：1秒100ms时刻，该W个码元承载这个“1秒100毫秒”的信息，若第一设备与第二设备之间的传输路径延时为100ns(即第一时延为100ns)，则第二设备在作时间同步时，第二设备需要将该W个码元上承载的“1秒100毫秒”信息值与第一时延“100ns”相加，并将其自身的本地时间设置为与相加后的时间值“1秒100毫秒100ns”一致，即该W个码元中第一 个码元的下降沿到达第二设备时，第一设备的本地时间是“1秒100毫秒100ns”。
在本申请实施例中，上述W个码元承载的时间值的最小时间单位可以小于秒，从而能够提高时间同步过程中该时间值的精准度。另外，在通过数字电路实现该方案时，尽管数字电路的时钟不是理想的，会因为网络抖动或者温度漂移等原因导致实际计时步长与理论计时步长产生偏差(比如，以1GHz的时钟为例，理论计时步长为1ns、实际计时步长可能为0.95ns)，进而导致第一基准码元的升/降沿对应的时间值为非整秒时刻时，但由于上述W个码元能够承载小于秒的时间值，从而可以直接输出第一基准码元的升/降沿对应的时间值，避免了输出时间与实际时间存在偏差问题，同时数字电路的结构比较简单，实现成本、功耗和复杂度都比较低。因此，上述方法能够提高时间接口的同步性能。
上述主要从设备交互的角度对本申请实施例提供的方案进行了介绍，可以理解的是，第一设备和第二设备，为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本申请实施例可以根据上述方法示例对第一设备和第二设备进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述功能模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在采用对应各个功能划分各个功能模块的情况下，图8示出了上述实施例中所涉及的时间同步的装置的一种可能的结构示意图，该装置可以为第一设备或者第一设备中的芯片或者片上系统，还可以为第一设备中用于实现上述方法实施例中的电路、模块或者单元等。该装置包括：处理单元801和发送单元802。其中，处理单元801用于支持该装置执行上述方法实施例中的S401、或者上述方法实施例中的S701、和/或本文所描述的其他技术过程；发送单元802用于支持该装置执行上述方法实施例中的S402、或者上述方法实施例中的S702。
在采用对应各个功能划分各个功能模块的情况下，图9示出了上述实施例中所涉及的时间同步的装置的一种可能的结构示意图，该装置可以为第二设备或者第二设备中的芯片或者片上系统，还可以为第二设备中用于实现上述方法实施例中的电路、模块或者单元等。该装置包括：接收单元901和处理单元902。其中，接收单元901用于支持该装置执行上述方法实施例中的S403、或者上述方法实施例中的S703；处理单元902用于支持该装置执行上述方法实施例中的S404、或者上述方法实施例中的S704，和/或本文所描述的其他技术过程。
本申请实施例还提供一种时间同步的系统，该时间同步的系统包括第一设备和第二设备；其中，第一设备可以如上述图8所示，用于执行上述方法实施例中第一设备的步骤；第二设备可以如上述图9所示，用于执行上述方法实施例中第二设备的步骤。
在本申请实施例中，上述第一设备发送的时间值的最小时间单位可以小于秒，从而能够提高时间同步过程中该时间信息的精准度；此外，在通过数字电路实现上述方案时，能够避免了输出时间与实际时间存在偏差问题，同时数字电路的结构比较简单，实现成本、功耗和复杂度都比较低。因此，上述方案能够提高时间接口的同步性能。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是一个物理单元或多个物理单元，即可以位于一个地方，或者也可以分布到多个不同地方。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种时间同步的方法，其特征在于，所述方法包括：
    第一设备生成每秒N次脉冲NPPS信号和日时间TOD信号，所述TOD信号用于承载所述NPPS信号的升/降沿对应的时间值，所述时间值包括小于秒的时间值，所述N为大于1的整数；
    所述第一设备向第二设备发送所述NPPS信号和所述TOD信号，以使得所述第二设备与所述第一设备的时间同步。
  2. 根据权利要求1所述的方法，其特征在于，所述小于秒的时间值包括以下至少一项：毫秒、微秒、纳秒、或纳秒小数。
  3. 根据权利要求1或2所述的方法，其特征在于，所述TOD信号承载的时间值与所述NPPS信号的升/降沿对应的时间值一一对应。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，所述TOD信号还用于承载第一时延，所述第一时延包括所述第一设备内部的传输时延或者所述第一设备与所述第二设备之间的传输时延中的至少一种时延。
  5. 一种时间同步的方法，其特征在于，所述方法包括：
    第二设备接收第一设备发送的每秒N次脉冲NPPS信号和日时间TOD信号，所述TOD信号用于承载所述NPPS信号的升/降沿对应的时间值，所述时间值包括小于秒的时间值，所述N为大于1的整数；
    所述第二设备根据所述NPPS信号和所述TOD信号，将所述第二设备与所述第一设备的时间同步。
  6. 根据权利要求5所述的方法，其特征在于，所述小于秒的时间值包括以下至少一项：毫秒、微秒、纳秒、或纳秒小数。
  7. 根据权利要求5或6所述的方法，其特征在于，所述TOD信号承载的时间值与所述NPPS信号的升/降沿对应的时间值一一对应。
  8. 根据权利要求5-7任一项所述的方法，其特征在于，所述TOD信号还用于承载第一时延，所述第一时延包括所述第一设备内部的传输时延或者所述第一设备与所述第二设备之间的传输时延中的至少一种时延。
  9. 一种时间同步的装置，其特征在于，所述装置包括：
    处理单元，用于生成每秒N次脉冲NPPS信号和日时间TOD信号，所述TOD信号用于承载所述NPPS信号的升/降沿对应的时间值，所述时间值包括小于秒的时间值，所述N为大于1的整数；
    发送单元，用于向第二设备发送所述NPPS信号和所述TOD信号，以使得所述第二设备与所述装置的时间同步。
  10. 根据权利要求9所述的装置，其特征在于，所述小于秒的时间值包括以下至少一项：毫秒、微秒、纳秒、或纳秒小数。
  11. 根据权利要求9或10所述的装置，其特征在于，所述TOD信号承载的时间值与所述NPPS信号的升/降沿对应的时间值一一对应。
  12. 根据权利要求11所述的装置，其特征在于，所述TOD信号还用于承载第一 时延，所述第一时延包括所述装置内部的传输时延或者所述装置与所述第二设备之间的传输时延中的至少一种时延。
  13. 一种时间同步的装置，其特征在于，所述装置包括：
    接收单元，用于接收第一设备发送的每秒N次脉冲NPPS信号和日时间TOD信号，所述TOD信号用于承载所述NPPS信号的升/降沿对应的时间值，所述时间值包括小于秒的时间值，所述N为大于1的整数；
    处理单元，用于根据所述NPPS信号和所述TOD信号，将所述装置与所述第一设备的时间同步。
  14. 根据权利要求13所述的装置，其特征在于，所述小于秒的时间值包括以下至少一项：毫秒、微秒、纳秒、或纳秒小数。
  15. 根据权利要求13或14所述的装置，其特征在于，所述TOD信号承载的时间值与所述NPPS信号的升/降沿对应的时间值一一对应。
  16. 根据权利要求13-15任一项所述的装置，其特征在于，所述TOD信号还用于承载第一时延，所述第一时延包括所述第一设备内部的传输时延或者所述第一设备与所述装置之间的传输时延中的至少一种时延。
  17. 一种时间同步的系统，其特征在于，所述系统包括第一设备和第二设备，所述第一设备为上述权利要求9-12任一项所述的时间同步的装置，所述第二设备为上述权利要求13-16任一项所述的时间同步的装置。
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