WO2020147023A1 - Procédé et appareil de conversion de signaux par salves en signaux continus - Google Patents

Procédé et appareil de conversion de signaux par salves en signaux continus Download PDF

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Publication number
WO2020147023A1
WO2020147023A1 PCT/CN2019/071848 CN2019071848W WO2020147023A1 WO 2020147023 A1 WO2020147023 A1 WO 2020147023A1 CN 2019071848 W CN2019071848 W CN 2019071848W WO 2020147023 A1 WO2020147023 A1 WO 2020147023A1
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Prior art keywords
continuous
data packet
burst
bits
signal
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PCT/CN2019/071848
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English (en)
Chinese (zh)
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周雷
刘翔
李胜平
聂世玮
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华为技术有限公司
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Priority to CN201980059707.0A priority Critical patent/CN112690007B/zh
Priority to PCT/CN2019/071848 priority patent/WO2020147023A1/fr
Publication of WO2020147023A1 publication Critical patent/WO2020147023A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems

Definitions

  • This application relates to the field of communications, and more specifically, to a method and device for converting a burst signal to a continuous signal.
  • the PON system includes two types of network elements: optical line terminal (OLT) and optical network unit (ONU).
  • OLT optical line terminal
  • ONU optical network unit
  • the PON system is a point-to-multipoint time-division multiplexing system, and usually the working mode of upstream transmission is burst mode. In other words, the OLT needs to receive signals from different ONUs at different times. Because the physical distance between each ONU and the OLT is different, the signals sent by different ONUs received by the OLT may have different amplitudes and a series of burst data packets with different intervals in time.
  • the OLT side optical module can only pass the burst serializer/deserializer (serializer/deserializer, SerDes) and the OLT single board after receiving the burst signal of the ONU.
  • SerDes serializer/deserializer
  • the OLT single board After receiving the burst signal of the ONU.
  • SerDes serializer/deserializer
  • the MAC chip connection and data transmission On the MAC chip connection and data transmission.
  • 25G/50G/100G and other next-generation PONs the continued use of burst SerDes for data transmission in optical modules and MAC chips will result in a significant reduction in the efficiency of data transmission.
  • This application provides a method and device for converting burst signals to continuous signals, which can convert burst signals received from multiple ONUs into continuous signals, so that the OLT side optical module can realize data transmission to the MAC chip through continuous SerDes. This can improve the efficiency of data transmission.
  • a method for converting a burst signal to a continuous signal includes: an optical processing device performs data filling on the interval between the burst data packets contained in the burst signal to obtain a continuous signal containing continuous data packets , Wherein the burst signal comes from multiple ONUs; the continuous data packet is encoded to obtain a continuous signal containing the encoded continuous data packet; and the continuous SerDes is used to convert the continuous data packet containing the encoded continuous data packet The signal is sent to the network processing device.
  • the optical processing device can convert the burst signal into a continuous signal, the optical processing device can use continuous SerDes to transmit the continuous signal to the network processing device. Using this solution can improve the efficiency of data transmission.
  • the optical processing device can also perform various processing on the burst optical signals sent by multiple ONUs, for example:
  • the burst optical signal is converted into a current signal;
  • the optical processing device converts the current signal into a voltage signal, and amplifies the voltage signals with different amplitudes to basically the same amplitude;
  • the optical processing device converts the analog voltage signal into a digital signal;
  • optical processing samples multiple burst data packets contained in the digital signal to obtain multiple optimal sampling points and interference information, and then these optimal sampling points and interference information form a burst data packet;
  • optical processing equipment can also shape and process, The above interference information is removed, and only the burst data packet containing the best sampling point is retained;
  • the optical processing device can also decode the burst data packet;
  • the optical processing device can also demodulate the decoded burst data packet, Obtain burst data packets containing only 0 or 1.
  • the optical processing device in the embodiment of the present application may be an optical module of an OLT.
  • the optical module in the embodiment of the present application fills the intervals between the burst data packets contained in the burst signal, which may be specifically: using a scrambling polynomial to correct the burst.
  • the burst data packet contained in the signal and the interval between the burst data packet are calculated and processed.
  • the interval between the burst data packet and the burst data packet Take n bits from all the bits included in the interval in turn, take the m-th bit and the n-th bit in every n bits; take the m-th bit and the n-th bit in every n bits Adding the first bit in every n bits to obtain the scrambled data of every n bits, and all the scrambled data of every n bits form a continuous data packet.
  • a method for converting a burst signal to a continuous signal includes: a network processing device receives a continuous signal sent by an optical processing device through a continuous SerDes, and the continuous signal contains an encoded continuous data packet; The encoded continuous data packet is decoded to obtain a continuous signal including the decoded continuous data packet; the data filled in the decoded continuous data packet is removed to obtain the decoded burst data packet.
  • removing the data filled in the decoded continuous data packet may be specifically: using a descrambling code polynomial to calculate the decoded continuous data packet Processing, wherein the descrambling code polynomial and the scrambling code polynomial adopted by the optical processing device are the same or have a reciprocal relationship.
  • the descrambling code polynomial is used to calculate and process the decoded continuous data packet, which can be understood as: take out n bits in turn from all the bits contained in the encoded continuous data packet, and take out every n bits The mth bit and the nth bit; in each n bits, the mth bit and the nth bit are subtracted from the first bit in every n bits to obtain the every n
  • the data after the descrambling code of one bit, and all the data after the descrambling code of every n bits form a burst data packet.
  • an embodiment of the present application provides an optical processing device, which includes several functional units for implementing any method of the first aspect.
  • the optical processing equipment may include:
  • the scrambling code module is used to fill the intervals between the burst data packets contained in the burst signal to obtain a continuous signal containing continuous data packets, where the burst signal comes from multiple ONUs.
  • the encoding module is configured to encode the continuous data packet to obtain a continuous signal containing the encoded continuous data packet, and send the continuous signal containing the encoded continuous data packet to the network processing device through the continuous SerDes.
  • an embodiment of the present application provides a network processing device, including several functional units for implementing any method of the second aspect.
  • the network processing equipment may include:
  • the decoding module is used to receive the continuous signal sent by the optical processing device through the continuous SerDes, the continuous signal contains the encoded continuous data packet, decode the encoded continuous data packet, and obtain the continuous signal containing the decoded continuous data packet Continuous signal.
  • the descrambling code module is used to remove the data filled in the decoded continuous data packet to obtain the decoded burst data packet.
  • an embodiment of the present application provides an optical processing device, including: a non-volatile memory and a processor coupled with each other, the processor calls the program code stored in the memory to execute any of the first aspect Part or all of the steps of a method.
  • an embodiment of the present application provides a network processing device, including: a non-volatile memory and a processor coupled with each other, the processor calls the program code stored in the memory to execute any of the second aspect Part or all of the steps of a method.
  • an embodiment of the present application provides a computer-readable storage medium, the computer-readable storage medium stores program code, wherein the program code includes part or Instructions for all steps.
  • an embodiment of the present application provides a computer-readable storage medium, the computer-readable storage medium stores program code, wherein the program code includes part or Instructions for all steps.
  • the embodiments of the present application provide a computer program product, which when the computer program product runs on a computer, causes the computer to execute part or all of the steps of any method in the first aspect.
  • an embodiment of the present application provides a computer program product that, when the computer program product runs on a computer, causes the computer to perform part or all of the steps of any one of the methods of the first aspect.
  • an embodiment of the present application provides a system, including: an optical processing device as in any third aspect and a network processing device as in any fourth aspect.
  • Fig. 1 is a schematic diagram of an application scenario of a PON provided by an embodiment of the present application.
  • Fig. 2 is a schematic diagram of a PON reference model provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a reference model of an OLT provided by an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a method for converting a burst signal to a continuous signal according to an embodiment of the present application.
  • Fig. 5 is a schematic block diagram of scrambling code calculation of a scrambling code polynomial provided in an embodiment of the present application.
  • Fig. 6 is a schematic diagram of a frame format of a continuous data packet provided by an embodiment of the present application.
  • Fig. 7 is a schematic block diagram of the descrambling code calculation of the descrambling code polynomial provided.
  • Fig. 8 is a schematic diagram of a simulation example of an embodiment of the present application.
  • FIG. 9 is a schematic block diagram of an optical processing device 900 provided by an embodiment of the present application.
  • FIG. 10 is a schematic block diagram of a network processing device 1000 according to an embodiment of the present application.
  • FIG. 11 is a schematic block diagram of another optical processing device 1100 according to an embodiment of the present application.
  • FIG. 12 is a schematic block diagram of another network processing device 1200 according to an embodiment of the present application.
  • the technical solutions of the embodiments of the present invention can be applied to various Ethernet Passive Optical Network (EPON) and Gigabit Passive Optical Network (GPON), such as 10G EPON, single wave 25G EPON, 2x25G EPON, single-wave 50G EPON, 2x50G EPON, 100G EPON, etc., as well as GPON, XGPON, XGSPON, time and wavelength division multiplexing based passive optical networks (time wavelength division multiplexing, passive optical network, TWDMPON) or others Type of GPON.
  • EPON Ethernet Passive Optical Network
  • GPON Gigabit Passive Optical Network
  • 10G EPON single wave 25G EPON, 2x25G EPON, single-wave 50G EPON, 2x50G EPON, 100G EPON, etc.
  • GPON XGPON, XGSPON
  • time and wavelength division multiplexing based passive optical networks time wavelength division multiplexing, passive optical network, TWDMPON
  • the optical line terminal (optical line terminal, OLT) is the core component of the PON and provides a user-oriented optical fiber interface for the passive optical network.
  • OLT optical line terminal
  • One end of the OLT is connected to the upper network to complete the upstream access of the PON.
  • the upper network may be an Internet Protocol (IP) backbone network or a public switched telephone network (PSTN).
  • IP Internet Protocol
  • PSTN public switched telephone network
  • the other end of the OLT connects to an optical network unit (ONU) through an optical distribution network (optical distribution network, ODN), completes the downstream transmission of the PON, and realizes functions such as ONU control, management, and ranging.
  • ODN optical distribution network
  • the OLT in the figure can provide services for multiple ONUs at the same time through ODN, and one ONU can serve multiple user equipments at the same time, such as mobile phones, computers, etc., which is not limited here.
  • FIG. 2 is a schematic diagram of the architecture of a PON system to which various embodiments of the present invention are applied.
  • the PON system 200 includes at least one OLT 210, at least one ODN 220 and multiple ONUs 230.
  • the OLT 210 provides a network side interface for the PON system 200
  • the ONU 230 provides a user side interface for the PON system 200, which is connected to the ODN 220.
  • the ONU 230 directly provides the user port function, it is called an optical network terminal (Optical Network Terminal, ONT).
  • ONT optical Network Terminal
  • the ONU 230 mentioned below collectively refers to an ONT that can directly provide a user port function and an ONU that provides a user-side interface.
  • ODN 220 is a network composed of optical fibers and passive optical splitting devices, used to connect OLT210 equipment and ONU230 equipment, and used to distribute or multiplex data signals between OLT210 and ONU230.
  • the direction from the OLT 210 to the ONU 230 is defined as the downstream direction, and the direction from the ONU 230 to the OLT 210 is defined as the upstream direction.
  • the OLT 210 uses Time Division Multiplexing (TDM) to broadcast downstream data to multiple ONUs 230 managed by the OLT 110, and each ONU 230 only receives the data carrying its own identity; while in the upstream direction, multiple ONUs 230 It communicates with the OLT 210 in a Time Division Multiple Access (TDMA) manner, and each ONU 230 transmits uplink data according to the time domain resources (also referred to as time slots) allocated by the OLT 210 to it.
  • TDM Time Division Multiplexing
  • TDMA Time Division Multiple Access
  • the TDMA technology is used to divide the fiber occupation into time periods. In each time period, only one ONU can occupy the fiber to send data to the OLT, and the other ONUs turn off the laser and do not send optical signals.
  • the OLT specifies the time period for the ONU to send data by sending control data packets to avoid conflicts. In order to obtain the correct time offset and power adjustment, the OLT needs to perform ranging on different ONUs. Because the results of ranging may have errors, these errors may cause conflicts caused by the OLT receiving optical signals sent by different ONUs at the same time.
  • the OLT introduces a protection mechanism in which there is a time interval between optical signals sent by different ONUs to ensure that there is an interval between the OLT receiving optical signals sent by different ONUs, thereby avoiding the above conflicts, but also causing the OLT to receive different ONUs
  • the optical signals are bursty, that is, discontinuous. Therefore, using the above mechanism, the downstream optical signal sent by the OLT 210 is a continuous optical signal, and the upstream optical signal sent by the ONU 230 is a burst optical signal.
  • the OLT 210 is usually located in a central office (Central Office, CO), and can uniformly manage at least one ONU 230 and transmit data between the ONU 230 and the upper network. Specifically, the OLT 210 can act as an intermediary between the ONU 230 and the upper-layer network (such as the Internet, Public Switched Telephone Network (PSTN)), and forward data received from the upper-layer network to the ONU 230, and The data received by the ONU 230 is forwarded to the upper network.
  • the specific structure and configuration of the OLT 210 may vary depending on the specific type of the PON system 200. For example, in an embodiment, the OLT 210 may include a transmitter and a receiver.
  • the transmitter is used to send the downstream continuous optical signal to the ONU230, and the receiver is used to receive the upstream burst optical signal from the ONU230, wherein the downstream optical signal and the upstream optical signal can be transmitted through the ODN220, but the embodiment of the present invention is not limited to this.
  • the ONU 230 can be distributed in a user-side location (such as a user premises).
  • the ONU 230 may be a network device used to communicate with the OLT 210 and the user.
  • the ONU 230 may act as an intermediary between the OLT 210 and the user. For example, the ONU 230 may forward the data received from the OLT 210 to the user, and transfer The data received from the user is forwarded to the OLT 210.
  • ODN220 can be a data distribution network, which can include optical fibers, optical couplers, optical splitters, or other devices.
  • the optical fiber, optical coupler, optical splitter, or other device may be a passive optical device, specifically, the optical fiber, optical coupler, optical splitter, or other device may be distributed between the OLT 210 and the ONU 230 A device that does not require power support for data signals.
  • the optical splitter can be connected to the OLT 210 through a backbone fiber, and connected to multiple ONUs 230 through multiple branch fibers, thereby realizing the point between the OLT 210 and the ONU 230 To multipoint connection.
  • the ODN 220 may also include one or more processing devices, for example, an optical amplifier or a relay device (Relay device).
  • the ODN 220 may specifically extend from the OLT 210 to multiple ONUs 230, but may also be configured in any other point-to-multipoint structure, and the embodiment of the present invention is not limited thereto.
  • FIG. 3 is a schematic diagram of a reference model of an OLT provided by an embodiment of the present application.
  • the OLT includes a single board 31 and an optical template 32.
  • the single board 31 includes a clock module 311 and a media access control (media access control, MAC) chip 312.
  • the MAC chip 312 includes a MAC module 3121 , De-scrambling code module 3122 and hard decision decoder 3123.
  • the optical module 32 includes a burst-to-continuous module 321, a transimpedance amplifier (TIA) 322, and a photoelectric receiver (PD) 323.
  • TIA transimpedance amplifier
  • PD photoelectric receiver
  • the burst-to-continuous module 321 also includes a hard decision code A device 3211, a scrambling code module 3212, a demodulation module 3213, a soft decision decoder 3214, an equalizer 3215, a clock recovery module 3216, and an analog-to-digital converter (ADC) 3217.
  • the OLT may also include other components, such as a dust-proof net, a cable management frame, and a fan module, which are not limited here.
  • the optical module 32 may be integrated in the single board 31, or may be used as an external device of the single board, which is not limited here. In the following embodiment, an external device in which the optical module 32 is the single board 31 is taken as an example for description.
  • the MAC chip 312 can control the node's access to the physical layer through the MAC protocol.
  • the optical template 32 can perform photoelectric conversion of the received optical signal and conversion of a burst signal to a continuous signal.
  • the clock module 311 can send two differential clock signals to the optical module 32.
  • the clock signal is generated by a clock generator and has a fixed clock frequency. It is usually used in synchronization circuits to determine when the state in the logic unit is updated. It is a signal with a fixed period and independent of operation. , So as to play the role of a timer, to ensure that the related electronic components can be synchronized operation.
  • the clock generator uses an oscillator that can provide a square wave output to generate the clock.
  • the oscillator circuit always uses feedback to make the oscillator oscillate. By feeding back the corresponding parameters, the oscillator works at a specific frequency.
  • differential transmission and two differential clock signals are used to ensure that the MAC chip 312 and the optical module 32 operate in synchronization.
  • the clock module 311 may also be integrated in the MAC chip 312, which is not limited here.
  • the clock module provides clocks for both the MAC chip and the optical module at the same time (signal of a single frequency, drives the optical module and the MAC chip to perform business processing according to this frequency), so that the clocks of the optical module and the MAC chip remain the same, thereby ensuring the processing of the MAC chip and the optical module
  • the frequency of the received signal is the same, which ensures the synchronization of the two processing and avoids the congestion of the processing signal of one party.
  • the optical module PD323 can be used to convert upstream burst optical signals from different ONUs into current signals.
  • the PD323 can be a photodetector that uses the photoelectric effect to convert an optical signal in communication into a current signal, such as a photodetector or a photodiode (such as an avalanche diode).
  • TIA322 can be used to convert current signals into voltage signals and adjust the different amplitudes of the voltage signals to be basically the same.
  • TIA322 can adopt a high input impedance negative feedback structure, which has the characteristics of simple design and high bandwidth.
  • ADC3217 can convert analog signals (voltage signals) into digital signals.
  • the clock recovery module 3216 can extract the clock signal from the digital signal and find the correct phase relationship between the data and the clock, and use the recovered clock signal to sample the data in the data stream to obtain multiple data packets in each burst The best sampling point, all the best sampling points contained in each burst data packet reconstitute the burst data packet after clock recovery.
  • This burst data packet after clock recovery contains interference information.
  • the equalizer 3215 can be used for equalizing and shaping processing to remove interference information in the burst data packet after clock recovery.
  • the equalizer 3215 can be mainly used to compensate for the impact of insufficient bandwidth optical components or fiber dispersion on high-rate data, and to compensate for signal distortion caused by inter-symbol interference and channel fading in the transmission channel (ie, optical fiber).
  • the soft decision decoder 3214 can be used to perform error correction decoding on the burst data packet contained in the digital signal.
  • the demodulation module 3213 is used to demodulate the decoded burst data packet so that the demodulated burst data packet only contains 0 or 1 bits.
  • the scrambling code module 3212 is used to fill the intervals between discontinuous burst data packets with some scrambling codes, so that these discontinuous data become continuous signals.
  • the hard decision encoder 3211 can be used to perform error correction encoding on the converted continuous signal, and send the converted continuous signal to the MAC chip of the single board through continuous continuous SerDes.
  • the hard decision decoder 3123 of the MAC chip can be used to receive the converted continuous signal through continuous continuous SerDes, and perform error correction and decoding on the continuous digital signal.
  • the descrambling code module 3122 can be used to remove the scrambling code in the converted continuous signal and restore it to a non-continuous burst signal.
  • the MAC module 3121 may be used for MAC normal processing of discontinuous burst signals.
  • the following presents a method for processing burst signals to continuous signals in a PON system.
  • the time synchronization method provided by the embodiments of the present invention will be described in detail below in conjunction with FIGS. 3 and 4.
  • the method includes Steps S400 to S411, the specific implementation of each step is as follows:
  • the PD323 in the optical module 32 receives upstream optical signals sent from different ONUs. These optical signals carry user data. These optical signals are bursts. Therefore, the user data is also called burst data packets. Sending data packets forms a data stream. Since different ONUs have different physical distances from the OLT, the amplitudes of the optical signals from different ONUs when they reach the PD323 are different, such as burst packet 1, burst packet 2, and burst in Figure 3 Packet 3. In addition, because the OLT needs to perform ranging on the ONU, there may be errors in the results of the ranging, which may cause the OLT to receive the conflict between the optical signals sent by different ONUs at the same time.
  • the OLT introduces the optical signals sent by different ONUs.
  • There is a time interval protection mechanism so there is a certain interval in time between the OLT receiving the optical signals sent by different ONUs.
  • PD323 converts the received optical signal into a current signal E1, because the process of PD323 receiving the optical signal is continuous, and this conversion process is also continuous.
  • the burst data packet carried by the photoelectric conversion signal is unchanged, so the amplitude and interval of each burst data packet contained in the current signal E1 after conversion remain unchanged.
  • PD323 sends the current signal E1 to TIA322.
  • the TIA322 receives the current signal E1, can convert the current signal E1 into a voltage signal E2, and amplify the amplitudes of the voltage signals E2 carrying burst data packets with different amplitudes to be basically the same, for example: the unified amplified amplitude can be Set to 500mv.
  • the TIA322 sends the voltage signal E2 to the burst-to-continuous module 321.
  • the ADC 3217 in the burst-to-continuous module 321 receives the voltage signal E2, converts the voltage signal E2 into a digital signal E3, and sends the digital signal E3 to the clock recovery module 3216.
  • the different burst data packets contained in the digital signal E3 are close to the same in amplitude, but a certain interval is left between the different burst data packets in time, that is, the burst data packets are not continuous.
  • the clock recovery module 3216 receives the digital signal E3, uses clock data recovery (CDR) technology to extract the clock information from the digital signal E3 and finds the correct phase relationship between the burst data packet and the clock, and uses this The extracted clock signal samples different burst data packets to obtain the best sampling point of each burst data packet. These best sampling points form the digital signal E4. Because in the sampling process, each best sampling point is The optimal sampling point adjacent to the left and right may cause interference to the optimal sampling point, so the digital signal E4 also contains interference information.
  • the above clock information may be the transmission rate of burst data packets. There are multiple optimal sampling points contained in each burst data packet.
  • the time consumed to sample each burst data packet is the same, the time value occupied by each burst data packet is different. Therefore, the number of optimal sampling points contained in each burst data packet may also be different. For example: in Figure 3, the best sampling points contained in burst packet 1 may be 80, the best sampling points contained in burst packet 2 may be 100, and the best sampling points contained in burst packet 3 may be Is 50. All the best sampling points contained in each burst data packet reconstitute the burst data packet after clock recovery. This burst data packet after clock recovery contains interference information.
  • the equalizer 3215 receives the digital signal E4, performs equalization and shaping processing on the digital signal E4, removes the interference information contained in the digital signal E4, obtains the digital signal E5, and sends the digital signal E5 to the soft decision decoder 3214.
  • the equalizer 3215 can be used to optimize signal quality.
  • the digital signal E5 contains burst data packets from which interference information is removed.
  • the soft decision decoder 3214 receives the digital signal E5, performs error correction decoding on the digital signal E5, obtains the digital signal E6, and sends the digital signal E6 to the demodulation module 3213. Since the signals sent in the ONU are all error-corrected and encoded, the error-corrected-encoded signals cannot be filled with data. In order to fill the digital signal E5 with data, the soft decision decoder 3214 needs to perform error correction and decoding on the digital signal E5. The purpose of decoding here is to ensure error-free transmission between ONU and OLT. Since the ONU uses a soft decision encoder to encode burst data packets, a soft decision decoder is used in the optical module for decoding. The soft decision codec method can make the pre-correction error rate reach 2 ⁇ 10 -2 .
  • the demodulation module 3213 receives the digital signal E6, demodulates the digital signal E6, that is, each burst data packet contains 0 or 1 data bits, and obtains the digital signal E7 containing the demodulated burst data packet , And send the digital signal E7 to the scrambling module 3212.
  • the scrambling module 3212 receives the digital signal E7, and scrambles the interval between the burst data packet and the burst data packet, so that the interval between the burst data packets contained in the digital signal E7 is filled with data , Thereby realizing the conversion of the burst digital signal E7 into a continuous digital signal E8.
  • the scrambling module 3212 sends the digital signal E8 to the hard decision encoder 3211, and the digital signal E8 contains continuous data packets.
  • the scrambling method can use the scrambling polynomial to calculate the interval between the burst data packet and the burst data packet to obtain the scrambled data.
  • Using the scrambling code polynomial to calculate the interval between the burst data packet and the burst data packet can be understood as: Take n out of all the bits contained in the interval between the burst data packet and the burst data packet in sequence.
  • Bits (if the number of n bits taken in the last time is not enough for n, you can fill in the number of bits with an appropriate number of 0 or 1), take the mth bit and the nth bit in every n bits Bits, adding the mth bit and the nth bit in each n bits to the first bit in every n bits to obtain the scrambled data of every n bits , All the scrambled data of every n bits form a continuous data packet.
  • the polynomial operation process of Figure 5 is: sequentially take out 58 bits from the burst data packet and the interval between the burst data packet, and then take out every 58 bits
  • the 39th and 58th bits are two bits, and then the 39th and 58th bits are added to the first bit of the 58 bits to obtain the 58-bit scrambled data.
  • all Every 58 bits of scrambled data together form a continuous data packet, that is, the output data.
  • the hard decision encoder 3211 receives the digital signal E8, performs error correction coding on the digital signal E8, obtains the digital signal E9, and transmits the digital signal E9 to the serializer/deserializer (serializer/deserializer, SerDes) MAC chip. Because the signal transmitted between the optical module and the MAC chip needs to be encoded, the digital signal E8 needs to be coded with hard decision error correction. The pre-correction error rate of this hard decision can reach 1*10 -3 .
  • the frame format of the continuous data packet carried by the digital signal E9 may be shown in Figure 6.
  • the frame includes a delimiter (Dilimiter) and a series of codewords carrying specific content.
  • the delimiter is used to determine the frame header s position.
  • Each codeword also contains scrambled data (Scrambled Data) and parity (Parity), and the scrambled data is obtained by scrambling consecutive data packets.
  • the hard decision decoder 3123 of the MAC chip receives the digital signal E9 through continuous SerDes, performs error correction decoding on the digital signal E9, obtains the digital signal E10, and sends the digital signal E10 to the descrambling code module 3122. Because the encoder in the optical module is a hard decision encoder, the decoder in the MAC chip is a hard decision decoder.
  • the descrambling code module 3122 receives the digital signal E10, and removes the filling data between each continuous data packet contained in the digital signal E10, so that the continuous data packet is restored to a burst data packet with gaps between the data packets.
  • the continuous digital signal E10 is converted into a burst digital signal E11. Obtain the digital signal E11, and send the digital signal E11 to the MAC module 3121.
  • the process of descrambling code is the inverse process of data filling.
  • the interval between the burst data packet and the burst data packet can be calculated by using the descrambling code polynomial to obtain the data after the descrambling code.
  • Using the descrambling code polynomial to calculate the interval between the burst data packet and the burst data packet can be understood as: take out n bits in sequence from all the bits contained in the continuous data packet (if the last n bits are taken) If the number of bits is not enough n, the n number of bits can be filled with an appropriate number of 0s or 1s), the mth bit and the nth bit are taken out of every n bits, and in every n bits Subtract the mth bit and the nth bit from the first bit in every n bits to obtain the descrambling data of every n bits. After scrambling, the data is restored to burst data packets.
  • the calculation process using the descrambling code polynomial in Figure 5 is: sequentially take out 58 bits from the continuous data (if the number of 58 bits taken in the last time is not enough 58, then you can Fill in 58 bits with an appropriate number of 0s or 1s), then take out the 39th and 58th bits out of every 58 bits, and then combine the 39th and 58th bits with the 58 Subtract the first bit among the bits to obtain the 58-bit descrambling data. In this way, all the 58-bit descrambling data together form a burst data packet, that is, the output data .
  • the scrambling code mode adopted by the scrambling code module in step S407 has a certain relationship with the descrambling code mode adopted by the descrambling code module, and they are usually relative or the same, for example: the scrambling code in step S407
  • the polynomial is the same as the descrambling polynomial of S410.
  • the MAC module 3121 receives the digital signal E11, and performs regular corresponding processing on the digital signal E11.
  • Fig. 8 is the simulation result obtained according to the method of Fig. 4, where part A is the original burst data packet (Burst1,...BurstN) with different time intervals. Part B is to obtain continuous data packets after data filling. It can be seen from the simulation diagram that the intervals between burst data packets have been filled, and the burst data packets become continuous data packets. Part C is the digital signal E9 obtained after error correction coding. Part D refers to the digital signal E10 obtained after error correction and decoding on the MAC chip side. Part E refers to the burst data packet recovered after descrambling the digital signal E10 on the MAC side.
  • the continuous data packet is restored to a burst data packet
  • the recovered burst data packet It is basically the same as the burst data packet of part A, which shows that the burst-to-continuous processing in the embodiment of the present invention can be realized. Since the optical module can convert the burst signal into a continuous signal, the optical module can use the continuous SerDes to transmit the continuous signal to the MAC chip, improve the efficiency of data transmission, and restore the burst signal in the MAC chip without loss.
  • FIG. 9 shows a schematic block diagram of an optical processing device 900 according to an embodiment of the present application.
  • the modules in the optical processing device 900 are respectively used to perform actions or processing procedures performed by the optical module of the OLT in the foregoing method.
  • the optical processing device 900 may specifically be an optical module of an OLT.
  • FIG. 9 is a schematic block diagram of an optical processing device 900 provided by an embodiment of the present application.
  • the light processing device 900 may include:
  • the scrambling module 910 is used for data filling the intervals between the burst data packets contained in the burst signal to obtain a continuous signal containing continuous data packets, wherein the burst signal comes from multiple ONUs.
  • the scrambling module 910 is the scrambling module 3212 shown in FIG. 3.
  • the encoding module 920 is configured to encode the continuous data packet to obtain a continuous signal containing the encoded continuous data packet, and send the continuous signal containing the encoded continuous data packet to the network processing device through the continuous SerDes.
  • the burst signal comes from multiple ONUs; when the optical processing device is specifically an optical module of an OLT, the encoding module 920 is the hard decision encoder 3211 shown in FIG. 3.
  • the scrambling code module 910 is specifically configured to use a scrambling code polynomial to calculate and process the burst data packet contained in the burst signal and the interval between the burst data packet.
  • the data filling module 910 is specifically configured to: sequentially extract n bits from all bits included in the interval between the burst data packet and the burst data packet, and in every n bits Take out the mth bit and the nth bit; add the mth bit and the nth bit in each n bits to the first bit in every n bits to obtain the After n bits of scrambled data, all the scrambled data of every n bits form a continuous data packet.
  • the frame of the encoded continuous data packet includes a delimiter used to determine the position of the frame header and a codeword carrying specific content, wherein each codeword also includes a scrambled Data and check digit.
  • the optical processing device 900 may also include a demodulation module, a soft decision decoder, an equalizer, a clock recovery module, an analog-to-digital converter, a transimpedance amplifier, and a receiving module, the specific functions of which correspond to The demodulation module 3213, the soft decision decoder 3214, the equalizer 3215, the clock recovery module 3216, the analog-to-digital converter 3217, the transimpedance amplifier 322 and the optoelectronic receiver 323 shown in FIG. It is not shown in Figure 9 here.
  • FIG. 10 shows a schematic block diagram of a network processing device 1000 according to an embodiment of the present application.
  • the modules in the network processing device 1000 are respectively used to execute various actions or processing procedures performed by the MAC chip in the foregoing method.
  • the network processing device may specifically be the MAC chip of the OLT.
  • FIG. 10 is a schematic block diagram of a network processing device 1000 according to an embodiment of the present application.
  • the network processing device 1000 may include:
  • the decoding module 1010 is configured to receive a continuous signal sent by an optical processing device through a continuous SerDes, the continuous signal containing a continuous data packet after encoding, decoding the continuous data packet after encoding, to obtain a continuous data packet containing the decoded data Continuous signal.
  • the decoding module 1010 may specifically be a hard decision decoder 3123 as shown in FIG. 3,
  • the descrambling code module 1020 is used to remove the data filled in the decoded continuous data packet to obtain the decoded burst data packet.
  • the descrambling code module 1020 may be specifically configured to: use descrambling code polynomials to perform calculation processing on the decoded continuous data packets, where the descrambling code polynomials are The scrambling code polynomials used by the optical processing equipment are the same or have a reciprocal relationship.
  • the network processing device 1000 further includes a MAC module for receiving and performing MAC regular processing on the burst data table from the descrambling code module.
  • the MAC module may be as shown in FIG. 3
  • the MAC module 3121 is no longer shown in Figure 10.
  • FIG. 11 is a schematic block diagram of an optical processing device 1100 according to an embodiment of the present application.
  • the optical processing device 1100 may include: a processor 1101, a receiver 1102, a transmitter 1103, and a memory 1104.
  • the processor 1101 may be in communication connection with the receiver 1102 and the transmitter 1103.
  • the memory 1104 can be used to store the program code and data of the network device. Therefore, the memory 1104 may be a storage unit inside the processor 1101, an external storage unit independent of the processor 1101, or a storage unit inside the processor 1101 and an external storage unit independent of the processor 1101. part.
  • the optical processing device 1100 may further include a bus 1105.
  • the receiver 1102, the transmitter 1103, and the memory 1104 can be connected to the processor 1101 through a bus 1105;
  • the bus 1105 can be a peripheral component interconnect (PCI) bus or an extended industry standard structure (extended industry standard). architecture, EISA) bus, etc.
  • the bus 1105 can be divided into an address bus, a data bus, a control bus, and so on. For ease of representation, only a thick line is used in FIG. 11, but it does not mean that there is only one bus or one type of bus.
  • the processor 1101 may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (digital signal processor, DSP), an application-specific integrated circuit (ASIC), and a field programmable gate.
  • Array field programmable gate array, FPGA or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logical blocks, modules and circuits described in conjunction with the disclosure of the present application.
  • the processor may also be a combination for realizing computing functions, for example, a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and so on.
  • the receiver 1102 and the transmitter 1103 may be circuits including the above-mentioned antenna, transmitter chain and receiver chain, and the two may be independent circuits or the same circuit.
  • the receiver 1102 When the program is executed, the receiver 1102 is used to receive burst optical signals sent by multiple ONUs.
  • the transmitter 1103 performs the following operations through the processor 1101: for sending the continuous signal containing the encoded continuous data packet to the network processing device.
  • FIG. 12 is a schematic block diagram of a network processing device 1200 according to an embodiment of the present application.
  • the terminal device 1200 may include: a processor 1201, a receiver 1202, a transmitter 1203, and a memory 1204.
  • the processor 1201 may be connected to the receiver 1202 and the transmitter 1203 in communication.
  • the memory 1204 can be used to store the program code and data of the terminal device. Therefore, the memory 1204 may be a storage unit inside the processor 1201, or an external storage unit independent of the processor 1201, or may include a storage unit inside the processor 1201 and an external storage unit independent of the processor 1201. part.
  • the network processing device 1200 may further include a bus 1205.
  • the receiver 1202, the transmitter 1203, and the memory 1204 may be connected to the processor 1201 through a bus 1205; the bus 1205 may be a PCI bus or an extended EISA bus.
  • the bus 1205 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is used to represent in FIG. 12, but it does not mean that there is only one bus or one type of bus.
  • the processor 1201 may be, for example, a CPU, a general-purpose processor, DSP, ASIC, FPGA or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logical blocks, modules and circuits described in conjunction with the disclosure of the present application.
  • the processor may also be a combination for realizing computing functions, for example, including a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and so on.
  • the receiver 1202 and the transmitter 1203 may be circuits including the above-mentioned antenna, transmitter chain and receiver chain, and the two may be independent circuits or the same circuit.
  • the receiver 1202 is used to receive the continuous signal sent by the optical processing device.
  • the embodiment of the present application also provides a chip, including a memory, a processor, and a transceiver.
  • the memory is used to store a program; the processor is used to execute the program stored in the memory.
  • the processor executes the method described in any one of the possible implementations of the optical processing device.
  • the embodiment of the present application also provides a chip, including a memory, a processor, and a transceiver.
  • the memory is used to store a program; the processor is used to execute the program stored in the memory.
  • the processor executes the method described in any one of the possible implementation manners of the foregoing network processing equipment.
  • the embodiment of the present application also provides a computer-readable storage medium, including a computer program.
  • the computer program runs on a computer, the computer executes the method described in S400-S411 and the like.
  • the embodiments of the present application also provide a computer program product, which when the computer program product runs on a computer, causes the computer to execute the method described in steps S400-S411 and the like.
  • the embodiment of the present application also provides a system, including the foregoing optical processing device and/or the foregoing network processing device.
  • various aspects or features of the present application may be implemented as methods, devices, or articles using standard programming and/or engineering techniques.
  • article of manufacture encompasses a computer program accessible from any computer-readable device, carrier, or medium.
  • computer-readable media may include, but are not limited to: magnetic storage devices (eg, hard disks, floppy disks, or magnetic tapes, etc.), optical disks (eg, compact discs (CD), digital universal discs (digital) discs, DVDs) Etc.), smart cards and flash memory devices (for example, erasable programmable read-only memory (EPROM), cards, sticks or key drives, etc.).
  • various storage media described herein may represent one or more devices and/or other machine-readable media for storing information.
  • machine-readable medium may include, but is not limited to, wireless channels and various other media capable of storing, containing, and/or carrying instructions and/or data.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the unit is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical, or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of the present application essentially or part of the contribution to the existing technology or part of the technical solution can be embodied in the form of a software product
  • the computer software product is stored in a storage medium, including Several instructions are used to enable a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program codes .

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Abstract

L'invention concerne un procédé et un appareil destinés à convertir des signaux par salves en signaux continus. Le procédé comporte des étapes lors desquelles un appareil de traitement optique: remplit de données des espaces entre des paquets de données par salves contenus dans des signaux par salves pour obtenir des signaux continus contenant des paquets de données continues, les signaux par salves étant reçus en provenance d'ONU multiples; code les paquets de données continues pour obtenir des signaux continus contenant des paquets codés de données continues; et envoie, à un appareil de traitement de réseau, et au moyen d'un SerDes continu, les signaux continus contenant les paquets codés de données continues. Dans la solution ci-dessus, l'appareil de traitement optique peut convertir des signaux par salves en signaux continus, et transmettre les signaux continus à un appareil de traitement de réseau au moyen d'un SerDes continu, améliorant ainsi le rendement de transmission de données.
PCT/CN2019/071848 2019-01-16 2019-01-16 Procédé et appareil de conversion de signaux par salves en signaux continus WO2020147023A1 (fr)

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CN201980059707.0A CN112690007B (zh) 2019-01-16 2019-01-16 一种突发信号转连续信号的方法、设备
PCT/CN2019/071848 WO2020147023A1 (fr) 2019-01-16 2019-01-16 Procédé et appareil de conversion de signaux par salves en signaux continus

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