WO2020146997A1 - 扫描驱动单元、扫描驱动电路、阵列基板与显示装置 - Google Patents

扫描驱动单元、扫描驱动电路、阵列基板与显示装置 Download PDF

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Publication number
WO2020146997A1
WO2020146997A1 PCT/CN2019/071709 CN2019071709W WO2020146997A1 WO 2020146997 A1 WO2020146997 A1 WO 2020146997A1 CN 2019071709 W CN2019071709 W CN 2019071709W WO 2020146997 A1 WO2020146997 A1 WO 2020146997A1
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Prior art keywords
pull
transistor
electrically connected
node
scan
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PCT/CN2019/071709
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English (en)
French (fr)
Inventor
颜尧
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Priority to CN201980073434.5A priority Critical patent/CN113261041A/zh
Priority to PCT/CN2019/071709 priority patent/WO2020146997A1/zh
Publication of WO2020146997A1 publication Critical patent/WO2020146997A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the invention relates to the field of display driving, in particular to scanning driving technology in image display.
  • the scan driving circuit provides scan signals and the data driving circuit provides image data to cooperate with each other to drive the pixel array arranged in the image display area.
  • a scan driving circuit and a pixel array are fabricated on an array substrate together, which is also called a GOA (Gateon Array, gate driving array substrate) circuit.
  • the multiple scan driving units in the GOA circuit are usually designed in cascade to sequentially output the shifted scan signals to the pixel array.
  • the scan driving unit After the scan driving unit outputs the scan signal in a scan period, it must be stopped in time so that other scan lines can receive the scan signal normally.
  • the threshold voltage of the transistor in the GOA circuit will drift, which will cause the scan driving unit to fail to accurately output the scan signal during the scan period, resulting in the phenomenon that multiple scan lines cannot be scanned.
  • the pixel array cannot load the image data correctly, which brings trouble to the correct display of the image.
  • a scan driving unit that can prevent the scan signal from being unable to output accurately due to the drift of the threshold voltage of the transistor in the scan driving unit is provided.
  • a scan driving circuit an array substrate, and a display device as the scan driving unit.
  • the embodiment of the invention discloses a scan driving unit, including:
  • a pull-up control unit configured to receive a startup voltage, and transmit the startup voltage to a pull-up node in a first time period in a scan period to control the pull-up node to a high level state;
  • the pull-up output unit is electrically connected to the pull-up node, and transmits the received scan clock signal to the scan output terminal during the second time period in the scan period and when the pull-up node is in a high state Output as scanning signal;
  • the pull-down control unit is electrically connected to the pull-down node and the pull-up node, and controls the pull-down node to be in a low level state according to the received first control clock signal during the first time period, wherein the first time period ,
  • the second time period is uninterrupted and continuous in time and has no overlap;
  • the pull-down output unit is electrically connected to the pull-down node and the scan output terminal, and is used to control the scan output terminal to pull down to a low level state and stop outputting the scan when the pull-down node is in a high level state Signal, and stop working when the pull-down node is in a low state.
  • the embodiment of the present invention discloses a scan driving circuit including a plurality of scan driving units cascaded with each other.
  • An embodiment of the present invention discloses an array substrate including an image display area and a non-image display area, the image display area includes a pixel array for performing image display, and the non-image display area includes the aforementioned scan driving circuit.
  • the embodiment of the present invention discloses a display device including the aforementioned array substrate.
  • the pull-down control unit in the scan driving unit controls the pull-down node to be in a low level state according to the received first control clock signal during the first time period, it prevents the pull-down node from being in a low level accurately.
  • the high-level state of the pull-up node is affected by the state, which ensures the accurate output of the scan signal.
  • FIG. 1 is a schematic diagram of the layout structure of a scan driving circuit in an embodiment of the present invention
  • FIG. 2 is a schematic diagram of the circuit structure of the scan driving unit shown in FIG. 1;
  • Fig. 3 is a working timing diagram of the scan driving circuit described in Figs. 1-2.
  • the transistors used in all the embodiments of the present invention are N-type thin-film transistors (TFT) manufactured by indium gallium zinc oxide (IGZO) technology.
  • TFT thin-film transistors
  • IGZO indium gallium zinc oxide
  • the thin film transistor can also be P-type, and it is not limited thereto.
  • FIG. 1 is a schematic diagram of the layout structure of the scan driving circuit 100 in an embodiment of the present invention.
  • the scan driving circuit 100 is used to provide scan pulse signals for the pixel matrix 200.
  • the scan driving circuit 100 includes a plurality of scan driving units 10 cascaded with each other, and the plurality of scan driving units 10 cascaded with each other sequentially provide scan signals to a plurality of scan lines (not labeled) in the pixel array 200.
  • each scan driving unit 10 outputs a scan signal of one scan period to the scan line connected to it in the display driving of one frame of image.
  • a plurality of scan driving units 10 are respectively disposed on opposite sides of the pixel array 200, that is, part of the scan driving unit 10 is disposed on one side of the pixel array 200, and another part of the scan driving unit 10 is disposed on the side of the pixel array 200. The opposite side.
  • each scan line corresponds to one scan drive unit 10, and the scan drive units 10 corresponding to two adjacent scan lines are respectively arranged on opposite sides of the pixel array 200, that is, odd rows and even rows.
  • each scan driving unit 10 includes a driving enable terminal EN, a clock signal terminal CK, a reset terminal TRST, and a scan output terminal OUT.
  • the clock signal terminal in each scan driving unit includes a first clock signal terminal CKp1, a second clock signal terminal CKp2, and a third clock signal terminal CKp3, where the first clock signal terminal CKp1
  • the second clock signal terminal CKp2 and the third clock signal terminal CKp3 are used to receive the control clock signal.
  • the scan clock signal is used to control the scan driving unit 10 to output scan signals from the scan output terminal OUT
  • the control clock signal is used to control the scan driving unit 10 to stop outputting scan signals from the scan output terminal OUT.
  • the scan driving units corresponding to the odd-numbered scan lines are sequentially cascaded, and the scan driving units corresponding to the even-numbered scan lines are sequentially cascaded with each other.
  • the drive enable terminal EN of GOA1 is used to receive the start voltage STV, and at the same time, the scan output terminal OUT is connected to the first scan line and also electrically connected to GOA3.
  • the drive enable terminal EN of the number of scan lines can be cascaded sequentially.
  • the drive enable terminal EN of GOA2 is used to receive the start voltage STV, and at the same time, the scan output terminal OUT is connected to the second scan line while also being electrically connected to GOA4.
  • each of the 8 adjacent scan driving units 10 is a group of 8 clock signals CK1 to CK8 with a scan duration of 1H and the same amplitude, and two adjacent clock signals overlap by a duration of 1/2H.
  • the clock signal CK1 and the clock signal CK2 overlap for a period of 1/2H
  • the clock signal CK2 and the clock signal CK3 overlap for a period of 1/2H, and so on.
  • the H is a unit time length, for example, 1H can be 8 microseconds ( ⁇ s), of course, 1H can be set according to the actual requirements of image display, and is not limited thereto.
  • the clock signal CK1, the clock signal CK3, the clock signal CK5, and the clock signal CK7 form a group of clock signals that are continuous in time and without overlap, and are respectively provided to the multiple scan driving units on the right side.
  • GOA; and the clock signal CK2, clock signal CK4, clock signal CK6, and clock signal CK8 are formed as a set of clock signals continuously and without overlap in time, and are respectively provided to a plurality of scan driving units GOA on the left.
  • the scan driving circuit 100, the corresponding scan lines, and the pixel array 200 are all disposed in the array substrate AY.
  • the pixel array 200 for performing image display is arranged in the image display area (not marked) of the array substrate
  • the scan driving circuit 100 is arranged in the non-image display area
  • the scan line extends from the image display area to the non-image display area In order to connect the scan driving circuit 100 and the pixel array 200.
  • the scan driving circuit 100 is directly fabricated on the array substrate AY using GOA technology.
  • the array substrate AY can be applied to a display device (not labeled), for example, to a display device such as a liquid crystal display, an organic electroluminescence display, or to an electronic device such as a mobile phone or a tablet computer with a display screen.
  • a display device such as a liquid crystal display, an organic electroluminescence display, or to an electronic device such as a mobile phone or a tablet computer with a display screen.
  • FIG. 2 is a schematic diagram of the circuit structure of any scan driving unit 10 shown in FIG. 1.
  • the scan driving unit GOAN that provides scan signals for the nth scan line is taken as an example, and the circuit structure of the scan driving unit GOA is specifically described, where N is a positive integer. For example, when the pixel area 200 includes 1920 scan lines, then N is any number between 1 and 1920.
  • the scan driving unit GOAN includes a pull-up control unit 11, a pull-up output unit 12, a pull-down control unit 13, a pull-down output unit 14, a drift correction unit 15, and a reset unit 16.
  • the pull-up control unit 11 is configured to receive the start voltage STV from the drive enable terminal EN, and transmit the start voltage STV to the pull-up node PU during the first time period of a scan period to control the pull-up node PU to be High state.
  • the first GOA1 receives the start voltage STV as the enable voltage
  • the other scan driving units GOAN all use the scan driving signal output by the n-2th scan driving unit GOAN-2 as the enabling voltage.
  • the pull-up output unit 12 is electrically connected to the pull-up node PU, and when the pull-up node PU is in a high level state, the scan clock received from the first clock signal terminal CK1 during the second period of the scan period The signal CKi is transmitted to the scan output terminal OUT as a scan signal output.
  • the pull-down control unit 13 is electrically connected to the pull-down node PD and the pull-up node PU, and is used for the first time period to control the pull-down node PD to be in a low level state according to a first control clock signal, and in a scan period In other time periods, the pull-up node PU is controlled to be in a low level state and the pull-down node PD is controlled to be in a high level state alternately according to a predetermined time interval between the first control clock signal and the second control clock signal.
  • the high-level state means that the voltage of the node is a high voltage and is sufficient to drive the corresponding transistor to be in the on state, which can be expressed as the voltage of the node is at a high-level reference voltage VGH;
  • the low-level state means that the voltage of the node is low and is not enough to maintain the transistor in the on state, which can be expressed as the voltage of the node is at the low-level reference voltage VGL.
  • the pull-down output unit 14 is electrically connected to the pull-down node PD and the scan output terminal OUT, and is used to control the scan output terminal OUT to pull down to a low voltage and stop outputting the scan output terminal OUT when the pull-down node PD is in a high level state. Scan signal.
  • the drift correction unit 15 is electrically connected to the pull-up node PU, and is configured to receive a drift correction signal after one scan period to control the pull-up node PU to be in a low level state.
  • the drift correction unit 15 can quickly and accurately pull the pull-up node PU to low power when the scan driving unit 10 is in a non-scan period pull-down node PD and cannot accurately control the pull-up node PU in a low state in time to stop outputting the scan signal.
  • the flat state prevents multiple scan drive units from outputting scan signals to multiple scan lines at the same time, ensuring the accuracy of image display.
  • the drift correction signal may be a clock signal provided externally, or may be a scan signal output by an adjacent scan driving unit in a subsequent scan period.
  • the drift correction signal may be the scan signal output by the scan driving unit GOA3.
  • the reset unit 16 is electrically connected to the pull-up node PU, and is used to control the pull-up node PU to be in a low level state according to the reset signal TRST.
  • the scan driving circuit 100 When the scan driving circuit 100 is reset as a whole, it accurately controls all the scan driving units 10
  • the pull-up output unit 12 stops outputting the scan driving signal.
  • the pull-up control unit 11 includes a first transistor M1, the gate and drain of the first transistor M1 are electrically connected to the drive enable terminal EN, and the source of the first transistor M1 is electrically connected to the pull-up Node PU.
  • the scan signal Gout N-2 output by the scan driving unit GOA N-2 is used as the driving voltage.
  • the pull-up output unit 12 includes a third transistor M3 and a first capacitor C1.
  • the gate of the third transistor M3 is electrically connected to the pull-up node PU, and the drain of the third transistor M3 is electrically connected to the first capacitor.
  • the clock signal terminal CKp1 receives the clock signal CKi, and the source of the third transistor M3 is electrically connected to the scan output terminal OUT.
  • the first capacitor C1 is electrically connected between the pull-up node PU and the scan output terminal OUT.
  • the clock signal CK1 corresponds to the pulse signal at a high level during the period when the scan driving unit GOAN needs to output the scan signal, and the clock signal CKi is used as the scan clock signal.
  • the pull-down control unit 13 includes a second transistor M2, a fourth transistor M4, a seventh transistor M7, and an eighth transistor M8.
  • the gate and drain of the second transistor M2 are electrically connected to the second clock signal terminal CKp2 for receiving the clock signal Cki+2, and the source of the second transistor M2 is electrically connected to the pull-down node PD.
  • the clock signal CKi+2 is used as the second control clock signal.
  • the gate of the fourth transistor M4 is electrically connected to the pull-down node PD, the source of the fourth transistor M4 is electrically connected to the pull-up node PU, and the drain of the fourth transistor M4 is electrically connected to the low reference voltage terminal VGL , Used to receive the low-level reference voltage VGL.
  • the gate of the seventh transistor M7 is electrically connected to the third clock signal terminal CKp3 for receiving the clock signal CKi-2, the source of the seventh transistor M7 is electrically connected to the pull-down node PD, and the seventh transistor M7 is electrically connected to the pull-down node PD.
  • the drain of the transistor M7 is electrically connected to the low reference voltage terminal VGL for receiving the low reference voltage VGL.
  • the clock signal CKi-2 is used as the first control clock signal.
  • the gate of the eighth transistor M8 is electrically connected to the pull-up node PU, the drain of the eighth transistor M8 is electrically connected to the low reference voltage terminal VGL, and the source of the eighth transistor M8 is electrically connected to the The drop-down node PD.
  • the pull-down output unit 14 includes a pull-down transistor M14, a gate of the pull-down transistor M14 is electrically connected to the pull-down node PD, a drain of the pull-down transistor M14 is electrically connected to the scan output terminal OUT, and the pull-down transistor M14 The source of 14 is electrically connected to the low reference voltage terminal VGL.
  • the scan driving unit 10 further includes an auxiliary pull-down control unit 13', an auxiliary pull-down output unit 14', and an auxiliary pull-down node PD'.
  • auxiliary pull-down control unit 13', the auxiliary pull-down output unit 14', and the auxiliary pull-down node PD' all alternate with the pull-down control unit 13, the pull-down output unit 14 and the pull-down node PD in two adjacent scan cycles. The loop is working.
  • the pull-down control unit 13 the pull-down output unit 14 and the pull-down node PD are in working state, and the auxiliary pull-down control unit 13', the auxiliary pull-down output unit 14' and the auxiliary pull-down node PD' In a non-working state;
  • the pull-down control unit 13, the pull-down output unit 14 and the pull-down node PD are in a non-working state, and the auxiliary pull-down control unit 13', the auxiliary pull-down output unit 14' and the auxiliary pull-down node PD 'In working condition.
  • each clock signal CK corresponds to the length of one scan period H, and any two adjacent clock signals differ by 1/2H time length.
  • the clock signal CKi and the clock signal CKi+4 differ by 2 clock signal lengths 2H.
  • the clock signal CKi received by the first clock signal terminal CKp1 is obviously different from the clock signal CKi+2 received by the second clock signal terminal CKp2 and the clock signal CKi-2 received by the third clock signal terminal CKp3 by a time length corresponding to the clock signal.
  • the three clock signals are clock signals that are continuous and without overlap in time.
  • the clock signals are all high-level effective pulse signals.
  • the auxiliary pull-down control unit 13' includes a second symmetric transistor M2', a fourth symmetric transistor M4', a seventh symmetric transistor M7', and an eighth symmetric transistor M8'.
  • the gate and drain of the second symmetrical transistor M2' are electrically connected to the third clock signal terminal CKp3 for receiving the clock signal CKi-2, and the source of the second symmetrical transistor M2' is electrically connected to the auxiliary pull-down node PD '.
  • the gate of the fourth symmetric transistor M4' is electrically connected to the auxiliary pull-down node PD', the source of the fourth symmetric transistor M4' is electrically connected to the pull-up node PU, and the fourth symmetric transistor M4 The drain of 'is electrically connected to the low reference voltage terminal VGL.
  • the gate of the seventh symmetrical transistor M7' is electrically connected to the second clock signal terminal CKp2 for receiving a clock signal Cki+2, and the drain of the seventh symmetrical transistor M7' is electrically connected to the low reference
  • the voltage terminal VGL receives a low-level reference voltage VGL, and the source of the seventh symmetrical transistor M7' is electrically connected to the auxiliary pull-down node PD'.
  • the gate of the eighth symmetrical transistor M8' is electrically connected to the pull-up node PU, the drain of the eighth symmetrical transistor M8' is electrically connected to the low reference voltage terminal VGL, and the The source is electrically connected to the auxiliary pull-down node PD'.
  • the auxiliary pull-down output unit 14' includes a pull-down symmetrical transistor M14', the gate of the pull-down symmetrical transistor M14' is electrically connected to the auxiliary pull-down node PD', and the source of the pull-down auxiliary transistor M14' is electrically connected to the For the scan output terminal OUT, the drain of the pull-down symmetrical transistor M14' is electrically connected to the low reference voltage terminal VGL.
  • the pull-down control unit 13 and the pull-down auxiliary control unit 13' are alternately in working state at intervals of 2 scan periods, so as to prevent the pull-down control unit 13 or the pull-down auxiliary control unit 13' from being in working state for a long time and cause the performance of the transistor to be affected .
  • the scan driving unit 10 further includes a second capacitor C2, the second capacitor C2 is electrically connected between the pull-down node PD and the auxiliary pull-down node PD', and the second capacitor C2 is used to ensure pull-down control
  • the unit 13 and the auxiliary pull-down control unit 13' accurately maintain the voltages of the pull-down node PD and the auxiliary pull-down node PD' when switching work projects.
  • the auxiliary pull-down node PD' is at a high level.
  • the clock signal received by the second clock signal terminal CKp2 is bound to At a low level, that is, the pull-down node PD is in a low-level state. Therefore, the second capacitor C2 can effectively maintain the voltage difference between the auxiliary pull-down node PD' and the pull-down node PD due to the voltage difference characteristics of the capacitor, so as to ensure the pull-down control unit 13 Working accuracy with auxiliary pull-down control unit 13'.
  • the drift correction unit 15 includes a correction transistor M15, the gate of the correction transistor M15 receives a drift correction signal, the source of the correction transistor M15 is electrically connected to the pull-up node PU, and the drain of the correction transistor M15 The low reference voltage terminal VGL is electrically connected.
  • the reset unit 16 includes a reset transistor M20, the gate of the reset transistor M20 is electrically connected to the reset terminal TRST to receive a reset signal, the source of the reset transistor M20 is electrically connected to the pull-up node PU, and the drain of the reset transistor M20 is electrically connected. Connect the low reference voltage terminal VGL.
  • FIG. 3 is a working timing diagram of the scan driving circuit 100 shown in FIGS. 1-2.
  • the symbols in the figure represent the corresponding signals received in Figure 1-2.
  • VGL represents the voltage waveform provided by the low reference voltage terminal VGL
  • STV-L represents the starting voltage provided to the left scan driving unit
  • STV-R represents the starting voltage provided to the right scan driving unit
  • CK1-CK8 represents 8 clock signals
  • Gout1-Gout1920 respectively represent the scan signal provided by the scan drive unit of the corresponding serial number.
  • the scanning drive unit GOA1 sorted in the first position is taken as an example to illustrate its working process.
  • one scanning period of GOA1 includes three consecutive time periods t1-t3.
  • GOA1 receives the start voltage STV-L in the left signal and the clock signal CK1 provided from the third clock signal terminal CKp3, and the first transistor M1 in the pull-up unit 11 is turned on, thereby pulling up the node PU The voltage is pulled up to a high level state, and at the same time, the first capacitor C1 also starts to charge and further increases the voltage of the pull-up node PU until the pull-up node PU is in a high level state.
  • the clock signal CK1 is provided from the third clock signal terminal CKp3 to control the seventh transistor M7 to be in the on state, so as to accurately maintain the pull-down node PD in the low state, and the clock signal CK1 controls the second symmetrical transistor M2' to be in the on state Therefore, the auxiliary pull-down node PD' is accurately maintained in a high level state, and the pull-down symmetrical transistor M14' in the auxiliary pull-down output unit 14' is controlled to be in a conductive state to ensure that the scan output terminal OUT of the GOA1 is at a low voltage.
  • the second capacitor C2 ensures the voltage difference between the pull-down node PD and the auxiliary pull-down node PD', and accurately maintains the voltage state of the pull-down node PD and the auxiliary pull-down node PD'.
  • the voltage of the pull-up node PU is higher than the threshold voltage Vth of the third transistor M3 (not marked) ,
  • the third transistor M3 is turned on, the clock signal CK3 is transmitted to the scan output terminal OUT through the turned-on third transistor M3, and the clock signal CK3 at this time is output as the scan signal Gout1.
  • the clock signal CK3 is stopped, and the clock signal CK5 is provided from the second clock signal terminal CKp2.
  • the clock signal CK5 provided from the second clock signal terminal CKp2 controls the seventh symmetrical transistor M7' to be in the on state, so as to accurately maintain the auxiliary pull-down node PD' in the low state, and the clock signal CK5 controls the second transistor M2 to be on Therefore, the pull-down node PD is accurately maintained in the high-level state, and the pull-down transistor M14 in the pull-down output unit 14 is controlled to be in the on state to ensure that the scan output terminal OUT of the GOA1 is at a low voltage.
  • the scan output terminal OUT in the scan driving unit GOA3 has finished outputting the high-voltage scan signal at the same time as the clock signal CK5 is output, so as to control the correction transistor M15 in the drift correction unit 15 to be in the on state, which is more accurate and instant.
  • the ground pulls the pull-up node PU to the level state, so that the voltage of the pull-down node is the low-level reference voltage VGL.
  • the second frame image scanning period period is the same as the first frame image scanning period corresponding to the multiple scan driving units GOA. No longer.
  • the pull-down control unit 14 or the auxiliary pull-down control unit 14' controls the pull-down node PD to be in a low state according to the received first control clock signal during the first time period, the pull-down node PD is prevented
  • the inability to be in the low-level state accurately results in the high-level state of the pull-up node PU being affected, ensuring accurate output of the scan signal.

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  • Physics & Mathematics (AREA)
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Abstract

一种扫描驱动单元(10)、扫描驱动电路(100)、阵列基板(AY)与显示装置。扫描驱动单元(10)包括上拉控制单元(11)、上拉输出单元(12)、下拉控制单元(13)、下拉输出单元(14)、漂移校正单元(15)以及复位单元(16)。上拉控制单元(11)在扫描周期的第一时间段接收启动电压(STV)以控制上拉节点(PU)为高电平状态，并且在第二时间段通过上拉输出单元(12)将接收的扫描时钟信号(CKi)传输至扫描输出端(OUT)作为扫描信号输出。下拉控制单元(13)在第一时间段依据第一控制时钟信号控制下拉节点(PD)处于低电平状态，以保证上拉节点(PU)准确处于高电平状态，下拉输出单元(14)在下拉节点(PD)处于低电平状态时停止工作。

Description

扫描驱动单元、扫描驱动电路、阵列基板与显示装置 技术领域
本发明涉及显示驱动领域，具体涉及图像显示中的扫描驱动技术。
背景技术
在显示面板图像显示过程中，需要扫描驱动电路提供扫描信号与数据驱动电路提供图像数据相互配合驱动设置在图像显示区的像素阵列。近年来，为了提高显示面板的集成度，将扫描驱动电路与像素阵列一并制作于阵列基板上，亦称为GOA(Gateon Array，栅极驱动阵列基板)电路。
GOA电路中的多个扫描驱动单元通常被设计成级联形式以依次输出移位后的扫描信号至像素阵列。但是当扫描驱动单元在一个扫描周期输出扫描信号以后就必须及时停止，以便于其他扫描线能够正常接收扫描信号。但是GOA电路在实际工作过程中，GOA电路中的晶体管的阈值电压会出现漂移现象，进而导致扫描驱动单元在扫描周期时无法准确输出扫描信号，从而导致多个扫描线无法被扫描的现象，从而导致像素阵列无法正确加载图像数据，给图像的正确显示带来困扰。
发明内容
为解决前述问题，提供一种能够防止由于扫描驱动单元中晶体管阈值电压漂移而无法准确输出扫描信号的扫描驱动单元。
进一步，还提供一种包括前述作为前述扫描驱动单元的扫描驱动电路、阵列基板以及显示装置。
本发明实施例公开了一种扫描驱动单元，包括：
上拉控制单元，用于接收启动电压，并且在一个扫描周期内的第一时间段将所述启动电压传输至上拉节点以控制所述上拉节点为高电平状态；
上拉输出单元，电性连接所述上拉节点，在所述扫描周期内的第二时间段并且当所述上拉节点为高电平状态时，将接收的扫描时钟信号传输至扫描输出端作为扫描信号输出；
下拉控制单元，电性连接下拉节点与所述上拉节点，在所述第一时间段依据接收的第一控制时钟信号控制所述下拉节点处于低电平状态，其中，所述第一时间段、第二时间段在时间上无间断连续且无重叠；
下拉输出单元，电性连接于所述下拉节点以及所述扫描输出端，用于在所述下拉节点处于高电平状态时控制所述扫描输出端下拉至低电平状态并停止输出所述扫描信号，并且在所述下拉节点处于低电平状态时停止工作。
本发明实施例公开了一种包括多个相互级联的扫描驱动单元的扫描驱动电路。
本发明实施例公开了一种阵列基板，包括图像显示区与非图像显示区，所述图像显示区包括用于执行图像显示的像素阵列，所述非图像显示区包括前述的扫描驱动电路。
本发明实施例公开了一种包括前述阵列基板的显示装置。
相较于现有技术，由于扫描驱动单元中下拉控制单元在所述第一时间段依据接收的第一控制时钟信号控制所述下拉节点处于低电平状态，防止下拉节点无法准确处于低电平状态而导致上拉节点高电平状态受到影响，保证扫描信号的准确输出。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一实施例中扫描驱动电路的布局结构示意图；
图2为如图1所示扫描驱动单元的电路结构示意；
图3为图1-2所述扫描驱动电路的工作时序图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是 全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
下面结合附图，具体说明扫描驱动电路以及扫描驱动单元的电路结构及其工作过程。
本发明所有实施方式中采用的晶体管均为通过铟镓锌氧化物工艺(indium gallium zinc oxide,IGZO)制作的N型薄膜晶体管(Thin-filmtransistor，TFT)。当然，在其他变更实施例中，薄膜晶体管还也可以为P型，并不以此为限。
请参阅图1，其为本发明一实施例中扫描驱动电路100的布局结构示意图。
如图1所示，本发明实施方式的扫描驱动电路100用于为像素矩阵200提供扫描脉冲信号。
扫描驱动电路100包括相互级联的多个扫描驱动单元10，相互级联的多个扫描驱动单元10依次向像素阵列200中的多个扫描线(未标识)提供扫描信号。其中，每个扫描驱动单元10在一帧图像的显示驱动中输出一个扫描周期的扫描信号至与之连接的扫描线。
本实施例中，多个扫描驱动单元10分别设置于像素阵列200的相对两侧，即，部分扫描驱动单元10设置于像素阵列200的一侧，另一部分扫描驱动单元10设置于像素阵列200的相对的另一侧。
其中，依据每一条扫描线对应一个扫描驱动单元10，并且相邻的两条扫描线对应的扫描驱动单元10分别设置于像素阵列200的相对两侧的方式设置，也即是奇数行、偶数行扫描线对应的扫描驱动单元10分别位于像素阵列200的相对两侧，例如奇数行的扫描线对应的扫描驱动单元GOA1、GOA3、GOA5、GOA7……、GOA(2N-3)、GOA2N-1、GOA(2N+1)、……位于像素阵列200的右边；偶数行的扫描线对应的扫描驱动单元GOA2、GOA4、GOA6、GOA8……、GOA(2N-2)、GOA(2N)、GOA(2N+2)……位于像素阵列200的左边。
请一并参阅图1与图2，其中，每个扫描驱动单元10包括驱动使能端EN、时钟信号端CK、复位端TRST以及扫描输出端OUT。本实施例中，如图2所示，每个扫描驱动单元中时钟信号端包括第一时钟信号端CKp1、第二时钟信号端CKp2以及第三时钟信号端CKp3，其中，第一时钟信号端CKp1用于接收扫描 时钟信号，第二时钟信号端CKp2与第三时钟信号端CKp3用于接收控制时钟信号。其中，所述扫描时钟信号用于控制所述扫描驱动单元10自扫描输出端OUT输出扫描信号，而所述控制时钟信号用于控制所述扫描驱动单元10停止从扫描输出端OUT输出扫描信号。
相互级联时，奇数行扫描线对应的扫描驱动单元依次级联，而偶数行扫描线对应的扫描驱动单元依次相互级联。具体的，对于右侧的多个扫描驱动单元10，GOA1的驱动使能端EN用于接收启动电压STV，同时，扫描输出端OUT连接第一个扫描线的同时，还一并电性连接GOA3的驱动使能端EN，以此类推，而使得奇数行扫描线对应的扫描驱动单元10依次级联。对应地，对于左侧的多个扫描驱动单元10，GOA2的驱动使能端EN用于接收启动电压STV，同时，扫描输出端OUT连接第二个扫描线的同时，还一并电性连接GOA4的驱动使能端EN，以此类推，而使得偶数行扫描线对应的扫描驱动单元10依次级联。
同时，每相邻的8个扫描驱动单元10为一组分别接收8个具有扫描时长均为1H且幅度相同的时钟信号CK1-CK8，相邻的2个时钟信号重叠1/2H时长。举例而言，时钟信号CK1与时钟信号CK2交叠有1/2H时长，而时钟信号CK2与时钟信号CK3交叠有1/2H时长，以此类推循环。其中，需要说明的是，所述H为一个单位时间长度，例如，1H可以为8微秒(μs)，当然，1H可以依据图像显示的实际需求进行设定，并不以此为限。
本实施例中，时钟信号CK1、时钟信号CK3、时钟信号CK5、时钟信号CK7则形成在时间上连续无间断并且无重叠地的一组时钟信号，并分别提供给右侧的多个扫描驱动单元GOA；而时钟信号CK2、时钟信号CK4、时钟信号CK6、时钟信号CK8则形成在时间上连续无间断并且无重叠地为一组时钟信号，并分别提供给左侧的多个扫描驱动单元GOA。
本实施例中，所述扫描驱动电路100、相应的扫描线以及像素阵列200均设置于阵列基板AY中。其中，用于执行图像显示的像素阵列200设置于阵列基板的图像显示区(未标识)，扫描驱动电路100则设置于非图像显示区，而扫描线则自图像显示区域延伸至非图像显示区域以连接所述扫描驱动电路100与像素阵列200。本实施例中，扫描驱动电路100采用GOA技术直接制作于阵列基板AY上。
另外，阵列基板AY可以应用于显示装置(未标识)中，例如应用于液晶显示器、有机电致发光显示器等显示装置中，或者应用于具有显示屏的手机、平板电脑等电子装置中。
具体地，请参阅图2，其为图1所示任意一个扫描驱动单元10的电路结构示意图。
如图2所示，以为第n条的扫描线提供扫描信号的扫描驱动单元GOAN为例，具体说明扫描驱动单元GOA的电路结构，其中N为正整数。举例而言，当像素区域200包括有1920条扫描线，那么N就为1至1920之间任意一个数字。
扫描驱动单元GOAN包括上拉控制单元11、上拉输出单元12、下拉控制单元13、下拉输出单元14、漂移校正单元15以及复位单元16。
其中，上拉控制单元11用于从驱动使能端EN接收启动电压STV，并且在一个扫描周期的第一时间段将所述启动电压STV传输至上拉节点PU以控制所述上拉节点PU为高电平状态。当然，除第一个GOA1是接收启动电压STV作为使能电压外，其他的扫描驱动单元GOAN均由第n-2个扫描驱动单元GOAN-2输出的扫描驱动信号作为使能电压。
上拉输出单元12电性连接所述上拉节点PU，并且当所述上拉节点PU为高电平状态时，在扫描周期的第二时间段将自第一时钟信号端CK1接收的扫描时钟信号CKi传输至扫描输出端OUT作为扫描信号输出。
下拉控制单元13，电性连接下拉节点PD与所述上拉节点PU，用于所述第一时间段依据第一控制时钟信号控制所述下拉节点PD处于低电平状态，并且在一个扫描周期之内的其他时间段均依据第一控制时钟信号与第二控制时钟信号间隔预定时长交替控制所述上拉节点PU处于低电平状态以及控制所述下拉节点PD处于高电平状态。
本实施例中，需要说明的是，所述高电平状态为所述节点的电压为高电压并且足以驱动对应的晶体管处于导通状态，可以表示为所述节点的电压处于高电平参考电压VGH；低电平状态则为所述节点的电压为低电压且不足以将晶体管维持在导通状态，可以表示为所述节点的电压处于低电平参考电压VGL。
下拉输出单元14，电性连接于下拉节点PD以及所述扫描输出端OUT，用 于在所述下拉节点PD处于高电平状态时控制所述扫描输出端OUT下拉至低电压并停止输出所述扫描信号。
漂移校正单元15，电性连接于所述上拉节点PU，用于在一个扫描周期之后接收漂移校正信号以控制所述上拉节点PU处于低电平状态。漂移校正单元15能够在扫描驱动单元10处于非扫描周期下拉节点PD无法及时准确控制上拉节点PU处于低电平状态以停止输出扫描信号时，快速、准确地将上拉节点PU下拉至低电平状态，防止多个扫描驱动单元同时输出扫描信号至多条扫描线，保证图像显示的准确性。
所述漂移校正信号可以为外部提供的时钟信号，也可以为与之相邻的扫描驱动单元在后一个扫描周期输出的扫描信号。例如，当前扫描驱动单元为扫描驱动单元GOA1，那么漂移校正信号可以为扫描驱动单元GOA3输出的扫描信号。
复位单元16电性连接所述上拉节点PU，用于依据复位信号TRST控制所述上拉节点PU处于低电平状态，当扫描驱动电路100整体复位时，准确控制全部扫描驱动单元10中的上拉输出单元12停止输出扫描驱动信号。
更为具体地，如图2所示：
上拉控制单元11包括第一晶体管M1，所述第一晶体管M1的栅极与漏极电性连接至驱动使能端EN，所述第一晶体管M1的源极电性连接至所述上拉节点PU。本实施例中，扫描驱动单元GOA N-2输出的扫描信号Gout N-2作为驱动电压。
上拉输出单元12包括第三晶体管M3与第一电容C1，所述第三晶体管M3的栅极电性连接所述上拉节点PU，所述第三晶体管M3的漏极电性连接至第一时钟信号端CKp1以接收时钟信号CKi，所述第三晶体管M3的源极电性连接所述扫输出端OUT。所述第一电容C1电性连接于所述上拉节点PU与所述扫描输出端OUT之间。本实施例中，时钟信号CK1对应于扫描驱动单元GOAN需要输出扫描信号的时间段处于高电平的脉冲信号，并且时钟信号CKi作为扫描时钟信号。
所述下拉控制单元13包括第二晶体管M2、第四晶体管M4、第七晶体管 M7与第八晶体管M8。
所述第二晶体管M2的栅极与漏极电性连接至第二时钟信号端CKp2，用于接收时钟信号CKi+2，第二晶体管M2的源极电性于所述下拉节点PD。本实施例中，时钟信号CKi+2作为第二控制时钟信号。
第四晶体管M4的栅极电性连接所述下拉节点PD，第四晶体管M4的源极电性连接所述上拉节点PU，所述第四晶体管M4的漏极电性连接低参考电压端VGL，用于接收低电平参考电压VGL。
第七晶体管M7的栅极电性连接所述第三时钟信号端CKp3，用于接收时钟信号CKi-2，所述第七晶体管M7的源极电性连接所述下拉节点PD，所述第七晶体管M7的漏极电性连接低参考电压端VGL，用于接收低电平参考电压VGL。本实施例中，时钟信号CKi-2作为第一控制时钟信号。
第八晶体管M8的栅极电性连接所述上拉节点PU，所述第八晶体管M8的漏极电性连接所述低参考电压端VGL，所述第八晶体管M8的源极电性连接所述下拉节点PD。
所述下拉输出单元14包括下拉晶体管M14，所述下拉晶体管M14的栅极电性连接所述下拉节点PD，所述下拉晶体管M14的漏极电性连接所述扫描输出端OUT，所述下拉晶体管14的源极电性连接所述低参考电压端VGL。
较佳地，所述扫描驱动单元10还包括辅助下拉控制单元13’、辅助下拉输出单元14’与辅助下拉节点PD’。
具体地，所述辅助下拉控制单元13’、辅助下拉输出单元14’以及辅助下拉节点PD’均与所述下拉控制单元13、下拉输出单元14以及下拉节点PD在相邻2个扫描周期时间交替循环处于工作状态。
例如，在第i个时钟信号CKi对应的扫描周期，下拉控制单元13、下拉输出单元14以及下拉节点PD处于工作状态，辅助下拉控制单元13’、辅助下拉输出单元14’以及辅助下拉节点PD’处于非工作状态；
而第i+4时钟信号CKi+4扫描周期时，下拉控制单元13、下拉输出单元14以及下拉节点PD处于非工作状态，辅助下拉控制单元13’、辅助下拉输出单元14’以及辅助下拉节点PD’处于工作状态。本实施例中i≤8且为自然数。
需要说明的是，每个时钟信号CK对应一个扫描周期H的长度，任意相邻2 个时钟信号相差1/2H个时长。如此一来，时钟信号CKi与时钟信号CKi+4相差2个时钟信号长度2H。
另外，第一时钟信号端CKp1接收的时钟信号CKi显然与第二时钟信号端CKp2接收的时钟信号CKi+2、第三时钟信号端CKp3接收时钟信号CKi-2均相差一个时钟信号对应的时间长度，那么，该三个时钟信号为在时间上无间断连续且无交叠的时钟信号。本实施例中，所述时钟信号均为高电平有效的脉冲信号。
具体地，所述辅助下拉控制单元13’包括第二对称晶体管M2’、第四对称晶体管M4’，第七对称晶体管M7’以及第八对称晶体管M8’。
所述第二对称晶体管M2’的栅极与漏极电性连接至第三时钟信号端CKp3，用于接收时钟信号CKi-2，第二对称晶体管M2’的源极电性连接辅助下拉节点PD’。
所述第四对称晶体管M4’的栅极电性连接所述辅助下拉节点PD’，所述第四对称晶体管M4’的源极电性连接所述上拉节点PU，所述第四对称晶体管M4’的漏极电性连接所述低参考电压端VGL。
所述第七对称晶体管M7’的栅极电性连接所述第二时钟信号端CKp2，用于接收时钟信号CKi+2，所述第七对称晶体管M7’的漏极电性连接所述低参考电压端VGL，接收低电平参考电压VGL，所述第七对称晶体管M7’的源极电性连接所述辅助下拉节点PD’。
所述第八对称晶体管M8’的栅极电性连接所述上拉节点PU，所述第八对称晶体管M8’的漏极电性连接所述低参考电压端VGL，所述第八对称晶体管的源极电性连接所述辅助下拉节点PD’。
所述辅助下拉输出单元14’包括下拉对称晶体管M14’，所述下拉对称晶体管M14’的栅极电性连接所述辅助下拉节点PD’，所述下拉辅助晶体管M14’的源极电性连接所述扫描输出端OUT，所述下拉对称晶体管M14’的漏极电性连接所述低参考电压端VGL。
下拉控制单元13与下拉辅助控制单元13’在间隔2个扫描周期的时长交替处于工作状态，从而能够防止下拉控制单元13或者下拉辅助控制单元13’长时间处于工作状态而导致晶体管的性能受到影响。
较佳地，所述扫描驱动单元10还包括第二电容C2，第二电容C2电性连接 于所述下拉节点PD与辅助下拉节点PD’之间，所述第二电容C2用于保证下拉控制单元13与辅助下拉控制单元13’切换工作工程时准确维持下拉节点PD与辅助下拉节点PD’的电压。
举例而言，当第三时钟信号端CKp3接收的时钟信号CKi-2处于高电平期间，辅助下拉节点PD’处于高电平状态，显然，此时第二时钟信号端CKp2接收的时钟信号势必处于低电平，也即是下拉节点PD处于低电平状态，故而，第二电容C2由于电容的压差特性能够有效维持辅助下拉节点PD’与下拉节点PD的电压差，保证下拉控制单元13与辅助下拉控制单元13’的工作准确性。
所述漂移校正单元15包括校正晶体管M15，所述校正晶体管M15的栅极接收漂移校正信号，所述校正晶体管M15的源极电性连接所述上拉节点PU，所述校正晶体管M15的漏极电性连接低参考电压端VGL。
所述复位单元16包括复位晶体管M20，复位晶体管M20的栅极电性连接复位端TRST以接收复位信号，复位晶体管M20的源极电性连接所述上拉节点PU，复位晶体管M20的漏极电性连接低参考电压端VGL。
请参阅图3，其为图1-2所示扫描驱动电路100的工作时序图。其中，图中的符号表示为图1-2中所接收的相应的信号。具体地，符号VGL表征低参考电压端VGL提供的电压波形，STV-L表征提供到左侧扫描驱动单元的启动电压，STV-R表征提供到右侧扫描驱动单元的启动电压，CK1-CK8表征8个时钟信号，Gout1-Gout1920分别表征对应序号的扫描驱动单元提供的扫描信号。本实施例中，以排序在第一位置的扫描驱动单元GOA1为例说明其工作过程。
其中，对于第一帧图像扫描期周期时，GOA1的一个扫描周期包括三个连续的时间段t1-t3。
在时间段t1，GOA1接收到左侧信号中的启动电压STV-L与自第三时钟信号端CKp3提供时钟信号CK1，上拉单元11中的第一晶体管M1开启，从而将上拉节点PU的电压拉升至高电平状态，与此同时，第一电容C1也开始充电并且进一步提升上拉节点PU的电压直至上拉节点PU处于高电平状态。
自第三时钟信号端CKp3提供时钟信号CK1，以控制第七晶体管M7处于导通状态，从而准确维持下拉节点PD处于低电平状态，并且时钟信号CK1控制 第二对称晶体管M2’处于导通状态，从而准确维持辅助下拉节点PD’处于高电平状态，进而控制辅助下拉输出单元14’中下拉对称晶体管M14’处于导通状态，以保证GOA1的扫描输出端OUT处于低电压。
第二电容C2保证下拉节点PD与辅助下拉节点PD’的电压差，准确维持下拉节点PD与助下拉节点PD’的电压状态。
在时间段t2，停止提供启动电压STV-L与时钟信号CK1，同时自第一时钟信号端CKp1提供时钟信号CK3，上拉节点PU的电压高于第三晶体管M3的阈值电压Vth(未标识)，第三晶体管M3导通，时钟信号CK3通过导通的第三晶体管M3传输至扫描输出端OUT，并且将此时的时钟信号CK3作为扫描信号Gout1输出。
在时间段t3，停止提供时钟信号CK3，同时自第二时钟信号端CKp2提供时钟信号CK5。自第二时钟信号端CKp2提供的时钟信号CK5控制第七对称晶体管M7’处于导通状态，从而准确维持辅助下拉节点PD’处于低电平状态，并且时钟信号CK5控制第二晶体管M2处于导通状态，从而准确维持下拉节点PD处于高电平状态，进而控制下拉输出单元14中下拉晶体管M14处于导通状态，以保证GOA1的扫描输出端OUT处于低电压。
与此同时，扫描驱动单元GOA3中的扫描输出端OUT在时钟信号CK5输出的同时已经完成输出高电压的扫描信号，从而控制漂移校正单元15中的校正晶体管M15处于导通状态，进一步准确、即时地将上拉节点PU下拉至电平状态，使下拉节点的电压为低电平参考电压VGL。
需要说明的是，其他扫描驱动单元的工作过程与GOA1相同，在此不再赘述，第二帧图像扫描期周期与第一帧图像扫描周期对应的多个扫描驱动单元GOA工作原理相同，在此不再赘述。
相较于现有技术，由于下拉控制单元14或者辅助下拉控制单元14’在所述第一时间段依据接收的第一控制时钟信号控制所述下拉节点PD处于低电平状态，防止下拉节点PD无法准确处于低电平状态而导致上拉节点PU高电平状态受到影响，保证扫描信号的准确输出。
本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的核心思想；同时，对于本领域的一般技 术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (15)

  1. 一种扫描驱动单元，其特征在于，所述扫描驱动单元包括：
    上拉控制单元，用于接收启动电压，并且在一个扫描周期内的第一时间段将所述启动电压传输至上拉节点以控制所述上拉节点为高电平状态；
    上拉输出单元，电性连接所述上拉节点，在所述扫描周期内的第二时间段并且当所述上拉节点为高电平状态时，将接收的扫描时钟信号传输至扫描输出端作为扫描信号输出；
    下拉控制单元，电性连接下拉节点与所述上拉节点，在所述第一时间段依据接收的第一控制时钟信号控制所述下拉节点处于低电平状态，其中，所述第一时间段、第二时间段在时间上无间断连续且无重叠；
    下拉输出单元，电性连接于所述下拉节点以及所述扫描输出端，用于在所述下拉节点处于高电平状态时控制所述扫描输出端下拉至低电平状态并停止输出所述扫描信号，并且在所述下拉节点处于低电平状态时停止工作。
  2. 根据权利要求1所述的扫描驱动单元，其特征在于，所述下拉控制单元还在所述扫描周期的第三时间段接收第二控制时钟信号，且依据所述第二控制时钟信号控制所述上拉节点处于低电平状态以及控制所述下拉节点处于高电平状态，所述第一时间段、第二时间段与所述第三时间段在时间上无间断连续且无重叠。
  3. 根据权利要求2所述的扫描驱动单元，其特征在于，所述扫描时钟信号、第一控制时钟信号与所述第二时钟时钟信号包含的脉冲信号的时间长度与幅度相同。
  4. 根据权利要求3所述的扫描驱动单元，其特征在于，所述第一控制时钟信号与所述第二控制时钟信号在所述扫描周期之内间隔两个脉冲信号的时间长度交替控制所述上拉节点处于低电平状态。
  5. 根据权利要求4所述的扫描驱动单元，其特征在于，所述上拉控制单元 包括第一晶体管，所述第一晶体管的栅极与漏极电性连接至驱动使能端，所述驱动使能端用于接收所述启动电压，所述第一晶体管的源极电性连接至所述上拉节点。
  6. 根据权利要求5所述的扫描驱动单元，其特征在于，所述上拉输出单元包括第三晶体管、第一电容以及第一时钟信号端，所述第三晶体管的栅极电性连接所述上拉节点，所述第三晶体管的漏极电性连接至所述第一时钟信号端以接收扫描时钟信号，所述第三晶体管的源极电性连接所述扫描输出端，所述第一电容电性连接于所述上拉节点与所述扫描输出端之间。
  7. 根据权利要求6所述的扫描驱动单元，其特征在于，所述下拉控制单元包括第二晶体管、第四晶体管、第七晶体管、第八晶体管、第二时钟信号端与第三时钟信号端，所述第二晶体管的栅极与漏极电性连接至所述第二时钟信号端以接收所述第二控制时钟信号，所述第二晶体管的源极电性于所述下拉节点，所述第四晶体管的栅极电性连接所述下拉节点，所述第四晶体管的源极电性连接所述上拉节点，所述第四晶体管的漏极电性连接低参考电压端，所述第七晶体管的栅极电性连接所述第三时钟信号端以接收所述第一控制时钟信号，所述第七晶体管的源极电性连接所述下拉节点，所述第七晶体管的漏极电性连接所述低参考电压端，所述第八晶体管的栅极电性连接所述上拉节点，所述第八晶体管的源极电性连接所述下拉节点，所述第八晶体管的源极电性连接所述低参考电压端；
    所述下拉输出单元包括下拉晶体管，所述下拉晶体管的栅极电性连接所述下拉节点，所述下拉晶体管的源极电性连接所述扫描输出端，所述下拉晶体管的漏极接收所述低参考电压端。
  8. 根据权利要求7所述的扫描驱动单元，其特征在于，所述扫描驱动单元还包括辅助下拉控制单元、辅助下拉输出单元以及辅助下拉节点，所述辅助下拉控制单元与所述下拉控制单元在所述第一控制时钟信号与所述第二控制时钟信号控制下交替处于工作状态，当所述辅助下拉控制单元处于工作状态时对 应控制所述辅助下拉节点处于所述高电平状态或者低电平状态，所述辅助下拉输出单元在所述辅助下拉节点处于高电平状态时控制所述扫描输出端处于所述低电压。
  9. 根据权利要求8所述的扫描驱动单元，其特征在于，所述辅助下拉控制单元包括第二对称晶体管、第四对称晶体管，第七对称晶体管以及第八对称晶体管，所述第二对称晶体管的栅极与漏极电性连接至所述第三时钟信号端以接收所述第一控制时钟信号，第二对称晶体管的源极电性连接辅助下拉节点；所述第四对称晶体管的栅极电性连接所述辅助下拉节点，所述第四对称晶体管的源极电性连接所述上拉节点，所述第四对称晶体管的漏极电性连接所述低参考电压端；所述第七对称晶体管的栅极电性连接所述第二时钟信号端以接收所述第二控制时钟信号，所述第七对称晶体管的源极电性连接所述辅助下拉节点，所述第七对称晶体管的漏极电性连接所述低参考电压端；所述第八对称晶体管的栅极电性连接所述上拉节点，所述第八对称晶体管的源极电性连接所述辅助下拉节点，所述第八对称晶体管的漏极电性连接所述低参考电压端；
    所述辅助下拉输出单元包括下拉对称晶体管，所述下拉对称晶体管的栅极电性连接所述辅助下拉节点，所述下拉对称晶体管的源极电性连接所述扫描输出端，所述下拉对称晶体管的漏极电性连接所述低参考电压端。
  10. 根据权利要求9所述的扫描驱动单元，其特征在于，所述扫描驱动单元还包括第二电容，所述第二电容电性连接于所述下拉节点与所述辅助下拉节点，用于维持所述下拉节点与所述辅助下拉节点的电压。
  11. 根据权利要求1所述的扫描驱动单元，其特征在于，所述扫描驱动单元还包括漂移校正单元，所述漂移校正单元电性连接于所述上拉节点，用于在所述一个扫描周期之后依据漂移校正信号控制所述上拉节点处于低电平状态，其中，所述漂移校正单元包括校正晶体管，所述校正晶体管的栅极接收所述漂移校正信号，所述校正晶体管的漏极电性连接所述上拉节点，所述校正晶体管的源极电性连接接地参考电压。
  12. 根据权利要求1所述的扫描驱动单元，其特征在于，所述扫描驱动单元还包括复位单元，所述复位单元电性连接于所述上拉节点，用于在接收到复位信号时控制所述上拉节点处于所述低电平状态，其中，所述复位单元包括复位晶体管，所述复位晶体管的栅极接收复位信号，所述复位晶体管的漏极电性连接于所述上拉节点，所述复位晶体管的源极接收低电平参考电压。
  13. 一种扫描驱动电路，其特征在于，包括多个相互级联的如权利要求1-12任意一项所述的扫描驱动单元。
  14. 一种阵列基板，其特征在于，包括图像显示区与非图像显示区，所述图像显示区包括用于执行图像显示的像素阵列，所述非图像显示区包括权利要求13所述的扫描驱动电路。
  15. 一种显示装置，其特征在于，包括如权利要求14所述的阵列基板。
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CN105304011A (zh) * 2015-12-09 2016-02-03 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
CN106023946A (zh) * 2016-08-04 2016-10-12 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置以及显示装置
CN106356015A (zh) * 2016-10-31 2017-01-25 合肥鑫晟光电科技有限公司 移位寄存器及驱动方法、显示装置
CN106782282A (zh) * 2017-02-23 2017-05-31 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示面板及驱动方法
CN108564927A (zh) * 2018-01-12 2018-09-21 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置

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CN113284459A (zh) * 2021-07-19 2021-08-20 深圳市柔宇科技股份有限公司 扫描驱动单元、扫描驱动电路、阵列基板及显示器
CN113284459B (zh) * 2021-07-19 2021-10-22 深圳市柔宇科技股份有限公司 扫描驱动单元、扫描驱动电路、阵列基板及显示器
CN113643641A (zh) * 2021-08-03 2021-11-12 武汉华星光电技术有限公司 栅极驱动电路及显示面板
CN114937431A (zh) * 2022-05-31 2022-08-23 惠科股份有限公司 扫描驱动电路、显示面板和显示装置

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