WO2020144998A1 - Dispositif d'affichage - Google Patents

Dispositif d'affichage Download PDF

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Publication number
WO2020144998A1
WO2020144998A1 PCT/JP2019/048125 JP2019048125W WO2020144998A1 WO 2020144998 A1 WO2020144998 A1 WO 2020144998A1 JP 2019048125 W JP2019048125 W JP 2019048125W WO 2020144998 A1 WO2020144998 A1 WO 2020144998A1
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WO
WIPO (PCT)
Prior art keywords
insulating film
color filter
common electrode
layer
semiconductor layer
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PCT/JP2019/048125
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English (en)
Japanese (ja)
Inventor
一秀 望月
真 内田
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株式会社ジャパンディスプレイ
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Application filed by 株式会社ジャパンディスプレイ filed Critical 株式会社ジャパンディスプレイ
Publication of WO2020144998A1 publication Critical patent/WO2020144998A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • Embodiments of the present invention relate to a display device.
  • a technique of combining a first switching element including an oxide semiconductor layer and a second switching element including a polycrystalline silicon semiconductor layer has been proposed.
  • the first switching element is provided in each pixel, and the second switching element is provided in the peripheral circuit.
  • the allowable margin is becoming smaller.
  • the purpose of this embodiment is to provide a display device capable of suppressing deterioration of display quality.
  • the first switching element includes a first semiconductor layer formed of an oxide semiconductor
  • the second switching element includes a second semiconductor layer formed of a polycrystalline silicon semiconductor
  • the first semiconductor layer Is provided between the color filter layer and the second inorganic insulating film
  • the second semiconductor layer is provided between the insulating substrate and the first inorganic insulating film.
  • the present embodiment it is possible to provide a display device capable of suppressing deterioration of display quality.
  • FIG. 1 is a plan view showing the configuration of the display device DSP according to this embodiment.
  • FIG. 2 is a plan view showing the sub-pixels SP(R), SP(G) and SP(B) of the first substrate SUB1.
  • FIG. 3 is another plan view showing the sub-pixels SP(R), SP(G) and SP(B) of the first substrate SUB1.
  • FIG. 4 is a cross-sectional view of the display panel PNL taken along the line AB shown in FIG.
  • FIG. 5 is a cross-sectional view of the display panel PNL taken along the line CD shown in FIG.
  • FIG. 6 is a cross-sectional view of the display panel PNL taken along the line EF shown in FIG.
  • FIG. 7 is a sectional view showing the second switching element SW2 shown in FIG.
  • FIG. 8 is a sectional view showing a modified example of the display panel PNL.
  • FIG. 9 is a cross-sectional view showing the second switching element SW2 in the modified example.
  • FIG. 10 is a cross
  • a liquid crystal display device will be described as an example of the display device.
  • the main configuration disclosed in the present embodiment is a self-luminous display device having an organic electroluminescence display element or the like, an electronic paper type display device having an electrophoretic element, a MEMS (Micro Electro Mechanical Systems).
  • the present invention can also be applied to a display device to which it is applied or a display device to which electrochromism is applied.
  • FIG. 1 is a plan view showing the configuration of the display device DSP according to the present embodiment.
  • the display device DSP includes a display panel PNL and an illumination device IL.
  • the display panel PNL includes a first substrate SUB1, a second substrate SUB2, and a liquid crystal layer LC.
  • the liquid crystal layer LC is an example of a display function layer, and is enclosed between the first substrate SUB1 and the second substrate SUB2.
  • the display panel PNL includes a display area DA for displaying an image and a peripheral area SA around the display area DA in an area where the first substrate SUB1 and the second substrate SUB2 overlap each other.
  • the display panel PNL includes a plurality of pixels PX in the display area DA. The plurality of pixels PX are arranged in a matrix.
  • the first substrate SUB1 includes a plurality of scanning lines G and a plurality of signal lines S in the display area DA.
  • the scanning lines G extend in the first direction X and are arranged in the second direction Y.
  • the signal lines S extend in the second direction Y and are arranged in the first direction X.
  • the scanning lines G and the signal lines S are shown by straight lines, but the scanning lines G and the signal lines S may be bent or meandered.
  • the first substrate SUB1 includes a scanning line drive circuit GD and a signal line drive circuit SD in the peripheral area SA.
  • the scanning line G is electrically connected to the scanning line driving circuit GD.
  • the signal line S is electrically connected to the signal line drive circuit SD.
  • the pixel PX has a plurality of sub-pixels SP.
  • Each sub-pixel SP corresponds to, for example, a region partitioned by two adjacent scanning lines G and two adjacent signal lines S. Note that in the present disclosure, the subpixel may be simply referred to as a pixel.
  • one pixel PX includes three sub-pixels SP(R), SP(G) and SP(B).
  • the sub-pixel SP(R) displays red
  • the sub-pixel SP(G) displays green
  • the sub-pixel SP(B) displays blue.
  • the pixel PX may include more sub-pixels SP.
  • the colors displayed by the sub-pixels SP are not limited to red, green, and blue, and may be other colors such as white and yellow.
  • the first substrate SUB1 includes the first switching element SW1 and the pixel electrode PE.
  • the first switching element SW1 is electrically connected to the scanning line G and the signal line S.
  • the pixel electrode PE is electrically connected to the first switching element SW1.
  • the first substrate SUB1 also includes a common electrode CE.
  • the common electrode CE is provided commonly to the plurality of sub-pixels SP.
  • the common electrode CE may be provided on the second substrate SUB2.
  • the first substrate SUB1 has a terminal area TA that does not overlap with the second substrate SUB2.
  • the IC chip 1 and the flexible printed circuit board 2 are mounted in the terminal area TA.
  • the IC chip 1 may be mounted on the flexible printed circuit board 2.
  • the IC chip 1 is electrically connected to the common electrode CE, the scanning line driving circuit GD, and the signal line driving circuit SD.
  • the IC chip 1 supplies the common voltage Vcom to the common electrode CE.
  • the IC chip 1 supplies various signals to the scanning line drive circuit GD and the signal line drive circuit SD.
  • the signal line drive circuit SD supplies a video signal to each signal line S.
  • the scanning line drive circuit GD includes a plurality of vertical circuits 40.
  • each vertical circuit 40 includes a shift register and a buffer.
  • the vertical circuit 40 supplies a scanning signal to the scanning line G.
  • the vertical circuit 40 includes a second switching element SW2 described later.
  • another circuit provided in the peripheral area SA such as the signal line drive circuit SD may include the second switching element SW2.
  • the first substrate SUB1 includes the first switching element SW1 provided in the display area DA and the second switching element SW2 provided in the peripheral area SA.
  • the first switching element SW1 has a first semiconductor layer made of a transparent oxide semiconductor
  • the second switching element SW2 has a second semiconductor layer made of a polycrystalline silicon semiconductor.
  • the illumination device IL is provided on the back side of the display panel PNL and illuminates the display area DA. Although details of the illuminator IL are omitted, the illuminator IL includes a flat light guide plate and a plurality of light sources arranged along the end surface of the light guide plate.
  • FIG. 2 is a plan view showing the sub-pixels SP(R), SP(G), SP(B) of the first substrate SUB1.
  • the first substrate SUB1 includes a color filter layer CF, a first light shielding layer BM1, signal lines S1 to S4, a scanning line G1, and first switching elements SW11 to SW13.
  • the color filter layer CF includes a red color filter CFR provided in the sub pixel SP(R), a green color filter CFG provided in the sub pixel SP(G), and a blue color provided in the sub pixel SP(B). And a filter CFB.
  • the color filters CFR, CFG, CGB are arranged in the first direction X and extend in the second direction Y.
  • the first light shielding layer BM1 extends along the second direction Y.
  • the first light shielding layer BM1 is provided so as to overlap with the boundary between the color filters CFR, CFG, and CGB that are adjacent to each other in the first direction X.
  • Such a first light-shielding layer BM1 partitions the sub-pixels SP(R), SP(G), and SP(B) arranged in the first direction X.
  • the signal lines S1 to S4 are arranged in the first direction X and extend along the second direction Y.
  • the signal lines S1 to S4 are provided so as to overlap with the first light shielding layer BM1.
  • the scanning line G1 includes a first scanning line G11, a second scanning line G12, and a third scanning line G13.
  • the second scanning line G12 is provided so as to overlap the first scanning line G11.
  • the third scanning line G13 is provided so as to overlap the second scanning line G12.
  • the first to third scanning lines G11 to G13 extend along the first direction X and intersect the signal lines S1 to S4.
  • the first switching element SW11 is provided in the sub-pixel SP(R) and is electrically connected to the scanning line G1 and the signal line S1.
  • the first switching element SW12 is provided in the sub-pixel SP(G) and is electrically connected to the scanning line G1 and the signal line S2.
  • the first switching element SW13 is provided in the sub-pixel SP(B) and is electrically connected to the scanning line G1 and the signal line S3.
  • the first switching elements SW11 to SW13 include first semiconductor layers SC11 to SC13, respectively. As described above, the first semiconductor layers SC11 to SC13 are transparent oxide semiconductors.
  • the first switching elements SW11 to SW13 have the same single gate structure. The structure of the first switching element SW11 will be described below, focusing on the first switching element SW11.
  • the first semiconductor layer SC11 is provided so that a part thereof overlaps the signal line S1, and the other part extends between the signal lines S1 and S2.
  • the first semiconductor layer SC11 has an intersection (channel region) SCC that intersects the scanning line G1 between the signal lines S1 and S2.
  • the intersecting portion SCC corresponds to a shaded area in the drawing.
  • a region overlapping with the first semiconductor layer SC11 (or the intersection SCC) functions as the gate electrode GE.
  • the first semiconductor layer SC11 has one end SCA and the other end SCB.
  • the intersection SCC is located between the one end SCA and the other end SCB.
  • the shape of the first semiconductor layer SC11 is not limited to that shown in FIG.
  • the one end SCA is electrically connected to a pixel electrode described later in the opening OP1.
  • the other end SCB is in contact with the signal line S1 at the opening OP2.
  • the first scanning line G11 is provided below the second scanning line G12 and the third scanning line G13.
  • the first scanning line G11 is electrically connected to the second scanning line G12 and the third scanning line G13.
  • the width W11 of the first scanning line G11 in the second direction Y is larger than the widths W12 and W13 of the second scanning line G12 and the third scanning line G13 in the second direction Y, respectively.
  • the first scanning line G11 overlaps the entire second scanning line G12 and the third scanning line G13.
  • the width of each of the first scanning line G11, the second scanning line G12, and the third scanning line G13 does not need to be constant as illustrated.
  • the first semiconductor layer SC11 is provided between the first scanning line G11 and the second scanning line G12. That is, the intersecting portion SCC of the first semiconductor layer SC11 overlaps the first scanning line G11 in plan view. That is, the first scanning line G11 has a function as a light blocking film that blocks the light traveling from the illumination device IL toward the intersection SCC. Therefore, it is possible to suppress the current leakage of the first switching element SW11 due to the irradiation of the intersection SCC with light.
  • the first light shielding layer BM1 is provided below the signal line S1.
  • the width W21 of the first light shielding layer BM1 in the first direction X is larger than the width W22 of the signal line S1 in the first direction X.
  • the first light-shielding layer BM1 overlaps the entire signal line S1 in a plan view.
  • the width of each of the first light-shielding layer BM1 and the signal line S1 need not be constant as illustrated.
  • FIG. 3 is another plan view showing the sub-pixels SP(R), SP(G) and SP(B) of the first substrate SUB1.
  • the first substrate SUB1 includes metal wirings M1 to M4, pixel electrodes PE11 to PE13, a first common electrode CE1, and a second common electrode CE2.
  • the color filter layer CF and the first light shielding layer BM1 shown in FIG. 2 are omitted.
  • the pixel electrode PE11 is provided in the sub-pixel SP(R) and is in contact with the first semiconductor layer SC11 in the opening OP1. As a result, the pixel electrode PE11 is electrically connected to the first switching element SW11. Similarly, the pixel electrode PE12 is provided in the sub-pixel SP(G) and is electrically connected to the first switching element SW12. Similarly, the pixel electrode PE13 is also provided in the sub-pixel SP(B) and is electrically connected to the first switching element SW13. In the illustrated example, the pixel electrodes PE11 to PE13 are all flat plate electrodes having no slits.
  • the first common electrode CE1 is provided so as to overlap the signal lines S1 to S4 and the pixel electrodes PE11 to PE13.
  • the first common electrode CE1 is provided above the signal lines S1 to S4 and below the pixel electrodes PE11 to PE13.
  • the first common electrode CE1 does not overlap the scanning line G1, the first switching elements SW11 to SW13, and the first semiconductor layers SC11 to SC13.
  • the first common electrode CE1 is a flat plate electrode having no slit in the sub-pixels SP(R), SP(G) and SP(B).
  • the second common electrode CE2 is provided so as to overlap the scanning line G1, the signal lines S1 to S4, the first switching elements SW11 to SW13, and the first semiconductor layers SC11 to SC13. Further, the second common electrode CE2 is provided above the pixel electrodes PE11 to PE13, overlapping the pixel electrodes PE11 to PE13.
  • the second common electrode CE2 has openings AP11 to AP13 that overlap the pixel electrodes PE11 to PE13, respectively.
  • the openings AP11 to AP13 are formed in a substantially trapezoidal shape in which the width in the first direction X expands as they approach the scanning line G1.
  • the shapes of the openings AP11 to AP13 are not limited to the illustrated example.
  • the openings AP11 to AP13 may have a shape extending in the first direction X.
  • the second common electrode CE2 may have a strip electrode extending in the first direction X or the second direction Y.
  • the metal wirings M1 to M4 are arranged in the first direction X and extend along the second direction Y.
  • the metal wirings M1 to M4 are provided so as to overlap the signal lines S1 to S4, respectively.
  • the metal wirings M1 to M4 are provided above the first common electrode CE1 and below the second common electrode CE2.
  • the width W23 of the metal wiring M1 in the first direction X is equal to the width W22 of the signal line S1.
  • FIG. 4 is a cross-sectional view of the display panel PNL taken along the line AB shown in FIG.
  • the illustrated example corresponds to an example in which the FFS (Fringe Field Switching) mode, which is one of the display modes using the lateral electric field, is applied.
  • FIG. 4 corresponds to a cross-sectional view of the display panel PNL in the sub-pixel SP(R) shown in FIG.
  • the first substrate SUB1 includes an insulating substrate 10, insulating films 11 to 21, a color filter layer CF, a first light shielding layer BM1, a signal line S1, a scanning line G1, a metal wiring M1, a first switching element SW11, and a first common electrode CE1.
  • the color filter CFR is provided between the insulating film 13 corresponding to the first inorganic insulating film and the insulating film 15 corresponding to the second inorganic insulating film.
  • the pixel electrode PE11 is provided immediately above the color filter CFR and is electrically connected to the first switching element SW11.
  • the first switching element SW11 includes a first semiconductor layer SC11 made of a transparent oxide semiconductor, and the first semiconductor layer SC11 is provided between the color filter CFR and the insulating film 15.
  • the insulating film 14 corresponding to the transparent first organic insulating film covers at least a part of the color filter CFR.
  • the first semiconductor layer SC11 is provided on the insulating film 14.
  • the signal line S1 is electrically connected to the first semiconductor layer SC11.
  • the metal wiring M1 is provided immediately above the signal line S1.
  • the first light shielding layer BM1 is provided immediately below the signal line S1.
  • the insulating film 14 covers the first light shielding layer BM1 and the color filter CFR.
  • the insulating film 19 corresponding to the second organic insulating film covers the signal line S1.
  • the first common electrode CE1 is provided on the insulating film 19 and overlaps the pixel electrode PE11.
  • the second common electrode CE2 is electrically connected to the first common electrode CE1 and overlaps the pixel electrode PE11.
  • the insulating film 20 corresponding to the third inorganic insulating film is provided between the first common electrode CE1 and the pixel electrode PE11.
  • the insulating film 21 corresponding to the fourth inorganic insulating film is provided between the pixel electrode PE11 and the second common electrode CE2.
  • the metal wiring M1 is in contact with the first common electrode CE1.
  • the insulating film 11 is provided on the insulating substrate 10.
  • the insulating film 12 is provided on the insulating film 11.
  • the first scanning line G11 is provided on the insulating film 12.
  • the insulating film 13 is provided on the insulating film 12 and covers the first scanning line G11.
  • the color filter layer CF including the color filters CFB and CFR is provided on the insulating film 13.
  • the first light shielding layer BM1 is provided on the boundary between the color filters CFB and CFR.
  • the insulating film 14 covers the color filters CFB and CFR and the first light shielding layer BM1.
  • the first semiconductor layer SC11 is provided on the insulating film 14.
  • the insulating film 15 is provided on the insulating film 14 and covers the first semiconductor layer SC11. That is, the first semiconductor layer SC11 is provided above the color filter layer CF.
  • the second scanning line G12 (or the gate electrode GE) is provided on the insulating film 15. That is, the first semiconductor layer SC11 is provided between the first scanning line G11 and the second scanning line G12.
  • the insulating film 16 is provided on the insulating film 15 and covers the second scanning line G12.
  • the insulating film 17 is provided on the insulating film 16.
  • the third scanning line G13 is provided on the insulating film 17.
  • the insulating film 18 is provided on the insulating film 17 and covers the third scanning line G13.
  • the signal line S1 is provided on the insulating film 18 immediately above the first light shielding layer BM1.
  • the signal line S1 is in contact with the first semiconductor layer SC11 at the opening OP2 penetrating the insulating films 15 to 18.
  • the signal line S1 is electrically connected to the first semiconductor layer SC11.
  • the insulating film 19 is provided on the insulating film 18 and covers the signal line S1.
  • the metal wiring M1 is provided on the insulating film 19 immediately above the signal line S1.
  • the first common electrode CE1 is provided on the insulating film 19. However, the metal wiring M1 and the common electrode CE are formed of conductive materials different from each other.
  • the insulating film 20 is provided on the insulating film 19 and covers the metal wiring M1 and the first common electrode CE1.
  • the pixel electrode PE11 is provided on the insulating film 20 and is in contact with the first semiconductor layer SC1 in the opening OP1 penetrating the insulating films 15 to 20.
  • the pixel electrode PE11 is in direct contact with the first semiconductor layer SC11, but is not limited to this.
  • the connection electrode formed of the same material as the signal line S1, the connection electrode formed of the same material as the first common electrode CE1, or the connection electrode formed of the same material as the metal wiring M1 is the first semiconductor layer. It may be interposed between SC11 and the pixel electrode PE11.
  • the pixel electrode PE11 overlaps the first common electrode CE1 via the insulating film 20 and forms a capacitance in the sub-pixel SP(R).
  • the insulating film 21 is provided on the insulating film 20 and covers the pixel electrode PE11.
  • the second common electrode CE2 is provided on the insulating film 21.
  • the alignment film AL1 covers the insulating film 21 and the second common electrode CE2.
  • the second common electrode CE2 has the same potential as the first common electrode CE1.
  • a part of the second common electrode CE2 overlaps the pixel electrode PE11 via the insulating film 21 to form a capacitance in the sub-pixel SP(R).
  • the insulating substrate 10 is a light transmissive substrate such as a glass substrate or a flexible resin substrate.
  • the insulating films 11 to 13, the insulating films 15 to 18, and the insulating films 20 and 21 are transparent inorganic insulating films formed of an insulating material such as silicon oxide, silicon nitride, and silicon oxynitride, and have a single-layer structure. Or may have a multilayer structure.
  • the insulating films 14 and 19 are transparent organic insulating films formed of an insulating material such as acrylic resin, for example.
  • Each of the color filters CFR, CFG, CFB is an organic insulating film colored with a corresponding color.
  • the first light shielding layer BM1 is, for example, a black organic insulating film.
  • the first scanning line G11, the second scanning line G12, and the third scanning line G13 are made of, for example, molybdenum-tungsten alloy.
  • the signal line S1 and the metal wiring are, for example, configured by a laminated body in which a plurality of metal layers are laminated.
  • the laminated body is, for example, a layer including titanium (Ti), a layer including aluminum (Al), and a layer including titanium (Ti), which are laminated in this order.
  • the stacked body may be one in which a layer containing molybdenum (Mo), a layer containing aluminum (Al), and a layer containing molybdenum (Mo) are stacked in this order.
  • the first common electrode CE1, the pixel electrode PE11, and the second common electrode CE2 are transparent electrodes formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). ..
  • the second substrate SUB2 includes an insulating substrate 30 and an alignment film AL2.
  • the insulating substrate 30, like the insulating substrate 10, is a substrate having optical transparency such as a glass substrate or a resin substrate.
  • the alignment film AL2 is provided on the lower surface 30A of the insulating substrate 30. In the illustrated example, an insulating layer such as a light shielding layer or a color filter layer is not provided between the insulating substrate 30 and the alignment film AL2. Therefore, the alignment film AL2 is in contact with the lower surface 30A.
  • the alignment films AL1 and AL2 are formed of, for example, a material exhibiting horizontal alignment.
  • the liquid crystal layer LC is located between the first substrate SUB1 and the second substrate SUB2, and is provided between the alignment films AL1 and AL2.
  • the illumination device IL shown in FIG. 1 is provided below the insulating substrate 10, but is not shown. Further, in a normal transmissive liquid crystal display device, polarizing plates are adhered to the insulating substrates 10 and 20, respectively, but not shown.
  • FIG. 5 is a cross-sectional view of the display panel PNL taken along the line CD shown in FIG.
  • FIG. 5 corresponds to a cross-sectional view of the display panel PNL in the sub-pixel SP(G) shown in FIG.
  • the first substrate SUB1 includes a color filter CFG in the color filter layer CF.
  • the first semiconductor layer SC12 of the first switching element SW12 is provided on the insulating film 16. That is, the first semiconductor layer SC12 is provided between the second scanning line G12 and the third scanning line G13.
  • the first semiconductor layer SC11 of the adjacent sub-pixel SP(R) is provided on the insulating film 14 and is located in a layer different from the illustrated first semiconductor layer SC12.
  • the signal line S2 is provided directly above the first light shielding layer BM1 and is in contact with the first semiconductor layer SC12 at the opening OP4 penetrating the insulating films 17 and 18.
  • the pixel electrode PE12 is in contact with the first semiconductor layer SC12 in the opening OP3 penetrating the insulating films 17 to 20.
  • the metal wiring M2 is provided immediately above the signal line S2.
  • FIG. 6 is a cross-sectional view of the display panel PNL taken along the line EF shown in FIG.
  • FIG. 6 corresponds to a cross-sectional view of the display panel PNL in the sub-pixels SP(R) and SP(G) shown in FIG.
  • the first light-shielding layer BM1 is provided on the boundary between the color filter CFR and the color filter CFG, the boundary between the color filter CFG and the color filter CFB, and the boundary between the color filter CFR and the color filter CFB, respectively.
  • Each of the signal lines S1 to S3 is provided immediately above the first light shielding layer.
  • the first common electrode CE1 is provided immediately below the pixel electrodes PE11 and PE12 and is provided directly above the signal lines S1 to S3.
  • the metal wirings M1 to M3 are provided directly above the signal lines S1 to S3, respectively, and are in contact with the first common electrode CE1.
  • the metal wirings M1 to M3 are provided between the first common electrode CE1 and the insulating film 20, but may be provided between the insulating film 19 and the first common electrode CE1.
  • the metal wirings M1 to M3 may be provided so as to be in contact with the second common electrode CE2.
  • the second common electrode CE2 is provided immediately above the metal wirings M1 to M3. That is, the metal wirings M1 to M3 are provided immediately above the boundary between the adjacent color filters.
  • the openings AP11 and AP12 are formed directly above the pixel electrodes PE11 and PE12, respectively.
  • FIG. 7 is a sectional view showing the second switching element SW2 shown in FIG. FIG. 7 corresponds to a cross-sectional view of the first substrate SUB1 in the peripheral area SA shown in FIG. In the first substrate SUB1, the second switching element SW2 is provided in the peripheral area SA.
  • the second switching element SW2 includes a second semiconductor layer SC2 made of a polycrystalline silicon semiconductor.
  • the second semiconductor layer SC2 is provided between the insulating substrate 10 and the insulating film 13 corresponding to the first inorganic insulating film.
  • the second light-shielding layer overlaps the second semiconductor layer SC2 and is covered with the insulating film 14 corresponding to the first organic insulating film.
  • the second switching element SW2 includes a second semiconductor layer SC2, a gate electrode GE2, a source electrode SE2, and a drain electrode DE2.
  • the second semiconductor layer SC2 is provided on the insulating film 11 and covered with the insulating film 12. That is, the second semiconductor layer SC2 is located in a layer different from the first semiconductor layer SC11 shown in FIG. 4 and the first semiconductor layer SC12 shown in FIG.
  • the second semiconductor layer SC2 is provided below the first semiconductor layers SC11 and SC12 (on the side close to the insulating substrate 10).
  • the gate electrode GE2 is provided on the insulating film 12 and covered with the insulating film 13.
  • the gate electrode GE2 is located in the same layer as the first scanning line G11 shown in FIG. 4 and is made of the same material as the first scanning line G11.
  • the color filter layer CF was provided between the insulating films 13 and 14 in the display area DA shown in FIG. 4, but not provided in the peripheral area SA.
  • the first substrate SUB1 includes the second light shielding layer BM2 in the peripheral area SA.
  • the second light shielding layer BM2 is provided on the insulating film 13 and covered with the insulating film 14. That is, the second light shielding layer BM2 overlaps the second semiconductor layer SC2 and shields the second switching element SW2.
  • the second light-shielding layer BM2 is located in the same layer as the first light-shielding layer BM1 shown in FIG. 4 and is made of the same material as the first light-shielding layer BM1.
  • the source electrode SE2 and the drain electrode DE2 are provided on the insulating film 15 and covered with the insulating film 16.
  • the source electrode SE2 is in contact with the second semiconductor layer SC2 in the opening OP11 penetrating the insulating films 12 to 15 and the second light shielding layer BM2.
  • the drain electrode DE2 is in contact with the second semiconductor layer SC2 at the opening OP12 penetrating the insulating films 12 to 15 and the second light shielding layer BM2.
  • the source electrode SE2 and the drain electrode DE2 are located in the same layer as the second scanning line G12 shown in FIG. 4 and are made of the same material as the second scanning line G12.
  • the conductive layers CL1 and CL2 are provided on the insulating film 18 and covered with the insulating film 19.
  • the conductive layer CL1 is in contact with the source electrode SE2 in the opening OP13 penetrating the insulating films 16 to 18.
  • the conductive layer CL2 is in contact with the drain electrode DE2 in the opening OP14 penetrating the insulating films 16 to 18.
  • the conductive layers CL1 and CL2 are located in the same layer as the signal line S1 shown in FIG. 4 and are made of the same material as the signal line S1.
  • the second common electrode CE2 is in contact with the first common electrode CE1 at the opening OP15 penetrating the insulating films 20 and 21. As a result, the first common electrode CE1 and the second common electrode CE2 are electrically connected to each other.
  • the first substrate SUB1 includes the pixel electrode PE and the color filter layer CF. Therefore, it is possible to suppress the displacement between the pixel electrode PE and the color filter layer CF due to the displacement when the first substrate SUB1 and the second substrate SUB2 are bonded together.
  • the pixel electrode is provided on the first substrate and the color filter layer is provided on the second substrate, even when a deviation of only a few ⁇ m occurs when the first substrate and the second substrate are attached to each other.
  • there is a possibility that color mixture or color misregistration may occur, and the margin for misregistration is becoming smaller.
  • even if the first substrate SUB1 and the second substrate SUB2 are attached with a deviation larger than the pixel pitch it is possible to suppress color mixing and color deviation. Therefore, it is possible to suppress the deterioration of display quality.
  • the color filter layer CF is provided between the insulating substrate 10 and the first switching element SW1 in the display area DA. That is, the color filter layer CF is provided below the first switching element SW and the pixel electrode PE. Therefore, it is not necessary to form an opening (contact hole) penetrating the color filter layer CF.
  • the openings are formed in the color filter layer CF, the processing accuracy is different between the color filters of different colors, and the sizes of the openings are likely to vary. Further, since the color filter layer CF is an organic insulating film, the size of the opening tends to increase.
  • the ratio of the opening occupied in one pixel is large, which may lead to a reduction in the area contributing to display.
  • the color filter layer CF since the color filter layer CF has no opening, it is possible to suppress a reduction in the area contributing to display.
  • the metal wiring M1 closer to the liquid crystal layer LC than the signal line S1 is provided immediately above the boundary between the adjacent color filters. Therefore, when viewed from an oblique direction, the light transmitted through the adjacent sub-pixels is blocked by the metal wiring M1, and color mixing can be suppressed. In addition, since the metal wiring M1 is in contact with the first common electrode CE1, the resistance of the first common electrode CE1 and the second common electrode CE2 electrically connected to each other can be reduced.
  • FIG. 8 is a sectional view showing a modified example of the display panel PNL.
  • FIG. 8 corresponds to a cross-sectional view of the display panel PNL taken along the line EF in the sub-pixels SP(R) and SP(G) shown in FIG.
  • the modification shown in FIG. 8 is different from the structure shown in FIG. 6 in that the first light shielding layer BM1 is omitted and the metal wirings M1 to M3 are in contact with the second common electrode CE2. .. Since the first light shielding layer BM1 is omitted, the insulating film 14 covers the entire color filter layer. That is, the insulating film 14 directly covers not only the pixel electrodes PE11 to PE13 of the color filters CFR, CFG, and CFB but also the boundary between the adjacent color filters.
  • the signal line S1 and the pixel electrode PE11 are electrically connected to the first semiconductor layer SC11, as shown in FIG.
  • the signal line S2 and the pixel electrode PE12 are similarly connected to the first semiconductor layer SC12, and the signal line S3 and the pixel electrode PE13 are also connected to the first semiconductor layer SC13.
  • the metal wirings M1 to M3 are provided directly above the signal lines S1 to S3, respectively, and are in contact with the second common electrode CE2. In the illustrated example, the metal wirings M1 to M3 are provided between the second common electrode CE2 and the alignment film AL1, but may be provided between the insulating film 21 and the second common electrode CE2.
  • FIG. 9 is a cross-sectional view showing the second switching element SW2 in the modified example.
  • the second switching element SW2 of the modified example shown in FIG. 9 is different from the second switching element SW2 shown in FIG. 7 in that the second light shielding layer BM2 between the insulating film 13 and the insulating film 14 is omitted,
  • the difference is that a metal layer ML that blocks light traveling to the second switching element SW2 is provided instead of the two light blocking layer BM2.
  • the insulating film 14 is in contact with the insulating film 13.
  • the metal layer ML is located in the same layer as the metal wirings M1 to M3 shown in FIG. 8 and is made of the same material as the metal wirings M1 to M3.
  • the metal layer ML is provided between the second common electrode CE2 and the alignment film AL1 and is in contact with the second common electrode CE2. Also in such a modified example, the same effect as described above can be obtained. In addition, since the first light-shielding layer BM1 wider than the signal line and the metal wiring is omitted, the area contributing to the display per pixel can be increased.
  • FIG. 10 is a cross-sectional view showing another peripheral area SA in the modified example.
  • the modification shown in FIG. 10 is different from the modification shown in FIG. 9 in that a light shielding layer 31 is provided on the second substrate SUB2 instead of the metal layer ML.
  • the light shielding layer 31 is provided between the insulating substrate 30 and the alignment film AL2.
  • the light-shielding layer 31 is provided over almost the entire peripheral area SA and shields light traveling toward the second switching element SW2. Also in such a modified example, the same effect as described above can be obtained.
  • DSP Display device PNL... Display panel DA... Display area SA... Peripheral area LC... Liquid crystal layer BM... Light-shielding layer PE... Pixel electrode CE... Common electrode SW1... First switching element SC1... First semiconductor layer SW2... Second switching element SC2... Second semiconductor layer CF... Color filter layer CFR... Red color filter CFG... Green color filter CFB... Blue color filter G... Scan line S... Signal line M... Metal wiring G11... First scan line G12... Second scan line G13... 3rd scanning line CE1... 1st common electrode CE2... 2nd common electrode BM1... 1st light-shielding layer BM2... 2nd light-shielding layer

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Abstract

Le but de la présente invention est de fournir un dispositif d'affichage dans lequel une réduction de qualité d'affichage peut être supprimée.　Le dispositif d'affichage du présent mode de réalisation comprend un substrat isolant, un premier film isolant inorganique, un second film isolant inorganique, une couche de filtre coloré qui est disposée entre le premier et le second film isolant inorganique, un premier élément de commutation qui est disposé dans une région d'affichage dans laquelle une image est affichée, une électrode de pixel qui est disposée sur la couche de filtre de couleur et est électriquement connectée au premier élément de commutation, et un second élément de commutation qui est disposé dans une région environnante autour de la région d'affichage, le premier élément de commutation comprenant une première couche semi-conductrice comprenant un semi-conducteur à oxyde, le second élément de commutation comprenant une seconde couche semi-conductrice comprenant un semi-conducteur de silicium polycristallin. La première couche semi-conductrice est disposée entre la couche de filtre coloré et le second film isolant inorganique et la seconde couche semi-conductrice est disposée entre le substrat isolant et le premier film isolant inorganique.
PCT/JP2019/048125 2019-01-08 2019-12-09 Dispositif d'affichage WO2020144998A1 (fr)

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JP2019001267A JP2020112600A (ja) 2019-01-08 2019-01-08 表示装置
JP2019-001267 2019-01-08

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016006551A (ja) * 2015-10-12 2016-01-14 株式会社半導体エネルギー研究所 液晶表示装置
JP2017111328A (ja) * 2015-12-17 2017-06-22 株式会社ジャパンディスプレイ 液晶表示装置
US20170219877A1 (en) * 2016-02-03 2017-08-03 Samsung Display Co., Ltd. Liquid crystal display device
JP2018066847A (ja) * 2016-10-19 2018-04-26 株式会社ジャパンディスプレイ 表示装置及び表示装置の製造方法
JP2018072838A (ja) * 2016-10-31 2018-05-10 エルジー ディスプレイ カンパニー リミテッド カラーフィルタ層を備えた平板表示装置用薄膜トランジスタ基板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016006551A (ja) * 2015-10-12 2016-01-14 株式会社半導体エネルギー研究所 液晶表示装置
JP2017111328A (ja) * 2015-12-17 2017-06-22 株式会社ジャパンディスプレイ 液晶表示装置
US20170219877A1 (en) * 2016-02-03 2017-08-03 Samsung Display Co., Ltd. Liquid crystal display device
JP2018066847A (ja) * 2016-10-19 2018-04-26 株式会社ジャパンディスプレイ 表示装置及び表示装置の製造方法
JP2018072838A (ja) * 2016-10-31 2018-05-10 エルジー ディスプレイ カンパニー リミテッド カラーフィルタ層を備えた平板表示装置用薄膜トランジスタ基板

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