WO2020140489A1 - 像素电路及其驱动方法以及显示面板 - Google Patents

像素电路及其驱动方法以及显示面板 Download PDF

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Publication number
WO2020140489A1
WO2020140489A1 PCT/CN2019/107530 CN2019107530W WO2020140489A1 WO 2020140489 A1 WO2020140489 A1 WO 2020140489A1 CN 2019107530 W CN2019107530 W CN 2019107530W WO 2020140489 A1 WO2020140489 A1 WO 2020140489A1
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Prior art keywords
transistor
electrically connected
circuit
signal
pole
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PCT/CN2019/107530
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English (en)
French (fr)
Inventor
黄应龙
杨炳伟
高文宝
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京东方科技集团股份有限公司
绵阳京东方光电科技有限公司
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Priority to US16/649,283 priority Critical patent/US11127347B2/en
Publication of WO2020140489A1 publication Critical patent/WO2020140489A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects

Definitions

  • the embodiments of the present disclosure relate to the field of display technology, and in particular, to a pixel circuit, a driving method thereof, and a display panel.
  • the embodiments of the present disclosure provide a pixel circuit, a driving method thereof, and a display panel.
  • a pixel circuit includes: a light-emitting element; a driving sub-circuit configured to generate a current for causing the light-emitting element to emit light; a first light-emitting control sub-circuit and a second light-emitting control sub-circuit, the first light-emitting control sub-circuit is electrically connected To the driving sub-circuit and electrically connected to the first node with the driving sub-circuit; the second light-emitting control sub-circuit is electrically connected between the driving sub-circuit and the first end of the light-emitting element, and Electrically connected to the driving sub-circuit at a second node, the first lighting control sub-circuit and the second lighting control sub-circuit are configured to receive a first control signal and under the control of the first control signal , The current for making the light-emitting element emit light is supplied to the first end of the light-emitting element; a drive control sub-
  • the driving sub-circuit includes a driving transistor, a first transistor, and a storage capacitor.
  • the gate of the driving transistor is electrically connected to the third node, the first pole is electrically connected to the first node, and the second pole is electrically connected to the second node; the gate of the first transistor is electrically connected to receive the third control Signal, the first pole is electrically connected to the third node, the second pole is electrically connected to the second node; and the first pole of the storage capacitor is electrically connected to receive a second voltage signal, and the second pole is electrically connected to the first node Three nodes.
  • the reset sub-circuit includes a second transistor, a third transistor, and a fourth transistor.
  • the gate of the second transistor is electrically connected to receive the first reset signal
  • the first pole is electrically connected to receive the first voltage signal
  • the second pole is electrically connected to the third node
  • the gate of the third transistor The electrical connection is to receive the second reset signal
  • the first pole is electrically connected to receive the first voltage signal
  • the second pole is electrically connected to the first end of the light emitting unit
  • the gate of the fourth transistor is electrically connected to Receiving the first reset signal
  • the first pole is electrically connected to receive the first voltage signal
  • the second pole is electrically connected to the second node.
  • the reset sub-circuit includes a second transistor and a third transistor, wherein the gate of the second transistor is electrically connected to receive the first reset signal, and the first electrode is electrically connected to receive the The first voltage signal, the second electrode is electrically connected to the second node, the gate of the third transistor is electrically connected to receive the second reset signal, and the first electrode is electrically connected to receive the first voltage signal, the first The two electrodes are electrically connected to the first end of the light emitting element.
  • the first emission control sub-circuit includes a fifth transistor
  • the second emission control sub-circuit includes a sixth transistor.
  • the gate of the fifth transistor is electrically connected to receive the first control signal, the first pole is electrically connected to receive the second voltage signal, and the second pole is electrically connected to the first node;
  • the gate is electrically connected to receive the first control signal, the first pole is electrically connected to the second node, and the second pole is electrically connected to the first end of the light emitting element.
  • the drive control sub-circuit includes a seventh transistor.
  • the gate of the seventh transistor is electrically connected to receive the second control signal, the first pole is electrically connected to receive the data signal, and the second pole is electrically connected to the first node.
  • the reset sub-circuit uses the first voltage signal to charge the voltage of the first node to the sum of the threshold voltage corresponding to the driving sub-circuit and the voltage of the first voltage signal .
  • the first reset signal is the same as the second reset signal.
  • the second reset signal is the same as the first reset signal delayed by half a clock cycle.
  • a display panel includes: a plurality of scanning lines; a plurality of data lines, which are arranged vertically and horizontally with the plurality of scanning lines; and a plurality of pixel units, which are arranged at the intersection of each data line and each scanning line in the form of a matrix And electrically connected to the corresponding data line and scan line, each pixel unit includes the pixel circuit according to any one of the above embodiments.
  • the data signal received by the pixel circuit is provided by the corresponding data line of the pixel unit, and the second control signal received by the pixel circuit is provided by the corresponding scan line of the pixel unit.
  • the display panel further includes a plurality of light-emitting control lines.
  • the plurality of light emission control lines are arranged in parallel with the plurality of scan lines or the plurality of data lines, and are electrically connected to the same pixel unit respectively with the plurality of scan lines or the plurality of data lines.
  • the first control signal and the third control signal received by the pixel circuit are provided by corresponding light emission control lines of the pixel unit.
  • the first reset signal and the second reset signal received by the pixel circuit are provided by the previous scan line of the corresponding scan line of the pixel unit in the scan order.
  • a method of driving the pixel circuit includes: during a first period, providing a first control signal, a second control signal, and a third control signal having a first level, and providing a first reset signal and a second reset signal having a second level; In the second period, the first control signal, the first reset signal, and the second reset signal having the first level are provided, the second control signal and the third control signal having the second level are provided, or the first level is provided.
  • the first control signal, the third control signal, the first reset signal and the second reset signal provide a second control signal with a second level; in the third period, provide a second control signal with a first level,
  • the third control signal, the first reset signal and the second reset signal provide the first control signal with the second level, or provide the second control signal with the first level, the first reset signal and the second reset signal,
  • the first control signal and the third control signal having the second level are provided.
  • the first voltage signal is used to charge the voltage of the first node to the sum of the threshold voltage corresponding to the driving sub-circuit and the voltage of the first voltage signal.
  • a display panel including a plurality of pixel units, at least one pixel unit of the plurality of pixel units including the pixel circuit according to the above embodiment.
  • Each of the at least one pixel unit includes: a substrate; a first transistor, a third transistor, a fourth transistor, and a sixth transistor, wherein each transistor includes an active layer, including a first electrode region and a second electrode region, And a channel region between the first electrode region and the second electrode region, a first insulating layer covering the active layer, the gate layer, and provided in the first insulating layer electrically insulated from the active layer On an insulating layer, and a second insulating layer covering the gate layer and the first insulating layer; a shield connection layer including a first shield line and a second shield line, the first shield line
  • the second electrode region of the three transistors is electrically connected to the second electrode region of the sixth transistor, and the second shield line electrically connects the second electrode region of the fourth transistor and the first
  • the third transistor has a first through hole penetrating the first insulating layer and the second insulating layer of the third transistor to expose a part of the second electrode region of the third transistor
  • the sixth transistor has a second through hole and a third through hole penetrating the first insulating layer and the second insulating layer of the sixth transistor to respectively expose the first electrode region of the sixth transistor A part and a part of the second-stage region of the sixth transistor
  • the fourth transistor has a fourth through hole penetrating the first insulating layer and the second insulating layer of the fourth transistor to expose the first A part of the second pole region of the four transistors, wherein the first shield line connects the second pole region of the third transistor with the sixth transistor via the first through hole and the third through hole
  • the second electrode region is electrically connected
  • the second shield line electrically connects the second electrode region of the fourth transistor and the first electrode region of the sixth transistor via the second through hole and the fourth through hole connection.
  • FIG. 1 shows a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 2 shows an example structure of the pixel circuit of FIG. 1.
  • FIG. 3A shows a signal timing diagram of the pixel circuit of FIG. 2.
  • 3B-3D are schematic diagrams illustrating the principle of each period of the pixel circuit of FIG. 2.
  • FIG. 4 shows another example structure of the pixel circuit of FIG. 1.
  • FIG. 5A shows a signal timing diagram of the pixel circuit of FIG. 4.
  • 5B-5D are schematic diagrams illustrating the principle of each period of the pixel circuit of FIG. 4.
  • FIG. 6 shows a schematic block diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 7 shows a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 8 shows a schematic diagram of an example structure of a transistor in a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 9 shows a schematic diagram of an example layout of each transistor on the display panel in the pixel circuit of FIG. 2.
  • FIG. 10 shows a schematic diagram of an example layout with a first shield line and a second shield line.
  • FIG. 11 shows a structural diagram including the electrical connection of the shield connection layer and the transistor.
  • the term “electrically connected” may refer to the direct electrical connection between two components, or may refer to the electrical connection between two components via one or more other components.
  • the two components may be electrically connected or coupled through wired or wireless means.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other devices with the same characteristics. According to the function in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the thin film transistor used here are symmetrical, the source and drain can be interchanged. In the embodiment of the present disclosure, one of the source electrode and the drain electrode is called a first electrode, and the other of the source electrode and the drain electrode is called a second electrode. In the following example, the case where the driving transistor is a P-type thin film transistor is described, and other transistors have the same or different types as the driving transistor according to the circuit design.
  • the driving transistor may also be shown as an N-type thin film transistor.
  • the technology of the present disclosure can also be implemented by changing the types of other transistors accordingly and inverting the drive signals and level signals (and/or performing other additional adaptive modifications) Program.
  • first level and “second level” are only used to distinguish that the amplitudes of the two levels are different.
  • the "first level” may be a high level
  • the “second level” may be a low level.
  • first level is exemplified as a high level
  • second level is exemplified as a low level.
  • FIG. 1 shows a schematic block diagram of a pixel circuit 100 according to an embodiment of the present disclosure.
  • the pixel circuit 100 may include a light-emitting element 110, a driving sub-circuit 120, a first light-emitting control sub-circuit 130, a second light-emitting control sub-circuit 140, a drive control sub-circuit 150 and a reset sub-circuit 160.
  • the light emitting element 110 may be any light emitting element driven by current, for example, an OLED or AMOLED light emitting element.
  • the light emitting element 110 includes a first end and a second end, the first end is electrically connected to the second light emission control sub-circuit 140, and the second end is electrically connected to the fixed voltage terminal ELVSS.
  • the first end is the anode of the light-emitting element 110 and the second end is the cathode of the light-emitting element 110.
  • the driver sub-circuit 120 generates a current for causing the light-emitting element 110 to emit light.
  • the first light emission control sub-circuit 130 is electrically connected between the second voltage line and the driving sub-circuit 120, and is electrically connected to the first node N1 with the driving sub-circuit 120.
  • the first light emission control sub-circuit 130 is configured to receive the first control signal Con1, and receive the second voltage V2 from the second voltage line under the control of the first control signal Con1, and apply the second voltage V2 to the driving sub-circuit 120.
  • the second voltage V2 may be the power supply voltage ELVDD.
  • ELVDD is higher than the first level (ie, high level).
  • the first control signal Con1 is exemplified as the light emission control signal.
  • the second light emission control sub-circuit 140 is electrically connected between the drive sub-circuit 120 and the first end of the light-emitting element 110, and is electrically connected to the second node N2 with the drive sub-circuit 120.
  • the second light-emission control sub-circuit 140 is configured to receive the first control signal Con1, and under the control of the first control signal Con1, supply the current generated by the drive sub-circuit 120 for causing the light-emitting element 110 to emit light to the first light-emitting element 110 One end.
  • the driving control sub-circuit 150 is electrically connected between the data voltage line and the driving sub-circuit 120, and is configured to receive the second control signal Con2. Under the control of the second control signal Con2, the driving control sub-circuit 150 will The data signal Data is supplied to the driving sub-circuit 120.
  • the second control signal Con2 is exemplified as the gate driving signal.
  • the drive control sub-circuit 150 and the first light emission control sub-circuit 130 are electrically connected to the drive sub-circuit 120 through the same first node N1.
  • the reset sub-circuit 160 is electrically connected between the first voltage line and the driving sub-circuit 120, and is configured to receive the first reset signal Reset1 and the second reset signal reset2, and the reset sub-circuit 160 is connected between the first reset signal Reset1 and the second reset Under the control of the signal Reset2, the first voltage V1 from the first voltage line is used to reset the driving sub-circuit 120, the first end of the light emitting element 110, and the second node N2.
  • the first voltage V1 may have a second level.
  • the first reset signal Reset1 is, for example, a gate driving signal for the pixel unit of the previous row in the scanning order.
  • the first reset signal Reset1 is the same as the second reset signal Reset2.
  • the second reset signal Reset2 is the same as the first reset signal Reset1 delayed by half a clock cycle, that is, the second reset signal Reset2 lags behind the first reset signal Reset1 by half a clock cycle.
  • the clock period corresponds to the period of the clock signal in the gate driving circuit for driving the pixel circuit.
  • the gate driving circuit provides a gate driving signal, for example, the second control signal Con2 in the embodiment is exemplified as the gate driving signal.
  • the second sub-node N2 is reset together with the driving sub-circuit 120 by using the reset sub-circuit 160, so that the driving sub-circuit 120 has a fixed initial state before writing the data signal Data, and the improvement of short-term afterimage is achieved purpose.
  • FIG. 2 shows an example structure of the pixel circuit 100 of FIG. 1.
  • the driving sub-circuit 120 includes a driving transistor Md, a first transistor M1 and a storage capacitor Cst.
  • the gate of the driving transistor Md is electrically connected to the third node N3, the first electrode and the first emission control sub-circuit 130 are electrically connected to the first node N1, and the second electrode and the second emission control sub-circuit 140 are electrically connected to the second node N2 .
  • the first pole of the driving transistor Md is the source and the second pole is the drain.
  • the gate of the first transistor M1 is electrically connected to receive the third control signal Con3, the first pole is electrically connected to the third node N3, and the second pole is electrically connected to the second node N2.
  • the first pole of the storage capacitor Cst is electrically connected to the second voltage line to receive the second voltage V2, and the second pole is electrically connected to the third node N3.
  • the first transistor M1 and the driving transistor Md may be P-type transistors or N-type transistors. In the present exemplary embodiment, the description is made with the driving transistor Md as a P-type transistor. In the present exemplary embodiment, the first transistor M1 is exemplarily a P-type transistor.
  • the reset sub-circuit 160 includes a second transistor M2, a third transistor M3, and a fourth transistor M4.
  • the gate of the second transistor M2 is electrically connected to receive the first reset signal Reset1, the first pole is electrically connected to the first voltage line to receive the first voltage V1, and the second pole is electrically connected to the third node N3.
  • the gate of the third transistor M3 is electrically connected to receive the second reset signal Reset2, the first pole is electrically connected to the first voltage line to receive the first voltage V1, and the second pole is electrically connected to the first end of the light emitting element 110.
  • the gate of the fourth transistor M4 is electrically connected to receive the first reset signal Reset1, the first pole is electrically connected to the first voltage line to receive the first voltage V1, and the second pole is electrically connected to the second node N2.
  • the second transistor M2, the third transistor M3, and the fourth transistor M4 may be P-type transistors or N-type transistors.
  • the second transistor M2, the third transistor M3, and the fourth transistor M4 are exemplified as P-type transistors.
  • the first light emission control sub-circuit 130 includes a fifth transistor M5, and the second light emission control sub-circuit 140 includes a sixth transistor M6.
  • the gate of the fifth transistor M5 is electrically connected to receive the first control signal Con1
  • the first pole is electrically connected to the second voltage line to receive the second voltage V2
  • the second pole is electrically connected to the first node N1.
  • the gate of the sixth transistor M6 is electrically connected to receive the first control signal Con1, the first pole is electrically connected to the second node N2, and the second pole is electrically connected to the first end of the light emitting element 110,
  • the fifth transistor M5 and the sixth transistor M6 may be P-type transistors or N-type transistors.
  • the fifth transistor M5 and the sixth transistor M6 are exemplified as P-type transistors.
  • the drive control sub-circuit 150 includes a seventh transistor M7.
  • the gate of the seventh transistor M7 is electrically connected to receive the second control signal Con2, the first pole is electrically connected to the data voltage line to receive the data signal Data, and the second pole is electrically connected to the first node N1.
  • the seventh transistor may be a P-type transistor or an N-type transistor.
  • the seventh transistor M7 is exemplified as a P-type transistor.
  • FIG. 3A shows a signal timing diagram of the pixel circuit 100 of FIG. 2.
  • a first control signal Con1 having a first level (ie, a high level), a second control signal Con2, and a third control signal Con3 are provided, and a second power supply is provided.
  • the second reset signal Reset2 is the same as the first reset signal Reset1.
  • the second reset signal Reset2 is used to control the resetting of the first end of the light emitting element 110, and the reset will not be performed on the embodiments of the present disclosure as long as it occurs before the light emitting period (ie, the third period T3)
  • the residual image elimination and the luminescence effect have a substantial impact. Therefore, those skilled in the art can understand that the embodiment of the present disclosure can also be implemented in the case where the second reset signal Reset2 lags the first reset signal Reset1 by half a clock cycle.
  • the fifth transistor M5 and the sixth transistor M6 are turned off.
  • the seventh transistor M7 is turned off.
  • the first transistor M1 is turned off.
  • the second transistor M2 and the fourth transistor M4 are turned on.
  • the third transistor M3 is turned on.
  • the schematic diagram of the principle of the pixel circuit 100 at this time is shown in FIG. 3B. It should be pointed out that the transistors turned off in this period are marked with diagonal crosses “ ⁇ ” in FIG. 3B.
  • the driving transistor Md when the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned on, the low-level first voltage V1 is applied to the third node N3, the second node N2, and the light emitting element 110 At the first end of the drive, so that the gate of the driving transistor Md becomes the low level V1.
  • the driving transistor Md is in an off-bias (off-bias) state, and Vgs is a fixed value -Vth.
  • the voltage of the second node N2 stabilizes at V1.
  • the first end (for example, anode) of the light-emitting element 110 is also reset to the low level V1.
  • both the second electrode of the driving transistor Md and the anode of the light emitting element 110 are reset to the low level V1. Therefore, the first period T1 is also referred to as a "reset period”.
  • the first control signal Con1 having the first level (ie high level), the first reset signal Reset1 and the first reset signal Reset2 are provided, and the second control level (ie low level) is provided ) Of the second control signal Con2 and the third control signal Con3.
  • the fifth transistor M5 and the sixth transistor M6 are turned off.
  • the seventh transistor M7 is turned on.
  • the first transistor M1 is turned on.
  • the second transistor M2 and the fourth transistor M4 are turned off.
  • the third transistor M3 is turned off.
  • the schematic diagram of the principle of the pixel circuit 100 at this time is shown in FIG. 3C. It should be noted that the transistor in FIG. 3C that turns off in this period is marked with an oblique cross “ ⁇ ”.
  • the high-level data signal Data (voltage Vdata) is applied to the first node N1 so that the voltage of the first node N1 is from V1 at the end of the reset period T1 +Vth starts to rise to high level.
  • the driving transistor Md changes from an unbiased state to an on-bias state (on-bias), and the driving transistor Md is turned on, so that the high-level data signal Data continues to be applied to the second node N2.
  • the data signal Data at a high level continues to be applied to the third node N3 to charge the third node N3 at a low level.
  • Vdata may have a first level.
  • a second control signal Con2 a third control signal Con3, a first reset signal Reset1 and a first reset signal Reset2 having a first level (ie, a high level) are provided, and a second power supply is provided.
  • the first control signal Con1 which is flat (ie low level).
  • the fifth transistor M5 and the sixth transistor M6 are turned on.
  • the seventh transistor M7 is turned off.
  • the first transistor M1 is turned off.
  • the second transistor M2 and the fourth transistor M4 are turned off.
  • the third transistor M3 is turned off.
  • the schematic diagram of the principle of the pixel circuit 100 at this time is shown in FIG. 3D. It should be pointed out that in FIG. 3D, the transistors that are turned off in this period are marked with oblique crosses “ ⁇ ”.
  • the third node N3 cannot be charged, so that the voltage of the third node N3 is maintained at Vdata-Vth, that is, the gate of the driving transistor Md
  • the third period T3 is also referred to as a "light emission period”.
  • the expression of the drive current Id is:
  • K is the current constant associated with the driving transistor Md, and is related to the process parameters and geometric dimensions of the driving transistor Md. It can be seen from the above formula that the driving current Id for driving the light emitting element 110 to emit light is independent of the threshold voltage Vth of the driving transistor Md, thereby eliminating the phenomenon of uneven brightness of the light emitting element due to the difference in the threshold voltage Vth of the driving transistor Md . In addition, during the driving process, after the reset period ends, the second node N2 is reset so that Vgs has a fixed value, which can effectively suppress the afterimage.
  • FIG. 4 shows another example structure of the pixel circuit 100 of FIG. 1.
  • the difference between the structure of the pixel circuit shown in FIG. 4 and the structure of the pixel circuit shown in FIG. 2 is that the type and connection relationship of the first transistor M1 are different, and the reset sub-circuit does not include the fourth transistor M4.
  • the driving sub-circuit 120 includes a driving transistor Md, a first transistor M1 and a storage capacitor Cst.
  • the gate of the driving transistor Md is electrically connected to the third node N3, the first electrode and the first emission control sub-circuit 130 are electrically connected to the first node N1, and the second electrode and the second emission control sub-circuit 140 are electrically connected to the second node N2 .
  • the first pole of the driving transistor Md is the source and the second pole is the drain.
  • the gate of the first transistor M1 is electrically connected to receive the third control signal Con3, the first pole is electrically connected to the third node N3, and the second pole is electrically connected to the second node N2.
  • the first pole of the storage capacitor Cst is electrically connected to the second voltage line to receive the second voltage V2, and the second pole is electrically connected to the third node N3.
  • the first transistor M1 and the driving transistor Md may be P-type transistors or N-type transistors. In the present exemplary embodiment, the description is made with the driving transistor Md as a P-type transistor. In the present exemplary embodiment, the first transistor M1 is exemplarily an N-type transistor.
  • the reset sub-circuit 160 includes a second transistor M2 and a third transistor M3.
  • the gate of the second transistor M2 is electrically connected to receive the first reset signal Reset1, the first pole is electrically connected to the first voltage line to receive the first voltage V1, and the second pole is electrically connected to the second node N2.
  • the gate of the third transistor M3 is electrically connected to receive the second reset signal Reset2, the first pole is electrically connected to the first voltage line to receive the first voltage V1, and the second pole is electrically connected to the first end of the light emitting element 110.
  • the second transistor M2 and the third transistor M3 may be P-type transistors or N-type transistors.
  • the second transistor M2 and the third transistor M3 are exemplified as P-type transistors.
  • the first light emission control sub-circuit 130 includes a fifth transistor M5, and the second light emission control sub-circuit 140 includes a sixth transistor M6.
  • the gate of the fifth transistor M5 is electrically connected to receive the first control signal Con1
  • the first pole is electrically connected to the second voltage line to receive the second voltage V2
  • the second pole is electrically connected to the first node N1.
  • the gate of the sixth transistor M6 is electrically connected to receive the first control signal Con1, the first pole is electrically connected to the second node N2, and the second pole is electrically connected to the first end of the light emitting element 110,
  • the fifth transistor M5 and the sixth transistor M6 may be P-type transistors or N-type transistors.
  • the fifth transistor M5 and the sixth transistor M6 are exemplified as P-type transistors.
  • the drive control sub-circuit 150 includes a seventh transistor M7.
  • the gate of the seventh transistor M7 is electrically connected to receive the second control signal Con2, the first pole is electrically connected to the data voltage line to receive the data signal Data, and the second pole is electrically connected to the first node N1.
  • the seventh transistor M7 may be a P-type transistor or an N-type transistor.
  • the seventh transistor M7 is exemplified as a P-type transistor.
  • FIG. 5A shows a signal timing diagram of the pixel circuit 100 of FIG. 4.
  • a first control signal Con1 having a first level (ie, a high level), a second control signal Con2, and a third control signal Con3 are provided, and a second control signal Con3 is provided.
  • the second reset signal Reset2 is the same as the first reset signal Reset1.
  • the second reset signal Reset2 is used to control the resetting of the first end of the light emitting element 110, and the reset will not be performed on the embodiments of the present disclosure as long as it occurs before the light emitting period (ie, the third period T3)
  • the residual image elimination and the luminescence effect have a substantial impact. Therefore, those skilled in the art can understand that the embodiment of the present disclosure can also be implemented in the case where the second reset signal Reset2 lags the first reset signal Reset1 by half a clock cycle.
  • the fifth transistor M5 and the sixth transistor M6 are turned off.
  • the first transistor M1 is turned on.
  • the seventh transistor M7 is turned off.
  • the second transistor M2 is turned on.
  • the third transistor M3 is turned on.
  • the schematic diagram of the principle of the pixel circuit 100 at this time is shown in FIG. 5B. It should be pointed out that the transistors turned off in this period in FIG. 5B are marked with diagonal crosses " ⁇ ".
  • the driving transistor Md when the first transistor M1, the second transistor M2, and the third transistor M3 are turned on, the low-level first voltage V1 is applied to the third node N3, the second node N2, and the light emitting element 110 At the first end of the drive, so that the gate of the driving transistor Md becomes the low level V1.
  • the driving transistor Md is in an off-bias (off-bias) state, and Vgs is a fixed value -Vth.
  • the voltage of the second node N2 stabilizes at V1.
  • the first end (for example, anode) of the light-emitting element 110 is also reset to the low level V1.
  • both the second electrode of the driving transistor Md and the anode of the light emitting element 110 are reset to the low level V1. Therefore, the first period T1 is also referred to as a "reset period”.
  • the first control signal Con1, the third control signal Con3, the first reset signal Reset1, and the first reset signal Reset2 having the first level (ie, high level) are provided, and the second The second control signal Con2 is flat (ie low level).
  • the high-level data signal Data (voltage Vdata) is applied to the first node N1 so that the voltage of the first node N1 is from V1 at the end of the reset period T1 +Vth starts to rise to high level.
  • the driving transistor Md changes from an unbiased state to an on-bias state (on-bias), and the driving transistor Md is turned on, so that the high-level data signal Data continues to be applied to the second node N2.
  • the data signal Data at a high level continues to be applied to the third node N3 to charge the third node N3 at a low level.
  • Vdata may have a first level.
  • a second control signal Con2 a first reset signal Reset1 and a first reset signal Reset2 having a first level (ie high level) are provided, and a second level (ie low level) is provided ) Of the first control signal Con1 and the third control signal Con3.
  • the fifth transistor M5 and the sixth transistor M6 are turned on.
  • the seventh transistor M7 is turned off.
  • the first transistor M1 is turned off.
  • the second transistor M2 is turned off.
  • the third transistor M3 is turned off.
  • the schematic diagram of the principle of the pixel circuit 100 at this time is shown in FIG. 5D. It should be pointed out that in FIG. 5D, the transistors that are turned off in this period are marked with diagonal crosses " ⁇ ".
  • the third period T3 is also referred to as a "light emission period”.
  • the expression of the driving current Id is:
  • K is the current constant associated with the driving transistor Md, and is related to the process parameters and geometric dimensions of the driving transistor Md. It can be seen from the above formula that the driving current Id for driving the light emitting element 110 to emit light is independent of the threshold voltage Vth of the driving transistor Md, thereby eliminating the phenomenon of uneven brightness of the light emitting element due to the difference in the threshold voltage Vth of the driving transistor Md . In addition, during the driving process, after the reset period ends, the second node N2 is reset so that Vgs has a fixed value, which can effectively suppress the afterimage.
  • FIG. 6 shows a schematic block diagram of a display panel 600 according to an embodiment of the present disclosure.
  • the display panel 600 may include a plurality of scanning lines SL, a plurality of data lines DL, and a plurality of pixel units 610, the plurality of data lines DL and the plurality of scanning signal lines SL are arranged in a horizontal and vertical cross, and the plurality of pixel units 610 It is provided in the form of a matrix at the intersection of each scanning signal line and each data line, and is electrically connected to the corresponding data line DL and scanning line SL.
  • Each of the plurality of pixel units 610 is provided with a pixel circuit according to an embodiment of the present disclosure, for example, the pixel circuit 100 shown in FIGS. 1, 2 or 4.
  • the data voltage line electrically connected to the pixel circuit 100 is served by the corresponding data line DL of the pixel unit 610, and the second control signal Con2 received by the pixel circuit 100 is provided by the corresponding scan line SL of the pixel unit 610.
  • the display panel 600 may further include a plurality of emission control lines (not shown in FIG. 6), the plurality of emission control lines are arranged in parallel with the plurality of scan lines SL or the plurality of data lines DL, and are in parallel with Multiple scan lines SL or multiple data lines DL are electrically connected to the same pixel unit 610,
  • the first control signal Con1 and the third control signal Con3 received by the pixel circuit 100 are provided by corresponding light emission control lines of the pixel unit 610.
  • the first reset signal Reset1 and the second reset signal Reset2 received by the pixel circuit 100 are provided by the previous scan line SL of the corresponding scan line SL of the pixel unit 610 in the scanning order.
  • FIG. 7 shows a flowchart of a driving method 700 of a pixel circuit according to an embodiment of the present disclosure.
  • the driving method 700 may be used to drive the pixel circuit 100 shown in FIGS. 1, 2 or 4.
  • step S710 in a first period, a first control signal, a second control signal, and a third control signal having a first level are provided, and a first reset signal having a second level and The second reset signal.
  • step S720 during the second period, the first control signal, the first reset signal, and the second reset signal having the first level are provided, and the second control signal and the third control signal having the second level are provided, or A first control signal, a third control signal, a first reset signal, and a second reset signal having a first level are provided, and a second control signal having a second level is provided.
  • step S730 in the third period, a second control signal having a first level, a first reset signal and a second reset signal are provided, a first control signal having a second level is provided, or a The second control signal, the first reset signal, and the second reset signal having the first level provide the first control signal and the third control signal having the second level.
  • the first level is, for example, a high level, corresponding to a P-type transistor, which can turn off the related switching transistor; for an N-type transistor, it can turn on the related switching transistor.
  • the second level is, for example, a low level, corresponding to a P-type transistor, which can turn on the related switching transistor; for an N-type transistor, it can turn off the related switching transistor.
  • a display panel including a plurality of pixel units, and at least one pixel unit of the plurality of pixel units includes the pixel circuit 100 of the embodiment shown in FIG. 2.
  • An example layout and layered structure of each transistor in the pixel circuit 100 of the embodiment shown in FIG. 2 will be described below with reference to FIGS. 8-11.
  • FIG. 8 shows a schematic diagram of an example structure of a transistor M in a pixel circuit according to an embodiment of the present disclosure.
  • the transistors in the above embodiments can be realized by the structure of the transistor M shown in FIG. 8.
  • the pixel unit includes a substrate 810 and a transistor M arranged on the substrate 810.
  • the transistor M includes an active layer 820, a first insulating layer 830, a gate layer 840, and a second insulating layer 850.
  • the active layer 820 includes a first pole region 822 and a second pole region 824, and a channel region 826 between the first pole region 822 and the second pole region 824.
  • the first insulating layer 830 covers the active layer 820.
  • the gate layer 840 is disposed on the first insulating layer 830, and the gate layer 840 is electrically insulated from the active layer 820.
  • the second insulating layer 850 covers the gate layer 840 and the first insulating layer 830.
  • FIG. 9 shows an example layout of each transistor in the pixel circuit 100 of FIG. 2 on the display panel, where each transistor has a structure as illustrated in FIG. 8.
  • FIG. 9 shows only the channel region therein for each transistor (shown by the black fill pattern, which is the same as the illustrated pattern of the channel region 826 of the transistor M shown in FIG. 8) To indicate the location of the transistor layout.
  • FIG. 9 assumes that the second reset signal Reset2 is the same as the first reset signal Reset1, the third control signal Con3 is the same as the second control signal Con2, and in order to facilitate understanding of the positional relationship between the transistors, it is omitted The structure of the storage capacitor Cst is described.
  • the first voltage line providing the first voltage V1 is shown by a semi-transparent scatter pattern in FIG. 9, and the control signal lines for providing the control signals Reset1, Con1 and Con2 are shown by the right diagonal line pattern. These controls The signal lines can be set on the same layer.
  • the second voltage line may be arranged in the same layer or in different layers from these control signal lines.
  • the second transistor M2, the third transistor M3, and the fourth transistor M4 are arranged at the upper part of the pixel unit, and one ends (for example, the first pole) of each of them is electrically connected to the first voltage line via the through hole (for example, h1). connection.
  • the first transistor M1 and the seventh transistor M7 are arranged in the middle part of the pixel unit, and the fifth transistor M5 and the sixth transistor M6 are arranged in the lower part of FIG. 9.
  • the first transistor M1 has a double gate structure.
  • FIG. 10 shows an embodiment in which the above connection is made through the first shield line L1 and the second shield line L2.
  • the first shield line L1 and the second shield line L2 are located in the shield connection layer and are shown translucently by a horizontal line pattern.
  • the first shield line L1 is electrically connected to the second electrode of the third transistor M3 and the second electrode of the sixth transistor M6 via via holes (for example, h2) at both ends thereof.
  • the second shield line L2 is electrically connected to the second electrode of the fourth transistor M4 and the first electrode of the sixth transistor M6 via via holes at both ends thereof.
  • the second shield line L2 at least partially overlaps the first transistor M1 to shield at least a part of the first transistor M1. That is, the orthographic projection of the second shield line L2 on the substrate of the display panel and the orthographic projection of the channel region of the first transistor M1 on the substrate at least partially overlap.
  • the shielded wire is made of a conductor (for example, metal), in which a parasitic capacitance is generated with the transistor when a current passes, and the parasitic capacitance has a function of stabilizing the current passing through the transistor. Therefore, the shielding of the above-mentioned shielding line to M1 can on one hand play a good shielding effect on M1, thereby avoiding the influence of temperature and light on M1, and on the other hand, can also reduce the leakage current of M1, making the light-emitting current more stable.
  • a conductor for example, metal
  • the first shield line L1 may also be configured to cover at least a part of the first transistor M1. As shown in FIG. 10, the first shield line L1 also overlaps at least partially with the channel region of the first transistor M1.
  • the third transistor M3 is located to the left of the fourth transistor M4.
  • the positions of the two are interchangeable.
  • FIG. 11 is a structural diagram showing the electrical connection of the shield connection layer and the transistor.
  • FIG. 11 is drawn on the basis of FIG. 8.
  • a shield connection layer 860 is further formed on the second insulating layer 850.
  • the shield connection layer 860 may include a first shield line L1 and a second shield line L2.
  • the shield connection layer 860 is electrically connected to the second electrode region 824 of the third transistor M3 via a through hole 870 (ie, a through hole h2) penetrating the first insulating layer 830 and the second insulating layer 850 of the third transistor M3.
  • a through hole 870 ie, a through hole h2
  • the third transistor M3 may have a first through hole penetrating the first insulating layer and the second insulating layer of the third transistor M3 to expose a part of the second electrode region of the third transistor M3;
  • the sixth transistor M6 may Second and third through holes penetrating the first and second insulating layers of the sixth transistor M6 to expose a portion of the first electrode region of the sixth transistor M6 and the second stage of the sixth transistor M6, respectively A part of the region;
  • the fourth transistor M4 may have a fourth through hole penetrating the first insulating layer and the second insulating layer of the fourth transistor M4 to expose a part of the second electrode region of the fourth transistor M4.
  • the first shield line L1 electrically connects the second electrode region of the third transistor M3 and the second electrode region of the sixth transistor M6 via the first through hole and the third through hole; the second shield line L2 passes through the second through hole and the first The four vias electrically connect the second electrode region of the fourth transistor M4 and the first electrode region of the sixth transistor M6.

Abstract

一种像素电路（100）及其驱动方法和显示面板。该像素电路（100）包括：发光元件（110）；驱动子电路（120），用于产生使发光元件（110）发光的电流；第一和第二发光控制子电路（130，140），分别被构造为在第一控制信号（Con1）的控制下，将用于使发光元件（110）发光的电流提供到发光元件（110）的第一端；驱动控制子电路（150），在第二控制信号（Con2）的控制下将数据信号（Data）提供到驱动子电路（120）；复位子电路（160），在第一复位信号（Reset1）和第二复位信号（Reset2）的控制下使用第一电压（V1）对驱动子电路(120)、发光元件（110）的第一端以及第二节点（N2）进行复位。该像素电路（100）能够抑制残像。

Description

像素电路及其驱动方法以及显示面板
本申请要求于2019年1月2日提交的、申请号为201910001300.4的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开实施例涉及显示技术领域，具体地涉及一种像素电路及其驱动方法以及显示面板。
背景技术
在OLED(有机发光二极管，Organic Light Emitting Diode)显示面板中，由于驱动晶体管的迟滞效应，会产生残像。可以通过改变栅极绝缘层的模质和厚度、多晶硅层的掺杂量以及两层之间的界面质量等方式来试图改善残像的影响，但效果并不显著。
发明内容
本公开实施例提供了一种像素电路及其驱动方法以及显示面板。
根据本公开实施例的一个方面，提供了一种像素电路。所述像素电路包括：发光元件；驱动子电路，被构造为产生用于使发光元件发光的电流；第一发光控制子电路和第二发光控制子电路，所述第一发光控制子电路电连接至所述驱动子电路，并且与所述驱动子电路电连接于第一节点；所述第二发光控制子电路电连接在所述驱动子电路与所述发光元件的第一端之间，并且与所述驱动子电路电连接于第二节点，所述第一发光控制子电路和所述第二发光控制子电路被构造为接收第一控制信号，并在所述第一控制信号的控制下，将所述用于使发光元件发光的电流提供到所述发光元件的第一端；驱动控制子电路，电连接至所述驱动子电路，被构造为接收数据信号和第二控制信号，并在所述第二控制信号的控制下，将所述数据信号提供到所述驱动子电路；以及复位子电路，电连接至所述驱动子电路，被构造为接收第一电压信号、第一复位信号和第二复位信号，并在所述第一复位信号和第二复位信号的控制下使用所述第一电压信号对所述驱动子电路、所述发光元件的第一端以及所述第二节点进行复位。
在一些实施例中，所述驱动子电路包括驱动晶体管、第一晶体管和存储电容。所述 驱动晶体管的栅极电连接第三节点，第一极电连接所述第一节点，第二极电连接所述第二节点；所述第一晶体管的栅极电连接为接收第三控制信号，第一极电连接所述第三节点，第二极电连接所述第二节点；以及所述存储电容的第一极电连接为接收第二电压信号，第二极电连接所述第三节点。
在一些实施例中，所述复位子电路包括第二晶体管、第三晶体管和第四晶体管。所述第二晶体管的栅极电连接为接收所述第一复位信号，第一极电连接为接收第一电压信号，第二极电连接所述第三节点，所述第三晶体管的栅极电连接为接收所述第二复位信号，第一极电连接为接收所述第一电压信号，第二极电连接所述发光单元的第一端，所述第四晶体管的栅极电连接为接收所述第一复位信号，第一极电连接为接收所述第一电压信号，第二极电连接所述第二节点。
在另一些实施例中，所述复位子电路包括第二晶体管和第三晶体管，其中所述第二晶体管的栅极电连接为接收所述第一复位信号，第一极电连接为接收所述第一电压信号，第二极电连接所述第二节点，所述第三晶体管的栅极电连接为接收所述第二复位信号，第一极电连接为接收所述第一电压信号，第二极电连接所述发光元件的第一端。
在一些实施例中，所述第一发光控制子电路包括第五晶体管，所述第二发光控制子电路包括第六晶体管。所述第五晶体管的栅极电连接为接收所述第一控制信号，第一极电连接为接收所述第二电压信号，第二极电连接所述第一节点；所述第六晶体管的栅极电连接为接收所述第一控制信号，第一极电连接所述第二节点，第二极电连接所述发光元件的第一端。
在一些实施例中，所述驱动控制子电路包括第七晶体管。所述第七晶体管的栅极电连接为接收所述第二控制信号，第一极电连接接收所述数据信号，第二极电连接所述第一节点。
在一些实施例中，所述复位子电路使用所述第一电压信号将所述第一节点的电压充电为与所述驱动子电路相对应的阈值电压与所述第一电压信号的电压之和。
在一些实施例中，所述第一复位信号与所述第二复位信号相同。
在另一些实施例中，所述第二复位信号与延迟半个时钟周期的第一复位信号相同。
根据本公开的另一方面，提供了一种显示面板。所述显示面板包括：多条扫描线；多条数据线，与所述多条扫描线纵横交叉设置；以及多个像素单元，以矩阵的形式设置在每个数据线和每个扫描线交叉处，并与对应的数据线和扫描线电连接，每个像素单元 包括根据上述任一实施例所述的像素电路。所述像素电路所接收的数据信号由所述像素单元的对应数据线提供，所述像素电路所接收的第二控制信号由所述像素单元的对应扫描线提供。
在一些实施例中，所述显示面板还包括多条发光控制线。所述多条发光控制线与所述多条扫描线或所述多条数据线平行地布置，并与所述多条扫描线或所述多条数据线分别电连接到相同的像素单元。所述像素电路所接收的第一控制信号和第三控制信号由所述像素单元的对应发光控制线提供。
在一些实施例中，所述像素电路所接收的第一复位信号和第二复位信号由所述像素单元的对应扫描线的按照扫描顺序的前一扫描线提供。
根据本公开实施例的又一方面，提供了一种对根据上述任一实施例的像素电路进行驱动的方法。所述方法包括：在第一时段，提供具有第一电平的第一控制信号、第二控制信号和第三控制信号，提供具有第二电平的第一复位信号和第二复位信号；在第二时段，提供具有第一电平的第一控制信号、第一复位信号和第二复位信号，提供具有第二电平的第二控制信号和第三控制信号，或者提供具有第一电平的第一控制信号、第三控制信号、第一复位信号和第二复位信号，提供具有第二电平的第二控制信号；在第三时段，提供具有第一电平的第二控制信号、第三控制信号、第一复位信号和第二复位信号，提供具有第二电平的第一控制信号，或者提供具有第一电平的第二控制信号、第一复位信号和第二复位信号，提供具有第二电平的第一控制信号和第三控制信号。
在一些实施例中，使用第一电压信号将第一节点的电压充电为与驱动子电路相对应的阈值电压与所述第一电压信号的电压之和。
根据本公开实施例的又一方面，提供了一种显示面板，包括多个像素单元，所述多个像素单元中的至少一个像素单元包括根据上述实施例的像素电路。所述至少一个像素单元中的每一个包括：基板；第一晶体管、第三晶体管、第四晶体管和第六晶体管，其中每个晶体管包括有源层，包括第一极区域和第二极区域，以及位于所述第一极区域和第二极区域之间的沟道区域，第一绝缘层，覆盖所述有源层，栅极层，与所述有源层电绝缘地设置在所述第一绝缘层上，以及第二绝缘层，覆盖所述栅极层和所述第一绝缘层；屏蔽连接层，包括第一屏蔽线和第二屏蔽线，所述第一屏蔽线将所述第三晶体管的第二极区域与所述第六晶体管的第二极区域电连接，所述第二屏蔽线将所述第四晶体管的第二极区域与所述第六晶体管的第一极区域电连接。所述第一屏蔽线和所述第二屏蔽线中 的至少一个在所述基板上的正投影与所述第一晶体管的沟道区域在所述基板上的正投影至少部分地重叠。
在一些实施例中，在所述第三晶体管中具有贯穿所述第三晶体管的第一绝缘层和第二绝缘层的第一通孔，以暴露所述第三晶体管的第二极区域的一部分，在所述第六晶体管中具有贯穿所述第六晶体管的第一绝缘层和第二绝缘层的第二通孔和第三通孔，以分别暴露所述第六晶体管的第一极区域的一部分和所述第六晶体管的第二级区域的一部分，在所述第四晶体管中具有贯穿所述第四晶体管的第一绝缘层和第二绝缘层的第四通孔，以暴露所述第四晶体管的第二极区域的一部分，其中，所述第一屏蔽线经由所述第一通孔和所述第三通孔将所述第三晶体管的第二极区域与所述第六晶体管的第二极区域电连接，所述第二屏蔽线经由所述第二通孔和所述第四通孔将所述第四晶体管的第二极区域与所述第六晶体管的第一极区域电连接。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，图中：
图1示出了根据本公开实施例的像素电路的示意方框图。
图2示出了图1的像素电路的一个示例结构。
图3A示出了图2的像素电路的信号时序图。
图3B-图3D示出了图2的像素电路的各时段原理示意图。
图4示出了图1的像素电路的另一示例结构。
图5A示出了图4的像素电路的信号时序图。
图5B-图5D示出了图4的像素电路的各时段原理示意图。
图6示出了根据本公开实施例的显示面板的示意方框图。
图7示出了根据本公开实施例的像素电路的驱动方法的流程图。
图8示出了根据本公开实施例的像素电路中的晶体管的示例结构的示意图。
图9示出了图2的像素电路中的各晶体管在显示面板上的示例布局的示意图。
图10示出了具有第一屏蔽线和第二屏蔽线的示例布局的示意图。
图11示出了包括屏蔽连接层与晶体管的电连接的结构图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而只是用于区分不同的组成部分。
此外，在本公开实施例的描述中，术语“电连接”可以是指两个组件直接电连接，也可以是指两个组件之间经由一个或多个其他组件电连接。此外，这两个组件可以通过有线或无线方式电连接或耦接。
本公开实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。根据在电路中的作用，本公开实施例使用的晶体管主要为开关晶体管。由于这里采用的薄膜晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，将源极和漏极中的一个称为第一极，将源极和漏极中的另一个称为第二极。在以下示例中以驱动晶体管为P型薄膜晶体管的情况进行描述，其他晶体管根据电路设计与驱动晶体管具有相同或不同的类型。类似地，在其他实施例中，驱动晶体管也可以被示为N型薄膜晶体管。本领域技术人员能够理解的是，通过将其他晶体管的类型相应地改变并将各驱动信号和电平信号进行反相(和/或进行其他附加的适应性修改)，同样能够实现本公开的技术方案。
此外，在本公开实施例的描述中，术语“第一电平”和“第二电平”仅用于区别两个电平的幅度不同。在一些实施例中，“第一电平”可以是高电平，“第二电平”可以是低电平。下文中，由于驱动晶体管被示例为P型薄膜晶体管，因此“第一电平”被示例 为高电平，“第二电平”被示例为低电平。
以下参考附图对本公开的实施例进行具体描述。
图1示出了根据本公开实施例的像素电路100的示意方框图。
如图1所示，像素电路100可以包括发光元件110、驱动子电路120、第一发光控制子电路130、第二发光控制子电路140、驱动控制子电路150和复位子电路160。
发光元件110可以是任何以电流驱动的发光元件，例如OLED或AMOLED发光元件。发光元件110包括第一端和第二端，第一端电连接第二发光控制子电路140，第二端电连接固定电压端ELVSS。在一些实施例中，第一端为发光元件110的阳极，第二端为发光元件110的阴极。
驱动子电路120产生用于使发光元件110发光的电流。
第一发光控制子电路130电连接在第二电压线与驱动子电路120之间，并且与驱动子电路120电连接于第一节点N1。第一发光控制子电路130被构造为接收第一控制信号Con1，并且在第一控制信号Con1的控制下从第二电压线接收第二电压V2，并将该第二电压V2施加到驱动子电路120。在一些实施例中，第二电压V2可以是电源电压ELVDD。在一些实施例中，ELVDD高于第一电平(即高电平)。在一些实施例中，第一控制信号Con1例示为发光控制信号。
第二发光控制子电路140电连接在驱动子电路120与发光元件110的第一端之间，并且与驱动子电路120电连接于第二节点N2。第二发光控制子电路140被构造为接收第一控制信号Con1，并且在第一控制信号Con1的控制下将驱动子电路120产生的用于使发光元件110发光的电流提供给发光元件110的第一端。
驱动控制子电路150电连接在数据电压线与驱动子电路120之间，并且被构造为接收第二控制信号Con2，驱动控制子电路150在第二控制信号Con2的控制下将来自数据电压线的数据信号Data提供到驱动子电路120。在一些实施例中，第二控制信号Con2例示为栅极驱动信号。
在一些实施例中，驱动控制子电路150与第一发光控制子电路130通过相同的第一节点N1与驱动子电路120电连接。
复位子电路160电连接在第一电压线与驱动子电路120之间，并且被构造为接收第一复位信号Reset1和第二复位信号reset2，复位子电路160在第一复位信号Reset1和第二复位信号Reset2的控制下使用来自第一电压线的第一电压V1对驱动子电路120、发 光元件110的第一端以及第二节点N2进行复位。在一些实施例中，第一电压V1可以具有第二电平。在一些实施例中，第一复位信号Reset1是例如用于按照扫描顺序的前一行像素单元的栅极驱动信号。
在一些实施例中，第一复位信号Reset1与第二复位信号Reset2相同。在另一些实施例中，第二复位信号Reset2与延迟半个时钟周期的第一复位信号Reset1相同，即第二复位信号Reset2比第一复位信号Reset1落后半个时钟周期。本领域技术人员应当理解的是，时钟周期对应于用于驱动像素电路的栅极驱动电路中的时钟信号的周期。栅极驱动电路提供栅极驱动信号，例如实施例中的第二控制信号Con2例示为栅极驱动信号。
在本公开的实施例中，通过使用复位子电路160将第二节点N2与驱动子电路120一起复位，使得驱动子电路120在写入数据信号Data之前具有固定的初始状态，达到改善短期残像的目的。
图2示出了图1的像素电路100的一个示例结构。
如图2所示，驱动子电路120包括驱动晶体管Md、第一晶体管M1和存储电容Cst。
驱动晶体管Md的栅极电连接第三节点N3，第一极与第一发光控制子电路130电连接于第一节点N1，第二极与第二发光控制子电路140电连接于第二节点N2。在一些实施例中，驱动晶体管Md的第一极为源极，第二极为漏极。
第一晶体管M1的栅极电连接为接收第三控制信号Con3，第一极电连接第三节点N3，第二极电连接第二节点N2。
存储电容Cst的第一极电连接第二电压线以接收第二电压V2，第二极电连接第三节点N3。
第一晶体管M1与驱动晶体管Md可以是P型晶体管或N型晶体管。在本示例性实施例中，以驱动晶体管Md为P型晶体管进行描述。在本示例性实施例中，第一晶体管M1示例性地为P型晶体管。
复位子电路160包括第二晶体管M2、第三晶体管M3和第四晶体管M4。
第二晶体管M2的栅极电连接为接收第一复位信号Reset1，第一极电连接第一电压线以接收第一电压V1，第二极电连接第三节点N3。
第三晶体管M3的栅极电连接为接收第二复位信号Reset2，第一极电连接第一电压线以接收第一电压V1，第二极电连接发光元件110的第一端。
第四晶体管M4的栅极电连接为接收第一复位信号Reset1，第一极电连接第一电压 线以接收第一电压V1，第二极电连接第二节点N2。
第二晶体管M2、第三晶体管M3和第四晶体管M4可以是P型晶体管或N型晶体管。在本示例性实施例中，第二晶体管M2、第三晶体管M3和第四晶体管M4例示为P型晶体管。
第一发光控制子电路130包括第五晶体管M5，并且第二发光控制子电路140包括第六晶体管M6。
具体地，第五晶体管M5的栅极电连接为接收第一控制信号Con1，第一极电连接第二电压线以接收第二电压V2，第二极电连接第一节点N1。
第六晶体管M6的栅极电连接为接收第一控制信号Con1，第一极电连接第二节点N2，第二极电连接发光元件110的第一端，
第五晶体管M5和第六晶体管M6可以是P型晶体管或N型晶体管。在本示例性实施例中，第五晶体管M5和第六晶体管M6例示为P型晶体管。
驱动控制子电路150包括第七晶体管M7。
第七晶体管M7的栅极电连接为接收第二控制信号Con2，第一极电连接数据电压线以接收数据信号Data，第二极电连接第一节点N1。
第七晶体管可以是P型晶体管或N型晶体管。在本示例性实施例中，第七晶体管M7例示为P型晶体管。
图3A示出了图2的像素电路100的信号时序图。
例如，参见图3A，在第一时段T1期间，提供具有第一电平(即高电平)的第一控制信号Con1、第二控制信号Con2和第三控制信号Con3，并且提供具有第二电平(即低电平)的第一复位信号Reset1和第二复位信号Reset2。在图3A-3D所示的实施例中，以第二复位信号Reset2与第一复位信号Reset1相同的情况进行示例性描述。在其他的实施例中，由于第二复位信号Reset2用于控制对发光元件110的第一端进行复位，并且该复位只要在发光时段(即第三时段T3)之前发生便不会对本公开实施例的残像消除以及发光效果产生实质的影响，因此，本领域技术人员能够理解，在第二复位信号Reset2落后第一复位信号Reset1半个时钟周期的情况中，也能够实施本公开的实施例。
由此，在第一时段T1期间，在第一控制信号Con1的控制下，第五晶体管M5和第六晶体管M6关断。在第二控制信号Con2的控制下，第七晶体管M7关断。在第三控制信号Con3的控制下，第一晶体管M1关断。在第一复位信号Reset1的控制下，第二晶 体管M2和第四晶体管M4导通。在第二复位信号Reset2(在本实施例中与Reset1相同)的控制下，第三晶体管M3导通。此时像素电路100的原理示意图如图3B所示，应该指出的是，图3B中将本时段中关断的晶体管通过斜十字“×”标记。
如图3B所示，在第二晶体管M2、第三晶体管M3和第四晶体管M4导通的情况下，低电平的第一电压V1施加到第三节点N3、第二节点N2和发光元件110的第一端，从而驱动晶体管Md的栅极变为低电平V1。驱动晶体管Md导通，低电平V1经由驱动晶体管Md持续对第一节点N1充电，直到第一节点N1的电压变为Vs＝V1+Vth为止，其中Vth为Md的阈值电压。此时，驱动晶体管Md处于无偏压(off-bias)状态，Vgs为固定值-Vth。第二节点N2的电压稳定为V1。发光元件110的第一端(例如，阳极)也被复位至低电平V1。从而，驱动晶体管Md的第二极和发光元件110的阳极均被复位至低电平V1。因此，第一时段T1也被称为“复位时段”。
在第二时段T2期间，提供具有第一电平(即高电平)的第一控制信号Con1、第一复位信号Reset1和第一复位信号Reset2，并且提供具有第二电平(即低电平)的第二控制信号Con2和第三控制信号Con3。
由此，在第二时段T2期间，在第一控制信号Con1的控制下，第五晶体管M5和第六晶体管M6关断。在第二控制信号Con2的控制下，第七晶体管M7导通。在第三控制信号Con3的控制下，第一晶体管M1导通。在第一复位信号Reset1的控制下，第二晶体管M2和第四晶体管M4关断。在第二复位信号Reset2的控制下，第三晶体管M3关断。此时像素电路100的原理示意图如图3C所示，应该指出的是，图3C中将本时段关断的晶体管通过斜十字“×”标记。
如图3C所示，在第七晶体管M7导通的情况下，高电平的数据信号Data(电压Vdata)施加到第一节点N1，使得第一节点N1的电压从复位时段T1结束时的V1+Vth开始升至高电平。驱动晶体管Md从无偏压状态变为有偏压状态(on-bias)，驱动晶体管Md导通，从而高电平的数据信号Data继续施加到第二节点N2。在第一晶体管M1导通的情况下，高电平的数据信号Data继续施加到第三节点N3，对处于低电平的第三节点N3进行充电。随着第三节点N3的电压不断上升，驱动晶体管Md的栅源电压Vgs从V1-Vdata逐渐增加，直到Vgs＝-Vth为止。此时，驱动晶体管Md再次回到off-bias状态，同时停止对第三节点N3进行充电。此时，第三节点N3处(即Md的栅极)的电压为Vg＝Vgs+Vs＝Vdata-Vth。数据信号Data的电压Vdata已经写入第三节点N3。因此，此 第二时段T2也可以称为“数据电压写入时段”。在一些实施例中，Vdata可以具有第一电平。
在第三时段T3期间，提供具有第一电平(即高电平)的第二控制信号Con2、第三控制信号Con3、第一复位信号Reset1和第一复位信号Reset2，并且提供具有第二电平(即低电平)的第一控制信号Con1。
由此，在第三时段T3期间，在第一控制信号Con1的控制下，第五晶体管M5和第六晶体管M6导通。在第二控制信号Con2的控制下，第七晶体管M7关断。在第三控制信号Con3的控制下，第一晶体管M1关断。在第一复位信号Reset1的控制下，第二晶体管M2和第四晶体管M4关断。在第二复位信号Reset2的控制下，第三晶体管M3关断。此时像素电路100的原理示意图如图3D所示，应该指出的是，图3D中将本时段关断的晶体管通过斜十字“×”标记。
如图3D所示，在第五晶体管M5导通的情况下，第二电压V2(即ELVDD)施加到第一节点N1，即驱动晶体管Md的源极电压Vs＝ELVDD。此时，由于第一晶体管M1、第三晶体管和第四晶体管M4都关断，无法对第三节点N3进行充电，从而第三节点N3的电压保持为Vdata-Vth，即驱动晶体管Md的栅极电压Vg＝Vdata-Vth，从而，Vgs＝Vdata-Vth-ELVDD，其小于-Vth(ELVDD大于Vdata)，使得驱动晶体管Md导通。在第六晶体管M6导通的情况下，驱动晶体管Md产生的驱动电流Id施加到发光元件110的阳极，并驱动发光元件发光。因此，第三时段T3也被称为“发光时段”。
例如，驱动电流Id的表达式为：
I d＝K〃(Vsg-Vth) 2
＝K〃(Vth+ELVDD-Vdata-Vth) 2
＝K〃(ELVDD-Vdata) 2
其中，K为与驱动晶体管Md相关联的电流常数，与驱动晶体管Md的工艺参数和几何尺寸有关。由以上公式可知，用于驱动发光元件110进行发光的驱动电流Id与驱动晶体管Md的阈值电压Vth无关，从而可以消除由于驱动晶体管Md的阈值电压Vth存在差异而导致的发光元件亮度不均的现象。此外，在驱动的过程中，在复位时段结束后，通过对第二节点N2的复位，使得Vgs具有固定值，这能够有效地抑制残像。
图4示出了图1的像素电路100的另一示例结构。图4所示的像素电路的结构与图2所示的像素电路的结构的区别在于第一晶体管M1的类型以及连接关系不同，并且复 位子电路不包括第四晶体管M4。
具体地，如图4所示，驱动子电路120包括驱动晶体管Md、第一晶体管M1和存储电容Cst。
驱动晶体管Md的栅极电连接第三节点N3，第一极与第一发光控制子电路130电连接于第一节点N1，第二极与第二发光控制子电路140电连接于第二节点N2。在一些实施例中，驱动晶体管Md的第一极为源极，第二极为漏极。
第一晶体管M1的栅极电连接为接收第三控制信号Con3，第一极电连接第三节点N3，第二极电连接第二节点N2。
存储电容Cst的第一极电连接第二电压线以接收第二电压V2，第二极电连接第三节点N3。
第一晶体管M1与驱动晶体管Md可以是P型晶体管或N型晶体管。在本示例性实施例中，以驱动晶体管Md为P型晶体管进行描述。在本示例性实施例中，第一晶体管M1示例性地为N型晶体管。
复位子电路160包括第二晶体管M2和第三晶体管M3。
第二晶体管M2的栅极电连接为接收第一复位信号Reset1，第一极电连接第一电压线以接收第一电压V1，第二极电连接第二节点N2。
第三晶体管M3的栅极电连接为接收第二复位信号Reset2，第一极电连接第一电压线以接收第一电压V1，第二极电连接发光元件110的第一端。
第二晶体管M2和第三晶体管M3可以是P型晶体管或N型晶体管。在本示例性实施例中，第二晶体管M2、第三晶体管M3例示为P型晶体管。
第一发光控制子电路130包括第五晶体管M5，并且第二发光控制子电路140包括第六晶体管M6。
例如，第五晶体管M5的栅极电连接为接收第一控制信号Con1，第一极电连接第二电压线以接收第二电压V2，第二极电连接第一节点N1。
第六晶体管M6的栅极电连接为接收第一控制信号Con1，第一极电连接第二节点N2，第二极电连接所述发光元件110的第一端，
第五晶体管M5和第六晶体管M6可以是P型晶体管或N型晶体管。在本示例性实施例中，第五晶体管M5和第六晶体管M6例示为P型晶体管。
驱动控制子电路150包括第七晶体管M7。
第七晶体管M7的栅极电连接为接收第二控制信号Con2，第一极电连接数据电压线以接收数据信号Data，第二极电连接第一节点N1。
第七晶体管M7可以是P型晶体管或N型晶体管。在本示例性实施例中，第七晶体管M7例示为P型晶体管。
图5A示出了图4的像素电路100的信号时序图。
具体地，参见图5A，在第一时段T1期间，提供具有第一电平(即高电平)的第一控制信号Con1、第二控制信号Con2和第三控制信号Con3，并且提供具有第二电平(即低电平)的第一复位信号Reset1和第二复位信号Reset2。在图5A-5D所示的实施例中，以第二复位信号Reset2与第一复位信号Reset1相同的情况进行示例性描述。在其他的实施例中，由于第二复位信号Reset2用于控制对发光元件110的第一端进行复位，并且该复位只要在发光时段(即第三时段T3)之前发生便不会对本公开实施例的残像消除以及发光效果产生实质的影响，因此，本领域技术人员能够理解，在第二复位信号Reset2落后第一复位信号Reset1半个时钟周期的情况中，也能够实施本公开的实施例。
由此，在第一时段T1期间，在第一控制信号Con1的控制下，第五晶体管M5和第六晶体管M6关断。在第三控制信号Con3的控制下，第一晶体管M1导通。在第二控制信号Con2的控制下，第七晶体管M7关断。在第一复位信号Reset1的控制下，第二晶体管M2导通。在第二复位信号Reset2(在本实施例中与Reset1相同)的控制下，第三晶体管M3导通。此时像素电路100的原理示意图如图5B所示，应该指出的是，图5B中将本时段关断的晶体管通过斜十字“×”标记。
如图5B所示，在第一晶体管M1、第二晶体管M2和第三晶体管M3导通的情况下，低电平的第一电压V1施加到第三节点N3、第二节点N2和发光元件110的第一端，从而驱动晶体管Md的栅极变为低电平V1。驱动晶体管Md导通，低电平V1经由驱动晶体管Md持续对第一节点N1充电，直到第一节点N1的电压变为Vs＝V1+Vth为止，其中Vth为Md的阈值电压。此时，驱动晶体管Md处于无偏压(off-bias)状态，Vgs为固定值-Vth。第二节点N2的电压稳定为V1。发光元件110的第一端(例如，阳极)也被复位至低电平V1。从而，驱动晶体管Md的第二极和发光元件110的阳极均被复位至低电平V1。因此，第一时段T1也被称为“复位时段”。
在第二时段T2期间，提供具有第一电平(即高电平)的第一控制信号Con1、第三控制信号Con3、第一复位信号Reset1和第一复位信号Reset2，并且提供具有第二电平 (即低电平)的第二控制信号Con2。
由此，在第二时段T2期间，在第一控制信号Con1的控制下，第五晶体管M5和第六晶体管M6关断。在第三控制信号Con3的控制下，第一晶体管M1导通。在第二控制信号Con2的控制下，第七晶体管M7导通。在第一复位信号Reset1的控制下，第二晶体管M2关断。在第二复位信号Reset2的控制下，第三晶体管M3关断。此时像素电路100的原理示意图如图5C所示，应该指出的是，图5C中将本时段关断的晶体管通过斜十字“×”标记。
如图5C所示，在第七晶体管M7导通的情况下，高电平的数据信号Data(电压Vdata)施加到第一节点N1，使得第一节点N1的电压从复位时段T1结束时的V1+Vth开始升至高电平。驱动晶体管Md从无偏压状态变为有偏压状态(on-bias)，驱动晶体管Md导通，从而高电平的数据信号Data继续施加到第二节点N2。在第一晶体管M1导通的情况下，高电平的数据信号Data继续施加到第三节点N3，对处于低电平的第三节点N3进行充电。随着第三节点N3的电压不断上升，驱动晶体管Md的栅源电压Vgs从V1-Vdata逐渐增加，直到Vgs＝-Vth为止。此时，驱动晶体管Md再次回到off-bias状态，同时停止对第三节点N3进行充电。此时，第三节点N3处(即Md的栅极)的电压为Vg＝Vgs+Vs＝Vdata-Vth。数据信号Data的电压Vdata已经写入第三节点N3。因此，此第二时段T2也可以称为“数据电压写入时段”。在一些实施例中，Vdata可以具有第一电平。
在第三时段T3期间，提供具有第一电平(即高电平)的第二控制信号Con2、第一复位信号Reset1和第一复位信号Reset2，并且提供具有第二电平(即低电平)的第一控制信号Con1和第三控制信号Con3。
由此，在第三时段T3期间，在第一控制信号Con1的控制下，第五晶体管M5和第六晶体管M6导通。在第二控制信号Con2的控制下，第七晶体管M7关断。在第三控制信号Con3的控制下，第一晶体管M1关断。在第一复位信号Reset1的控制下，第二晶体管M2关断。在第二复位信号Reset2的控制下，第三晶体管M3关断。此时像素电路100的原理示意图如图5D所示，应该指出的是，图5D中将本时段关断的晶体管通过斜十字“×”标记。
如图5D所示，在第五晶体管M5导通的情况下，第二电压V2(即ELVDD)施加到第一节点N1，即驱动晶体管Md的源极电压Vs＝ELVDD。此时，由于第一晶体管 M1关断，无法对第三节点N3进行充电，从而第三节点N3的电压保持为Vdata-Vth，即驱动晶体管Md的栅极电压Vg＝Vdata-Vth，从而，Vgs＝Vdata-Vth-ELVDD，其小于-Vth(ELVDD大于Vdata)，使得驱动晶体管Md导通。在第六晶体管M6导通的情况下，驱动晶体管Md产生的驱动电流Id施加到发光元件110的阳极，并驱动发光元件发光。因此，第三时段T3也被称为“发光时段”。
具体地，驱动电流Id的表达式为：
I d＝K〃(Vsg-Vth) 2
＝K〃(Vth+ELVDD-Vdata-Vth) 2
＝K〃(ELVDD-Vdata) 2
其中，K为与驱动晶体管Md相关联的电流常数，与驱动晶体管Md的工艺参数和几何尺寸有关。由以上公式可知，用于驱动发光元件110进行发光的驱动电流Id与驱动晶体管Md的阈值电压Vth无关，从而可以消除由于驱动晶体管Md的阈值电压Vth存在差异而导致的发光元件亮度不均的现象。此外，在驱动的过程中，在复位时段结束后，通过对第二节点N2的复位，使得Vgs具有固定值，这能够有效地抑制残像。
图6示出了根据本公开实施例的显示面板600的示意方框图。如图6所示，显示面板600可以包括多条扫描线SL、多条数据线DL和多个像素单元610，多条数据线DL与多条扫描信号线SL纵横交叉设置，多个像素单元610以矩阵的形式设置在每个扫描信号线和每个数据线的交叉处，并且与对应的数据线DL和扫描线SL电连接。所述多个像素单元610中的每一个中设置有根据本公开实施例的像素电路，例如根据图1、图2或图4所示的像素电路100。
在一些实施例中，像素电路100所电连接的数据电压线由像素单元610的对应数据线DL充当，像素电路100所接收的第二控制信号Con2由像素单元610的对应扫描线SL提供。
在一些实施例中，显示面板600还可以包括多条发光控制线(在图6中未示出)，多条发光控制线与多条扫描线SL或多条数据线DL平行地布置，并与多条扫描线SL或多条数据线DL分别电连接到相同的像素单元610，
在一些实施例中，像素电路100所接收的第一控制信号Con1和第三控制信号Con3由像素单元610的对应发光控制线提供。
在一些实施例中，像素电路100所接收的第一复位信号Reset1和第二复位信号Reset2 由像素单元610的对应扫描线SL的按照扫描顺序的前一扫描线SL提供。
图7示出了根据本公开实施例的像素电路的驱动方法700的流程图。驱动方法700可以用于驱动根据图1、图2或图4所示的像素电路100。
如图7所示，在步骤S710中，在第一时段，提供具有第一电平的第一控制信号、第二控制信号和第三控制信号，提供具有第二电平的第一复位信号和第二复位信号。
在步骤S720中，在第二时段，提供具有第一电平的第一控制信号、第一复位信号和第二复位信号，提供具有第二电平的第二控制信号和第三控制信号，或者提供具有第一电平的第一控制信号、第三控制信号、第一复位信号和第二复位信号，提供具有第二电平的第二控制信号。
在步骤S730中，在第三时段，提供具有第一电平的第二控制信号、第三控制信号第一复位信号和第二复位信号，提供具有第二电平的第一控制信号，或者提供具有第一电平的第二控制信号、第一复位信号和第二复位信号，提供具有第二电平的第一控制信号和第三控制信号。
其中，第一电平例如是高电平，对应P型晶体管，是可以使相关开关晶体管关断的电平；对于N型晶体管，是可以使相关开关晶体管导通的电平。第二电平例如是低电平，对应P型晶体管，是可以使相关开关晶体管导通的电平；对于N型晶体管，是可以使相关开关晶体管关断的电平。
上文中结合图2和图4对方法700在不同实施例中的驱动过程进行了描述，在此不再赘述。
根据本公开的实施例，还提供了一种显示面板，其包括多个像素单元，多个像素单元中的至少一个像素单元包括如图2所示的实施例的像素电路100。以下结合图8-11对如图2所示的实施例的像素电路100中的各晶体管的示例布局和分层结构进行示例性描述。
图8示出了根据本公开实施例的像素电路中的晶体管M的示例结构的示意图。可以通过图8中所示的晶体管M的结构来实现以上实施例中的各个晶体管。
如图8所示，像素单元包括基板810以及布置在基板810上的晶体管M。晶体管M包括有源层820、第一绝缘层830、栅极层840和第二绝缘层850。
有源层820包括第一极区域822和第二极区域824，以及位于第一极区域822和第二极区域824之间的沟道区域826。
第一绝缘层830覆盖有源层820。
栅极层840设置在第一绝缘层830上，栅极层840与有源层820电绝缘。
第二绝缘层850覆盖栅极层840和第一绝缘层830。
图9示出了图2的像素电路100中的各晶体管在显示面板上的示例布局，其中，每个晶体管具有如图8所例示的结构。为了便于说明和理解，图9中针对每个晶体管只示出了其中的沟道区域(通过黑色填充图案示出，与图8中所示的晶体管M的沟道区域826的图示图案相同)以表明晶体管的位置布局。
需要指出的是，图9中假定了第二复位信号Reset2与第一复位信号Reset1相同，第三控制信号Con3与第二控制信号Con2相同，并且为了便于理解各晶体管之间的位置关系，略去了存储电容Cst的结构。
图9中通过半透明的散点图案示出了提供第一电压V1的第一电压线，通过右斜划线图案示出了用于提供控制信号Reset1、Con1和Con2的控制信号线，这些控制信号线可以同层设置。第二电压线可以与这些控制信号线同层或不同层设置。
如图9所示，第二晶体管M2、第三晶体管M3和第四晶体管M4布置在像素单元的上部，它们的一端(例如第一极)分别经由通孔(例如h1)与第一电压线电连接。
第一晶体管M1和第七晶体管M7布置在像素单元的中间部分，第五晶体管M5和第六晶体管M6布置在图9的下部。其中，在一些实施例中，如图9所示，第一晶体管M1具有双栅结构。
在图9所示的布局的基础上，为了实现图2中的像素电路结构，还需要将第三晶体管M3的第二极与第六晶体管M6的第二极电连接，并且将第四晶体管M4的第二极与第六晶体管M6的第一极电连接。
图10示出了通过第一屏蔽线L1和第二屏蔽线L2进行上述连接的实施例。其中，第一屏蔽线L1和第二屏蔽线L2位于屏蔽连接层中，通过横线图案半透明地示出。第一屏蔽线L1在其两端分别经由通孔(例如h2)与第三晶体管M3的第二极和第六晶体管M6的第二极电连接。第二屏蔽线L2在其两端分别经由通孔与第四晶体管M4的第二极和第六晶体管M6的第一极电连接。
如图10所示，第二屏蔽线L2与第一晶体管M1至少部分地重叠，以遮蔽第一晶体管M1的至少一部分。也就是说，第二屏蔽线L2在显示面板的基板上的正投影与第一晶体管M1的沟道区域在基板上的正投影至少部分地重叠。
屏蔽线由导体(例如，金属)制成，其中有电流通过时会与晶体管之间产生寄生电容，寄生电容有稳定晶体管中通过的电流的作用。因此，上述屏蔽线对M1的遮蔽一方面可以对M1起到很好的屏蔽作用，从而避免温度和光照对M1的影响，另一方面，也可以降低M1的漏电流，使得发光电流更加稳定。
此外，在一些实施例中，第一屏蔽线L1也可以被构造为覆盖第一晶体管M1的至少一部分。如图10所示，其中的第一屏蔽线L1也与第一晶体管M1的沟道区域至少部分地重叠。
在图9和图10的示例布局中，第三晶体管M3位于第四晶体管M4的左侧。然而，应该理解的是，在其他实施例中，二者的位置是可以互换的。
图11是示出了屏蔽连接层与晶体管的电连接的结构图。图11在图8的基础上绘制，与图8相比，在第二绝缘层850上进一步形成有屏蔽连接层860。其中，屏蔽连接层860可以包括第一屏蔽线L1和第二屏蔽线L2。
屏蔽连接层860经由贯穿第三晶体管M3的第一绝缘层830和第二绝缘层850的通孔870(即通孔h2)与第三晶体管M3的第二极区域824电连接。可以通过图11所示的结构来实现第一屏蔽线L1与第三晶体管M3的第二极区域以及第六晶体管M6的第二极区域之间的电连接，以及第二屏蔽线L2与第四晶体管M4的第二极区域以及第六晶体管M6的第一极区域之间的电连接。
例如，第三晶体管M3中可以具有贯穿第三晶体管M3的第一绝缘层和第二绝缘层的第一通孔，以暴露第三晶体管M3的第二极区域的一部分；第六晶体管M6中可以具有贯穿第六晶体管M6的第一绝缘层和第二绝缘层的第二通孔和第三通孔，以分别暴露第六晶体管M6的第一极区域的一部分和第六晶体管M6的第二级区域的一部分；第四晶体管M4中可以具有贯穿第四晶体管M4的第一绝缘层和第二绝缘层的第四通孔，以暴露第四晶体管M4的第二极区域的一部分。
第一屏蔽线L1经由第一通孔和第三通孔将第三晶体管M3的第二极区域与第六晶体管M6的第二极区域电连接；第二屏蔽线L2经由第二通孔和第四通孔将第四晶体管M4的第二极区域与第六晶体管M6的第一极区域电连接。
以上的详细描述通过使用示意图、流程图和/或示例，已经阐述了众多实施例。在这种示意图、流程图和/或示例包含一个或多个功能和/或操作的情况下，本领域技术人员应理解，这种示意图、流程图或示例中的每一功能和/或操作可以通过各种结构、硬 件、软件、固件或实质上它们的任意组合来单独和/或共同实现。
虽然已参照几个典型实施例描述了本公开，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本公开能够以多种形式具体实施而不脱离公开的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (16)

  1. 一种像素电路，包括：
    发光元件；
    驱动子电路，被构造为产生用于使发光元件发光的电流；
    第一发光控制子电路和第二发光控制子电路，所述第一发光控制子电路电连接至所述驱动子电路，并且与所述驱动子电路电连接于第一节点；所述第二发光控制子电路电连接在所述驱动子电路与所述发光元件的第一端之间，并且与所述驱动子电路电连接于第二节点，所述第一发光控制子电路和所述第二发光控制子电路被构造为接收第一控制信号，并在所述第一控制信号的控制下，将所述用于使发光元件发光的电流提供到所述发光元件的第一端；
    驱动控制子电路，电连接至所述驱动子电路，被构造为接收数据信号和第二控制信号，并在所述第二控制信号的控制下，将所述数据信号提供到所述驱动子电路；以及
    复位子电路，电连接至所述驱动子电路，被构造为接收第一电压信号、第一复位信号和第二复位信号，并在所述第一复位信号和第二复位信号的控制下使用所述第一电压信号对所述驱动子电路、所述发光元件的第一端以及所述第二节点进行复位。
  2. 根据权利要求1所述的像素电路，其中，所述驱动子电路包括驱动晶体管、第一晶体管和存储电容，其中，
    所述驱动晶体管的栅极电连接第三节点，第一极电连接所述第一节点，第二极电连接所述第二节点；
    所述第一晶体管的栅极电连接为接收第三控制信号，第一极电连接所述第三节点，第二极电连接所述第二节点；以及
    所述存储电容的第一极电连接为接收第二电压信号，第二极电连接所述第三节点。
  3. 根据权利要求2所述的像素电路，其中，所述复位子电路包括第二晶体管、第三晶体管和第四晶体管，其中
    所述第二晶体管的栅极电连接为接收所述第一复位信号，第一极电连接为接收所述第一电压信号，第二极电连接所述第三节点，
    所述第三晶体管的栅极电连接为接收所述第二复位信号，第一极电连接为接收所述第一电压信号，第二极电连接所述发光元件的第一端，
    所述第四晶体管的栅极电连接为接收所述第一复位信号，第一极电连接为接收所述第一电压信号，第二极电连接所述第二节点。
  4. 根据权利要求2所述的像素电路，其中，所述复位子电路包括第二晶体管和第三晶体管，其中
    所述第二晶体管的栅极电连接为接收所述第一复位信号，第一极电连接为接收所述第一电压信号，第二极电连接所述第二节点，
    所述第三晶体管的栅极电连接为接收所述第二复位信号，第一极电连接为接收所述第一电压信号，第二极电连接所述发光元件的第一端。
  5. 根据权利要求3或4所述的像素电路，其中，所述第一发光控制子电路包括第五晶体管，所述第二发光控制子电路包括第六晶体管，其中
    所述第五晶体管的栅极电连接为接收所述第一控制信号，第一极电连接为接收所述第二电压信号，第二极电连接所述第一节点；
    所述第六晶体管的栅极电连接为接收所述第一控制信号，第一极电连接所述第二节点，第二极电连接所述发光元件的第一端。
  6. 根据权利要求1-5中的任一项所述的像素电路，其中，所述驱动控制子电路包括第七晶体管，其中
    所述第七晶体管的栅极电连接为接收所述第二控制信号，第一极电连接为接收所述数据信号，第二极电连接所述第一节点。
  7. 根据权利要求1-6中的任一项所述的像素电路，其中，所述复位子电路使用所述第一电压信号将所述第一节点的电压充电为与所述驱动子电路相对应的阈值电压与所述第一电压信号的电压之和。
  8. 根据权利要求1-7中的任一项所述的像素电路，其中，所述第一复位信号与所述第二复位信号相同。
  9. 根据权利要求1-7中的任一项所述的像素电路，其中，所述第二复位信号与延迟半个时钟周期的第一复位信号相同。
  10. 一种显示面板，包括：
    多条扫描线；
    多条数据线，与所述多条扫描线纵横交叉设置；以及
    多个像素单元，以矩阵的形式设置在每个数据线和每个扫描线交叉处，并与对应的 数据线和扫描线电连接，每个像素单元包括根据权利要求1-9中任一项所述的像素电路，
    其中，所述像素电路所接收的数据信号由所述像素单元的对应数据线提供，所述像素电路所接收的第二控制信号由所述像素单元的对应扫描线提供。
  11. 根据权利要求10所述的显示面板，还包括多条发光控制线，所述多条发光控制线与所述多条扫描线或所述多条数据线平行地布置，并与所述多条扫描线或所述多条数据线分别电连接到相同的像素单元，
    其中，所述像素电路所接收的第一控制信号和第三控制信号由所述像素单元的对应发光控制线提供。
  12. 根据权利要求10所述的显示面板，其中，所述像素电路所接收的第一复位信号和第二复位信号由所述像素单元的对应扫描线的按照扫描顺序的前一扫描线提供。
  13. 一种对根据权利要求1-9中的任一项所述的像素电路进行驱动的方法，包括：
    在第一时段，提供具有第一电平的第一控制信号、第二控制信号和第三控制信号，提供具有第二电平的第一复位信号和第二复位信号；
    在第二时段，提供具有第一电平的第一控制信号、第一复位信号和第二复位信号，提供具有第二电平的第二控制信号和第三控制信号，或者提供具有第一电平的第一控制信号、第三控制信号、第一复位信号和第二复位信号，提供具有第二电平的第二控制信号；
    在第三时段，提供具有第一电平的第二控制信号、第三控制信号第一复位信号和第二复位信号，提供具有第二电平的第一控制信号，或者提供具有第一电平的第二控制信号、第一复位信号和第二复位信号，提供具有第二电平的第一控制信号和第三控制信号。
  14. 根据权利要求13所述的方法，其中，使用第一电压信号将第一节点的电压充电为与驱动子电路相对应的阈值电压与所述第一电压信号的电压之和。
  15. 一种显示面板，包括多个像素单元，所述多个像素单元中的至少一个像素单元包括根据权利要求5所述的像素电路，其中，所述至少一个像素单元中的每一个包括：
    基板；
    第一晶体管、第三晶体管、第四晶体管和第六晶体管，其中每个晶体管包括：
    有源层，包括第一极区域和第二极区域，以及位于所述第一极区域和第二极区域之间的沟道区域；
    第一绝缘层，覆盖所述有源层；
    栅极层，与所述有源层电绝缘地设置在所述第一绝缘层上；以及
    第二绝缘层，覆盖所述栅极层和所述第一绝缘层；
    屏蔽连接层，包括第一屏蔽线和第二屏蔽线，所述第一屏蔽线将所述第三晶体管的第二极区域与所述第六晶体管的第二极区域电连接，所述第二屏蔽线将所述第四晶体管的第二极区域与所述第六晶体管的第一极区域电连接，
    其中，所述第一屏蔽线和所述第二屏蔽线中的至少一个在所述基板上的正投影与所述第一晶体管的沟道区域在所述基板上的正投影至少部分地重叠。
  16. 根据权利要求15所述的显示面板，其中，
    在所述第三晶体管中具有贯穿所述第三晶体管的第一绝缘层和第二绝缘层的第一通孔，以暴露所述第三晶体管的第二极区域的一部分，
    在所述第六晶体管中具有贯穿所述第六晶体管的第一绝缘层和第二绝缘层的第二通孔和第三通孔，以分别暴露所述第六晶体管的第一极区域的一部分和所述第六晶体管的第二级区域的一部分，
    在所述第四晶体管中具有贯穿所述第四晶体管的第一绝缘层和第二绝缘层的第四通孔，以暴露所述第四晶体管的第二极区域的一部分，
    其中，所述第一屏蔽线经由所述第一通孔和所述第三通孔将所述第三晶体管的第二极区域与所述第六晶体管的第二极区域电连接，所述第二屏蔽线经由所述第二通孔和所述第四通孔将所述第四晶体管的第二极区域与所述第六晶体管的第一极区域电连接。
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CN105427803A (zh) * 2016-01-04 2016-03-23 京东方科技集团股份有限公司 像素驱动电路、方法、显示面板和显示装置
CN105679236A (zh) * 2016-04-06 2016-06-15 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板、显示面板和显示装置
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CN107358918A (zh) * 2017-08-25 2017-11-17 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN107358920A (zh) * 2017-09-08 2017-11-17 京东方科技集团股份有限公司 像素驱动电路及其驱动方法及显示装置
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