WO2020140281A1 - 图像数据处理方法及传输装置、图像显示方法及存储介质 - Google Patents

图像数据处理方法及传输装置、图像显示方法及存储介质 Download PDF

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Publication number
WO2020140281A1
WO2020140281A1 PCT/CN2019/070459 CN2019070459W WO2020140281A1 WO 2020140281 A1 WO2020140281 A1 WO 2020140281A1 CN 2019070459 W CN2019070459 W CN 2019070459W WO 2020140281 A1 WO2020140281 A1 WO 2020140281A1
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Prior art keywords
data
image data
processing method
column
consecutive
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PCT/CN2019/070459
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English (en)
French (fr)
Inventor
林琳
孙剑
郭子强
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to CN201980000041.1A priority Critical patent/CN109845282B/zh
Priority to US16/632,933 priority patent/US20210227173A1/en
Priority to PCT/CN2019/070459 priority patent/WO2020140281A1/zh
Publication of WO2020140281A1 publication Critical patent/WO2020140281A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/04—Systems for the transmission of one television signal, i.e. both picture and sound, by a single carrier
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/231—Content storage operation, e.g. caching movies for short term storage, replicating data over plural servers, prioritizing data for deletion
    • H04N21/23106—Content storage operation, e.g. caching movies for short term storage, replicating data over plural servers, prioritizing data for deletion involving caching operations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/50—Network services
    • H04L67/56—Provisioning of proxy services
    • H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/231—Content storage operation, e.g. caching movies for short term storage, replicating data over plural servers, prioritizing data for deletion
    • H04N21/23103—Content storage operation, e.g. caching movies for short term storage, replicating data over plural servers, prioritizing data for deletion using load balancing strategies, e.g. by placing or distributing content on different disks, different memories or different servers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/122—Tiling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/10—Use of a protocol of communication by packets in interfaces along the display data pipeline
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen

Definitions

  • the embodiments of the present disclosure relate to an image data processing method, an image display method, a data transmission device, and a storage medium.
  • Data communication is a communication method produced by the combination of communication technology and computer technology.
  • the data communication may include wired data communication and wireless data communication.
  • they all connect data terminals with computers through transmission channels, and enable data terminals in different locations to share software, hardware, and information resources.
  • At least one embodiment of the present disclosure provides an image data processing method, including: storing a set of object data to be transferred to a first cache space, wherein the set of object data includes N consecutive images arranged in order according to a first order Data; recombining the N consecutive image data into M data subsets, wherein each data subset includes N/M mutually selected in turn from the N consecutive image data according to the first rule Non-adjacent image data; transmit the M data subsets; where M is an integer greater than 1, and N is an integer multiple of M greater than 1.
  • the N consecutive image data sequentially arranged in the first order includes N consecutive image data sequentially arranged in the order from the first to the Nth Image data.
  • the image data processing method provided by an embodiment of the present disclosure further includes: receiving the transmitted M data subsets, and extracting the image data included in each of the M data subsets to the second cache space, wherein , Restoring the N consecutive image data sequentially arranged in the first order in the second buffer space based on the first rule.
  • an image data processing method for example, after restoring the N consecutive image data arranged in the first order in the second buffer space based on the first rule, Perform a check on each image data in the second buffer space, and if a transmission error or missing image data occurs, modify the image data having the transmission error or fill in the missing image data according to the interpolation method.
  • the first rule includes: cyclically selecting the data subset with L as a period, where L is an integer greater than 1.
  • the first cache space is a matrix cache space
  • the matrix cache space includes L*M image data
  • selecting the data subset cyclically with L as a cycle includes: sequentially outputting the Mth column and the Mth column of the matrix cache space in a column reverse order
  • the image data in -1 column, ..., column Mi, ..., column 1 are used as the data subsets respectively; each column includes L non-adjacent image data, i is greater than 1 and less than M Integer.
  • the image data in the M-i column is output in parallel.
  • At least one embodiment of the present disclosure also provides an image display method, including: acquiring pixel data of an image to be displayed; adopting the image data processing method provided by any of the embodiments of the present disclosure to transfer the pixel data of the image to be displayed line by line; The pixel data is output to the display panel line by line for display.
  • At least one embodiment of the present disclosure also provides a data transmission device, including: a cache unit configured to store a set of object data to be transferred to a first cache space, wherein the set of object data includes the data arranged in order according to the first order N consecutive image data; a data subset selection unit configured to reassemble the N consecutive image data into M data subsets, wherein each data subset includes the N N/M non-adjacent image data sequentially selected from consecutive image data; a transmission unit configured to transmit the M data subsets; wherein, M is an integer greater than 1, and N is an M greater than 1. Integer multiple.
  • a data transmission device provided by an embodiment of the present disclosure further includes: a reading unit configured to receive the transmitted M data subsets, and extract image data included in each of the M data subsets to the first Two cache spaces, wherein, in the second cache space, the N consecutive image data sequentially arranged in the first order are restored based on the first rule.
  • the data transmission device further includes: a verification unit configured to restore the N number arranged in the first order in the second buffer space based on the first rule After the continuous image data, perform a check on each image data in the second buffer space, and if there is a transmission error or missing image data, modify the image data with the transmission error or fill the missing according to the interpolation method Image data.
  • a verification unit configured to restore the N number arranged in the first order in the second buffer space based on the first rule After the continuous image data, perform a check on each image data in the second buffer space, and if there is a transmission error or missing image data, modify the image data with the transmission error or fill the missing according to the interpolation method Image data.
  • At least one embodiment of the present disclosure also provides a data transmission device, including: a processor; a memory; one or more computer program modules, the one or more computer program modules are stored in the memory and configured to The processor executes, and the one or more computer program modules include instructions for executing the image data processing method provided by any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure also provides a storage medium that non-transitory stores computer-readable instructions, and when the non-transitory computer-readable instructions are executed by a computer, image data provided according to any embodiment of the present disclosure can be executed Instructions for processing methods.
  • Figure 1 is a matrix representation of pixel data of an image to be displayed
  • FIG. 2 is a schematic diagram of a serial data stream corresponding to the pixel data of the first row shown in FIG. 1;
  • FIG. 3 is a flowchart of an image data processing method provided by some embodiments of the present disclosure.
  • FIG. 4 is a schematic diagram of storage of a first cache space provided by some embodiments of the present disclosure.
  • FIG. 5 is a schematic diagram of extracting data subsets and parallel-serial conversion operations provided by some embodiments of the present disclosure
  • FIG. 6 is a schematic diagram of serial transmission of M data subsets provided by some embodiments of the present disclosure.
  • FIG. 7 is a flowchart of another image data processing method provided by some embodiments of the present disclosure.
  • FIG. 8 is a flowchart of an image display method provided by some embodiments of the present disclosure.
  • FIG. 9 is a schematic block diagram of a data transmission device according to some embodiments of the present disclosure.
  • FIG. 10 is a schematic block diagram of another data transmission device according to some embodiments of the present disclosure.
  • FIG. 11 is a schematic diagram of a storage medium provided by some embodiments of the present disclosure.
  • data communication can suppress channel noise by adding scrambling codes, but the introduction of scrambling codes reduces the transmission efficiency of effective data.
  • the scrambling code is added during data transmission, which causes the data volume of the display part to increase continuously, thereby further expanding the data transmission volume and increasing the device’s data volume.
  • Operating power consumption; and for the scrambling code added during transmission it is necessary to add anti-jamming part in the peripheral interface (such as HDMI, DP) part, thereby further improving the operating loss of the peripheral interface.
  • the computing power of the processing unit in the VR system is limited, and the addition of the descrambling code increases the workload of the processing unit, which is not conducive to reducing the operating power consumption and manufacturing cost of the device, and is not conducive to improving the response speed of the device.
  • FIG. 1 is a matrix representation of pixel data of an image to be displayed.
  • the pixel data matrix of the image to be displayed includes m*n pixel data (for example, including A1, 1, A1,2, ..., Am, n), respectively corresponding to m displayed on the display screen Pixels in row *n column.
  • the m*n pixel data in the image to be displayed can be serially transmitted line by line in sequence, and displayed on the display screen in a progressive scanning manner.
  • FIG. 2 is a schematic diagram of the serial data stream corresponding to the pixel data of the first row shown in FIG. 1.
  • the pixel data A1, 1, A1,2, ..., A1, n of the first line shown in FIG. 1 are sequentially sent one by one and stored in the line vector space shown in FIG. 2 , Forming a serial data stream of the first row as shown in FIG. 2: the first (1st) pixel data (ie A1,1), the second (2nd) pixel data (ie A1,2),..., n (nth) pixel data (ie A1, n).
  • 2, 3, or more similar row vector spaces can be opened up to alternately store pixel data of adjacent rows in the pixel data matrix shown in FIG. 1 to meet the cycle requirements of algorithm operations .
  • the display data may be incomplete and affect the display quality of the display panel.
  • At least one embodiment of the present disclosure provides an image data processing method, including: storing a set of object data to be transferred to a first cache space, where the set of object data includes N consecutive data sequentially arranged in a first order; N consecutive data are recombined into M data subsets, where each data subset includes N/M non-adjacent data sequentially selected from N consecutive data according to the first rule; M data are transmitted Data subset; where M is an integer greater than 1, and N is an integer multiple of M greater than 1.
  • At least one embodiment of the present disclosure also provides a data transmission device, an image display method, and a storage medium corresponding to the above image data processing method.
  • the image data processing method provided by the above embodiments of the present disclosure can reduce the impact of channel noise and other interference on the transmitted data by changing the data transmission order during the data transmission process, without occupying additional transmission bandwidth and improving the data received by the signal receiving end
  • the quality and implementation process are relatively simple, which is beneficial to simplify the subsequent signal processing process, reduce the operating power consumption and manufacturing cost of the device, and improve the response speed of the device.
  • FIG. 3 is a flowchart of an image data processing method provided by some embodiments of the present disclosure.
  • the image data processing method can be implemented in software, hardware, or a combination thereof, and is loaded and executed by processors in devices such as mobile phones, notebook computers, virtual reality devices, augmented reality devices, desktop computers, network servers, digital cameras, etc.
  • processors used in the transmission process of image (frame) data, voice data, etc., to change the data transmission sequence in the data transmission process, reduce the impact of channel noise and other interference on the transmitted data, and at the same time can improve the quality of the data received at the signal receiving end, Simplify the subsequent signal processing operations such as filtering and reduce the operating power consumption of the device.
  • image data used as an example for description, but the embodiment of the present disclosure does not limit this.
  • the image data processing method includes steps S110 to S130.
  • Step S110 Store the to-be-transmitted object data set in the first cache space.
  • Step S120 Regroup N consecutive data into M data subsets.
  • Step S130 Transmit M data subsets.
  • M is an integer greater than 1
  • N is an integer multiple of M greater than 1.
  • the object data set includes N consecutive data sequentially arranged in the first order, for example, the N consecutive data is a row of image data.
  • the object data set may also include other data, such as data used to express various information, such as compression methods, sender identification, and the like.
  • the N consecutive data includes any one or more lines of pixel data of the image to be displayed shown in FIG. 1, and the following N consecutive data are used as pixel data A1, 1, A1,2 of the first row , ..., A1, n are introduced as examples, and the embodiments of the present disclosure do not limit this.
  • N n.
  • the first order is the arrangement order of the first pixel data, the second pixel data, ..., to the n-th pixel data shown in FIG. 2.
  • the N consecutive data are sequentially stored in the first buffer space shown in FIG. 4 in a serpentine manner as shown in FIG. 4, for example, the first of the N consecutive data
  • the data is the last one in the last row
  • the Nth data is the first one in the first row.
  • the first cache space is a matrix cache space
  • the matrix cache space includes L*M (L is an integer greater than 1) data, that is, the N consecutive data are sequentially stored into a matrix cache space of L rows and M columns in.
  • step S110 by storing a row of data as a matrix in step S110, it may be helpful to select data that are not adjacent to each other to output in sequence in subsequent steps.
  • a cache unit may be provided, and the object data collection to be transmitted is stored in the first cache space through the cache unit; for example, a central processing unit (CPU), an image processor (GPU), and a tensor processor ( TPU), Field Programmable Logic Gate Array (FPGA) or other forms of processing units with data processing capabilities and/or instruction execution capabilities and corresponding computer instructions to implement the cache unit.
  • CPU central processing unit
  • GPU image processor
  • TPU tensor processor
  • FPGA Field Programmable Logic Gate Array
  • each data subset includes N/M non-adjacent data sequentially selected from N consecutive data according to the first rule.
  • an appropriate first rule can be selected, so that N/M non-adjacent data that are not adjacent to each other can be sequentially selected from N consecutive data.
  • the first rule includes: cyclically selecting data subsets with L as the cycle, that is, selecting L data as a data subset each time until all data are selected into the data subset.
  • the Mth column, the M-1th column, ..., the Mith column (i is an integer greater than 1 and less than M), ..., and the first column of the matrix cache space can be sequentially output in a column reverse order .
  • Each column is used as a subset of data.
  • the rightmost column in the matrix cache space (including the first data, (n/4)+1 data, (n/2)+1 data and (3n/4)+ 1 data) is the Mth column, and so on from right to left, and so on. It is the M-1th column, ..., Mith column, ..., the 1st column.
  • the first column is the leftmost column in the matrix cache space (including the (n/4) data, (n/2) data, (3n/4) data, and n data).
  • the data subset can also be selected in a ladder (oblique) manner, and 1 data arranged in a ladder is selected in each row.
  • a data subset may include (3n/4)+1 data in line 1, (n/2)+2 data in line 2, and (n/4) in line 3.
  • the following takes a data subset including the data of the M-i column in the matrix cache space as an example for introduction, and the data of the remaining columns are the same, which will not be described in detail.
  • the data in the M-i column is output in parallel.
  • a parallel-serial conversion operation is performed on the data in the M-(i-1) column to convert the data in the M-(i-1) column to serial data .
  • the following describes the process of parallel data output by taking the Mth column and the M-1th column (that is, the two columns in the dotted frame in FIG. 5) as an example.
  • N consecutive pixel data are stored in the matrix buffer space in a serpentine manner as shown in FIG. 4, and pixel data is not sequentially output from the matrix buffer space one by one. For example, consider the data in each column as an array.
  • the Mth The 4 channels of the column simultaneously output the first, [(n/4)+1], [(n/2)+1] and [(3n/4)+1] data in parallel, that is, at the same time ⁇ A1,1 ⁇ , ⁇ A[(n/4)+1],1 ⁇ , ⁇ A[(n/2)+1],1 ⁇ , ⁇ A[(n3/4)+1 ],1 ⁇ The four data; when the [[3n/4)+2] element ⁇ A[(3n/4)+2],1 ⁇ is stored in the matrix cache space, the M-1 column 4 channels simultaneously output the 2nd, [(n/4)+2], [(n/2)+2] and [(3n/4)+2] data, ie output array at the same time ⁇ A2,1 ⁇ , ⁇ A[(n/4)+2],1 ⁇ , ⁇ A[(n/2)+2],1 ⁇ , ⁇ A[(n3/4)
  • M represents the number of interleaved data
  • M-1 represents the interleaved data interval.
  • the interleaved data interval can be monitored to ensure that the interval of each row of data address is correct, so that a subset of data can be selected in an orderly manner to ensure the normal reading of pixel data.
  • a data subset selection unit can be provided, and N consecutive data can be recombined into M data subsets through the data subset selection unit; for example, a central processing unit (CPU) or an image processor (GPU) can also be used ), Tensor Processor (TPU), Field Programmable Logic Gate Array (FPGA) or other forms of processing units with data processing capabilities and/or instruction execution capabilities and corresponding computer instructions to implement the data subset selection unit.
  • CPU central processing unit
  • GPU image processor
  • TPU Tensor Processor
  • FPGA Field Programmable Logic Gate Array
  • M data subsets may be transmitted serially or in parallel.
  • 6 is a schematic diagram of serial transmission of M data subsets according to an embodiment of the present disclosure.
  • the M parallel output data subsets shown in FIG. 5 are sequentially converted into serial data streams through parallel-serial conversion operations and then transmitted, thereby forming a serial data stream with discontinuous addresses as shown in FIG. 6 .
  • the serial data stream includes the above N data, but the addresses of the N data are arranged in the order of the selected M data subsets.
  • the serial data stream is transmitted to the signal receiving end, for example, the second buffer space.
  • the sending end of the serial data stream is an AP (application processor), and the signal receiving end is a driving circuit of a display panel.
  • AP application processor
  • a transmission unit may be provided, and M data subsets are transmitted through the transmission unit; for example, the transmission unit may be a wired unit or a wireless transmission unit.
  • the wired transmission may be an electrical signal transmission device or an optical signal transmission device, the electrical signal transmission device transmits data through, for example, a coaxial cable, and the optical signal transmission device transmits data through an optical fiber, for example, and they are based on respective relevant data transmission standards, such as a synchronous digital system (SDH), Dense Wavelength Division Multiplexing (DWDM), etc.
  • SDH synchronous digital system
  • DWDM Dense Wavelength Division Multiplexing
  • the wireless transmission unit may be based on wireless communication devices of various standards, such as WIFI, Bluetooth, ZigBee, infrared, 2G/3G/4G/5G mobile communication, and the like.
  • the transmission unit includes a central processing unit (CPU), an image processor (GPU), a tensor processor (TPU), a field programmable logic gate array (FPGA), or other forms with data processing capabilities and/or instruction execution capabilities
  • CPU central processing unit
  • GPU image processor
  • TPU tensor processor
  • FPGA field programmable logic gate array
  • the image data processing method provided by the above embodiments of the present disclosure can reduce the impact of channel noise and other interference on the transmitted data by changing the data transmission sequence during the data transmission process, without occupying additional transmission bandwidth and improving the data received by the signal receiving end
  • the quality is relatively simple, and the implementation process is relatively simple, which is beneficial to simplify the subsequent signal processing process, reduce the operating power consumption and manufacturing cost of the device, and improve the response speed of the device.
  • FIG. 7 is a flowchart of another image data processing method provided by some embodiments of the present disclosure.
  • the image data processing methods provided by some embodiments of the present disclosure can also read and verify the transmitted data subset, and fill and modify the transmitted data according to the verification result.
  • the image data processing method further includes steps S140 to S170. Next, the image data processing method will be described with reference to FIG. 7.
  • Step S140 Receive the transmitted M data subsets, and extract the data included in each of the M data subsets to the second buffer space.
  • the second cache space N consecutive data sequentially arranged in the first order are restored based on the first rule, for example, so that the arrangement order of the stored data in the second cache space and the first cache space is the same.
  • the second cache space is a matrix cache space and is the same as the first cache space.
  • this step is similar to decoding the serial data stream formed in the above step S120 and step S130 to restore it to N consecutive data arranged in order according to the first order, for example, to restore as shown in FIG. 4
  • the corresponding pixel data is read to the corresponding position according to the arrangement rule before data transmission. Therefore, although the image data processing method of the embodiment of the present disclosure changes the data transmission order, it can read the transmitted pixel data to the original position through dynamic addressing, thereby not affecting the display content of the display panel and improving the display of the display panel quality.
  • a reading unit may be provided, and the transmitted M data subsets may be received through the reading unit, and the data included in each of the M data subsets may be extracted to the second cache space; for example, it may also be passed through the central processing unit ( CPU), image processor (GPU), tensor processor (TPU), field programmable logic gate array (FPGA) or other forms of processing units with data processing capabilities and/or instruction execution capabilities and corresponding computer instructions to Implement the reading unit.
  • CPU central processing unit
  • CPU central processing unit
  • GPU image processor
  • TPU tensor processor
  • FPGA field programmable logic gate array
  • Step S150 Perform verification on each data in the second cache space.
  • the data after transmission ie, the second The data in the cache space
  • the data after transmission ie, the second The data in the cache space
  • it can be based on various data check methods, such as parity check, Hamming check, cyclic redundancy code (CRC) check, etc.
  • CRC cyclic redundancy code
  • a verification unit may be provided, and the verification unit performs verification on each data in the second cache space; for example, it may also be processed by a central processing unit (CPU), an image processor (GPU), or tensor processing Verification unit (TPU), field programmable logic gate array (FPGA) or other forms of processing units with data processing capabilities and/or instruction execution capabilities and corresponding computer instructions.
  • CPU central processing unit
  • GPU image processor
  • TPU tensor processing Verification unit
  • FPGA field programmable logic gate array
  • Step S160 determine whether there is transmission error or missing data in the second buffer space, and if so, perform step S170.
  • step S150 it can be determined whether a data transmission error or loss occurs. For example, if the data in the second cache space is different from the original transmission data, it means that a data transmission error occurred during the transmission process; if the data in the second cache space is less than the original data, it means that it was lost during the data transmission process Corresponding data.
  • Step S170 Modify the data with transmission errors or fill in the missing data according to the interpolation method.
  • the transmission error or missing pixel data can be based on The pixel data in the address unit adjacent to it that is not lost in the original image is restored. For example, you can modify the data with transmission errors or fill in the missing data by performing mathematical fitting calculations on the pixel data adjacent to it, such as interpolation, etc., which can reduce the impact of channel noise and other interference during data transmission. Improve the display quality of the display panel. For example, when an error occurs in a certain item of data, the arithmetic average of the previous item and the next item of data adjacent to the item is used to assign a value to the item, and the new data is used for subsequent display operations .
  • the processing may further include: Perform filtering processing.
  • common filtering methods such as Gaussian filtering and median filtering can be used to implement filtering processing on the received data, thereby weakening the noise generated during transmission, improving the quality of display data, and thus improving the display quality of the display panel.
  • the flow of the image data processing method may include more or fewer operations, and these operations may be performed sequentially or in parallel.
  • the flow of the image data processing method described above includes multiple operations occurring in a specific order, it should be clearly understood that the order of multiple operations is not limited.
  • the image data processing method described above may be executed once or multiple times according to predetermined conditions.
  • FIG. 8 is a flowchart of an image display method provided by some embodiments of the present disclosure.
  • the image display method includes steps S210 to S230. Next, the image display method will be described with reference to FIG. 8.
  • Step S210 Obtain pixel data of the image to be displayed.
  • the pixel data matrix of the image to be displayed includes m*n pixel data (for example, including pixel data A1, 1, A1,2, ..., Am, n shown in FIG. 1).
  • Step S220 Transmit pixel data of the image to be displayed line by line.
  • the pixel data of the image to be displayed can be transmitted line by line through the above steps S110 to S170, so that the influence caused by interference such as channel noise during the data transmission process can be reduced.
  • each line of data is received by the data driving circuit of the display panel and After buffering, it is applied to a row of pixel units for display in the progressive scan display operation of the display panel, so that a higher display quality can be obtained.
  • Step S230 Output the pixel data line by line to the display panel for display.
  • the pixel data is transmitted line by line to the data driving circuit of the display panel.
  • the data driving circuit receives and buffers a line of data signals
  • the pixel data is output line by line to the corresponding line of pixel units through the data line to achieve display The corresponding display on the panel.
  • the data transmission device 100 includes a cache unit 110, a data subset selection unit 120, and a transmission unit 130.
  • these units may be implemented by hardware (eg, circuit) modules or software modules.
  • the cache unit 110 is configured to store the to-be-transmitted object data set in the first cache space.
  • the object data set includes N consecutive data arranged sequentially in the first order.
  • the cache unit 110 may implement step S110.
  • step S110 For a specific implementation method, reference may be made to the relevant description of step S110, and details are not described herein again.
  • the data subset selection unit 120 is configured to reassemble N consecutive data into M data subsets.
  • each data subset includes N/M non-adjacent data sequentially selected from N consecutive data according to the first rule.
  • the data subset selection unit 120 may implement step S120.
  • step S120 For a specific implementation method, reference may be made to the relevant description of step S120, and details are not described herein again.
  • the transmission unit 130 is configured to transmit M data subsets.
  • the transmission unit 130 may implement step S130.
  • step S130 For a specific implementation method, reference may be made to the relevant description of step S130, and details are not described herein again.
  • the data transmission device 100 further includes a reading unit and a verification unit (not shown in the figure).
  • the reading unit is configured to receive the transmitted M data subsets, and extract the data included in each of the M data subsets to the second buffer space. For example, in the second cache space, based on the first rule, N consecutive data sequentially arranged in the first order are restored.
  • the reading unit may implement step S140.
  • step S140 For a specific implementation method, reference may be made to the relevant description of step S140, and details are not described herein again.
  • the verification unit is configured to perform verification on each data in the second cache space after recovering N consecutive data arranged in the first order based on the first rule in the second cache space. For example, if there is a transmission error or missing data, you can modify the transmission error data or fill in the missing data according to the interpolation method.
  • the verification unit may implement steps S150 to S170. For a specific implementation method, reference may be made to related descriptions of steps S150 to S170, and details are not described herein again.
  • the data transmission device may include more or fewer circuits or units, and the connection relationship between the circuits or units is not limited, and may be determined according to actual needs.
  • the specific configuration of each circuit is not limited, and may be composed of analog devices, digital chips, or other suitable methods according to the circuit principle.
  • the data transmission device 200 includes a processor 210, a memory 220, and one or more computer program modules 221.
  • the processor 210 and the memory 220 are connected through the bus system 230.
  • one or more computer program modules 221 are stored in the memory 220.
  • one or more computer program modules 221 include instructions for performing the image data processing method provided by any embodiment of the present disclosure.
  • the instructions in one or more computer program modules 221 may be executed by the processor 210.
  • the bus system 230 may be a commonly used serial or parallel communication bus, etc. The embodiments of the present disclosure do not limit this.
  • the processor 210 may be a central processing unit (CPU), an image processor (GPU), or other forms of processing units with data processing capabilities and/or instruction execution capabilities, and may be general-purpose processors or dedicated processors, and Other components in the data transmission device 200 may be controlled to perform desired functions.
  • CPU central processing unit
  • GPU image processor
  • Other components in the data transmission device 200 may be controlled to perform desired functions.
  • the memory 220 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory.
  • the volatile memory may include, for example, random access memory (RAM) and/or cache memory.
  • the non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, and the like.
  • One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 210 may execute the program instructions to implement the functions (implemented by the processor 210) and/or other desired functions in the embodiments of the present disclosure, For example, image data processing methods.
  • Various application programs and various data may also be stored in the computer-readable storage medium, such as various data subsets and various data used and/or generated by the application programs.
  • An embodiment of the present disclosure also provides a storage medium.
  • 11 is a schematic diagram of a storage medium provided by some embodiments of the present disclosure.
  • the storage medium 300 non-transitory stores computer-readable instructions 301.
  • the image data processing method provided by any embodiment of the present disclosure may be executed.
  • the storage medium may be any combination of one or more computer-readable storage media.
  • a computer-readable storage medium contains computer-readable program code that stores the set of object data to be transferred to the first cache space.
  • a computer-readable storage medium contains computer-readable program code that extracts M data subsets.
  • the computer can execute the program code stored in the computer storage medium to perform, for example, the image data processing method provided by any embodiment of the present disclosure.
  • the storage medium may include a memory card of a smartphone, a storage part of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read only memory (ROM), an erasable programmable read only memory (EPROM),
  • RAM random access memory
  • ROM read only memory
  • EPROM erasable programmable read only memory
  • CD-ROM compact disk read-only memory
  • flash memory or any combination of the above storage media may also be other suitable storage media.

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Abstract

一种图像数据处理方法、图像显示方法、数据传输装置及存储介质。该图像数据处理方法包括：将待传输的对象数据集合存储至第一缓存空间，其中，对象数据集合包括按照第一顺序依次排列的N个连续的图像数据；将N个连续的图像数据重新组合为M个数据子集，其中，每个数据子集包括按照第一规则从N个连续的图像数据中依次选取的N/M个互不相邻的图像数据；传输M个数据子集；其中，M为大于1的整数，N是M的大于1的整数倍。该图像数据处理方法通过改变数据传输过程中的数据传输顺序，可以降低信道噪声等干扰带来的影响，提高信号接收端接收的数据质量。

Description

图像数据处理方法及传输装置、图像显示方法及存储介质 技术领域
本公开的实施例涉及一种图像数据处理方法、图像显示方法、数据传输装置和存储介质。
背景技术
数据通信是通信技术和计算机技术相结合而产生的一种通信方式。例如，根据传输媒体的不同，该数据通信可以包括有线数据通信与无线数据通信。例如，它们都是通过传输信道将数据终端与计算机联结起来，而使不同地点的数据终端实现软、硬件和信息资源的共享。
发明内容
本公开至少一实施例提供一种图像数据处理方法，包括：将待传输的对象数据集合存储至第一缓存空间，其中，所述对象数据集合包括按照第一顺序依次排列的N个连续的图像数据；将所述N个连续的图像数据重新组合为M个数据子集，其中，每个数据子集包括按照第一规则从所述N个连续的图像数据中依次选取的N/M个互不相邻的图像数据；传输所述M个数据子集；其中，M为大于1的整数，N是M的大于1的整数倍。
例如，在本公开一实施例提供的图像数据处理方法中，所述按照第一顺序依次排列的N个连续的图像数据包括按照从第1个至第N个的顺序依次排列的N个连续的图像数据。
例如，本公开一实施例提供的图像数据处理方法，还包括：接收传输的所述M个数据子集，并且提取所述M个数据子集每个包括的图像数据至第二缓存空间，其中，在所述第二缓存空间中基于所述第一规则恢复按照所述第一顺序依次排列的所述N个连续的图像数据。
例如，在本公开一实施例提供的图像数据处理方法中，在所述第二缓存空间中基于所述第一规则恢复按照所述第一顺序依次排列的所述N个连续的图像数据之后，对所述第二缓存空间中的每个图像数据执行校验，如果出现 传输错误或丢失的图像数据，根据插值法修改出现所述传输错误的图像数据或填补所述丢失的图像数据。
例如，在本公开一实施例提供的图像数据处理方法中，所述第一规则包括：以L为周期，循环选择所述数据子集，其中，L为大于1的整数。
例如，在本公开一实施例提供的图像数据处理方法中，所述第一缓存空间为矩阵缓存空间，所述矩阵缓存空间包括L*M个图像数据。
例如，在本公开一实施例提供的图像数据处理方法中，以L为周期，循环选择所述数据子集，包括：按列逆序的方式依次输出所述矩阵缓存空间的第M列、第M-1列、…、第M-i列、……、第1列中的图像数据分别作为所述数据子集；其中，每列中包括L个互不相邻的图像数据，i为大于1小于M的整数。
例如，在本公开一实施例提供的图像数据处理方法中，在所述第M-i列中的第L个数据写入所述矩阵缓存空间后，并行输出所述第M-i列中的图像数据。
例如，在本公开一实施例提供的图像数据处理方法中，在并行输出所述第M-i列中的图像数据时，对第M-(i-1)列中的图像数据进行并串转换操作以将所述第M-(i-1)列中的图像数据转换为串行数据。
本公开至少一实施例还提供一种图像显示方法，包括：获取待显示图像的像素数据；采用本公开上述任一实施例提供的图像数据处理方法逐行传输所述待显示图像的像素数据；将所述像素数据逐行输出至显示面板以用于显示。
本公开至少一实施例还提供一种数据传输装置，包括：缓存单元，配置为将待传输的对象数据集合存储至第一缓存空间，其中，所述对象数据集合包括按照第一顺序依次排列的N个连续的图像数据；数据子集选取单元，配置为将所述N个连续的图像数据重新组合为M个数据子集，其中，每个数据子集包括按照第一规则从所述N个连续的图像数据中依次选取的N/M个互不相邻的图像数据；传输单元，配置为传输所述M个数据子集；其中，M为大于1的整数，N是M的大于1的整数倍。
例如，本公开一实施例提供的数据传输装置，还包括：读取单元，配置为接收传输的所述M个数据子集，并且提取所述M个数据子集每个包括的 图像数据至第二缓存空间，其中，在所述第二缓存空间中基于所述第一规则恢复按照所述第一顺序依次排列的所述N个连续的图像数据。
例如，本公开一实施例提供的数据传输装置，还包括：校验单元，配置为在所述第二缓存空间中基于所述第一规则恢复按照所述第一顺序依次排列的所述N个连续的图像数据之后，对所述第二缓存空间中的每个图像数据执行校验，如果出现传输错误或丢失的图像数据，根据插值法修改出现所述传输错误的图像数据或填补所述丢失的图像数据。
本公开至少一实施例还提供一种数据传输装置，包括：处理器；存储器；一个或多个计算机程序模块，所述一个或多个计算机程序模块被存储在所述存储器中并被配置为由所述处理器执行，所述一个或多个计算机程序模块包括用于执行实现本公开任一实施例提供的图像数据处理方法的指令。
本公开至少一实施例还提供一种存储介质，非暂时性地存储计算机可读指令，当所述非暂时性计算机可读指令由计算机执行时可以执行根据本公开任一实施例提供的图像数据处理方法的指令。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种待显示图像的像素数据的矩阵表示形式；
图2为图1中所示的第1行像素数据对应的串行数据流的示意图；
图3为本公开一些实施例提供的一种图像数据处理方法的流程图；
图4为本公开一些实施例提供的一种第一缓存空间的存储示意图；
图5为本公开一些实施例提供的一种提取数据子集和并串转换操作的示意图；
图6为本公开一些实施例提供的一种串行传输M个数据子集的示意图；
图7为本公开一些实施例提供的另一种图像数据处理方法的流程图；
图8为本公开一些实施例提供的一种图像显示方法的流程图；
图9本公开一些实施例提供的一种数据传输装置的示意框图；
图10为本公开一些实施例提供的另一种数据传输装置的示意框图；以及
图11为本公开一些实施例提供的一种存储介质的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面通过几个具体的实施例对本公开进行说明。为了保持本公开实施例的以下说明清楚且简明，可省略已知功能和已知部件的详细说明。当本公开实施例的任一部件在一个以上的附图中出现时，该部件在每个附图中由相同或类似的参考标号表示。
通常，数据通信可以通过增加扰码的方式抑制信道噪声，但是，扰码的引入降低了有效数据的传输效率。例如，以VR(Virtual Reality，虚拟现实)设备为例进行说明，由于在数据传输过程中增加了扰码，使得显示部分的数据量不断增加，从而进一步扩大了数据的传输量，增加了设备的运行功耗；而且针对在传输过程中增加的扰码，需要在外围接口(例如HDMI、DP)部分增加抗扰部分，从而进一步提高了外围接口的运行损耗。此外，VR系统中处理单元的运算能力有限，而解扰码的加入增加了处理单元的工作量，不 利于降低设备的运行功耗和制造成本，并且不利于提高设备的响应速度。
图1为一种待显示图像的像素数据的矩阵表示形式。如图1所示，该待显示图像的像素数据矩阵包括m*n个像素数据(例如，包括A1,1、A1,2、…、Am,n)，分别对应于显示在显示屏幕中的m行*n列中的像素。例如，该待显示图像中的m*n个像素数据可以依次逐行串行传输，并且以逐行扫描的方式显示在显示屏幕上。
图2为图1中所示的第1行像素数据对应的串行数据流的示意图。例如，在进行逐行传输时，将图1中所示的第1行像素数据A1,1、A1,2、…、A1,n依次逐个发送，并存储在图2所示的行向量空间中，形成如图2所示的第1行的串行数据流：第1个(1st)像素数据(即A1,1)，第2个(2nd)像素数据(即A1,2)，…，第n个(nth)像素数据(即A1,n)。例如，在实际应用中，可以开辟2个、3个或更多个类似的行向量空间，交替存储图1中所示的像素数据矩阵中相邻行的像素数据，以满足算法运算的周期要求。
然而，在通过图2所示的图像数据处理方法传输像素数据时，由于行向量空间中相邻地址中的像素数据是连续的，因此当该行向量空间中的串行数据流因信道噪声等干扰发生数据丢失或损坏时，丢失或损坏的像素数据可能是待显示图像中某一部分连续的数据，从而通过该传输方法传输数据后可能使得显示数据不完整，影响显示面板的显示质量。
本公开至少一实施例提供一种图像数据处理方法，包括：将待传输的对象数据集合存储至第一缓存空间，其中，对象数据集合包括按照第一顺序依次排列的N个连续的数据；将N个连续的数据重新组合为M个数据子集，其中，每个数据子集包括按照第一规则从N个连续的数据中依次选取的N/M个互不相邻的数据；传输M个数据子集；其中，M为大于1的整数，N是M的大于1的整数倍。
本公开至少一实施例还提供一种对应于上述图像数据处理方法的数据传输装置、图像显示方法和存储介质。
本公开上述实施例提供的图像数据处理方法，通过改变数据传输过程中的数据传输顺序，可以降低信道噪声等干扰对传输数据的影响，不需要占用额外的传输带宽，提高信号接收端接收的数据质量，且实现过程比较简单，有利于简化后续信号处理过程，降低设备的运行功耗和制造成本，提高设备 的响应速度。
下面结合附图对本公开的实施例及其示例进行详细说明。
图3为本公开一些实施例提供的一种图像数据处理方法的流程图。该图像数据处理方法可以以软件、硬件或其组合的方式实现，由例如手机、笔记本电脑、虚拟现实设备、增强现实设备、桌面电脑、网络服务器、数码相机等设备中的处理器加载并执行，用于在图像(帧)数据、语音数据等的传输过程中，以改变数据传输过程中的数据传输顺序，降低信道噪声等干扰对传输数据的影响，同时可以提高信号接收端接收的数据质量，简化后续例如滤波等信号处理操作，降低设备的运行功耗。下面以图像数据为例进行说明，但是本公开的实施例对此不作限定。
下面，参考图3对本公开至少一实施例提供的图像数据处理方法进行说明。如图3所示，该图像数据处理方法包括步骤S110至步骤S130。
步骤S110：将待传输的对象数据集合存储至第一缓存空间。
步骤S120：将N个连续的数据重新组合为M个数据子集。
步骤S130：传输M个数据子集。
例如，M为大于1的整数，N是M的大于1的整数倍。
对于步骤S110，例如，对象数据集合包括按照第一顺序依次排列的N个连续的数据，例如，该N个连续的数据为一行图像数据。例如，除了该N个连续的数据之外，该对象数据集合还可以包括其他数据，例如用于表述各种信息的数据，例如压缩方式、发送者标识等。例如，该N个连续的数据包括图1中所示的待显示图像的任意一行或多行像素数据，且下面以该N个连续的数据为第1行的像素数据A1,1、A1,2、…、A1,n为例进行介绍，且本公开的实施例对此不作限制。例如，在该示例中，N＝n。例如，该第一顺序为图2中所示的第1个像素数据，第2个像素数据，…，至第n个像素数据的排列顺序。
例如，按照第一顺序将上述N个连续的数据以图4所示的蛇形方式依次存储至如图4所示的第一缓存空间中，例如，上述N个连续的数据中的第1个数据在最后1行的最后一个，第N个数据在第1行的第1个。例如，该第一缓存空间为矩阵缓存空间，该矩阵缓存空间包括L*M(L为大于1的整数)个数据，即将上述N个连续的数据依次存储至一个L行M列的矩阵缓存空 间中。
例如，通过步骤S110将一行数据存储为矩阵的方式，可以有助于在后续步骤中选取互不相邻的数据依次进行输出。
例如，可以提供缓存单元，并通过该缓存单元将待传输的对象数据集合存储至第一缓存空间；例如，也可以通过中央处理单元(CPU)、图像处理器(GPU)、张量处理器(TPU)、现场可编程逻辑门阵列(FPGA)或者具有数据处理能力和/或指令执行能力的其它形式的处理单元以及相应的计算机指令来实现缓存单元。
对于步骤S120，例如，每个数据子集包括按照第一规则从N个连续的数据中依次选取的N/M个互不相邻的数据。
例如，可以选择适当的第一规则，从而可以从N个连续的数据中依次选取的N/M个互不相邻的数据。例如，该第一规则包括：以L为周期，循环选择数据子集，即每次选取L个数据作为一个数据子集，直至所有的数据均被选入数据子集中为止。具体地，例如，可以按列逆序的方式依次输出矩阵缓存空间的第M列、第M-1列、…、第M-i列(i为大于1小于M的整数)、……、第1列中的数据，每一列分别作为数据子集。例如，每列数据中包括L(L＝N/M)个互不相邻的数据，即一个数据子集可以包括矩阵缓存空间中一列的数据，从而使得该数据子集中的各个数据互不相邻。
如图5所示，矩阵缓存空间中最右边的一列(包括第1个数据、第(n/4)+1个数据、第(n/2)+1个数据和第(3n/4)+1个数据)为第M列，由右向左依次类推，为第M-1列、…、第M-i列、……、第1列。例如，第1列是矩阵缓存空间中最左边的一列(包括第(n/4)个数据、第(n/2)个数据、第(3n/4)个数据和第n个数据)。
需要注意的是，还可以采用其他的选取方式选取数据子集，只要满足循环选择数据子集的周期为L即可，本公开的实施例对此不做限制。例如，数据子集还可以按阶梯(斜着)的方式选取，在每一行中选取按阶梯排列的1个数据。例如，当L＝4时，一个数据子集可以包括第1行第(3n/4)+1个数据、第2行第(n/2)+2个数据、第3行第(n/4)+3个(图中未示出)数据、第4行第4个(图中未示出)数据；或者包括第1行第n个数据、第2行第(3n/4)-1个数据、第3行第(n/2)-2个(图中未示出)数据、第4行第(n/4)-3个(图中未 示出)数据。
下面以一个数据子集包括矩阵缓存空间中第M-i列的数据为例进行介绍，其余各列的数据与此相同，不再赘述。
例如，在第M-i列中的第L个数据写入矩阵缓存空间后，并行输出第M-i列中的数据。例如，在并行输出第M-i列中的数据时，对第M-(i-1)列中的数据进行并串转换操作以将第M-(i-1)列中的数据转换为串行数据。例如，下面以第M列、第M-1列(即图5中虚线框中的两列)为例介绍数据并行输出的过程。
例如，如图4和图5所示，N个连续的像素数据以图4所示的蛇形方式存储至矩阵缓存空间，此时不逐个将像素数据从矩阵缓存空间中依次输出。例如，将每一列中的数据看做一个数组，当第[(3n/4)+1]个元素{A[(3n/4)+1],1}被存储至矩阵缓存空间后，第M列的4路同时并行输出第1个、第[(n/4)+1]个、第[(n/2)+1]个和第[(3n/4)+1]个数据，即同时输出数组中的{A1,1}、{A[(n/4)+1],1}、{A[(n/2)+1],1}、{A[(n3/4)+1],1}这4个数据；当第[(3n/4)+2]个元素{A[(3n/4)+2],1}被存储至矩阵缓存空间后，第M-1列的4路同时并行输出第2个，第[(n/4)+2]个、第[(n/2)+2]个和第[(3n/4)+2]个数据，即同时输出数组中的{A2,1}、{A[(n/4)+2],1}、{A[(n/2)+2],1}、{A[(n3/4)+2],1}这4个数据；以此类推……。
如图5所示，在并行输出第M-1列的4个数据的同时，对第M列的4个并行输出的数据进行并串转换操作，即第M-1列的输出和第M列的并串转换操作同步进行，其余任意相邻的两列数据均满足此规律。例如，对第M列的4个并行输出的像素数据进行并串转换操作后形成图5所示的横向的串行数据流，从而可以使得不相邻的像素数据可以依次逐个输出。
例如，通过上述步骤传输的串行数据流在遇到噪声等干扰发生数据丢失或传输错误时，由于其传输的像素数据两两之间互不相邻，使得传输错误或丢失的是间隔的像素数据而不是连续的像素数据，因此传输错误或丢失的像素数据可以根据其位于原图像中未丢失的且与其相邻的地址单元中的像素数据恢复，例如，通过对与其邻近的像素数据进行数学拟合计算，例如插值法等，修改出现传输错误的数据或填补丢失的数据，类似于RGB(YCbCr4:4:4)转为YCbCr4:2:0。由于人眼分辨能力有限，小部分差异并不会破坏画面感官， 因此，该方法基本上不会影响图像的显示效果，从而可以降低数据传输过程中由于信道噪声等干扰带来的影响，提高显示面板的显示质量。
例如，M表示交错数据个数，M-1表示交错数据间隔。例如，当M＝10，N＝n＝40时，图4所示的第一缓存空间的每行包括10个数据，第1个(1st)数据和第(n/4)+1个(即11th)数据之间间隔了M-1＝9个数据(即第2至n/4(即第10个数据))。例如，当该第1个数据和第(n/4)+1个数据之间丢失一个数据时，即交错数据间隔变为8，那么第(n/4)+2(即第12th)个数据会写入第(n/4)+1个数据的位置，以此类推……，从而在选取数据子集时造成混乱。因此，可以通过监测该交错数据间隔保证各行数据地址的间隔是正确的，从而可以有序的选取数据子集，保证像素数据的正常读取。
例如，可以提供数据子集选取单元，并通过该数据子集选取单元将N个连续的数据重新组合为M个数据子集；例如，也可以通过中央处理单元(CPU)、图像处理器(GPU)、张量处理器(TPU)、现场可编程逻辑门阵列(FPGA)或者具有数据处理能力和/或指令执行能力的其它形式的处理单元以及相应的计算机指令来实现数据子集选取单元。
对于步骤S130，例如，可以串行或并行传输M个数据子集。图6为本公开一实施例提供的一种串行传输M个数据子集的示意图。例如，图5中所示的M个并行输出的数据子集分别通过并串转换操作依次转换成串行数据流后进行传输，从而形成如图6中所示的地址不连续的串行数据流。例如，该串行数据流包括上述N个数据，但该N个数据的地址按照选取的M个数据子集中的顺序排列。例如，将该串行数据流传输至信号接收端，例如，第二缓存空间。例如，在一个示例中，在VR系统中，该串行数据流的发送端为AP(应用处理器)，信号接收端为显示面板的驱动电路。
例如，可以提供传输单元，并通过该传输单元传输M个数据子集；例如该传输单元可以是有线单元或无线传输单元。该有线传输可以为电信号传输装置或光信号传输装置，电信号传输装置通过例如同轴电缆传输数据，光信号传输装置例如通过光纤传输数据，并且它们基于各自相关数据传输标准，例如同步数字体系(SDH)、密集波分复用(DWDM)等。该无线传输单元可以基于各种标准的无线通信装置，例如WIFI、蓝牙、ZigBee、红外、2G/3G/4G/5G移动通信等。例如，传输单元包括中央处理单元(CPU)、图 像处理器(GPU)、张量处理器(TPU)、现场可编程逻辑门阵列(FPGA)或者具有数据处理能力和/或指令执行能力的其它形式的处理单元以及相应的计算机指令。
本公开上述实施例提供的图像数据处理方法，可以通过改变数据传输过程中的数据传输顺序，降低信道噪声等干扰对传输数据的影响，不需要占用额外的传输带宽，提高信号接收端接收的数据质量，且实现过程比较简单，有利于简化后续信号处理过程，以及降低设备的运行功耗和制造成本，提高设备的响应速度。
图7为本公开一些实施例提供的另一种图像数据处理方法的流程图。如图7所示，本公开一些实施例提供的图像数据处理方法还可以对传输的数据子集进行读取和校验，以及根据校验结果对传输的数据进行填补和修改。如图7所示，该图像数据处理方法还包括步骤S140至步骤S170。下面，参考图7对该图像数据处理方法进行说明。
步骤S140：接收传输的M个数据子集，并且提取M个数据子集每个包括的数据至第二缓存空间。
例如，在第二缓存空间中基于第一规则恢复按照第一顺序依次排列的N个连续的数据，例如，使得第二缓存空间和第一缓存空间中的存储数据的排列顺序相同。例如，该第二缓存空间为矩阵缓存空间，且与第一缓存空间相同。例如，该步骤类似于对上述步骤S120和步骤S130中形成的串行数据流进行解码，以将其恢复为按照第一顺序依次排列的N个连续的数据，例如，恢复为在图4中所示的矩阵缓存空间中的排列方式。例如，在信号输出端按照数据传输之前的排列规律将相应的像素数据读取至相应的位置。因此，本公开实施例的图像数据处理方法虽然改变了数据的传输顺序，但可以通过动态寻址读取传输的像素数据至原先的位置，从而不影响显示面板的显示内容，提高显示面板的显示质量。
例如，可以提供读取单元，并通过该读取单元接收传输的M个数据子集，并且提取M个数据子集每个包括的数据至第二缓存空间；例如，也可以通过中央处理单元(CPU)、图像处理器(GPU)、张量处理器(TPU)、现场可编程逻辑门阵列(FPGA)或者具有数据处理能力和/或指令执行能力的其它形式的处理单元以及相应的计算机指令来实现读取单元。
步骤S150：对第二缓存空间中的每个数据执行校验。
在传输过程中，由于信道噪声等干扰的存在，会发生数据传输错误(某个字节由1变0，或由0变1)或丢失的情况，因此需要对传输后的数据(即第二缓存空间中的数据)执行校验。例如，可以基于各种数据校验方法，例如奇偶校验、海明校验、循环冗余码(CRC)校验等，例如，还可以通过将第二缓存空间中的数据与原始数据(例如，第一缓存空间中的数据)进行比较，判断是否相同来执行校验。
例如，可以提供校验单元，并通过该校验单元对第二缓存空间中的每个数据执行校验；例如，也可以通过中央处理单元(CPU)、图像处理器(GPU)、张量处理器(TPU)、现场可编程逻辑门阵列(FPGA)或者具有数据处理能力和/或指令执行能力的其它形式的处理单元以及相应的计算机指令来实现校验单元。
步骤S160：判断第二缓存空间中是否有传输错误或丢失的数据，如果有，则执行步骤S170。
例如，根据步骤S150中的数据校验结果，可判断是否发生数据传输错误或丢失的情况。例如，如果第二缓存空间中的数据与原始传输数据不同，则说明数据在传输过程中出现了传输错误；如果在第二缓存空间中的数据少于原始数据，则说明在数据传输过程中丢失了相应的数据。
步骤S170：根据插值法修改出现传输错误的数据或填补丢失的数据。
由于通过步骤S110-步骤S130传输的像素数据两两之间互不相邻，使得传输错误或丢失的数据是间隔的像素数据而不是连续的像素数据，因此该传输错误或丢失的像素数据可以根据其位于原图像中未丢失的且与其相邻的地址单元中的像素数据恢复。例如，可以通过对与其邻近的像素数据进行数学拟合计算，例如插值法等，修改出现传输错误的数据或填补丢失的数据，从而可以降低数据传输过程中由于信道噪声等干扰带来的影响，提高显示面板的显示质量。例如，当某一项数据出现错误时，以与该项数据相邻的前一项数据和后一项数据的算术平均值来对该项数据赋值，并将新的数据用于后续的显示操作。
例如，在第二缓存空间中基于第一规则恢复按照第一顺序依次排列的N个连续的数据之后，或者，在上述步骤S170之后，为了进行显示操作，还 可以包括：对N个连续的数据进行滤波处理。
例如，可以采用高斯滤波、中值滤波等常用的滤波方法对接收的数据实现滤波处理，从而弱化传输过程中产生的噪声，提高显示数据的质量，从而提高显示面板的显示质量。
需要说明的是，在本公开的实施例中，该图像数据处理方法的流程可以包括更多或更少的操作，这些操作可以顺序执行或并行执行。虽然上文描述的图像数据处理方法的流程包括特定顺序出现的多个操作，但是应该清楚地了解，多个操作的顺序并不受限制。上文描述的图像数据处理方法可以执行一次，也可以按照预定条件执行多次。
图8位本公开一些实施例提供的一种图像显示方法的流程图。例如，如图8所示，该图像显示方法包括步骤S210至步骤S230。下面，参考图8对图像显示方法进行说明。
步骤S210：获取待显示图像的像素数据。
例如，该待显示图像的像素数据矩阵包括m*n个像素数据(例如，包括如图1所示的像素数据A1,1、A1,2、…、Am,n)。
步骤S220：逐行传输待显示图像的像素数据。
例如，可以通过上述步骤S110至步骤S170逐行传输待显示图像的像素数据，从而可以降低数据传输过程中由于信道噪声等干扰带来的影响，当每一行数据被显示面板的数据驱动电路接收并缓存之后，在显示面板的逐行扫描显示操作中被施加到一行像素单元中显示，从而可以获得较高的显示质量。具体的图像数据处理方法可参考上述步骤S110至步骤S170的详细介绍，在此不再赘述。
步骤S230：将像素数据逐行输出至显示面板以用于显示。
例如，通过步骤S220将像素数据逐行传输至显示面板的数据驱动电路，由数据驱动电路接收并缓存一行数据信号之后，再通过数据线将像素数据逐行输出对应的一行像素单元，以实现显示面板相应的显示。
本公开上述实施例提供的图像显示方法的技术效果可以参考本公开的实施例中提供的图像数据处理方法的技术效果，这里不再赘述。
图9位本公开一些实施例提供的一种数据传输装置的示意框图。例如，在图9所示的示例中，该数据传输装置100包括缓存单元110、数据子集选 取单元120和传输单元130。例如，这些单元可以通过硬件(例如电路)模块或软件模块等实现。
该缓存单元110配置为将待传输的对象数据集合存储至第一缓存空间。例如，该对象数据集合包括按照第一顺序依次排列的N个连续的数据。例如，该缓存单元110可以实现步骤S110，其具体实现方法可以参考步骤S110的相关描述，在此不再赘述。
该数据子集选取单元120配置为将N个连续的数据重新组合为M个数据子集。例如，每个数据子集包括按照第一规则从N个连续的数据中依次选取的N/M个互不相邻的数据。例如，该数据子集选取单元120可以实现步骤S120，其具体实现方法可以参考步骤S120的相关描述，在此不再赘述。
该传输单元130配置为传输M个数据子集。例如，该传输单元130可以实现步骤S130，其具体实现方法可以参考步骤S130的相关描述，在此不再赘述。
例如，在另一个示例中，该数据传输装置100还包括读取单元和校验单元(图中未示出)。
例如，该读取单元配置为接收传输的M个数据子集，并且提取M个数据子集每个包括的数据至第二缓存空间。例如，在第二缓存空间中基于第一规则恢复按照第一顺序依次排列的N个连续的数据。例如，该读取单元可以实现步骤S140，其具体实现方法可以参考步骤S140的相关描述，在此不再赘述。
该校验单元配置为在第二缓存空间中基于第一规则恢复按照第一顺序依次排列的N个连续的数据之后，对第二缓存空间中的每个数据执行校验。例如，如果出现传输错误或丢失的数据，可以根据插值法修改出现传输错误的数据或填补丢失的数据。例如，该校验单元可以实现步骤S150至步骤S170，其具体实现方法可以参考步骤S150至步骤S170的相关描述，在此不再赘述。
需要注意的是，在本公开实施例提供的数据传输装置中，可以包括更多或更少的电路或单元，并且各个电路或单元之间的连接关系不受限制，可以根据实际需求而定。各个电路的具体构成方式不受限制，可以根据电路原理由模拟器件构成，也可以由数字芯片构成，或者以其他适用的方式构成。
图10为本公开一些实施例提供的另一种数据传输装置的示意框图。如图 10所示，该数据传输装置200包括处理器210、存储器220以及一个或多个计算机程序模块221。
例如，处理器210与存储器220通过总线系统230连接。例如，一个或多个计算机程序模块221被存储在存储器220中。例如，一个或多个计算机程序模块221包括用于执行本公开任一实施例提供的图像数据处理方法的指令。例如，一个或多个计算机程序模块221中的指令可以由处理器210执行。例如，总线系统230可以是常用的串行、并行通信总线等，本公开的实施例对此不作限制。
例如，该处理器210可以是中央处理单元(CPU)、图像处理器(GPU)或者具有数据处理能力和/或指令执行能力的其它形式的处理单元，可以为通用处理器或专用处理器，并且可以控制数据传输装置200中的其它组件以执行期望的功能。
存储器220可以包括一个或多个计算机程序产品，该计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易失性存储器。该易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。该非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器210可以运行该程序指令，以实现本公开实施例中(由处理器210实现)的功能以及/或者其它期望的功能，例如图像数据处理方法等。在该计算机可读存储介质中还可以存储各种应用程序和各种数据，例如各个数据子集以及应用程序使用和/或产生的各种数据等。
需要说明的是，为表示清楚、简洁，本公开实施例并没有给出该数据传输装置200的全部组成单元。为实现数据传输装置200的必要功能，本领域技术人员可以根据具体需要提供、设置其他未示出的组成单元，本公开的实施例对此不作限制。
关于不同实施例中的数据传输装置100和数据传输装置200的技术效果可以参考本公开的实施例中提供的图像数据处理方法的技术效果，这里不再赘述。
本公开一实施例还提供一种存储介质。图11为本公开一些实施例提供的一种存储介质的示意图。例如，该存储介质300非暂时性地存储计算机可读 指令301，当非暂时性计算机可读指令301由计算机(包括处理器)执行时可以执行本公开任一实施例提供的图像数据处理方法。
例如，该存储介质可以是一个或多个计算机可读存储介质的任意组合，例如一个计算机可读存储介质包含将待传输的对象数据集合存储至第一缓存空间的计算机可读的程序代码，另一个计算机可读存储介质包含提取M个数据子集的计算机可读的程序代码。例如，当该程序代码由计算机读取时，计算机可以执行该计算机存储介质中存储的程序代码，执行例如本公开任一实施例提供的图像数据处理方法。
例如，存储介质可以包括智能电话的存储卡、平板电脑的存储部件、个人计算机的硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM)、便携式紧致盘只读存储器(CD-ROM)、闪存、或者上述存储介质的任意组合，也可以为其他适用的存储介质。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (15)

  1. 一种图像数据处理方法，包括：
    将待传输的对象数据集合存储至第一缓存空间，其中，所述对象数据集合包括按照第一顺序依次排列的N个连续的图像数据；
    将所述N个连续的图像数据重新组合为M个数据子集，其中，每个数据子集包括按照第一规则从所述N个连续的图像数据中依次选取的N/M个互不相邻的图像数据；
    传输所述M个数据子集；
    其中，M为大于1的整数，N是M的大于1的整数倍。
  2. 根据权利要求1所述的图像数据处理方法，其中，所述按照第一顺序依次排列的N个连续的图像数据包括按照从第1个至第N个的顺序依次排列的N个连续的图像数据。
  3. 根据权利要求1或2所述的图像数据处理方法，还包括：
    接收传输的所述M个数据子集，并且提取所述M个数据子集每个包括的图像数据至第二缓存空间，
    其中，在所述第二缓存空间中基于所述第一规则恢复按照所述第一顺序依次排列的所述N个连续的图像数据。
  4. 根据权利要求3所述的图像数据处理方法，其中，在所述第二缓存空间中基于所述第一规则恢复按照所述第一顺序依次排列的所述N个连续的图像数据之后，
    对所述第二缓存空间中的每个数据执行校验，如果出现传输错误或丢失的图像数据，根据插值法修改出现所述传输错误的图像数据或填补所述丢失的图像数据。
  5. 根据权利要求1-4任一所述的图像数据处理方法，其中，所述第一规则包括：以L为周期，循环选择所述数据子集，其中，L为大于1的整数。
  6. 根据权利要求5所述的图像数据处理方法，其中，所述第一缓存空间为矩阵缓存空间，所述矩阵缓存空间包括L*M个图像数据。
  7. 根据权利要求6所述的图像数据处理方法，其中，以L为周期，循环选择所述数据子集，包括：
    按列逆序的方式依次输出所述矩阵缓存空间的第M列、第M-1列、…、第M-i列、……、第1列中的图像数据分别作为所述数据子集；
    其中，每列中包括L个互不相邻的图像数据，
    i为大于1小于M的整数。
  8. 根据权利要求7所述的图像数据处理方法，其中，在所述第M-i列中的第L个图像数据写入所述矩阵缓存空间后，并行输出所述第M-i列中的图像数据。
  9. 根据权利要求7或8所述的图像数据处理方法，其中，在并行输出所述第M-i列中的图像数据时，对第M-(i-1)列中的图像数据进行并串转换操作以将所述第M-(i-1)列中的图像数据转换为串行数据。
  10. 一种图像显示方法，包括：
    获取待显示图像的像素数据；
    采用如权利要求1-9任一所述的图像数据处理方法逐行传输所述待显示图像的像素数据；
    将所述像素数据逐行输出至显示面板以用于显示。
  11. 一种数据传输装置，包括：
    缓存单元，配置为将待传输的对象数据集合存储至第一缓存空间，其中，所述对象数据集合包括按照第一顺序依次排列的N个连续的图像数据；
    数据子集选取单元，配置为将所述N个连续的图像数据重新组合为M个数据子集，其中，每个数据子集包括按照第一规则从所述N个连续的图像数据中依次选取的N/M个互不相邻的图像数据；
    传输单元，配置为传输所述M个数据子集；
    其中，M为大于1的整数，N是M的大于1的整数倍。
  12. 根据权利要求11所述的数据传输装置，还包括：
    读取单元，配置为接收传输的所述M个数据子集，并且提取所述M个数据子集每个包括的图像数据至第二缓存空间，
    其中，在所述第二缓存空间中基于所述第一规则恢复按照所述第一顺序依次排列的所述N个连续的图像数据。
  13. 根据权利要求12所述的数据传输装置，还包括：
    校验单元，配置为在所述第二缓存空间中基于所述第一规则恢复按照所 述第一顺序依次排列的所述N个连续的图像数据之后，对所述第二缓存空间中的每个图像数据执行校验，如果出现传输错误或丢失的图像数据，根据插值法修改出现所述传输错误的图像数据或填补所述丢失的图像数据。
  14. 一种数据传输装置，包括：
    处理器；
    存储器；一个或多个计算机程序模块，所述一个或多个计算机程序模块被存储在所述存储器中并被配置为由所述处理器执行，所述一个或多个计算机程序模块包括用于执行实现权利要求1-9任一所述的图像数据处理方法的指令。
  15. 一种存储介质，非暂时性地存储计算机可读指令，当所述非暂时性计算机可读指令由计算机执行时可以执行根据权利要求1-9任一所述的图像数据处理方法的指令。
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