WO2020139955A1 - Annular capacitor rf, microwave and mm wave systems - Google Patents

Annular capacitor rf, microwave and mm wave systems Download PDF

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Publication number
WO2020139955A1
WO2020139955A1 PCT/US2019/068590 US2019068590W WO2020139955A1 WO 2020139955 A1 WO2020139955 A1 WO 2020139955A1 US 2019068590 W US2019068590 W US 2019068590W WO 2020139955 A1 WO2020139955 A1 WO 2020139955A1
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WIPO (PCT)
Prior art keywords
substrate
metal
depositing
trench
annular shape
Prior art date
Application number
PCT/US2019/068590
Other languages
French (fr)
Inventor
Jeb H. Flemming
Original Assignee
3D Glass Solutions, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3D Glass Solutions, Inc. filed Critical 3D Glass Solutions, Inc.
Priority to AU2019416327A priority Critical patent/AU2019416327B2/en
Priority to KR1020217014441A priority patent/KR102392858B1/en
Priority to US17/259,887 priority patent/US11270843B2/en
Priority to JP2021503065A priority patent/JP7257707B2/en
Priority to CA3107812A priority patent/CA3107812C/en
Priority to EP19905255.6A priority patent/EP3903339A4/en
Publication of WO2020139955A1 publication Critical patent/WO2020139955A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/248—Terminals the terminals embracing or surrounding the capacitive element, e.g. caps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/40—Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers

Definitions

  • the present invention relates in general to the field of creating a planar surface between via(s) and other structures and the substrate used for RF microwave and millimeter wave applications reducing device/system size and lowering parasitic noise and signals.
  • Planarizing generally uses a form of chemical mechanical polishing (CMP) of the substrate and structure on/in the substrate to bring the surface to be flat and parallel.
  • CMP chemical mechanical polishing
  • the challenge is that the substrates are quite hard relative to the other material on or in the substrate.
  • boron silicate quartz and silicon have a hardness between 6 to 7 Mohs while typical metals (copper, gold and silver) used in high frequency application have a hardness of 2.5 to 3 Mohs.
  • This hardness differential creates a fundamental problem when using CMP to planarize the surface.
  • the softer metal structures are removed at a higher rate than the harder substrate. This creates a lower surface in the metal structure relative to the surface of the harder substrate.
  • the transition from substrate to metal structure can be as great as 0.5 pm. In general, the magnitude of the depth of this transition is not uniform across a wafer. This transition or step creates a random thinning of structures/devices that are made on top of, or that cross the substrate metal transition.
  • Variations in the thickness results in random capacitors across the die/substrate, creating random capacitance and filters RF, millimeter, and microwave circuits making the circuit/device. Placing a filter, capacitor, other passive device or/or active device adjacent and greater than 250 pm from the via induces parasitic inductance from the metal trace between the passive device and the via/imbedded metal structure.
  • the passive device can be placed in conjunction with active devices and can be combined to make a wide array of RF systems and subsystems including: antennas with gain, RF Circulators, RF Isolators, RF Combiners, RF Couplers, RF Splitters, Transformers, Switches, Multiplexors, Duplexers, and/or Diplexers that are connected by via as well as metal lines and via to each other and ground planes.
  • FIG. 1 shows a schematic of an annular RF shunt capacitor.
  • FIG. 2 shows a schematic of an annular RF shunt capacitor with dimensional information between the adjacent annular element and the via.
  • FIG. 3 shows a schematic of a cross section for annular RF shunt capacitor.
  • FIGS. 4A to 4F show a step-by-step method of making the device of the present invention.
  • FIGS. 4A and 4B show cross-sectional side views of two of the steps of the method.
  • FIGS. 4C to 4F show the remained of the steps for making the annular capacitor RF, microwave and millimeter (MM) wave systems of the present invention.
  • MM millimeter
  • the present invention includes a method for creating a substrate, an annular capacitor structure where the adjacent edge of the capacitive structure less than 250 pm of the via or imbedded metal structure in the substrate eliminates or minimizes the inductance associated with the metal line.
  • FIG. 1 shows an example of the device 10, that includes ports 12 and 14 that connect to a top metal 16, which can be a copper layer that connected to, or shunted, to a through-via hole 18.
  • the design of the present invention reduces the variability from the capacitor build. In this design, the through-via hole is formed but does not affect the capacitor, thus eliminating that variable from design consideration(s).
  • a top insulator 20 is positioned between the top metal 16 at the via 18, and a second metal layer 22 is deposited on the insulator 20. The structure is formed in a substrate 24.
  • FIG. 2 shows an internal view of the device 10, that shows the gap 26, between the through-hole via 18 and the first metal layer 16. Ports 12 and 14 that connect to a top metal 16, which can be a copper layer that connected to, or shunted, to a through-via hole 18.
  • FIG. 3 is a cross-section side view of the device 10. Ports 12 and 14 are shown in this configuration as being on opposite sides of the through-hole via 18, which is isolated from the top metal layer 16 and the second top metal layer 22, by insulator 20. A bottom metal ground plane 28 is depicted connected to through-hole via 18.
  • Table 1 and FIGS. 4A to 4F show a step-by-step method of making the device 10 of the present invention. The process flow to create a planarized surface in a substrate with dissimilar materials to eliminate vertical transitions from a substrate to an added material is as follows:
  • the words“comprising” (and any form of comprising, such as“comprise” and“comprises”),“having” (and any form of having, such as “have” and“has”),“including” (and any form of including, such as“includes” and“include”) or“containing” (and any form of containing, such as“contains” and“contain”) are inclusive or open-ended and do not exclude additional, unrecited elements or method steps.
  • “comprising” may be replaced with“consisting essentially of’ or“consisting of’.
  • the phrase “consisting essentially of’ requires the specified integer(s) or steps as well as those that do not materially affect the character or function of the claimed invention.
  • the term “consisting” is used to indicate the presence of the recited integer (e.g., a feature, an element, a characteristic, a property, a method/process step or a limitation) or group of integers (e.g., feature(s), element(s), characteristic(s), property(ies), method/process steps or limitation(s)) only.
  • words of approximation such as, without limitation, “about”, “substantial” or “substantially” refers to a condition that when so modified is understood to not necessarily be absolute or perfect but would be considered close enough to those of ordinary skill in the art to warrant designating the condition as being present.
  • the extent to which the description may vary will depend on how great a change can be instituted and still have one of ordinary skilled in the art recognize the modified feature as still having the required characteristics and capabilities of the unmodified feature.
  • a numerical value herein that is modified by a word of approximation such as“about” may vary from the stated value by at least ⁇ 1, 2, 3, 4, 5, 6, 7, 10, 12 or 15%.
  • compositions and/or methods disclosed and claimed herein can be made and executed without undue experimentation in light of the present disclosure. While the compositions and methods of this invention have been described in terms of preferred embodiments, it will be apparent to those of skill in the art that variations may be applied to the compositions and/or methods and in the steps or in the sequence of steps of the method described herein without departing from the concept, spirit and scope of the invention. All such similar substitutes and modifications apparent to those skilled in the art are deemed to be within the spirit, scope and concept of the invention as defined by the appended claims.

Abstract

The present invention includes a method for creating an annular capacitor adjacent to via or imbedded metal structure allowing for device to be made in close proximity to the via connecting to a ground plane. The annular capacitor in close proximity to the metal filled via or imbedded metal structure allows the construction of capacitors, filters, or active devices enabling a smaller RF device and/or to shunt a signal to the integrated ground plane. This reduces the RF, Electronic noise and results in a reduced device size.

Description

ANNULAR CAPACITOR RF, MICROWAVE AND MM WAVE SYSTEMS
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This PCT International Patent Application claims priority to U.S. Provisional Patent Application Serial No. 62/786,165 filed December 28, 2018, the contents of which is incorporated by reference herein in its entirety.
STATEMENT OF FEDERALLY FUNDED RESEARCH
[0002] None.
TECHNICAL FIELD OF THE INVENTION
[0003] The present invention relates in general to the field of creating a planar surface between via(s) and other structures and the substrate used for RF microwave and millimeter wave applications reducing device/system size and lowering parasitic noise and signals.
SUMMARY OF THE INVENTION
[0004] Without limiting the scope of the invention, its background is described in connection with creating a planar surface between vias and other structures and the substrate used for RF, microwave, and millimeter wave applications. The fundamental problem is the metals that fill a via or other metal structures in/on a substrate. Planarizing generally uses a form of chemical mechanical polishing (CMP) of the substrate and structure on/in the substrate to bring the surface to be flat and parallel. The challenge is that the substrates are quite hard relative to the other material on or in the substrate. As an example, boron silicate quartz and silicon have a hardness between 6 to 7 Mohs while typical metals (copper, gold and silver) used in high frequency application have a hardness of 2.5 to 3 Mohs. This hardness differential creates a fundamental problem when using CMP to planarize the surface. The softer metal structures are removed at a higher rate than the harder substrate. This creates a lower surface in the metal structure relative to the surface of the harder substrate. The transition from substrate to metal structure can be as great as 0.5 pm. In general, the magnitude of the depth of this transition is not uniform across a wafer. This transition or step creates a random thinning of structures/devices that are made on top of, or that cross the substrate metal transition.
[0005] At low frequencies, that solution is to simply create the device in the planar field of the substrate and run a metal interconnected to the metal structure such as a via or imbedded metal structure. Unfortunately, at RF, millimeter, and microwave frequencies this metal run creates to a via or imbedded metal structure, which creates additional inductive parasitic inductance and damages the performance of the circuit. Moving the device over the physical transition means that the device will have a random thickness variation, often referred to as necking of passive devices thickness as the device transitions from the substrate to the via or imbedded metal structure. One example of this is the creation of a capacitor where the metal electrodes and dielectric layer are thinner over the substrate metal transition. Variations in the thickness results in random capacitors across the die/substrate, creating random capacitance and filters RF, millimeter, and microwave circuits making the circuit/device. Placing a filter, capacitor, other passive device or/or active device adjacent and greater than 250 pm from the via induces parasitic inductance from the metal trace between the passive device and the via/imbedded metal structure.
[0006] The passive device can be placed in conjunction with active devices and can be combined to make a wide array of RF systems and subsystems including: antennas with gain, RF Circulators, RF Isolators, RF Combiners, RF Couplers, RF Splitters, Transformers, Switches, Multiplexors, Duplexers, and/or Diplexers that are connected by via as well as metal lines and via to each other and ground planes.
[0007] Constructing passive devices as close as possible to the via that shunts parasitic and electrical noise to a ground plane dramatically improves performance and reduces the die size for RF, microwave, and millimeter electronic systems. This invention provides a general solution to the constructing passive device in intimate proximity to metalized via or buried structure eliminating connecting to a ground plane and eliminating the random device performance and parasitic across the device substrate metal transition.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] For a more complete understanding of the features and advantages of the present invention, reference is now made to the detailed description of the invention along with the accompanying figures and in which:
FIG. 1 shows a schematic of an annular RF shunt capacitor.
FIG. 2 shows a schematic of an annular RF shunt capacitor with dimensional information between the adjacent annular element and the via.
FIG. 3 shows a schematic of a cross section for annular RF shunt capacitor. FIGS. 4A to 4F show a step-by-step method of making the device of the present invention. FIGS. 4A and 4B show cross-sectional side views of two of the steps of the method. FIGS. 4C to 4F show the remained of the steps for making the annular capacitor RF, microwave and millimeter (MM) wave systems of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0009] While the production and use of various embodiments of the present invention are discussed in detail below, it should be appreciated that the present invention provides many applicable, inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the invention and do not delimit the scope of the invention. To facilitate the understanding of this invention, a number of terms are defined below. Terms defined herein have meanings as commonly understood by a person of ordinary skill in the areas relevant to the present invention.
[0010] In one embodiment, the present invention includes a method for creating a substrate, an annular capacitor structure where the adjacent edge of the capacitive structure less than 250 pm of the via or imbedded metal structure in the substrate eliminates or minimizes the inductance associated with the metal line.
[0011] FIG. 1 shows an example of the device 10, that includes ports 12 and 14 that connect to a top metal 16, which can be a copper layer that connected to, or shunted, to a through-via hole 18. The design of the present invention reduces the variability from the capacitor build. In this design, the through-via hole is formed but does not affect the capacitor, thus eliminating that variable from design consideration(s). A top insulator 20 is positioned between the top metal 16 at the via 18, and a second metal layer 22 is deposited on the insulator 20. The structure is formed in a substrate 24.
[0012] FIG. 2 shows an internal view of the device 10, that shows the gap 26, between the through-hole via 18 and the first metal layer 16. Ports 12 and 14 that connect to a top metal 16, which can be a copper layer that connected to, or shunted, to a through-via hole 18.
[0013] FIG. 3 is a cross-section side view of the device 10. Ports 12 and 14 are shown in this configuration as being on opposite sides of the through-hole via 18, which is isolated from the top metal layer 16 and the second top metal layer 22, by insulator 20. A bottom metal ground plane 28 is depicted connected to through-hole via 18. [0014] Table 1 and FIGS. 4A to 4F show a step-by-step method of making the device 10 of the present invention. The process flow to create a planarized surface in a substrate with dissimilar materials to eliminate vertical transitions from a substrate to an added material is as follows:
Figure imgf000005_0001
Figure imgf000006_0001
[0015] It will be understood that particular embodiments described herein are shown by way of illustration and not as limitations of the invention. The principal features of this invention can be employed in various embodiments without departing from the scope of the invention. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, numerous equivalents to the specific procedures described herein. Such equivalents are considered to be within the scope of this invention and are covered by the claims.
[0016] All publications and patent applications mentioned in the specification are indicative of the level of skill of those skilled in the art to which this invention pertains. All publications and patent applications are herein incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference.
[0017] The use of the word“a” or“an” when used in conjunction with the term“comprising” in the claims and/or the specification may mean“one,” but it is also consistent with the meaning of“one or more,”“at least one,” and“one or more than one.” The use of the term “or” in the claims is used to mean“and/or” unless explicitly indicated to refer to alternatives only or the alternatives are mutually exclusive, although the disclosure supports a definition that refers to only alternatives and“and/or.” Throughout this application, the term“about” is used to indicate that a value includes the inherent variation of error for the device, the method being employed to determine the value, or the variation that exists among the study subjects.
[0018] As used in this specification and claim(s), the words“comprising” (and any form of comprising, such as“comprise” and“comprises”),“having” (and any form of having, such as “have” and“has”),“including” (and any form of including, such as“includes” and“include”) or“containing” (and any form of containing, such as“contains” and“contain”) are inclusive or open-ended and do not exclude additional, unrecited elements or method steps. In embodiments of any of the compositions and methods provided herein,“comprising” may be replaced with“consisting essentially of’ or“consisting of’. As used herein, the phrase “consisting essentially of’ requires the specified integer(s) or steps as well as those that do not materially affect the character or function of the claimed invention. As used herein, the term “consisting” is used to indicate the presence of the recited integer (e.g., a feature, an element, a characteristic, a property, a method/process step or a limitation) or group of integers (e.g., feature(s), element(s), characteristic(s), property(ies), method/process steps or limitation(s)) only.
[0019] The term“or combinations thereof’ as used herein refers to all permutations and combinations of the listed items preceding the term. For example,“A, B, C, or combinations thereof’ is intended to include at least one of: A, B, C, AB, AC, BC, or ABC, and if order is important in a particular context, also BA, CA, CB, CBA, BCA, ACB, BAC, or CAB. Continuing with this example, expressly included are combinations that contain repeats of one or more item or term, such as BB, AAA, AB, BBC, AAABCCCC, CBBAAA, CABABB, and so forth. The skilled artisan will understand that typically there is no limit on the number of items or terms in any combination, unless otherwise apparent from the context.
[0020] As used herein, words of approximation such as, without limitation, “about”, "substantial" or "substantially" refers to a condition that when so modified is understood to not necessarily be absolute or perfect but would be considered close enough to those of ordinary skill in the art to warrant designating the condition as being present. The extent to which the description may vary will depend on how great a change can be instituted and still have one of ordinary skilled in the art recognize the modified feature as still having the required characteristics and capabilities of the unmodified feature. In general, but subject to the preceding discussion, a numerical value herein that is modified by a word of approximation such as“about” may vary from the stated value by at least ±1, 2, 3, 4, 5, 6, 7, 10, 12 or 15%.
[0021] All of the compositions and/or methods disclosed and claimed herein can be made and executed without undue experimentation in light of the present disclosure. While the compositions and methods of this invention have been described in terms of preferred embodiments, it will be apparent to those of skill in the art that variations may be applied to the compositions and/or methods and in the steps or in the sequence of steps of the method described herein without departing from the concept, spirit and scope of the invention. All such similar substitutes and modifications apparent to those skilled in the art are deemed to be within the spirit, scope and concept of the invention as defined by the appended claims.

Claims

What is claimed is:
1. A method for creating a capacitor for RF, millimeter or microwave device that at least partially circumscribes a metal filled via or trench based transmission line that connects a passive device or an active device and one or more ground planes using the steps of:
cutting a trench or via in a first surface of a substrate;
filling the trench or via with a first metal layer, and optionally form on a second surface of the substrate opposite the first surface a ground plane;
coating, exposing, and developing photoresist into a first annular shape that circumscribes the trench or via on the first surface of the substrate;
depositing a first metal layer on the first surface of the substrate;
coating, exposing, and developing photoresist into a second annular shape that circumscribes the trench or via on the first surface of the substrate, where an inner radii of the second annular shape is between 2 pm and 300 pm from an outer edge of the metal filled via or trench, and an external radii of the second annular shape is between 10 pm and 500 pm;
depositing a dielectric material on the first surface of the substrate to form a dielectric layer;
coating, exposing, and developing photoresist in third annular shape on the first surface of the substrate, wherein the third annular shape is at least 2 pm greater than the dielectric layer and wherein at least a portion of the third annular shape transitions to one or more active or passive devices of a circuit;
depositing a second metal layer on the first surface of the substrate;
coating, exposing, and developing photoresist to connect the second metal between the first and second surfaces of the substrate; and
depositing a metal to connect the first metal layer and a ground plane on the second surfaces of the substrate to form an electrode on the first surface of the substrate.
2. The method of claim 1, further produces a transition less than 0.1pm.
3. The method of claim 1, further comprising an adhesion layer between at least one of a side or bottom on the trench or via in the substrate prior to depositing the first metal layer.
4. The method of claim 1, further comprising depositing an adhesion layer prior to depositing the second metal layer.
5. The method of claim 1, wherein the metal is copper, silver, gold, aluminum, or a metal alloy.
6. The method of claim 1, wherein the one or more active or passive devices is at least one of: RF Filters, RF Circulators, RF Isolators, Antenna, Impedance Matching Elements, 50 Ohm Termination Elements, Integrated Ground Planes, RF Shielding Elements, EMI Shielding Elements, RF Combiners, RF Splitters, Transformers, Switches, power splitters, power combiners, Duplexer, or Diplexers on the first surface of the substrate to one or more input/output ports.
7. The method of claim 6, wherein the device is a RF Circuit that eliminates at least 95% of the RF parasitic signal associated with the transition from a substrate to the embedded metal.
8. The method of claim 6, wherein the device is a RF Circuit that eliminates at least 85% of the RF parasitic signal associated with the packaging a mount elements to a substrate.
9. The method of claim 6, wherein the device is a RF Circuit that eliminates at least 75% of the RF parasitic signal associated with the packaging a mount elements to a substrate.
10. The method of claim 1, wherein the substrate or the dielectric is a photodefinable glass.
11. The method of claim 1 , wherein the electrode comprises a first and a second port.
12. An electrode comprising a capacitor for RF, millimeter or microwave device that at least partially circumscribes a metal filled via or trench based transmission line that connects a passive device or an active device and one or more ground planes, wherein the electrode is made by a method comprising:
cutting a trench or via in a first surface of a substrate;
filling the trench or via with a first metal layer, and optionally on a second surface of the substrate opposite the first surface;
coating, exposing, and developing photoresist into a first annular shape that circumscribes the trench or via on the first surface of the substrate;
depositing a first metal layer on the first surface of the substrate; coating, exposing, and developing photoresist into a second annular shape that circumscribes the trench or via on the first surface of the substrate, where an inner radii of the second annular shape is between 2 pm and 300 pm from an outer edge of the metal filled via or trench, and an external radii of the second annular shape is between 10 pm and 500 pm;
depositing a dielectric material on the first surface of the substrate to form a dielectric layer;
coating, exposing, and developing photoresist in third annular shape on the first surface of the substrate, wherein the third annular shape is at least 2 pm greater than the dielectric layer and wherein at least a portion of the third annular shape transitions to one or more active or passive devices of a circuit;
depositing a second metal layer on the first surface of the substrate;
coating, exposing, and developing photoresist to connect the second metal between the first and second surfaces of the substrate; and
depositing a metal to connect the first metal layer and a ground plane on the second surfaces of the substrate to form the electrode on the first surface of the substrate.
13. The method of claim 1, further produces a transition less than 0.1pm.
14. The method of claim 1, further comprising an adhesion layer between at least one of a side or bottom on the trench or via in the substrate prior to depositing the first metal layer.
15. The method of claim 1, further comprising depositing an adhesion layer prior to depositing the second metal layer.
16. The method of claim 1, wherein the metal is copper, silver, gold, aluminum, or a metal alloy.
17. The method of claim 1, wherein the one or more active or passive devices is at least one of: RF Filters, RF Circulators, RF Isolators, Antenna, Impedance Matching Elements, 50 Ohm Termination Elements, Integrated Ground Planes, RF Shielding Elements, EMI
Shielding Elements, RF Combiners, RF Splitters, Transformers, Switches, power splitters, power combiners, Duplexer, or Diplexers on the first surface of the substrate to one or more input/output ports.
18. The method of claim 6, wherein the device is a RF Circuit that eliminates at least 95% of the RF parasitic signal associated with the transition from a substrate to the embedded
19. The method of claim 6, wherein the device is a RF Circuit that eliminates at least 85% of the RF parasitic signal associated with the packaging a mount elements to a substrate.
20. The method of claim 6, wherein the device is a RF Circuit that eliminates at least 75% of the RF parasitic signal associated with the packaging a mount elements to a substrate.
21. The method of claim 1, wherein the substrate or the dielectric is a photodefmable glass.
22. The method of claim 1, wherein the electrode comprises a first and a second port.
PCT/US2019/068590 2018-12-28 2019-12-26 Annular capacitor rf, microwave and mm wave systems WO2020139955A1 (en)

Priority Applications (6)

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KR20210060636A (en) 2021-05-26
JP7257707B2 (en) 2023-04-14
US20210225591A1 (en) 2021-07-22
US11270843B2 (en) 2022-03-08
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CA3107812A1 (en) 2020-07-02
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