WO2020133261A1 - Dispositif électronique et procédé de transmission de signaux de commande interpuce - Google Patents

Dispositif électronique et procédé de transmission de signaux de commande interpuce Download PDF

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Publication number
WO2020133261A1
WO2020133261A1 PCT/CN2018/125019 CN2018125019W WO2020133261A1 WO 2020133261 A1 WO2020133261 A1 WO 2020133261A1 CN 2018125019 W CN2018125019 W CN 2018125019W WO 2020133261 A1 WO2020133261 A1 WO 2020133261A1
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WO
WIPO (PCT)
Prior art keywords
chip
control
control message
control signals
control signal
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PCT/CN2018/125019
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English (en)
Chinese (zh)
Inventor
周纪
阳宇
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华为技术有限公司
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Priority to PCT/CN2018/125019 priority Critical patent/WO2020133261A1/fr
Publication of WO2020133261A1 publication Critical patent/WO2020133261A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof

Definitions

  • the present application relates to the field of data transmission between slices, in particular to an electronic device and a method for transmitting control signals between slices.
  • control signals are usually transmitted between chips.
  • some control signals can be transmitted through a dedicated control bus. These control signals follow the protocol of the control bus and realize the control functions specified in the protocol. The other part of the control signal cannot be transmitted through the dedicated control bus, because these control signals follow the manufacturer's custom protocol to implement the manufacturer's specific control functions.
  • Embodiments of the present application provide an electronic device and a method for transmitting control signals between chips, which are used to reduce the number of pins for transmitting control signals between chips.
  • an electronic device including: a first chip and a second chip, the first chip is a control chip, the second chip is a controlled chip; the first chip and the second chip A serial data interface is connected between the chips; the first chip is used to: obtain N control signals; encode the N control signals to obtain control messages; and pass the serial data interface to the second chip Sending the control message, where N is a positive integer; the second chip is used to: receive the control message from the first chip through the serial data interface; decode the control message to obtain The N control signals; perform operations according to the N control signals.
  • the electronic device provided by the embodiment of the present application uses a serial data interface to transmit N control signals, so that the number of pins for transmitting control signals between the first chip and the second chip can be greatly reduced, and the transmission between chips is reduced.
  • the number of control signal pins is not limited to the number of control signal pins.
  • a timing line is further connected between the first chip and the second chip, and the first chip is further used to: send timing to the second chip through the timing line Pulse, the timing pulse is used for time synchronization between the first timer of the first chip and the second timer of the second chip; the control message also includes a count value of the first timer, The count value of the first timer is used to indicate the effective time of the control signal in the control message.
  • This embodiment can achieve precise control of the effective time of the control signal.
  • control message includes N cells, and each control signal of the N control signals occupies one cell of the N cells.
  • This embodiment provides a possible way of carrying N control signals in the control message.
  • control message includes a first cell and a second cell, the first cell represents a type of one of the N control signals, and the second cell Represents the value of the one control signal.
  • This embodiment provides another possible way of carrying N control signals in the control message.
  • the start position of the control message further includes a preamble, and the preamble is used to indicate that the control message is used to transmit a control signal.
  • This embodiment can distinguish between control signals and data signals.
  • the end position of the control message further includes error checking and correction ECC check. This embodiment can check and correct the control message.
  • an inter-chip control signal transmission method which includes: a first chip obtains N control signals, where N is a positive integer; and the first chip encodes the N control signals to obtain a control message
  • the first chip sends the control message to the second chip through the serial data interface; the second chip receives the control message through the first chip through the serial data interface; the second chip pair
  • the control message is decoded to obtain the N control signals; the second chip performs operations according to the N control signals.
  • the inter-chip control signal transmission method provided by the embodiment of the present application uses a serial data interface to transmit N control signals, so that the number of pins for transmitting control signals between the first chip and the second chip can be greatly reduced, reducing the chip The number of pins used to transmit control signals.
  • the method further includes: the first chip sends a timing pulse to the second chip through a timing line, and the timing pulse is used for the first timer of the first chip and The second timer of the second chip performs time synchronization; the control message further includes a count value of the first timer, wherein the count value of the first timer is used to indicate the control message The effective time of the control signal.
  • control message includes N cells, and each control signal of the N control signals occupies one cell of the N cells.
  • This embodiment provides a possible way of carrying N control signals in the control message.
  • control message includes a first cell and a second cell, the first cell represents a type of one of the N control signals, and the second cell Represents the value of the one control signal.
  • This embodiment provides another possible way of carrying N control signals in the control message.
  • the start position of the control message further includes a preamble, and the preamble is used to indicate that the control message is used to transmit a control signal.
  • This embodiment can distinguish between control signals and data signals.
  • the end position of the control message further includes error checking and correction ECC check. This embodiment can check and correct the control message.
  • a computer-readable storage medium storing one or more programs, the one or more programs including instructions, which when executed by a computer causes the computer to execute as described in the second aspect
  • the transmission method of control signal between chips is provided.
  • a computer program product containing instructions, which when executed on a computer, causes the computer to execute the method for transmitting control signals between chips as described in the second aspect.
  • FIG. 1 is a schematic structural diagram of an electronic device according to an embodiment of this application.
  • FIG. 2 is a schematic structural diagram of a system-on-chip of an electronic device according to an embodiment of the present application
  • FIG. 3 is a first schematic flowchart of a method for transmitting an inter-chip control signal according to an embodiment of the present application
  • FIG. 4 is a schematic diagram 1 of a control signal encoding method provided by an embodiment of the present application.
  • FIG. 5 is a second schematic diagram of a control signal encoding method provided by an embodiment of the present application.
  • FIG. 6 is a second schematic flowchart of a method for transmitting an inter-chip control signal according to an embodiment of the present application.
  • the electronic device may be a network device, a terminal device, or the like.
  • the network device may include, for example, a base station, an access management function (access management function, AMF) network element, a session management function (session management function, SMF) network element, and so on.
  • Terminal devices may include, for example, mobile phones, wearable electronic devices (such as smart watches, etc.), tablet computers, desktop computers, virtual reality devices, augmented reality devices, and so on.
  • the electronic device 100 may include a system on chip 101, a communication line 102 and a memory 103.
  • the memory 103 is used to store computer execution instructions (which may be called application program codes) for executing the solution of the present application, and the execution is controlled by the system on chip 101.
  • the system-on-chip 101 is used to execute computer-executed instructions stored in the memory 103, so as to implement steps or actions of each network element or device in the following embodiments of the present application.
  • the communication line 102 is used to transfer information between the system on chip 101 and the memory 103.
  • the electronic device 100 further includes at least one communication interface 104 for communicating with other devices or communication networks.
  • the communication network may be Ethernet, wireless access network (radio access network, RAN), or wireless local area network (wireless local area networks, WLAN), etc.
  • the communication interface 104 may use wired or wireless communication technology to communicate with other devices or communication networks. Specifically, it may be a device such as a transceiver, which is not limited.
  • the communication line 102 is also used to transfer information between at least one communication interface 104, the system-on-chip 101 and the memory 103.
  • the memory 103 may be read-only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (random access memory, RAM), or other types that can store information and instructions
  • the dynamic storage device can also be an electrically erasable programmable read-only memory (electrically erasable programmable-read-only memory (EEPROM), read-only compact disc (compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (Including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), disk storage media or other magnetic storage devices, or can be used to carry or store the desired program code in the form of instructions or data structures and can be used by a computer Access to any other media, but not limited to this.
  • EEPROM electrically erasable programmable read-only memory
  • CD-ROM compact disc read-only memory
  • optical disc storage including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.
  • the memory 103 may exist independently, and is connected to the system-on-chip 101 through the communication line 102.
  • the memory 103 may also be integrated with the system-on-chip 101.
  • the system-on-chip 101 may include a first chip 11 and a second chip 12.
  • the first chip 11 may be a digital intermediate frequency (DIF) chip, a central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC) and other control chips, or One or more integrated circuits for controlling the execution of the program procedures of the present application.
  • the second chip 12 may be a controlled chip such as an analog-to-digital/digital-to-analog (AD/DA) conversion chip.
  • AD/DA analog-to-digital/digital-to-analog
  • a serial data interface is connected between the first chip 11 and the second chip 12.
  • the first chip 11 sends a control message to the second chip 12 through the serial data interface.
  • the serial data interface may be a 204X-serializer/deserializer (SERDES) interface, which is usually used to transmit data signals, where part of its bandwidth (for example, a data block) may be used for transmission control Signals, that is, data signals and control signals are mixed and transmitted.
  • SERDES 204X-serializer/deserializer
  • the serial data interface may be a dedicated data interface, such as a general purpose output (GPIO) interface.
  • the GPIO interface includes at least one data line and a clock line. The clock line is used to transmit clock signals and data lines. Used to transmit control signals.
  • the first chip 11 sends a plurality of parallel control signals to the second chip 12 through a serial data interface, thereby reducing the number of pins for transmitting control signals between the first chip 11 and the second chip 12.
  • the control signal may be N channel enable switch signals, and the high and low levels of one channel enable switch signal are used
  • the first chip 11 and the second chip 12 each occupy N pins to transmit N channel enable switching signals.
  • An embodiment of the present application provides an inter-chip control signal transmission method. As shown in FIG. 3, the method includes:
  • the first chip obtains N control signals.
  • N is a positive integer.
  • SW1-SWn are N channel enable switch signals.
  • the channel enable switch signal is low (value 0) means that the corresponding channel is disabled, and the channel enable switch signal is high level (value 1 ) Indicates that the corresponding channel is enabled. If there is data in the i-th channel that needs to be received or sent, the first chip sets the i-th channel enable switch signal to 1, so that the i-th channel of the second chip can be used to receive or send data, and the first chip sets the remaining N The -1 channel enable switch signal is 0, and the remaining N-1 channels of the second chip are disabled to save power consumption.
  • the first chip encodes N control signals to obtain a control message.
  • control message includes N cells, and each of the N control signals occupies one of the N cells.
  • the N cells may be arranged in the order of N control signals, or in other orders, which is not limited in this application.
  • SW1-SW3 are three channel enable switch signals
  • each channel enable switch signal has only two states of 0 or 1, so each control signal occupies only one bit In the cell, three bits of SW1-SW3 are needed to transmit the switch enable signal.
  • control message includes a first cell and a second cell, where the first cell represents the type of one of the N control signals among the N control signals, and the second cell Represents the value of the one control signal.
  • SW1-SW3 are 3 channel enable switch signals
  • the first cell occupies the first 2 bits of 3 bits
  • the second cell occupies the last one of 3 bits Bit.
  • the position of the control signal in the control message is fixed, compared with the coding methods shown in Table 2 and Figure 5, the position of the control signal in the control message fixed.
  • the encoding methods shown in Table 2 and FIG. 5 can transmit only the changed control signals. When the number of control signals is large, the control message is short.
  • the length of the cell may be bits, bytes, double bytes, etc., which is not limited in this application.
  • ECC error checking and correction
  • a preamble may also be included at the beginning of the control message, which is the preamble Used to indicate that control messages are used to transmit control signals, not data signals.
  • a serial data interface that transmits in-phase quadrature (IQ) data is used to transmit the control signal.
  • IQ data a 32-bit all 1 (or all 0) can be defined as the preamble If the second chip receives consecutive 32-bit all ones, it is regarded as the preamble of the control message.
  • IQ data cannot contain all-ones of 32 bits (that is, 0xFFFF_FFFF). This method does not occupy a fixed bandwidth for transmitting data signals.
  • This application does not limit the specific value of the preamble, for example, it can also be 0xFFFF_FFFE.
  • the encoding method that does not use the preamble since there is no need to distinguish between the data signal and the control signal, it is suitable for the scenario where the control signal is transmitted through the dedicated data interface.
  • the coding method using the preamble it is applicable to the scenario of mixed transmission of data signals and control signals.
  • the first chip sends a control message to the second chip through the serial data interface.
  • the second chip receives the control message from the first chip through the serial data interface.
  • the control message may be sent periodically or triggered by an event (for example, when the control signal changes, or when error correction is required and retransmission is required), this application is not limited.
  • the second chip decodes the control message to obtain N control signals, and performs operations according to the N control signals.
  • the manner in which the second chip decodes the control message is the reverse operation of the manner in which the first chip encodes the control message.
  • the control signal 001 is obtained, then the second chip disables channel 2 and channel 3, and enables channel 1.
  • the electronic device and the method for transmitting control signals between chips use a serial data interface to transmit N control signals, so that the number of pins for transmitting control signals between the first chip and the second chip can be greatly reduced. The number of pins used for transmitting control signals between chips is reduced.
  • control signal Since the control signal is transmitted through the serial interface, there will be a transmission delay between the successive control signals. For applications that require high real-time performance or require precise timing, they may not meet the demand. Therefore, the effective time of the control signal can be indicated in the control message.
  • the method for transmitting control signals between chips further includes:
  • the first chip sends a timing pulse to the second chip through the timing line.
  • the timing pulse is used for time synchronization between the first timer 111 of the first chip 11 and the second timer 121 of the second chip 12.
  • the first chip 11 serves as a control chip, and the first timer 111 inside it can start counting first.
  • the first timer 111 restarts counting.
  • send a timing pulse to the second timer 121 of the second chip 12 through the timing line.
  • the timer 121 of the second chip 12 restarts counting according to the timing pulse, and the first timer 111 and the second timer 121 restart counting at the same time each time. Therefore, the first timer 111 of the first chip 11 and The time of the second timer 121 of the second chip 12 is synchronized.
  • the control message sent by the first chip to the second chip may further include a count value of the first timer, and the count value is used to indicate the effective time of the control signal in the control message.
  • the first timer 111 of the first chip 11 and the second timer 121 of the second chip 12 achieve time synchronization, the first timer 111 and the second timer 121 increase the same count value, and the obtained time is the same .
  • the second chip adds the count value and the agreed delay effective time to obtain the effective time of the control signal in the control message.
  • step S105 the first chip sends a timing pulse to the second chip at a fixed cycle, which is not directly related to steps S101-S104.
  • Embodiments of the present application also provide a computer-readable storage medium that stores one or more programs.
  • the one or more programs include instructions, which, when executed by a computer, cause the computer to perform the operations in FIGS. 3 and 6.
  • Related methods include instructions, which, when executed by a computer, cause the computer to perform the operations in FIGS. 3 and 6.
  • An embodiment of the present application also provides a computer program product containing instructions, which when executed on a computer, causes the computer to execute the related methods in FIGS. 3 and 6.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the unit is only a logical function division, and in actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a dedicated computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be from a website site, computer, server or data center Transmit to another website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (such as infrared, wireless, microwave, etc.).
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device including one or more servers and data centers that can be integrated with the medium.
  • the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)).

Abstract

La présente invention concerne un dispositif électronique et un procédé de transmission de signaux de commande interpuce, lesquels se rapportent au champ technique de la transmission de données interpuce et servent à réduire le nombre de broches destinées à transmettre des signaux de commande entre puces. Un dispositif électronique comprend : une première puce et une deuxième puce, la première puce étant une puce de commande, et la deuxième puce étant une puce commandée ; une interface de données en série est connectée entre la première puce et la deuxième puce ; la première puce sert à acquérir N signaux de commande, à coder N signaux de commande pour obtenir un message de commande, et à envoyer le message de commande à la deuxième puce au moyen de l'interface de données en série, N étant un entier positif ; et la deuxième puce sert à recevoir le message de commande au moyen de l'interface de données en série, à décoder le message de commande pour obtenir les N signaux de commande, et à exécuter une opération en fonction des N signaux de commande.
PCT/CN2018/125019 2018-12-28 2018-12-28 Dispositif électronique et procédé de transmission de signaux de commande interpuce WO2020133261A1 (fr)

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PCT/CN2018/125019 WO2020133261A1 (fr) 2018-12-28 2018-12-28 Dispositif électronique et procédé de transmission de signaux de commande interpuce

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1466185A (zh) * 2002-06-18 2004-01-07 华为技术有限公司 一种高速信元传输的实现方法
CN102736597A (zh) * 2012-06-13 2012-10-17 东莞广营电子科技有限公司 一种用于控制串行伺服机的系统
CN104217489A (zh) * 2014-09-25 2014-12-17 苏州保瑟佳货币检测科技有限公司 多路磁头信号输出装置、磁信号检测设备及方法
US20160373198A1 (en) * 2015-06-22 2016-12-22 Ricoh Company, Ltd. Serial communication device and serial communication method
CN106652427A (zh) * 2016-12-14 2017-05-10 南京长峰航天电子科技有限公司 电子阵列串行控制系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1466185A (zh) * 2002-06-18 2004-01-07 华为技术有限公司 一种高速信元传输的实现方法
CN102736597A (zh) * 2012-06-13 2012-10-17 东莞广营电子科技有限公司 一种用于控制串行伺服机的系统
CN104217489A (zh) * 2014-09-25 2014-12-17 苏州保瑟佳货币检测科技有限公司 多路磁头信号输出装置、磁信号检测设备及方法
US20160373198A1 (en) * 2015-06-22 2016-12-22 Ricoh Company, Ltd. Serial communication device and serial communication method
CN106652427A (zh) * 2016-12-14 2017-05-10 南京长峰航天电子科技有限公司 电子阵列串行控制系统

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