WO2020133261A1

WO2020133261A1 - Electronic device and inter-chip control signal transmission method

Info

Publication number: WO2020133261A1
Application number: PCT/CN2018/125019
Authority: WO
Inventors: 周纪; 阳宇
Original assignee: 华为技术有限公司
Priority date: 2018-12-28
Filing date: 2018-12-28
Publication date: 2020-07-02

Abstract

The present application discloses an electronic device and an inter-chip control signal transmission method, which relate to the field of inter-chip data transmission and are used for reducing the number of pins for transmitting control signals between chips. An electronic device comprises: a first chip and a second chip, the first chip being a control chip, and the second chip being a controlled chip; a serial data interface is connected between the first chip and the second chip; the first chip is used to acquire N control signals, encode the N control signals to obtain a control message, and send the control message to the second chip by means of the serial data interface, N being a positive integer; and the second chip is used to receive the control message by means of the serial data interface, decode the control message to obtain the N control signals, and execute an operation according to the N control signals.

Description

Electronic equipment and control signal transmission method between slices

Technical field

The present application relates to the field of data transmission between slices, in particular to an electronic device and a method for transmitting control signals between slices.

Background technique

In communication systems, control signals are usually transmitted between chips. Among them, some control signals can be transmitted through a dedicated control bus. These control signals follow the protocol of the control bus and realize the control functions specified in the protocol. The other part of the control signal cannot be transmitted through the dedicated control bus, because these control signals follow the manufacturer's custom protocol to implement the manufacturer's specific control functions.

For custom control signals that cannot be transmitted through a dedicated control bus, a separate bus needs to be designed for transmission. If there are many types of control signals, more input and output (IO) pins of the chip will be occupied, resulting in Board-level wiring is complex and increases chip area.

Summary of the invention

Embodiments of the present application provide an electronic device and a method for transmitting control signals between chips, which are used to reduce the number of pins for transmitting control signals between chips.

To achieve the above purpose, the embodiments of the present application adopt the following technical solutions:

In a first aspect, an electronic device is provided, including: a first chip and a second chip, the first chip is a control chip, the second chip is a controlled chip; the first chip and the second chip A serial data interface is connected between the chips; the first chip is used to: obtain N control signals; encode the N control signals to obtain control messages; and pass the serial data interface to the second chip Sending the control message, where N is a positive integer; the second chip is used to: receive the control message from the first chip through the serial data interface; decode the control message to obtain The N control signals; perform operations according to the N control signals. The electronic device provided by the embodiment of the present application uses a serial data interface to transmit N control signals, so that the number of pins for transmitting control signals between the first chip and the second chip can be greatly reduced, and the transmission between chips is reduced. The number of control signal pins.

In a possible implementation manner, a timing line is further connected between the first chip and the second chip, and the first chip is further used to: send timing to the second chip through the timing line Pulse, the timing pulse is used for time synchronization between the first timer of the first chip and the second timer of the second chip; the control message also includes a count value of the first timer, The count value of the first timer is used to indicate the effective time of the control signal in the control message. This embodiment can achieve precise control of the effective time of the control signal.

In a possible implementation manner, the control message includes N cells, and each control signal of the N control signals occupies one cell of the N cells. This embodiment provides a possible way of carrying N control signals in the control message.

In a possible implementation manner, the control message includes a first cell and a second cell, the first cell represents a type of one of the N control signals, and the second cell Represents the value of the one control signal. This embodiment provides another possible way of carrying N control signals in the control message.

In a possible implementation manner, the start position of the control message further includes a preamble, and the preamble is used to indicate that the control message is used to transmit a control signal. This embodiment can distinguish between control signals and data signals.

In a possible implementation manner, the end position of the control message further includes error checking and correction ECC check. This embodiment can check and correct the control message.

In a second aspect, an inter-chip control signal transmission method is provided, which includes: a first chip obtains N control signals, where N is a positive integer; and the first chip encodes the N control signals to obtain a control message The first chip sends the control message to the second chip through the serial data interface; the second chip receives the control message through the first chip through the serial data interface; the second chip pair The control message is decoded to obtain the N control signals; the second chip performs operations according to the N control signals. The inter-chip control signal transmission method provided by the embodiment of the present application uses a serial data interface to transmit N control signals, so that the number of pins for transmitting control signals between the first chip and the second chip can be greatly reduced, reducing the chip The number of pins used to transmit control signals.

In a possible implementation manner, the method further includes: the first chip sends a timing pulse to the second chip through a timing line, and the timing pulse is used for the first timer of the first chip and The second timer of the second chip performs time synchronization; the control message further includes a count value of the first timer, wherein the count value of the first timer is used to indicate the control message The effective time of the control signal. This embodiment can achieve precise control of the effective time of the control signal.

According to a third aspect, there is provided a computer-readable storage medium storing one or more programs, the one or more programs including instructions, which when executed by a computer causes the computer to execute as described in the second aspect The transmission method of control signal between chips.

According to a fourth aspect, there is provided a computer program product containing instructions, which when executed on a computer, causes the computer to execute the method for transmitting control signals between chips as described in the second aspect.

For the technical effects of the third aspect to the fourth aspect, reference may be made to the content described in various possible implementation manners of the first aspect and the second aspect.

BRIEF DESCRIPTION

FIG. 1 is a schematic structural diagram of an electronic device according to an embodiment of this application;

2 is a schematic structural diagram of a system-on-chip of an electronic device according to an embodiment of the present application;

3 is a first schematic flowchart of a method for transmitting an inter-chip control signal according to an embodiment of the present application;

4 is a schematic diagram 1 of a control signal encoding method provided by an embodiment of the present application;

5 is a second schematic diagram of a control signal encoding method provided by an embodiment of the present application;

6 is a second schematic flowchart of a method for transmitting an inter-chip control signal according to an embodiment of the present application.

detailed description

An embodiment of the present application provides an electronic device. The electronic device may be a network device, a terminal device, or the like. The network device may include, for example, a base station, an access management function (access management function, AMF) network element, a session management function (session management function, SMF) network element, and so on. Terminal devices may include, for example, mobile phones, wearable electronic devices (such as smart watches, etc.), tablet computers, desktop computers, virtual reality devices, augmented reality devices, and so on.

As shown in FIG. 1, the electronic device 100 may include a system on chip 101, a communication line 102 and a memory 103.

Among them, the memory 103 is used to store computer execution instructions (which may be called application program codes) for executing the solution of the present application, and the execution is controlled by the system on chip 101.

The system-on-chip 101 is used to execute computer-executed instructions stored in the memory 103, so as to implement steps or actions of each network element or device in the following embodiments of the present application.

The communication line 102 is used to transfer information between the system on chip 101 and the memory 103.

Optionally, the electronic device 100 further includes at least one communication interface 104 for communicating with other devices or communication networks.

Among them, the communication network may be Ethernet, wireless access network (radio access network, RAN), or wireless local area network (wireless local area networks, WLAN), etc.

For example, the communication interface 104 may use wired or wireless communication technology to communicate with other devices or communication networks. Specifically, it may be a device such as a transceiver, which is not limited.

The communication line 102 is also used to transfer information between at least one communication interface 104, the system-on-chip 101 and the memory 103.

The memory 103 may be read-only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (random access memory, RAM), or other types that can store information and instructions The dynamic storage device can also be an electrically erasable programmable read-only memory (electrically erasable programmable-read-only memory (EEPROM), read-only compact disc (compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (Including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), disk storage media or other magnetic storage devices, or can be used to carry or store the desired program code in the form of instructions or data structures and can be used by a computer Access to any other media, but not limited to this.

The memory 103 may exist independently, and is connected to the system-on-chip 101 through the communication line 102.

The memory 103 may also be integrated with the system-on-chip 101.

As shown in FIG. 2, the system-on-chip 101 may include a first chip 11 and a second chip 12. The first chip 11 may be a digital intermediate frequency (DIF) chip, a central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC) and other control chips, or One or more integrated circuits for controlling the execution of the program procedures of the present application. The second chip 12 may be a controlled chip such as an analog-to-digital/digital-to-analog (AD/DA) conversion chip.

A serial data interface is connected between the first chip 11 and the second chip 12. The first chip 11 sends a control message to the second chip 12 through the serial data interface. This application does not limit the specific physical form of the serial data interface. For example, the serial data interface may be a 204X-serializer/deserializer (SERDES) interface, which is usually used to transmit data signals, where part of its bandwidth (for example, a data block) may be used for transmission control Signals, that is, data signals and control signals are mixed and transmitted. Or, the serial data interface may be a dedicated data interface, such as a general purpose output (GPIO) interface. The GPIO interface includes at least one data line and a clock line. The clock line is used to transmit clock signals and data lines. Used to transmit control signals.

The first chip 11 sends a plurality of parallel control signals to the second chip 12 through a serial data interface, thereby reducing the number of pins for transmitting control signals between the first chip 11 and the second chip 12.

Exemplarily, for the first chip 11 to be a DIF chip and the second chip 12 to be an AD/DA conversion chip, the control signal may be N channel enable switch signals, and the high and low levels of one channel enable switch signal are used To control the switching state of one channel among the N channels of the second chip 12, in the prior art, it is required that the first chip 11 and the second chip 12 each occupy N pins to transmit N channel enable switching signals. After optimizing the solution provided by the embodiment of the present application, since the serial data interface is used to transmit the control signal, up to two pins are occupied, the number of pins for transmitting the control signal between the first chip 11 and the second chip 12 can be greatly reduced , And the more control signals, the more obvious the effect.

An embodiment of the present application provides an inter-chip control signal transmission method. As shown in FIG. 3, the method includes:

S101. The first chip obtains N control signals.

Among them, N is a positive integer.

Exemplarily, assume that SW1-SWn are N channel enable switch signals. The channel enable switch signal is low (value 0) means that the corresponding channel is disabled, and the channel enable switch signal is high level (value 1 ) Indicates that the corresponding channel is enabled. If there is data in the i-th channel that needs to be received or sent, the first chip sets the i-th channel enable switch signal to 1, so that the i-th channel of the second chip can be used to receive or send data, and the first chip sets the remaining N The -1 channel enable switch signal is 0, and the remaining N-1 channels of the second chip are disabled to save power consumption.

S102. The first chip encodes N control signals to obtain a control message.

In a possible implementation manner, the control message includes N cells, and each of the N control signals occupies one of the N cells. The N cells may be arranged in the order of N control signals, or in other orders, which is not limited in this application.

Exemplarily, as shown in Table 1 and FIG. 4, assume that SW1-SW3 are three channel enable switch signals, each channel enable switch signal has only two states of 0 or 1, so each control signal occupies only one bit In the cell, three bits of SW1-SW3 are needed to transmit the switch enable signal.

Table 1

二进制值Binary value	十进制值Decimal value	3个通道使能开关信号的含义The meaning of 3 channels enable switch signal
000000	00	SW3(0)、SW2(0)、SW1(0)SW3(0), SW2(0), SW1(0)
001001	11	SW3(0)、SW2(0)、SW1(1)SW3(0), SW2(0), SW1(1)
010010	22	SW3(0)、SW2(1)、SW1(0)SW3(0), SW2(1), SW1(0)
011011	33	SW3(0)、SW2(1)、SW1(1)SW3(0), SW2(1), SW1(1)
100100	44	SW3(1)、SW2(0)、SW1(0)SW3(1), SW2(0), SW1(0)
101101	55	SW3(1)、SW2(0)、SW1(1)SW3(1), SW2(0), SW1(1)

110110	66	SW3(1)、SW2(1)、SW1(0)SW3(1), SW2(1), SW1(0)
111111	77	SW3(1)、SW2(1)、SW1(1)SW3(1), SW2(1), SW1(1)

In another possible implementation manner, the control message includes a first cell and a second cell, where the first cell represents the type of one of the N control signals among the N control signals, and the second cell Represents the value of the one control signal.

Exemplarily, as shown in Table 2 and FIG. 5, assume that SW1-SW3 are 3 channel enable switch signals, the first cell occupies the first 2 bits of 3 bits, and the second cell occupies the last one of 3 bits Bit.

Table 2

二进制编码Binary code	十进制值Decimal value	N个通道使能开关信号含义N channel enable switch signal meaning
00(0)00(0)	00	SW1(0)SW1(0)
00(1)00(1)	11	SW1(1)SW1(1)
01(0)01(0)	22	SW2(0)SW2(0)
01(1)01(1)	33	SW2(1)SW2(1)
10(0)10(0)	44	SW3(0)SW3(0)
10(1)10(1)	55	SW3(1)SW3(1)

In the coding methods shown in Table 1 and Figure 4, the position of the control signal in the control message is fixed, compared with the coding methods shown in Table 2 and Figure 5, the position of the control signal in the control message fixed. In addition, the encoding methods shown in Table 2 and FIG. 5 can transmit only the changed control signals. When the number of control signals is large, the control message is short.

It should be noted that, according to different control signals, the length of the cell may be bits, bytes, double bytes, etc., which is not limited in this application.

Optionally, because high-speed channel transmission may generate error codes, and the reliability requirements of the control signal are very high, error checking and correction (ECC) can be used to check and correct errors. As shown in FIG. 4 or 5, the end position of the control message also includes an ECC check, which is used to check and correct the control signal in the control message. If the first frame is erroneous and cannot be corrected, the next frame can be used for error correction.

Optionally, for a scenario where a serial data interface for transmitting data signals is used to transmit control signals, in order to prevent confusion with data signals, as shown in FIG. 5, a preamble may also be included at the beginning of the control message, which is the preamble Used to indicate that control messages are used to transmit control signals, not data signals.

Exemplarily, suppose that a serial data interface that transmits in-phase quadrature (IQ) data is used to transmit the control signal. According to the characteristics of IQ data, a 32-bit all 1 (or all 0) can be defined as the preamble If the second chip receives consecutive 32-bit all ones, it is regarded as the preamble of the control message. However, it is required that IQ data cannot contain all-ones of 32 bits (that is, 0xFFFF_FFFF). This method does not occupy a fixed bandwidth for transmitting data signals. This application does not limit the specific value of the preamble, for example, it can also be 0xFFFF_FFFE.

For the encoding method that does not use the preamble, since there is no need to distinguish between the data signal and the control signal, it is suitable for the scenario where the control signal is transmitted through the dedicated data interface. For the coding method using the preamble, it is applicable to the scenario of mixed transmission of data signals and control signals.

S103. The first chip sends a control message to the second chip through the serial data interface.

Correspondingly, the second chip receives the control message from the first chip through the serial data interface.

The control message may be sent periodically or triggered by an event (for example, when the control signal changes, or when error correction is required and retransmission is required), this application is not limited.

S104. The second chip decodes the control message to obtain N control signals, and performs operations according to the N control signals.

The manner in which the second chip decodes the control message is the reverse operation of the manner in which the first chip encodes the control message.

Exemplarily, assuming that encoding is performed according to the encoding manner shown in Table 1, the control signal 001 is obtained, then the second chip disables channel 2 and channel 3, and enables channel 1.

The electronic device and the method for transmitting control signals between chips provided by the embodiments of the present application use a serial data interface to transmit N control signals, so that the number of pins for transmitting control signals between the first chip and the second chip can be greatly reduced. The number of pins used for transmitting control signals between chips is reduced.

Since the control signal is transmitted through the serial interface, there will be a transmission delay between the successive control signals. For applications that require high real-time performance or require precise timing, they may not meet the demand. Therefore, the effective time of the control signal can be indicated in the control message.

As shown in FIG. 6, the method for transmitting control signals between chips further includes:

S105. The first chip sends a timing pulse to the second chip through the timing line.

The timing pulse is used for time synchronization between the first timer 111 of the first chip 11 and the second timer 121 of the second chip 12. As shown in FIG. 2, the first chip 11 serves as a control chip, and the first timer 111 inside it can start counting first. When the count value of the first timer 111 reaches a certain counting threshold, the first timer 111 restarts counting. And send a timing pulse to the second timer 121 of the second chip 12 through the timing line. The timer 121 of the second chip 12 restarts counting according to the timing pulse, and the first timer 111 and the second timer 121 restart counting at the same time each time. Therefore, the first timer 111 of the first chip 11 and The time of the second timer 121 of the second chip 12 is synchronized.

The control message sent by the first chip to the second chip may further include a count value of the first timer, and the count value is used to indicate the effective time of the control signal in the control message.

Since the first timer 111 of the first chip 11 and the second timer 121 of the second chip 12 achieve time synchronization, the first timer 111 and the second timer 121 increase the same count value, and the obtained time is the same . The second chip adds the count value and the agreed delay effective time to obtain the effective time of the control signal in the control message.

It should be noted that, in step S105, the first chip sends a timing pulse to the second chip at a fixed cycle, which is not directly related to steps S101-S104.

Embodiments of the present application also provide a computer-readable storage medium that stores one or more programs. The one or more programs include instructions, which, when executed by a computer, cause the computer to perform the operations in FIGS. 3 and 6. Related methods.

An embodiment of the present application also provides a computer program product containing instructions, which when executed on a computer, causes the computer to execute the related methods in FIGS. 3 and 6.

The computer storage media and computer program products provided in this application are used to perform the method described above. Therefore, for the beneficial effects that can be achieved, reference may be made to the beneficial effects in the embodiments provided above, which will not be repeated here. .

It should be understood that in various embodiments of the present application, the size of the sequence numbers of the above processes does not mean that the execution order is sequential, and the execution order of each process should be determined by its function and inherent logic, and should not correspond to the embodiments of the present application The implementation process constitutes no limitation.

Persons of ordinary skill in the art may realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application of the technical solution and design constraints. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

Those skilled in the art can clearly understand that for the convenience and conciseness of the description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method may be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the unit is only a logical function division, and in actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.

In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer may be a general-purpose computer, a dedicated computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be from a website site, computer, server or data center Transmit to another website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device including one or more servers and data centers that can be integrated with the medium. The usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)).

The above is only the specific implementation of this application, but the scope of protection of this application is not limited to this, any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in this application. It should be covered by the scope of protection of this application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

An electronic device, comprising: a first chip and a second chip, the first chip is a control chip, the second chip is a controlled chip; and the first chip and the second chip There is a serial data interface between;

The first chip is used to: obtain N control signals; encode the N control signals to obtain a control message; send the control message to the second chip through the serial data interface, where N is Positive integer

The second chip is used to: receive the control message from the first chip through the serial data interface; decode the control message to obtain the N control signals; according to the N control signals Perform the operation.
The electronic device according to claim 1, wherein a timing line is further connected between the first chip and the second chip, and the first chip is further used to:

Sending a timing pulse to the second chip through the timing line, the timing pulse being used for time synchronization of the first timer of the first chip and the second timer of the second chip;

The control message further includes a count value of the first timer, where the count value of the first timer is used to indicate the effective time of the control signal in the control message.
The electronic device according to claim 1 or 2, wherein the control message includes N cells, and each control signal of the N control signals occupies one cell of the N cells .
The electronic device according to claim 1 or 2, wherein the control message includes a first cell and a second cell, and the first cell represents the type of one of the N control signals , The second cell represents the value of the one control signal.
The electronic device according to any one of claims 1 to 4, wherein the start position of the control message further includes a preamble, and the preamble is used to indicate that the control message is used to transmit a control signal.
The electronic device according to any one of claims 1 to 5, wherein the end position of the control message further includes error checking and correction ECC check.
An inter-chip control signal transmission method, characterized in that it includes:

The first chip obtains N control signals, where N is a positive integer;

The first chip encodes the N control signals to obtain a control message;

The first chip sends the control message to the second chip through a serial data interface;

The second chip receives the control message through the first chip through the serial data interface;

The second chip decodes the control message to obtain the N control signals;

The second chip performs operations according to the N control signals.
The method according to claim 7, wherein the method further comprises:

The first chip sends a timing pulse to the second chip through a timing line, and the timing pulse is used for time synchronization of the first timer of the first chip and the second timer of the second chip;

The control message further includes a count value of the first timer, where the count value of the first timer is used to indicate the effective time of the control signal in the control message.
The method according to claim 7 or 8, wherein the control message includes N cells, and each control signal of the N control signals occupies one cell of the N cells.
The method according to claim 7 or 8, wherein the control message includes a first cell and a second cell, the first cell represents a type of one of the N control signals, The second cell represents the value of the one control signal.
The method according to any one of claims 7-10, wherein the start position of the control message further includes a preamble, and the preamble is used to indicate that the control message is used to transmit a control signal.
The method according to any one of claims 7-11, wherein the end position of the control message further includes error checking and correction ECC check.
A computer-readable storage medium storing one or more programs, characterized in that the one or more programs include instructions, which when executed by a computer causes the computer to execute any one of claims 7-12 Item-to-chip control signal transmission method.
A computer program product containing instructions, characterized in that, when the instructions run on a computer, the computer is caused to execute the method for transmitting control signals between chips according to any one of claims 7-12.