WO2020132977A1

WO2020132977A1 - Semiconductor package and electronic device

Info

Publication number: WO2020132977A1
Application number: PCT/CN2018/124013
Authority: WO
Inventors: 葉冠宏; 汤佳杰; 林来存; 邱士超; 郝建霞
Original assignee: 华为技术有限公司
Priority date: 2018-12-26
Filing date: 2018-12-26
Publication date: 2020-07-02

Abstract

Provided are a semiconductor package and an electronic device, relating to the technical field of electronic packaging and used for solving the problem of the degradation of the underfill filling capacity due to the non-uniform distribution of bumps. The semiconductor package comprises a package substrate, a semiconductor device, a plurality of first electrical connectors and a plurality of auxiliary structures, wherein the package substrate has an upper surface and a lower surface arranged opposite one another; the semiconductor device is located on the upper surface of the package substrate; the plurality of first electrical connectors are distributed on a lower surface of the semiconductor device and are used for electrically connecting the semiconductor device to the package substrate; and the plurality of auxiliary structures are distributed on the upper surface of the package substrate and protrude from the upper surface of the package substrate. The orthographic projections of the auxiliary structures on the lower surface of the semiconductor device are located on a part of the lower surface of the semiconductor device where no first electrical connector is provided.

Description

Semiconductor package and electronic equipment

Technical field

The present application relates to the technical field of electronic packaging, in particular to a semiconductor package and electronic equipment.

Background technique

Flip chip packaging technology is to electrically connect the bumps of the chip to the substrate. There is a gap between the chip and the substrate. In order to protect the chip and the bumps, the dispensing process will dispense glue around the chip. Under the action of the gap between the chip and the substrate and the capillary phenomenon produced by the underfill material, the primer material penetrates into the gap between the chip and the substrate to fill the underfill. However, when the bumps are unevenly distributed, the capillary phenomenon at the positions where the bumps are not distributed in the gap will be weakened, so that the primer cannot effectively fill the gap. Decreased reliability.

Summary of the invention

The embodiments of the present invention provide a semiconductor package and an electronic device, which are used to solve the problem that the filling property of the primer decreases due to uneven distribution of the bumps.

To achieve the above purpose, the embodiments of the present application adopt the following technical solutions:

An aspect of an embodiment of the present application provides a semiconductor package, including a package substrate, a semiconductor device, a plurality of first electrical connectors, and a plurality of auxiliary structures. Wherein, the packaging substrate has an upper surface and a lower surface that are oppositely arranged. The semiconductor device is located on the upper surface of the package substrate. A plurality of first electrical connectors are arranged on the lower surface of the semiconductor device, and are used to electrically connect the semiconductor device and the packaging substrate. A plurality of auxiliary structures are arranged on the upper surface of the packaging substrate and protrude from the upper surface of the packaging substrate. The orthographic projection of the auxiliary structure on the lower surface of the semiconductor device is located on the portion of the lower surface of the semiconductor device where the first electrical connector is not provided. In this way, in the gap between the semiconductor device and the package substrate, a plurality of auxiliary structures can be used to compensate for the insufficient distribution of the first electrical connector. As can be seen from the above, when the dispensing device performs the dispensing operation around the semiconductor device, the primer material will penetrate into the gap between the semiconductor device and the packaging substrate in the direction of the arrow due to the capillary phenomenon. Based on the structure of the above semiconductor package, a plurality of first electrical connectors and a plurality of auxiliary structures distributed in different positions in the gap between the semiconductor device and the package substrate can enhance the above capillary phenomenon, so that the primer material can further enter the gap Inside, and to the location where the first electrical connection and the auxiliary structure are distributed. In this case, the primer material can fill the gaps approximately or completely, thereby improving the filling property of the primer. In addition, in the process of filling the primer, the primer material can fill the gap approximately or completely, so there is no need to use a pressure oven to press the primer material into the gap between the semiconductor device and the packaging substrate. Therefore, the production cost can be saved.

Optionally, the packaging substrate includes at least one metal wiring layer, and the metal wiring layer includes multiple metal wires. The material constituting the auxiliary structure is a metallic material. The auxiliary structure is in contact with the metal wires exposed on the upper surface of the packaging substrate. By contacting the auxiliary structure made of metal material with the metal wires exposed on the upper surface of the packaging substrate, the purpose of fixing the auxiliary structure is achieved.

Optionally, the material of the auxiliary structure is the same as the material of the metal wire. In this way, the materials constituting the auxiliary structure can be selected from the materials commonly used in the process of manufacturing the package substrate, thereby simplifying the manufacturing process.

Alternatively, optionally, the packaging substrate includes at least one metal wiring layer, and a solder resist layer covering the outermost metal wiring layer. The material constituting the auxiliary structure is the same as the material of the solder resist layer. In this way, the materials constituting the auxiliary structure can be selected from the materials commonly used in the process of manufacturing the package substrate, thereby simplifying the manufacturing process.

Optionally, the first electrical connector includes solder bumps, solder balls, or copper pillars.

Optionally, the auxiliary structure has the same shape and external dimensions as the first electrical connector. In this way, the gap between the semiconductor device and the package substrate can be further reduced, the primer material flows through the gap of the path, to achieve the above capillary phenomenon, and promote the primer material in the gap between the semiconductor device and the package substrate The purpose of the flow.

Optionally, the spacing between any two adjacent auxiliary structures is the same as the spacing between two adjacent first electrical connectors among the plurality of first electrical connectors. In this case, the plurality of first electrical connectors and the plurality of auxiliary structures may be approximately uniformly distributed in the gap between the semiconductor device and the package substrate. In this way, in the dispensing process, the primer material enters the gap between the semiconductor device and the package substrate under the action of the capillary phenomenon, and can be uniformly distributed in the plurality of first electrical connectors and the plurality of auxiliary structures Under the attraction of, it flows uniformly to the above gaps and fills the gap to improve the filling and distribution uniformity of the primer.

Optionally, the auxiliary structure is a cubic block, and the volume of the auxiliary structure is larger than the volume of the first electrical connector. In this way, the auxiliary structure has a large volume and does not require a high-precision manufacturing process to prepare it, so the production cost can be reduced.

Optionally, the auxiliary structure is in contact with a portion of the lower surface of the semiconductor device where the first electrical connector is not provided. Therefore, the gap between the semiconductor device and the packaging substrate can be further reduced, and the primer material flows through the gap of the path to achieve the effect of enhancing the capillary phenomenon.

Optionally, the above semiconductor package further includes a primer. The primer can be filled between the packaging substrate and the semiconductor device through the above dispensing process. The above primer can protect the first electrical connector arranged on the lower surface of the semiconductor device.

Optionally, the semiconductor device is a bare chip. The orthographic projection of the auxiliary structure on the active surface of the bare chip is located on the part of the bare chip active surface where the first electrical connector is not provided. In other optional embodiments, the semiconductor device may also be a chip entity obtained by packaging one or more bare chips.

Or, optionally, the semiconductor device includes: a redistribution layer, a bare chip, and a plurality of second electrical connections. The redistribution layer includes an upper surface and a lower surface disposed oppositely. The bare chip is located on the upper surface of the redistribution layer. A plurality of second electrical connectors are arranged on the active surface of the bare chip, and are used to electrically connect the bare chip and the redistribution layer. The orthographic projection of the auxiliary structure on the lower surface of the redistribution layer is located on the portion of the lower surface of the redistribution layer where the first electrical connector is not provided.

Another aspect of the embodiments of the present application provides an electronic device including a printed circuit board, a third electrical connector, and any semiconductor package as described above. The third electrical connector is located between the semiconductor package and the printed circuit board and is arranged on the semiconductor package; the third electrical connector is used to electrically connect the semiconductor package and the printed circuit board. The above-mentioned electronic device has the same technical effect as the semiconductor package provided in the foregoing embodiment, and will not be repeated here.

BRIEF DESCRIPTION

1 is a schematic structural diagram of a semiconductor package provided by some embodiments of this application;

2 is a schematic diagram of a distribution structure of the first electrical connector on the lower surface of the semiconductor device in FIG. 1;

FIG. 3 is a schematic diagram of a distribution structure of the front projection of the first electrical connector and the auxiliary structure on the lower surface of the semiconductor device in FIG. 1;

4 is a schematic diagram of manufacturing the semiconductor package shown in FIG. 1;

5 is a schematic structural diagram of another semiconductor package provided by some embodiments of the present application;

6 is a schematic structural diagram of another semiconductor package provided by some embodiments of the present application;

7 is a schematic structural diagram of another semiconductor package provided by some embodiments of the present application;

8 is a schematic diagram of another distribution structure of the orthographic projection of the first electrical connector and the auxiliary structure on the lower surface of the semiconductor device in FIG. 1;

9 is a schematic diagram of another distribution structure of the orthographic projection of the first electrical connector and the auxiliary structure on the lower surface of the semiconductor device in FIG. 1;

10 is a schematic structural diagram of another semiconductor package provided by some embodiments of the present application;

11 is a schematic diagram of another distribution structure of the front projection of the first electrical connector and the auxiliary structure on the lower surface of the semiconductor device in FIG. 1;

12 is a schematic diagram of a package substrate with auxiliary structures distributed according to some embodiments of the present application;

13 is a schematic diagram of another package substrate with auxiliary structures distributed according to some embodiments of the present application;

14 is a schematic diagram of another package substrate with auxiliary structures distributed according to some embodiments of the present application;

15 is a schematic diagram of another package substrate with auxiliary structures distributed according to some embodiments of the present application;

16 is a schematic diagram of another package substrate with auxiliary structures distributed according to some embodiments of the present application;

17 is a schematic diagram of another package substrate with auxiliary structures distributed according to some embodiments of the present application;

18 is a schematic diagram of another package substrate with auxiliary structures distributed according to some embodiments of the present application;

19 is a schematic diagram of another package substrate with auxiliary structures distributed according to some embodiments of the present application;

FIG. 20 is a schematic structural diagram of an electronic device provided by some embodiments of the present application.

Reference mark:

01- semiconductor package; 02- dispensing device; 03- electronic equipment; 10- package substrate; 11- semiconductor device; 110- bare chip; 120- redistribution layer; 201- dielectric layer; 202- metal wire; 12 -Primer; 20-core board; 21-first electrical connector; 210-under bump metal layer; 22-second electrical connector; 23-third electrical connector; 30- auxiliary structure; 40- solder resistance Floor.

detailed description

The technical solutions in the embodiments of the present invention will be described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all the embodiments.

Herein, the terms "first", "second", etc. are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise stated, "multiple" means two or more.

In addition, in this article, directional terms such as “upper” and “lower” are defined relative to the orientation in which the display panel in the drawing is schematically placed. It should be understood that these directional terms are relative concepts and they are used for relative For the description and clarification of Yu, it can change accordingly according to the change of the orientation of the display panel.

An embodiment of the present application provides a semiconductor package 01. As shown in FIG. 1, the package includes a packaging substrate 10, a semiconductor device 11, a plurality of first electrical connectors 21, a plurality of auxiliary structures 30, and a primer 12.

The package substrate 10 described above has an upper surface A1 and a lower surface A2 that are oppositely arranged. The semiconductor device 11 is located on the upper surface A1 of the package substrate 11. The package substrate 10 is used to support the semiconductor device 11.

In addition, the plurality of first electrical connectors 21 are arranged on the lower surface of the semiconductor device 11 (the surface close to the package substrate 10 ), and are used to electrically connect the semiconductor device 11 and the package substrate 10.

In this case, due to the influence of the circuit design layout in the semiconductor device 11, as shown in FIG. 2, on the lower surface of the semiconductor device 11, a plurality of first electrical connectors 21 are densely distributed in some areas and distributed in some areas Relatively sparse.

In this way, in the gap between the semiconductor device 11 and the package substrate 10, the plurality of first electrical connectors 21 are arranged in a relatively sparse area, and the capillary phenomenon is weak during the dispensing process. Therefore, the primer material cannot effectively fill the area.

In order to solve the problem of the gap between the semiconductor device 11 and the package substrate 10, the first electrical connectors 21 are distributed at sparse locations, and the underfill 12 is insufficiently filled. The semiconductor package 01 provided by the embodiment of the present application is shown in FIG. 1. The semiconductor package 01 also includes a plurality of auxiliary structures 30.

The plurality of auxiliary structures 30 are arranged on the upper surface A1 of the package substrate 10 and protrude from the upper surface A1 of the package substrate 10.

As shown in FIG. 3, the orthographic projection of the above-mentioned auxiliary structure 30 on the lower surface of the semiconductor device 11 is located on the portion of the lower surface of the semiconductor device 11 where the first electrical connector 21 is not provided.

In this way, in the gap between the semiconductor device 11 and the package substrate 10, the plurality of protruding auxiliary structures 30 can compensate for the insufficient distribution of the first electrical connectors 21.

As can be seen from the above, as shown in FIG. 4, when the dispensing device 02 performs the dispensing operation around the semiconductor device 11, the primer material will penetrate into the gap between the semiconductor device 11 and the package substrate 10 in the direction of the arrow due to the capillary phenomenon Inside.

Based on the structure of the semiconductor package 01 described above, in the gap between the semiconductor device 11 and the package substrate 10, a plurality of first electrical connectors 21 and a plurality of auxiliary structures 30 distributed at different positions can enhance the above-mentioned capillary phenomenon, making the primer The material can further enter the interior of the gap and flow to the location where the first electrical connection 21 and the auxiliary structure 30 are distributed. In this case, the primer material can fill the gaps approximately or completely, thereby improving the filling property of the primer 12.

In addition, in the process of filling the primer 12, the primer material can fill the gap approximately or completely, so there is no need to use a pressure oven to press the primer material into the gap between the semiconductor device 11 and the package substrate 10 Inside. Therefore, the production cost can be saved.

On this basis, in order to further enhance the above capillary phenomenon and promote the flow of the primer material in the gap between the semiconductor device 11 and the package substrate 10, the auxiliary structure 30 may be on the lower surface of the semiconductor device 21 without the first electrical The parts of the connector 21 are in contact. Therefore, in the gap between the semiconductor device 11 and the package substrate 10, the primer material flows through the gap of the path, and the effect of enhancing the capillary phenomenon is achieved.

The arrangement of the auxiliary structure 30 will be exemplified below.

Example one

In this example, the shape of the above-mentioned auxiliary structure 30 is the same as the first electrical connector 21.

For example, as shown in FIG. 5, the above-mentioned semiconductor chip 11 may be a bare chip (Die) 110.

In addition, the plurality of first electrical connectors 21 are solder bumps arranged on the active surface of the bare chip 110.

In this case, an under bump metallurgy (UBM) 210 is also provided on the active surface of the bare chip 110 corresponding to the solder bumps.

The under-bump metal layer 210 can cover the solder pads exposed on the active surface of the bare chip 110, thereby adhering to the solder bumps, and blocking the mutual diffusion of the metal materials constituting the solder bumps and the materials constituting the solder pads.

It should be noted that the active surface of the bare chip 110 is a surface provided with a circuit structure on the bare chip 110.

In this case, for the structure shown in FIG. 5, the orthographic projection of the auxiliary structure 30 on the active surface of the bare chip 110 is located on the active surface of the bare chip 110 where the first electrical connector 21 is not provided section.

At this time, as shown in FIG. 5, the shape of the auxiliary structure 30 may be the same as the shape of the solder bump (ie, the first electrical connector 21 ).

Or, for another example, as shown in FIG. 6, when the semiconductor chip 11 is a bare chip 110, the plurality of first electrical connectors 21 are a plurality of copper pillars arranged on the active surface of the bare chip 110.

In this case, the shape of the auxiliary structure 30 may be the same as the shape of the copper pillar, which is cylindrical.

Or, for example, in some other embodiments of the present application, the structure of the semiconductor chip 11 shown in FIG. 7 includes the bare chip 110, a redistribution layer (RDL) 120, and a second circuit Connector 22.

Among them, the redistribution layer 120 includes an upper surface B1 and a lower surface B2 that are oppositely arranged. The bare chip 110 is located on the upper surface B1 of the redistribution layer 120 described above.

It should be noted that the redistribution layer 120 includes multiple dielectric layers 201 and multiple metal wiring layers. Each metal wiring layer includes a plurality of metal wires 202.

A metal wiring layer and a dielectric layer 201 are alternately arranged. The above multilayer metal wiring layer constitutes the metal wiring structure in the redistribution layer. In addition, the dielectric layer 201 is also provided with via holes for electrically connecting two adjacent metal wiring layers 202.

On this basis, the plurality of second electrical connectors 22 are arranged on the active surface of the bare chip 110 for electrically connecting the bare chip and the redistribution layer 120.

The second electrical connector 22 may be the solder bump or the copper pillar.

In this case, the first electrical connection 21 may be a solder ball. A plurality of solder balls can be fabricated on the lower surface B2 of the redistribution layer 120 by using a ball grid array (BGA) ball planting process.

Based on this, the orthographic projection of the auxiliary structure 30 on the lower surface B2 of the redistribution layer 120 is located on the portion of the lower surface B2 of the redistribution layer 120 where the first electrical connector 21 is not provided.

At this time, the shape of the auxiliary structure 30 may be the same as the shape of the solder ball formed on the lower surface B2 of the redistribution layer 120.

On this basis, for any of the auxiliary structures 30 shown in FIGS. 5, 6, and 7, if the shape of the auxiliary structure 30 is the same as the shape of the first electrical connector 21, the above auxiliary structure The external dimensions of 30 and the first electrical connection 21 may also be the same. In this way, the gap between the semiconductor device 11 and the package substrate 10 can be further reduced, and the gap of the primer material flowing through the path can enhance the capillary phenomenon and promote the primer material between the semiconductor device 11 and the package substrate 10 The purpose of the flow in the gap.

In addition, in some embodiments of the present application, as shown in FIG. 8, the distance H1 between any two adjacent auxiliary structures 30 is different from the two adjacent first electrical connectors 21 The pitch H2 between the connecting members 21 is the same.

In this case, the plurality of first electrical connectors 21 and the plurality of auxiliary structures 30 may be approximately uniformly distributed in the gap between the semiconductor device 11 and the package substrate 10.

In this way, in the dispensing process, under the effect of the capillary phenomenon, the primer material enters the gap between the semiconductor device 11 and the package substrate 10, and can be evenly distributed in the plurality of first electrical connectors 21 and the multiple Under the attraction of each auxiliary structure 30, it uniformly flows to each position of the above-mentioned gap, and fills the gap, thereby improving the filling property and distribution uniformity of the primer 12.

Example 2

In this example, as shown in FIG. 9, the auxiliary structure 30 is a cubic block, and the volume of the auxiliary structure 30 is larger than the volume of the first electrical connection 21.

On this basis, as shown in FIG. 10, in the case where the auxiliary structure 30 is in contact with the lower surface of the semiconductor device 11 where no first electrical connector 21 is provided, the surface of the auxiliary structure 30 in contact with the semiconductor device 11 Can be flat.

In this way, compared to the solution in which the shape and the outer dimensions of the auxiliary structure 30 and the first electrical connector 21 are the same in Example 1, the auxiliary structure 30 in this example has a larger volume and does not require high-precision fabrication Process to prepare it, so it can reduce production costs.

It should be noted that, in some other examples of the present application, as shown in FIG. 11, a plurality of auxiliary structures 30 arranged on the upper surface A1 of the package substrate 10, and some auxiliary structures 30 may adopt the structure of Example 1. For example, it is spherical or cylindrical with the same shape as the first electrical connector 21. In addition, another part of the auxiliary structure 30 may adopt the structure of Example 2, for example, a cube.

The materials constituting the auxiliary structure 30 will be described below.

In the embodiment of the present application, the material constituting the auxiliary structure 30 may be a metal material or a resin material.

Based on this, in order to simplify manufacturing, the material constituting the auxiliary structure 30 may be a material commonly used in manufacturing the package substrate 10.

For example, in some embodiments of the present disclosure, as shown in FIGS. 12, 13, 14, and 15, the packaging substrate 10 may include at least one core board 20.

The core board 20 includes a dielectric layer 201 and metal layers on the upper and lower surfaces of the dielectric layer 201.

By patterning the metal layer, a plurality of metal wires 202 on the dielectric layer 201 can be formed. In the embodiment of the present application, a plurality of metal wires 202 located on the same dielectric layer 201 are called metal wiring layers.

It should be noted that the above-mentioned graphic processing includes processes such as sticking a dry film, exposure, development, etching, film stripping and the like.

When the package substrate 10 has a plurality of core plates 20, as shown in FIG. 12, the plurality of core plates 20 are stacked. There is an adhesive layer 30 between two adjacent core boards 20.

In addition, in the package substrate 10, the outer surfaces of the uppermost and lowermost core boards 20 are covered with a solder mask 40, or green oil. The solder resist layer 40 is used to protect the outermost metal wiring layer of the package substrate 10.

In this case, when the material constituting the auxiliary structure 30 is a metal material, in order to simplify the manufacturing process, the material of the auxiliary structure 30 may be the same as the material of the metal wire 202 described above.

Based on this, in order to enable the auxiliary structure 30 to be fixed to the upper surface A1 of the package substrate 10, a hole needs to be formed in the solder resist layer 40 to expose the metal wires 202 below. Then, a spherical auxiliary structure 30 is made by a ball-balling process.

The auxiliary structure 30 is in contact with the upper surface A1 of the package substrate 10 and the metal wires 202 exposed through the openings in the solder resist layer 40, so that the auxiliary structure 30 can be fixed to the upper surface A1 of the package substrate 10.

Alternatively, when the material constituting the auxiliary structure 30 is a resin material, in order to briefly describe the manufacturing process, the material of the auxiliary structure 30 may be the same as the material of the solder resist layer 40 described above.

Based on this, a ball bumping process may be used to form a spherical auxiliary structure 30 as shown in FIG. 13 on the surface of the solder resist layer 40.

Alternatively, a printing process is used to form an auxiliary structure 30 in the shape of a cube as shown in FIG. 14 on the surface of the solder resist layer 40.

In addition, in some embodiments of the present application, as shown in FIG. 15, on the upper surface A1 of the package substrate 10, both the auxiliary structure 30 made of resin material and the auxiliary structure 30 made of metal material can be made. As can be seen from the above, the auxiliary structure 30 made of a metal material is in contact with the metal wire 202 exposed on the upper surface A1 of the package substrate 10.

Alternatively, in some other embodiments of the present application, as shown in FIGS. 16, 17, 18 and 19, the package substrate 10 includes multiple dielectric layers 201 and multiple metal wiring layers.

Each metal wiring layer includes multiple metal wires 202. The above multilayer metal wiring layer constitutes the metal wiring structure in the package substrate 10.

In addition, the dielectric layer 201 is also provided with via holes for electrically connecting two adjacent metal wiring layers.

As shown in FIG. 16, a metal wiring layer 202 and a dielectric layer 201 are alternately arranged.

In manufacturing the package substrate 10 shown in FIG. 16, the metal wiring layer 202 is formed on the dielectric layer 201 underneath through a plating process, or on a carrier board used to carry the package substrate 10.

The above-mentioned dielectric layer 201 is made of semi-cured resin material, and can be pressed on the substrate on which the metal wire 202 has been formed by a pressing process, so that the metal wire 202 under the dielectric layer 201 is embedded in the above-mentioned dielectric layer 201.

In this case, when the material constituting the auxiliary structure 30 is a metal material, the same can be said that the material of the auxiliary structure 30 may be the same as the material of the metal wire 202 described above.

In addition, in order to enable the auxiliary structure 30 to be fixed to the upper surface A1 of the package substrate 10, a hole needs to be formed in the solder resist layer 40 to expose the metal wires 202 below. Then, a ball-shaped auxiliary structure 30 as shown in FIG. 16 is manufactured by a ball-balling process.

Alternatively, an electroplating process is used to form a cubic block-shaped auxiliary structure 30 as shown in FIG. 17 at the window opening position of the solder resist layer 40.

In other embodiments of the present application, when the material constituting the auxiliary structure 30 is a resin material, in order to briefly describe the manufacturing process, the material of the auxiliary structure 30 may be the same as the material of the solder resist layer 40 described above.

Based on this, a ball bumping process may be used to form a spherical auxiliary structure 30 as shown in FIG. 18 on the surface of the solder resist layer 40.

Alternatively, a printing process is used to form a cubic auxiliary structure 30 as shown in FIG. 19 on the surface of the solder resist layer 40.

An embodiment of the present application provides an electronic device 03, as shown in FIG. 20, which includes a printed circuit board (PCB), a third electrical connector 23, and any of the semiconductor packages 01 as described above.

The third electrical connector 23 is located between the semiconductor package 01 and the PCB, and is arranged on the lower surface of the semiconductor package 01 (ie, the side surface close to the PCB).

The third electrical connector 23 is used to electrically connect the semiconductor package 01 and the PCB.

The above-mentioned electronic device has the same technical effect as the semiconductor package 01 provided in the foregoing embodiment, and will not be repeated here.

The above are only the specific embodiments of the present invention, but the scope of protection of the present invention is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present invention. It should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

A semiconductor package is characterized by comprising:

The package substrate has an upper surface and a lower surface which are arranged oppositely;

A semiconductor device located on the upper surface of the packaging substrate;

A plurality of first electrical connectors are arranged on the lower surface of the semiconductor device, and are used to electrically connect the semiconductor device and the packaging substrate;

A plurality of auxiliary structures are arranged on the upper surface of the packaging substrate and protrude from the upper surface of the packaging substrate; the orthographic projection of the auxiliary structures on the lower surface of the semiconductor device is located under the semiconductor device No part of the first electrical connection is provided on the surface.
The semiconductor package according to claim 1, wherein the packaging substrate includes at least one metal wiring layer, and the metal wiring layer includes a plurality of metal wires;

The material constituting the auxiliary structure is a metal material; the auxiliary structure is in contact with the metal wires exposed on the upper surface of the packaging substrate.
The semiconductor package according to claim 1, wherein the material of the auxiliary structure is the same as the material of the metal wire.
The semiconductor package according to claim 1, wherein the packaging substrate includes at least one metal wiring layer, and a solder resist layer covering the outermost metal wiring layer;

The material constituting the auxiliary structure is the same as the material of the solder resist layer.
The semiconductor package according to any one of claims 1 to 4, wherein the first electrical connector includes solder bumps, solder balls, or copper pillars.
The semiconductor package according to claim 5, wherein the auxiliary structure has the same shape and external dimensions as the first electrical connector.
The semiconductor package according to claim 6, wherein:

The spacing between any two adjacent auxiliary structures is the same as the spacing between two adjacent first electrical connectors in the plurality of first electrical connectors.
The semiconductor package according to any one of claims 1 to 5, wherein the auxiliary structure is a cube, and the volume of the auxiliary structure is larger than the volume of the first electrical connection.
The semiconductor package according to any one of claims 1-8, wherein the auxiliary structure is in contact with a portion of the lower surface of the semiconductor device where the first electrical connector is not provided.
The semiconductor package according to any one of claims 1-9, wherein the semiconductor package further comprises a primer;

The primer is filled between the packaging substrate and the semiconductor device.
The semiconductor package according to any one of claims 1-10, wherein the semiconductor device is a bare chip;

An orthographic projection of the auxiliary structure on the active surface of the bare chip is located on a portion of the bare chip active surface where the first electrical connector is not provided.
The semiconductor package according to any one of claims 1-10, wherein the semiconductor device comprises:

Redistribution layer, including upper and lower surfaces oppositely arranged;

A bare chip, located on the upper surface of the redistribution layer;

A plurality of second electrical connectors are arranged on the active surface of the bare chip, and are used to electrically connect the bare chip and the redistribution layer;

An orthographic projection of the auxiliary structure on the lower surface of the redistribution layer is located on a portion of the lower surface of the redistribution layer where the first electrical connector is not provided.
An electronic device, comprising a printed circuit board, a third electrical connector, and the semiconductor package according to any one of claims 1-12;

The third electrical connector is located between the semiconductor package and the printed circuit board and is arranged on the semiconductor package; the third electrical connector is used to connect the semiconductor package and the The printed circuit board is electrically connected.