WO2020124820A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2020124820A1
WO2020124820A1 PCT/CN2019/078353 CN2019078353W WO2020124820A1 WO 2020124820 A1 WO2020124820 A1 WO 2020124820A1 CN 2019078353 W CN2019078353 W CN 2019078353W WO 2020124820 A1 WO2020124820 A1 WO 2020124820A1
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WO
WIPO (PCT)
Prior art keywords
signal connection
output signal
display panel
connection pads
microns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/078353
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English (en)
French (fr)
Inventor
蔡昆岳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US17/051,439 priority Critical patent/US20210223834A1/en
Publication of WO2020124820A1 publication Critical patent/WO2020124820A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for supporting printed circuit boards
    • G06F1/185—Mounting of expansion boards
    • G06F1/186—Securing of expansion boards in correspondence to slots provided at the computer enclosure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/189—Power distribution
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/1601—Constructional details related to the housing of computer displays, e.g. of CRT monitors, of flat displays
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/1613—Constructional details or arrangements for portable computers
    • G06F1/1633—Constructional details or arrangements of portable computers not specific to the type of enclosures covered by groups G06F1/1615 - G06F1/1626
    • G06F1/1637—Details related to the display arrangement, including those related to the mounting of the display in the housing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2200/00—Indexing scheme relating to G06F1/04 - G06F1/32
    • G06F2200/16—Indexing scheme relating to G06F1/16 - G06F1/18
    • G06F2200/161—Indexing scheme relating to constructional details of the monitor
    • G06F2200/1612—Flat panel monitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • the invention relates to the field of display technology, in particular to a display panel.
  • a conventional display panel is generally provided with a connection pad (Pad), a chip is disposed on the display panel, and the chip is connected to the display panel through the connection pad.
  • a connection pad (Pad)
  • a chip is disposed on the display panel, and the chip is connected to the display panel through the connection pad.
  • connection area corresponding to the chip on the display panel can only be adapted to a chip with a single pin type, but not to chips with different pin types.
  • An object of the present invention is to provide a display panel which can be adapted to various types of chips.
  • a display panel comprising a display area portion and a peripheral area portion, wherein the peripheral area portion is provided with a chip connection area, and the chip connection area is provided with an input signal connection pad array and an output signal connection pad array; wherein , The input signal connection pad array is located on one side of the chip connection area, and the output signal connection pad array is located on the other side of the chip connection area; the input signal connection pad array includes at least two input signal connection pads , At least two of the input signal connection pads are arranged in an array along the first direction; the output signal connection pad array includes at least six output signal connection pads, and at least six of the output signal connection pads are perpendicular to the first direction The second direction is arranged in three rows, at least six of the output signal connection pads are arranged in at least two columns along the first direction; in the first direction, the gap between two adjacent output signal connection pads The sum of the width of the output signal connection pad and the width of the output signal connection pad is in the range of 20 ⁇ m to 36 ⁇ m; in the first direction, the number of output
  • the sum of the width of the gap between two adjacent output signal connection pads and the width of the output signal connection pads is 28 ⁇ m.
  • the width of the gap between two adjacent output signal connection pads is in the range of 10 microns to 18 microns.
  • the width of the gap between two adjacent output signal connection pads is 14 ⁇ m.
  • a display panel comprising a display area portion and a peripheral area portion, wherein the peripheral area portion is provided with a chip connection area, and the chip connection area is provided with an input signal connection pad array and an output signal connection pad array; wherein , The input signal connection pad array is located on one side of the chip connection area, and the output signal connection pad array is located on the other side of the chip connection area; the input signal connection pad array includes at least two input signal connection pads , At least two of the input signal connection pads are arranged in an array along the first direction; the output signal connection pad array includes at least six output signal connection pads, and at least six of the output signal connection pads are perpendicular to the first direction The second direction is arranged in three rows, and at least six of the output signal connection pads are arranged in at least two columns along the first direction.
  • the sum of the width of the gap between two adjacent output signal connection pads and the width of the output signal connection pads is in the range of 20 ⁇ m to 36 ⁇ m.
  • the sum of the width of the gap between two adjacent output signal connection pads and the width of the output signal connection pads is 28 ⁇ m.
  • the width of the gap between two adjacent output signal connection pads is in the range of 10 microns to 18 microns.
  • the width of the gap between two adjacent output signal connection pads is 14 ⁇ m.
  • the number of output signal connection pads in a row of the output signal connection pads is in the range of 900 to 1020.
  • the number of output signal connection pads in a row of the output signal connection pads is 960.
  • the two edges of the output signal connection pad array and the chip connection area have a first pitch and a second pitch respectively; the first pitch and the second pitch
  • the pitch is in the range of 100 microns to 180 microns.
  • both the first pitch and the second pitch are 140 microns.
  • the display panel further includes a chip including at least two input pins and at least two output pins; the input pin is connected to the input signal connection pad, and the output pin is The output signal connection pad is connected.
  • a redundant connection pad array is further provided between the input signal connection pad array and the output signal connection pad array, and the redundant connection pad array includes at least two redundant connection pads; The remaining connection pad is used to support the chip fixed to the panel body.
  • the redundant connection pads are formed simultaneously during the process of forming the input signal connection pads and/or the output signal connection pads.
  • the area where the input pin overlaps the input signal connection pad is greater than 1000 square microns; the area where the output pin overlaps the output signal connection pad is greater than 1000 square microns.
  • the width of the input signal connection pad is in the range of 20 ⁇ m to 40 ⁇ m; the length of the input signal connection pad is in the range of 120 ⁇ m to 160 ⁇ m.
  • the width of the output signal connection pad is in the range of 10 microns to 18 microns; the length of the output signal connection pad is in the range of 100 microns to 160 microns.
  • At least one alignment mark is also provided in the chip connection area, the alignment mark is used to make the chip and the panel when the chip and the panel body are integrated into one Subject alignment.
  • the input signal connection pad array includes at least two input signal connection pads, at least two of which Input signal connection pads are arranged in an array along a first direction;
  • the output signal connection pad array includes at least six output signal connection pads, and at least six of the output signal connection pads are arranged in a second direction perpendicular to the first direction In three rows, at least six of the output signal connection pads are arranged in at least two columns along the first direction. Therefore, the present invention can be adapted to multiple types of chips, not limited to single-pin type chips.
  • FIG. 1 is a schematic diagram of a display panel of the present invention.
  • FIG. 2 is a schematic diagram of the chip connection area in the display panel shown in FIG. 1.
  • FIG. 3 is a positional relationship between two output signal connection pads in the chip connection area shown in FIG. 2.
  • FIG. 1 is a schematic diagram of a display panel 10 of the present invention
  • FIG. 2 is a schematic diagram of a chip connection area 1021 in the display panel 10 shown in FIG. 1
  • FIG. 3 is a chip shown in FIG. 2 The positional relationship between the two output signal connection pads 102111 in the connection area 1021.
  • the display panel 10 of the present invention may be an OLED (Organic Light Emitting Diode, organic light emitting diode display panel) or the like.
  • the display panel 10 of the present invention includes a flexible printed circuit (FPC, Flexible Printed Circuit) 101, a panel body 102, and a chip (DIC, Driver Integrated Circuit) 103.
  • the flexible circuit board 101 is connected to the panel body 102, and the panel
  • the main body 102 includes a display area portion and a peripheral area portion.
  • the peripheral area portion is provided with a chip connection area 1021 on which an input signal connection pad array 10212 and an output signal connection pad array 10211 are provided.
  • the chip 103 is disposed on the chip connection area 1021, and the chip 103 is connected to the input signal connection pad array 10212 and the output signal connection pad array 10211.
  • the input signal connection pad array 10212 is located on one side of the chip connection area 1021, and the output signal connection pad array 10211 is located on the other side of the chip connection area 1021.
  • the input signal connection pad array 10212 includes at least two input signal connection pads 102121, and at least two of the input signal connection pads 102121 are arranged in an array (one-dimensional array) along the first direction.
  • the output signal connection pad array 10211 includes at least six output signal connection pads 102111, at least six of the output signal connection pads 102111 are arranged in three rows along a second direction perpendicular to the first direction, and at least six of the output signal connections
  • the pads 102111 are arranged in at least two columns along the first direction. That is, at least six of the output signal connection pads 102111 are arranged in a two-dimensional array along the first direction and the second direction.
  • the input signal connection pad 102121 and the output signal connection pad 102111 are both disposed on the substrate or film layer of the peripheral area portion.
  • the first direction is a direction parallel to the straight line corresponding to the intersection of the display area portion and the peripheral area portion, or the first direction is perpendicular to the display area portion and the peripheral area portion The direction of the line corresponding to the intersection.
  • the sum of the width D4 of the gap between the two adjacent output signal connection pads 102111 and the width D3 of the output signal connection pads 102111 is in the range of 20 microns to 36 microns.
  • the sum of the width D4 of the gap between the two adjacent output signal connection pads 102111 and the width D3 of the output signal connection pads 102111 is 28 microns.
  • the width D4 of the gap between two adjacent output signal connection pads 102111 is in the range of 10 microns to 18 microns.
  • the width D4 of the gap between two adjacent output signal connection pads 102111 is 14 ⁇ m.
  • the number of output signal connection pads 102111 in a row of the output signal connection pads 102111 is in the range of 900 to 1020.
  • the number of output signal connection pads 102111 in a row of the output signal connection pads 102111 is 960.
  • the two edges of the output signal connection pad array 10211 and the chip connection area 1021 have a first pitch D1 and a second pitch D2, respectively;
  • Both the first pitch D1 and the second pitch D2 are in the range of 100 microns to 180 microns.
  • the first pitch D1 and the second pitch D2 are both 140 microns.
  • the chip 103 includes at least two input pins and at least two output pins.
  • the input pin is connected to the input signal connection pad 102121, and the output pin is connected to the output signal connection pad 102111.
  • the chip connection area 1021 is also provided with at least one alignment mark 10213.
  • the alignment mark 10213 is used to make the chip 103 and the panel body 102 be fixed (welded) as a whole
  • the panel body 102 is aligned, so that the chip 103 is disposed at a predetermined position of the chip connection area 1021 of the panel body 102.
  • the alignment mark 10213 is disposed at the edge or corner of the chip connection area 1021.
  • the edge of the output signal connection pad array 10211 and the edge of the peripheral area portion have a predetermined distance.
  • a redundant connection pad (Dummy Pad) array is further provided between the input signal connection pad array 10212 and the output signal connection pad array 10211, and the redundant connection pad array includes at least two redundant connection pads.
  • the redundant connection pads are formed simultaneously during the process of forming the input signal connection pads 102121 and/or the output signal connection pads 102111.
  • the redundant connection pad is used to support the chip 103 fixed to the panel body 102. Specifically, the redundant connection pad supports an intermediate region of the bottom of the chip 103 (the chip 103 An area between the input pin and the output pin) to improve the tightness of the connection between the input pin and the input signal connection pad 102121, and/or to increase the output pin and the output
  • the tightness of the connection of the signal connection pads 102111 so as to prevent the chip 103 from being effectively supported, so that the chip 103 exerts a force on the input pins and/or the output pins, which is helpful to avoid the
  • the input pin is disconnected from the input signal connection pad 102121, or the output pin is prevented from being disconnected from the output signal connection pad 102111.
  • the width (dimension in the first direction) of the input signal connection pad 102121 is in the range of 20 ⁇ m to 40 ⁇ m. Specifically, the width of the input signal connection pad 102121 is 30 ⁇ m. In the first direction, the width of the gap between two adjacent input signal connection pads 102121 is in the range of 10 ⁇ m to 20 ⁇ m, specifically, between the two adjacent input signal connection pads 102121 The width of the gap is 15 microns.
  • the length (dimension in the second direction) of the input signal connection pad 102121 is in the range of 120 ⁇ m to 160 ⁇ m. Specifically, the length of the input signal connection pad 102121 is 140 ⁇ m.
  • the width (dimension in the first direction) of the output signal connection pad 102111 is in the range of 10 microns to 18 microns. Specifically, the width of the output signal connection pad 102111 is 14 microns.
  • the length (dimension in the second direction) of the output signal connection pad 102111 is in the range of 100 ⁇ m to 160 ⁇ m. Specifically, the length of the output signal connection pad 102111 is 130 microns.
  • the area where the input pin overlaps (contacts) the input signal connection pad 102121 is greater than 1000 square microns.
  • the area where the output pin overlaps (contacts) the output signal connection pad 102111 is greater than 1000 square microns.
  • the input signal connection pad array includes at least two input signal connection pads, at least two of which Input signal connection pads are arranged in an array along a first direction;
  • the output signal connection pad array includes at least six output signal connection pads, and at least six of the output signal connection pads are arranged in a second direction perpendicular to the first direction In three rows, at least six of the output signal connection pads are arranged in at least two columns along the first direction. Therefore, the present invention can be adapted to multiple types of chips, not limited to single-pin type chips.

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Abstract

本发明公开了一种显示面板的外围区部分设置有芯片连接区，芯片连接区上设置有至少两输入信号连接垫和至少六输出信号连接垫，至少两输入信号连接垫沿第一方向以阵列的形式排列；至少六输出信号连接垫沿第二方向排列成三行，至少六输出信号连接垫沿第一方向排列成至少两列。本发明能适应多种类型的芯片。

Description

显示面板 技术领域
本发明涉及显示技术领域，特别涉及一种显示面板。
 背景技术
传统的显示面板一般设置有连接垫（Pad），芯片设置于所述显示面板上，并且所述芯片通过所述连接垫与所述显示面板连接。
在实践中，发明人发现现有技术至少存在以下技术问题：
所述显示面板上与所述芯片对应的连接区域仅能适应管脚类型单一的芯片，而无法适应不同管脚类型的芯片。
故有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种显示面板，其能适应多种类型的芯片。
 技术解决方案
为解决上述问题，本发明的技术方案如下：
一种显示面板，所述显示面板包括显示区部分和外围区部分，所述外围区部分设置有芯片连接区，所述芯片连接区上设置有输入信号连接垫阵列和输出信号连接垫阵列；其中，所述输入信号连接垫阵列位于所述芯片连接区的一侧，所述输出信号连接垫阵列位于所述芯片连接区的另一侧；所述输入信号连接垫阵列包括至少两输入信号连接垫，至少两所述输入信号连接垫沿第一方向以阵列的形式排列；所述输出信号连接垫阵列包括至少六输出信号连接垫，至少六所述输出信号连接垫沿与所述第一方向垂直的第二方向排列成三行，至少六所述输出信号连接垫沿所述第一方向排列成至少两列；在所述第一方向上，相邻两所述输出信号连接垫之间的间隙的宽度与所述输出信号连接垫的宽度之和处于20微米至36微米的范围内；在所述第一方向上，一行所述输出信号连接垫中所述输出信号连接垫的数量处于900至1020的范围内。
在上述显示面板中，在所述第一方向上，相邻两所述输出信号连接垫之间的间隙的宽度与所述输出信号连接垫的宽度之和为28微米。
在上述显示面板中，在所述第一方向上，相邻两所述输出信号连接垫之间的间隙的宽度处于10微米至18微米的范围内。
在上述显示面板中，在所述第一方向上，相邻两所述输出信号连接垫之间的间隙的宽度为14微米。
一种显示面板，所述显示面板包括显示区部分和外围区部分，所述外围区部分设置有芯片连接区，所述芯片连接区上设置有输入信号连接垫阵列和输出信号连接垫阵列；其中，所述输入信号连接垫阵列位于所述芯片连接区的一侧，所述输出信号连接垫阵列位于所述芯片连接区的另一侧；所述输入信号连接垫阵列包括至少两输入信号连接垫，至少两所述输入信号连接垫沿第一方向以阵列的形式排列；所述输出信号连接垫阵列包括至少六输出信号连接垫，至少六所述输出信号连接垫沿与所述第一方向垂直的第二方向排列成三行，至少六所述输出信号连接垫沿所述第一方向排列成至少两列。
在上述显示面板中，在所述第一方向上，相邻两所述输出信号连接垫之间的间隙的宽度与所述输出信号连接垫的宽度之和处于20微米至36微米的范围内。
在上述显示面板中，在所述第一方向上，相邻两所述输出信号连接垫之间的间隙的宽度与所述输出信号连接垫的宽度之和为28微米。
在上述显示面板中，在所述第一方向上，相邻两所述输出信号连接垫之间的间隙的宽度处于10微米至18微米的范围内。
在上述显示面板中，在所述第一方向上，相邻两所述输出信号连接垫之间的间隙的宽度为14微米。
在上述显示面板中，在所述第一方向上，一行所述输出信号连接垫中所述输出信号连接垫的数量处于900至1020的范围内。
在上述显示面板中，在所述第一方向上，一行所述输出信号连接垫中所述输出信号连接垫的数量960。
在上述显示面板中，在所述第一方向上，所述输出信号连接垫阵列与所述芯片连接区的两边缘分别具有第一间距和第二间距；所述第一间距和所述第二间距均处于100微米至180微米的范围内。
在上述显示面板中，所述第一间距和所述第二间距均为140微米。
在上述显示面板中，所述显示面板还包括芯片，所述芯片包括至少两输入管脚和至少两输出管脚；所述输入管脚与所述输入信号连接垫连接，所述输出管脚与所述输出信号连接垫连接。
在上述显示面板中，所述输入信号连接垫阵列和所述输出信号连接垫阵列之间还设置有冗余连接垫阵列，所述冗余连接垫阵列包括至少两冗余连接垫；所述冗余连接垫用于对与所述面板主体相固定的所述芯片进行支撑。
在上述显示面板中，所述冗余连接垫是在形成所述输入信号连接垫和/或所述输出信号连接垫的过程中同时形成的。
在上述显示面板中，所述输入管脚与所述输入信号连接垫重叠的面积大于1000平方微米；所述输出管脚与所述输出信号连接垫重叠的面积大于1000平方微米。
在上述显示面板中，所述输入信号连接垫的宽度处于20微米至40微米的范围内；所述输入信号连接垫的长度处于120微米至160微米的范围内。
在上述显示面板中，所述输出信号连接垫的宽度处于10微米至18微米的范围内；所述输出信号连接垫的长度处于100微米至160微米的范围内。
在上述显示面板中，所述芯片连接区中还设置有至少一对位标识，所述对位标识用于在所述芯片与所述面板主体相固定为一体时使得所述芯片与所述面板主体对位。
 有益效果
相对现有技术，由于所述显示面板的所述芯片连接区上设置有输入信号连接垫阵列和输出信号连接垫阵列，所述输入信号连接垫阵列包括至少两输入信号连接垫，至少两所述输入信号连接垫沿第一方向以阵列的形式排列；所述输出信号连接垫阵列包括至少六输出信号连接垫，至少六所述输出信号连接垫沿与所述第一方向垂直的第二方向排列成三行，至少六所述输出信号连接垫沿所述第一方向排列成至少两列，因此，本发明能适应多种类型的芯片，而不限于单一管脚类型的芯片。
 附图说明
图1为本发明的显示面板的示意图。
图2为图1所示的显示面板中芯片连接区的示意图。
图3为图2所示的芯片连接区中两输出信号连接垫之间的位置关系。
 本发明的实施方式
本说明书所使用的词语“实施例”意指实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为“一个或多个”，除非另外指定或从上下文可以清楚确定单数形式。
参考图1、图2和图3，图1为本发明的显示面板10的示意图，图2为图1所示的显示面板10中芯片连接区1021的示意图，图3为图2所示的芯片连接区1021中两输出信号连接垫102111之间的位置关系。
本发明的显示面板10可以是OLED（Organic Light Emitting Diode，有机发光二极管显示面板）等。
本发明的显示面板10包括柔性电路板（FPC，Flexible Printed Circuit）101、面板主体102和芯片（DIC，Driver Integrated Circuit）103，所述柔性电路板101与所述面板主体102相连，所述面板主体102包括显示区部分和外围区部分，所述外围区部分设置有芯片连接区1021，所述芯片连接区1021上设置有输入信号连接垫阵列10212和输出信号连接垫阵列10211。所述芯片103设置于所述芯片连接区1021上，并且，所述芯片103与所述输入信号连接垫阵列10212和所述输出信号连接垫阵列10211相连。
其中，所述输入信号连接垫阵列10212位于所述芯片连接区1021的一侧，所述输出信号连接垫阵列10211位于所述芯片连接区1021的另一侧。
所述输入信号连接垫阵列10212包括至少两输入信号连接垫102121，至少两所述输入信号连接垫102121沿第一方向以阵列（一维阵列）的形式排列。
所述输出信号连接垫阵列10211包括至少六输出信号连接垫102111，至少六所述输出信号连接垫102111沿与所述第一方向垂直的第二方向排列成三行，至少六所述输出信号连接垫102111沿所述第一方向排列成至少两列。即，至少六所述输出信号连接垫102111沿所述第一方向以及所述第二方向以二维阵列的形式排列。
所述输入信号连接垫102121和所述输出信号连接垫102111均设置于所述外围区部分的基板或膜层上。
所述第一方向为平行于所述显示区部分与所述外围区部分的交汇处所对应的直线的方向，或者，所述第一方向为垂直于所述显示区部分与所述外围区部分的交汇处所对应的直线的方向。
在所述第一方向上，相邻两所述输出信号连接垫102111之间的间隙的宽度D4与所述输出信号连接垫102111的宽度之和D3处于20微米至36微米的范围内。
在所述第一方向上，相邻两所述输出信号连接垫102111之间的间隙的宽度D4与所述输出信号连接垫102111的宽度之和D3为28微米。
在所述第一方向上，相邻两所述输出信号连接垫102111之间的间隙的宽度D4处于10微米至18微米的范围内。
在所述第一方向上，相邻两所述输出信号连接垫102111之间的间隙的宽度D4为14微米。
在所述第一方向上，一行所述输出信号连接垫102111中所述输出信号连接垫102111的数量处于900至1020的范围内。
在所述第一方向上，一行所述输出信号连接垫102111中所述输出信号连接垫102111的数量960。
在所述第一方向上，所述输出信号连接垫阵列10211与所述芯片连接区1021的两边缘分别具有第一间距D1和第二间距D2；
所述第一间距D1和所述第二间距D2均处于100微米至180微米的范围内。
所述第一间距D1和所述第二间距D2均为140微米。
所述芯片103包括至少两输入管脚和至少两输出管脚。
所述输入管脚与所述输入信号连接垫102121连接，所述输出管脚与所述输出信号连接垫102111连接。
所述芯片连接区1021中还设置有至少一对位标识10213，所述对位标识10213用于在所述芯片103与所述面板主体102相固定（焊接）为一体时使得所述芯片103与所述面板主体102对位，从而使得所述芯片103设置在所述面板主体102的所述芯片连接区1021的预定位置处。所述对位标识10213设置于所述芯片连接区1021的边缘或角落处。
在所述第二方向上，所述输出信号连接垫阵列10211的边缘与所述外围区部分的边缘具有预定间距。
所述输入信号连接垫阵列10212和所述输出信号连接垫阵列10211之间还设置有冗余连接垫（Dummy Pad）阵列，所述冗余连接垫阵列包括至少两冗余连接垫。所述冗余连接垫是在形成所述输入信号连接垫102121和/或所述输出信号连接垫102111的过程中同时形成的。
所述冗余连接垫用于对与所述面板主体102相固定的所述芯片103进行支撑，具体地，所述冗余连接垫支撑所述芯片103的底部的中间区域（所述芯片103的所述输入管脚和所述输出管脚之间的区域），以提高所述输入管脚与所述输入信号连接垫102121连接的紧密度，和/或提高所述输出管脚与所述输出信号连接垫102111连接的紧密度，从而避免所述芯片103因得不到有效支撑而使得所述芯片103向所述输入管脚和/或所述输出管脚施加作用力，有利于避免所述输入管脚与所述输入信号连接垫102121断开，或者避免所述输出管脚与所述输出信号连接垫102111断开。
所述输入信号连接垫102121的宽度（在所述第一方向上的尺寸）处于20微米至40微米的范围内，具体地，所述输入信号连接垫102121的宽度为30微米。在所述第一方向上，相邻两所述输入信号连接垫102121之间的间隙的宽度处于10微米至20微米的范围内，具体地，相邻两所述输入信号连接垫102121之间的间隙的宽度为15微米。所述输入信号连接垫102121的长度（在所述第二方向上的尺寸）处于120微米至160微米的范围内，具体地，所述输入信号连接垫102121的长度为140微米。
所述输出信号连接垫102111的宽度（在所述第一方向上的尺寸）处于10微米至18微米的范围内。具体地，所述输出信号连接垫102111的宽度为14微米。所述输出信号连接垫102111的长度（在所述第二方向上的尺寸）处于100微米至160微米的范围内。具体地，所述输出信号连接垫102111的长度为130微米。
所述输入管脚与所述输入信号连接垫102121重叠（接触）的面积大于1000平方微米。所述输出管脚与所述输出信号连接垫102111重叠（接触）的面积大于1000平方微米。
在本发明中，由于所述显示面板的所述芯片连接区上设置有输入信号连接垫阵列和输出信号连接垫阵列，所述输入信号连接垫阵列包括至少两输入信号连接垫，至少两所述输入信号连接垫沿第一方向以阵列的形式排列；所述输出信号连接垫阵列包括至少六输出信号连接垫，至少六所述输出信号连接垫沿与所述第一方向垂直的第二方向排列成三行，至少六所述输出信号连接垫沿所述第一方向排列成至少两列，因此，本发明能适应多种类型的芯片，而不限于单一管脚类型的芯片。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括显示区部分和外围区部分，所述外围区部分设置有芯片连接区，所述芯片连接区上设置有输入信号连接垫阵列和输出信号连接垫阵列；
    其中，所述输入信号连接垫阵列位于所述芯片连接区的一侧，所述输出信号连接垫阵列位于所述芯片连接区的另一侧；
    所述输入信号连接垫阵列包括至少两输入信号连接垫，至少两所述输入信号连接垫沿第一方向以阵列的形式排列；
    所述输出信号连接垫阵列包括至少六输出信号连接垫，至少六所述输出信号连接垫沿与所述第一方向垂直的第二方向排列成三行，至少六所述输出信号连接垫沿所述第一方向排列成至少两列；
    在所述第一方向上，相邻两所述输出信号连接垫之间的间隙的宽度与所述输出信号连接垫的宽度之和处于20微米至36微米的范围内；
    在所述第一方向上，一行所述输出信号连接垫中所述输出信号连接垫的数量处于900至1020的范围内。
  2. 根据权利要求1所述的显示面板，其中，在所述第一方向上，相邻两所述输出信号连接垫之间的间隙的宽度与所述输出信号连接垫的宽度之和为28微米。
  3. 根据权利要求1所述的显示面板，其中，在所述第一方向上，相邻两所述输出信号连接垫之间的间隙的宽度处于10微米至18微米的范围内。
  4. 根据权利要求3所述的显示面板，其中，在所述第一方向上，相邻两所述输出信号连接垫之间的间隙的宽度为14微米。
  5. 一种显示面板，其中，所述显示面板包括显示区部分和外围区部分，所述外围区部分设置有芯片连接区，所述芯片连接区上设置有输入信号连接垫阵列和输出信号连接垫阵列；
    其中，所述输入信号连接垫阵列位于所述芯片连接区的一侧，所述输出信号连接垫阵列位于所述芯片连接区的另一侧；
    所述输入信号连接垫阵列包括至少两输入信号连接垫，至少两所述输入信号连接垫沿第一方向以阵列的形式排列；
    所述输出信号连接垫阵列包括至少六输出信号连接垫，至少六所述输出信号连接垫沿与所述第一方向垂直的第二方向排列成三行，至少六所述输出信号连接垫沿所述第一方向排列成至少两列。
  6. 根据权利要求5所述的显示面板，其中，在所述第一方向上，相邻两所述输出信号连接垫之间的间隙的宽度与所述输出信号连接垫的宽度之和处于20微米至36微米的范围内。
  7. 根据权利要求6所述的显示面板，其中，在所述第一方向上，相邻两所述输出信号连接垫之间的间隙的宽度与所述输出信号连接垫的宽度之和为28微米。
  8. 根据权利要求6所述的显示面板，其中，在所述第一方向上，相邻两所述输出信号连接垫之间的间隙的宽度处于10微米至18微米的范围内。
  9. 根据权利要求8所述的显示面板，其中，在所述第一方向上，相邻两所述输出信号连接垫之间的间隙的宽度为14微米。
  10. 根据权利要求5所述的显示面板，其中，在所述第一方向上，一行所述输出信号连接垫中所述输出信号连接垫的数量处于900至1020的范围内。
  11. 根据权利要求10所述的显示面板，其中，在所述第一方向上，一行所述输出信号连接垫中所述输出信号连接垫的数量960。
  12. 根据权利要求5所述的显示面板，其中，在所述第一方向上，所述输出信号连接垫阵列与所述芯片连接区的两边缘分别具有第一间距和第二间距；
    所述第一间距和所述第二间距均处于100微米至180微米的范围内。
  13. 根据权利要求12所述的显示面板，其中，所述第一间距和所述第二间距均为140微米。
  14. 根据权利要求5所述的显示面板，其中，所述显示面板还包括芯片，所述芯片包括至少两输入管脚和至少两输出管脚；
    所述输入管脚与所述输入信号连接垫连接，所述输出管脚与所述输出信号连接垫连接。
  15. 根据权利要求5所述的显示面板，其中，所述输入信号连接垫阵列和所述输出信号连接垫阵列之间还设置有冗余连接垫阵列，所述冗余连接垫阵列包括至少两冗余连接垫；
    所述冗余连接垫用于对与所述面板主体相固定的所述芯片进行支撑。
  16. 根据权利要求15所述的显示面板，其中，所述冗余连接垫是在形成所述输入信号连接垫和/或所述输出信号连接垫的过程中同时形成的。
  17. 根据权利要求5所述的显示面板，其中，所述输入管脚与所述输入信号连接垫重叠的面积大于1000平方微米；
    所述输出管脚与所述输出信号连接垫重叠的面积大于1000平方微米。
  18. 根据权利要求5所述的显示面板，其中，所述输入信号连接垫的宽度处于20微米至40微米的范围内；
    所述输入信号连接垫的长度处于120微米至160微米的范围内。
  19. 根据权利要求5所述的显示面板，其中，所述输出信号连接垫的宽度处于10微米至18微米的范围内；
    所述输出信号连接垫的长度处于100微米至160微米的范围内。
  20. 根据权利要求5所述的显示面板，其中，所述芯片连接区中还设置有至少一对位标识，所述对位标识用于在所述芯片与所述面板主体相固定为一体时使得所述芯片与所述面板主体对位。
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