WO2020124774A1 - Tft阵列基板及其制作方法与oled显示面板 - Google Patents

Tft阵列基板及其制作方法与oled显示面板 Download PDF

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Publication number
WO2020124774A1
WO2020124774A1 PCT/CN2019/075633 CN2019075633W WO2020124774A1 WO 2020124774 A1 WO2020124774 A1 WO 2020124774A1 CN 2019075633 W CN2019075633 W CN 2019075633W WO 2020124774 A1 WO2020124774 A1 WO 2020124774A1
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Prior art keywords
layer
electrode
insulating layer
film
gate insulating
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French (fr)
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余赟
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/644,967 priority Critical patent/US11177332B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the invention relates to the field of display technology, in particular to a TFT array substrate, a manufacturing method thereof and an OLED display panel.
  • Organic light emitting diode display (Organic Light Emitting Display, OLED) has self-luminous, low driving voltage, high luminous efficiency, short response time, high definition and contrast, close to 180 ° viewing angle, wide use temperature range, can achieve flexible display and The large area full-color display and many other advantages are recognized by the industry as the most promising display device.
  • OLED can be divided into passive matrix OLED (Passive Matrix) OLED, PMOLED) and Active Matrix OLED (Active Matrix OLED, AMOLED) are two categories, namely direct addressing and thin film transistor (TFT) matrix addressing.
  • AMOLED has pixels arranged in an array, which is an active display type and has high luminous efficacy, and is generally used as a high-definition large-size display device.
  • OLED devices generally include: a substrate, an anode provided on the substrate, a hole injection layer provided on the anode, a hole transport layer provided on the hole injection layer, a light emitting layer provided on the hole transport layer, An electron transport layer on the light-emitting layer, an electron injection layer provided on the electron transport layer, and a cathode provided on the electron injection layer.
  • the principle of light emission of OLED devices is that semiconductor materials and organic light-emitting materials are driven by an electric field, which causes light emission through carrier injection and recombination.
  • OLED devices usually use indium tin oxide (ITO) electrodes and metal electrodes as the anode and cathode of the device, respectively, under a certain voltage drive, electrons and holes are injected from the cathode and anode into the electron transport layer and hole transport layer, respectively.
  • ITO indium tin oxide
  • the electrons and holes migrate to the light-emitting layer through the electron-transport layer and the hole-transport layer, and meet in the light-emitting layer to form excitons and excite the light-emitting molecules.
  • the latter emits visible light after radiation relaxation.
  • an existing OLED display panel includes a base substrate 100, a barrier layer 200 provided on the base substrate 100, an active layer 300 provided on the barrier layer 200, and the active layer 300 and The first gate insulating layer 410 on the barrier layer 200, the first gate 510 disposed on the first gate insulating layer 410 and above the active layer 300, the first gate insulating layer 410 and the first gate
  • the second gate insulating layer 420 on the electrode 510, the second gate 520 provided on the second gate insulating layer 420 and above the first gate 510, the second gate 520 and the second gate are insulated
  • the first gate insulating layer 410, the second gate insulating layer 420, and the interlayer insulating layer 600 are provided with a first via 411 and a second via 412 above the two ends of the active layer 300, a source 710 and a drain 720 is in contact with both ends of the active layer 300 through the first via 411 and the second via 412 respectively, the planarization layer 800 is provided with a third via 810 on the drain 720, and the first electrode 900 passes through the third via 810 is in contact with the drain 720, the pixel definition layer 1000 is provided with an opening 1010 on the first electrode 900, and the organic light emitting layer 1100 and the second electrode 1200 are both located in the opening 1010.
  • a capacitance is formed between the first gate 510 and the second gate 520.
  • Nine mask processes are required to fabricate the OLED display panel, which are used to form the active layer 300, the first gate 510, the second gate 520, the first via 411 and the second via 412, the source 710 and the drain 720, the third via 810, the first electrode 900, the opening 1010, and the spacer 1300 require a large number of photomasks and a complicated manufacturing process, which increases the cost of the OLED display panel.
  • the object of the present invention is to provide a method for manufacturing a TFT array substrate, which requires a small number of photomasks, a simple process, and can effectively reduce product costs.
  • Another object of the present invention is to provide a TFT array substrate with a small number of photomasks required for manufacturing, a simple manufacturing process, and low product cost.
  • Another object of the present invention is to provide an OLED display panel with a small number of masks required for manufacturing, a simple manufacturing process, and low product cost.
  • the present invention first provides a method for manufacturing a TFT array substrate, including the following steps:
  • Step S1 providing a base substrate, forming and patterning a semiconductor material film on the base substrate to form a first semiconductor pattern;
  • Step S2 forming a gate insulating layer on the first semiconductor pattern and the base substrate;
  • Step S3 forming and patterning a first metal film on the gate insulating layer to form a gate above the first semiconductor pattern; the gate exposes both ends of the first semiconductor pattern;
  • Step S4 Doping the first semiconductor pattern with the gate as a shield to form an active pattern
  • Step S5 forming and patterning a conductive material film on the gate insulating layer to form a first electrode spaced apart from the active pattern in the horizontal direction;
  • Step S6 forming an interlayer insulating layer on the first electrode, the gate and the gate insulating layer; patterning the interlayer insulating layer and the gate insulating layer to form a first opening above the first electrode and forming an active pattern on the first electrode A first via and a second via are formed above both ends of
  • Step S7 forming and patterning a second metal film on the first electrode and the interlayer insulating layer to form spaced source and drain electrodes; the source electrode and the drain electrode are active through the first via hole and the second via hole, respectively The two ends of the pattern are in contact; the end of the source electrode near the first electrode contacts the end of the first electrode near the source electrode through the first opening.
  • a barrier layer is also formed on the base substrate, and the semiconductor material film is formed on the barrier layer;
  • the gate insulating layer is formed on the first semiconductor pattern and the barrier layer;
  • the manufacturing method of the TFT array substrate further includes:
  • Step S8 forming a planarization layer on the interlayer insulating layer, the first electrode, the source and the drain, patterning the planarization layer, and forming a second opening in the first opening above the first electrode;
  • Step S9 Form and pattern an organic material film on the planarization layer to form a spacer.
  • step S1 while patterning the semiconductor material film to form a first semiconductor pattern, a second semiconductor pattern spaced apart from the first semiconductor pattern is also formed;
  • the gate insulating layer is also formed on the second semiconductor pattern
  • the first semiconductor pattern is doped with the gate as a shield to form an active pattern, and the second semiconductor pattern is also doped to form a first capacitive electrode plate;
  • the first electrode formed in step S5 is spaced apart from the first capacitor plate in the horizontal direction;
  • the interlayer insulating layer and the gate insulating layer are patterned to form the first opening, the first via hole and the second via hole, and also above the gate insulating layer on the first capacitor plate Forming a third opening;
  • step S7 while patterning the second metal film to form the source electrode and the drain electrode, a second capacitor electrode plate spaced apart from the source electrode and the drain electrode is formed; the second capacitor electrode plate is located on the first capacitor electrode Above the board, the second capacitive electrode plate covers the third opening.
  • the active pattern includes a channel opposite to the gate, and a source contact region and a drain contact region respectively located at both ends of the channel;
  • the first via hole and the second via hole are respectively located above the source contact region and the drain contact region; the source electrode and the drain electrode are in contact with the source contact region and the drain contact region via the first via hole and the second via hole, respectively .
  • a barrier layer is formed on the base substrate by means of plasma enhanced chemical vapor deposition;
  • the barrier layer is a silicon oxide layer, a silicon nitride layer, or a stacked structure of a silicon oxide layer and a silicon nitride layer;
  • the semiconductor material film is a polycrystalline silicon film.
  • the specific process of forming the semiconductor material film on the barrier layer in step S1 is: forming a single crystal silicon film on the barrier layer by plasma enhanced chemical vapor deposition The film is subjected to excimer laser annealing to form a polysilicon film;
  • a plasma-enhanced chemical vapor deposition method is used to form a gate insulating layer on the first semiconductor pattern and the barrier layer;
  • the gate insulating layer is a silicon oxide layer, a silicon nitride layer, or a silicon oxide layer and nitrogen Stacked structure of silicon layers;
  • a first metal film is formed on the gate insulating layer by physical vapor deposition;
  • the first metal film is a single-layer molybdenum film, a single-layer chromium film, a single-layer molybdenum tungsten film, and two layers of titanium One of film sandwiching one aluminum film and two molybdenum films sandwiching one aluminum film;
  • step S5 a physical vapor deposition method is used to form a conductive material film on the gate insulating layer;
  • the conductive material film is a two-layer indium tin oxide film sandwiched with an aluminum film or a single layer of indium tin oxide film, a single layer of aluminum Laminated structure of film and single-layer indium zinc oxide film;
  • an interlayer insulating layer is formed on the first electrode, the gate and the gate insulating layer by means of plasma enhanced chemical vapor deposition;
  • the interlayer insulating layer is a silicon oxide layer, a silicon nitride layer or an oxide Stacked structure of silicon layer and silicon nitride layer;
  • a second metal film is formed on the first electrode and the interlayer insulating layer by physical vapor deposition; the second metal film is two titanium films sandwiched by an aluminum film or two molybdenum films sandwiched by one Aluminum film
  • a planarizing layer is coated on the interlayer insulating layer, the first electrode, the source electrode and the drain electrode by using a coating machine; the material of the planarizing layer is an organic material.
  • step S9 an organic material film is coated on the planarizing layer with a coating machine.
  • the invention also provides a TFT array substrate, including a base substrate, an active pattern provided on the base substrate, a gate insulating layer provided on the base substrate and the active pattern, and provided on the gate insulating layer and A gate located above the active pattern, a first electrode disposed on the gate insulating layer and spaced from the active pattern, an interlayer insulating layer disposed on the first electrode, the gate and the gate insulating layer, and a layer disposed on the layer Separated source and drain on the inter-insulation layer;
  • the gate exposes both ends of the active pattern; the interlayer insulating layer is provided with a first opening above the first electrode; the interlayer insulating layer and the gate insulating layer are respectively above the two ends of the active pattern.
  • the first via hole and the second via hole are provided; the source electrode and the drain electrode are in contact with both ends of the active pattern through the first via hole and the second via hole; the end of the source electrode near the first electrode passes through the first opening and The end of the first electrode near the source contacts.
  • the TFT array substrate further includes a barrier layer provided on the base substrate, a first capacitive electrode plate provided on the barrier layer spaced from the active pattern, and an interlayer insulating layer spaced from both the source electrode and the drain electrode
  • the active pattern is provided on the barrier layer, and the gate insulating layer is provided on the active pattern, the barrier layer and the first capacitor plate; the first electrode and the first capacitor plate are spaced apart in the horizontal direction;
  • the planarization layer has a second opening above the first electrode in the first opening; the interlayer insulating layer forms a third opening above the gate insulating layer on the first capacitor plate; the second capacitor plate Located above the first capacitor plate, the second capacitor plate covers the third opening.
  • the barrier layer is a silicon oxide layer, a silicon nitride layer, or a stacked structure of a silicon oxide layer and a silicon nitride layer;
  • the materials of the active pattern and the second capacitor plate are both polysilicon, and both ends of the active pattern exposed by the gate and the second capacitor plate are ion-doped;
  • the gate insulating layer is a silicon oxide layer, a silicon nitride layer, or a stacked structure of a silicon oxide layer and a silicon nitride layer;
  • the structure of the grid is one of a single-layer molybdenum film, a single-layer chromium film, a single-layer molybdenum tungsten film, a two-layer titanium film sandwiching one aluminum film, and two two-layer molybdenum films sandwiching one aluminum film;
  • the structure of the first electrode is a stacked structure of two layers of indium tin oxide film sandwiched by an aluminum film or a single layer of indium tin oxide film, a single layer of aluminum film and a single layer of indium zinc oxide film;
  • the interlayer insulating layer is a silicon oxide layer, a silicon nitride layer, or a stacked structure of a silicon oxide layer and a silicon nitride layer;
  • the structure of the source electrode, the drain electrode and the second capacitor electrode plate are two layers of titanium film sandwiched with an aluminum film or two layers of molybdenum film sandwiched with an aluminum film;
  • the material of the planarization layer is an organic material.
  • the active pattern includes a channel opposite to the gate, and a source contact region and a drain contact region respectively located at both ends of the channel;
  • the first via hole and the second via hole are respectively located above the source contact region and the drain contact region; the source electrode and the drain electrode are in contact with the source contact region and the drain contact region via the first via hole and the second via hole, respectively .
  • the invention also provides an OLED display panel, including the above-mentioned TFT array substrate.
  • the manufacturing method of the TFT array substrate of the present invention respectively uses a photomask to make active patterns, gates, first electrodes, interlayer insulating layers, vias, openings in the gate insulating layer, and source electrodes ,
  • the drain, the opening on the planarization layer, and the spacer, the required number of photomasks is small, the process is simple, and the production efficiency can be effectively improved and the product cost can be reduced.
  • the TFT array substrate of the present invention requires a small number of photomasks, the manufacturing process is simple, and the product cost is low.
  • the OLED display panel of the present invention requires a small number of photomasks, the manufacturing process is simple, and the product cost is low.
  • FIG. 1 is a schematic structural diagram of an existing OLED display panel
  • FIG. 2 is a flowchart of a method for manufacturing a TFT array substrate of the present invention
  • step S1 of the method for manufacturing a TFT array substrate of the present invention is a schematic diagram of step S1 of the method for manufacturing a TFT array substrate of the present invention
  • step S2 is a schematic diagram of step S2 of the method for manufacturing a TFT array substrate of the present invention
  • step S3 is a schematic diagram of step S3 of the method for manufacturing a TFT array substrate of the present invention.
  • step S4 of the method for manufacturing a TFT array substrate of the present invention
  • step S5 is a schematic diagram of step S5 of the method for manufacturing a TFT array substrate of the present invention.
  • step S6 is a schematic diagram of step S6 of the method for manufacturing a TFT array substrate of the present invention.
  • step S7 of the method for manufacturing a TFT array substrate of the present invention.
  • step S8 of the method for manufacturing a TFT array substrate of the present invention is a schematic diagram of step S8 of the method for manufacturing a TFT array substrate of the present invention.
  • step S9 of the manufacturing method of the TFT array substrate of the present invention is a schematic diagram of step S9 of the manufacturing method of the TFT array substrate of the present invention and a schematic structural diagram of the TFT array substrate of the present invention
  • FIG. 12 is a schematic structural diagram of an OLED display panel of the present invention.
  • the manufacturing method of the array substrate includes the following steps:
  • step S1 Please refer to the picture 3 , Provide base substrate 1 , In the base substrate 1 A semiconductor material film is formed thereon and patterned using a first mask, while forming spaced first semiconductor patterns 38 And the second semiconductor pattern 39 .
  • the steps S1 Plasma enhanced chemical vapor deposition ( PECVD ) Way in the base substrate 1 Barrier layer 2 .
  • the barrier layer 2 It is a silicon oxide layer, a silicon nitride layer, or a stacked structure of a silicon oxide layer and a silicon nitride layer.
  • the semiconductor material film is a polysilicon film
  • the step S1 Middle barrier 2 The specific process of forming a semiconductor material film on the top is: using plasma enhanced chemical vapor deposition on the barrier layer 2 A single crystal silicon film is formed thereon, and the single crystal silicon film is subjected to excimer laser annealing to polycrystallize it to form a polycrystalline silicon film.
  • step S2 Please refer to the picture 4 , In the first semiconductor pattern 38 ⁇ Second semiconductor pattern 39 And substrate 1 Gate insulating layer 4 .
  • the steps S2 Plasma enhanced chemical vapor deposition is used in the first semiconductor pattern 38 ⁇ Second semiconductor pattern 39 Barrier layer 2 Gate insulating layer 4 .
  • the gate insulating layer 4 It is a silicon oxide layer, a silicon nitride layer, or a stacked structure of a silicon oxide layer and a silicon nitride layer.
  • step S3 Please refer to the picture 5 , In the gate insulating layer 4 Forming a first metal film on it and patterning with a second mask to form a pattern on the first semiconductor 38 Upper gate 5 . The gate 5 The first semiconductor pattern is exposed 38 Both ends.
  • the first metal film is formed thereon.
  • the first metal film is a single layer of molybdenum ( Mo ) Film, single layer chromium ( Cr ) Film, single layer molybdenum tungsten ( MoW ) Film, two layers of titanium ( Ti ) Film clip a layer of aluminum ( Al ) One of the film and the two-layer molybdenum film sandwiching one aluminum film
  • step S4 Please refer to the picture 6 .
  • Use self-aligned method 5 To block the first semiconductor pattern 38 Doping to form active patterns 31 , While also on the second semiconductor pattern 39 Doping to form the first capacitor plate 32 .
  • the active pattern 31 Included with gate 5 Opposite channel 311 And in the channel 311 Source contact area at both ends 312 Drain contact area 313 .
  • step S5 Please refer to the picture 7 , In the gate insulating layer 4 A conductive material film is formed and patterned using a third mask to form an active pattern 31 First electrodes spaced apart in the horizontal direction 6 .
  • steps S5 The first electrode formed 6 With the first capacitor plate 32 They are also spaced apart in the horizontal direction.
  • the steps S5 In the gate insulating layer physical vapor deposition is used 4 A conductive material film is formed thereon.
  • the conductive material film is two layers of indium tin oxide film sandwiched by an aluminum film or a single layer of indium tin oxide film, a single layer of aluminum film and a single layer of indium zinc oxide ( IZO ) The laminated structure of the film.
  • step S6 Please refer to the picture 8 , At the first electrode 6 Gate 5 Gate insulating layer 4 Interlayer insulating layer 7 . Use the fourth mask to interlayer insulation 7 Gate insulating layer 4 To pattern the first electrode 6
  • the first opening is formed above 71 , In active patterns 31 First vias are formed on both ends of 72 And the second via 73 , In the first capacitor plate 32 Gate insulating layer 4 Third opening formed above 74 .
  • the steps S6 Plasma enhanced chemical vapor deposition is used in the first electrode 6 Gate 5 Gate insulating layer 4 Interlayer insulating layer 7 .
  • the interlayer insulating layer 7 It is a silicon oxide layer, a silicon nitride layer, or a stacked structure of a silicon oxide layer and a silicon nitride layer.
  • step S7 Please refer to the picture 9 , At the first electrode 6 And interlayer insulation 7 Forming a second metal film on it and patterning with the fifth mask to form spaced source electrodes 81 , Drain 82 And the second capacitor plate 83 , Source 81 And drain 82 Via the first via 72 And the second via 73 With active pattern 31 Both ends of the contact, the source 81 Close to the first electrode 6 Through the first opening 71 With the first electrode 6 Close to source 81 One end of the contact, the second capacitor plate 83 Located on the first capacitor plate 32 Above, the second capacitor plate 83 Cover the third opening 74 .
  • the source 81 And drain 82 Via the first via 72 And the second via 73 Contact area with source 312 Drain contact area 313 .
  • the second metal film is formed thereon.
  • the second metal film is a two-layer titanium film sandwiched with an aluminum film or two molybdenum films sandwiched with an aluminum film.
  • step S8 Please refer to the picture 10 , In the interlayer insulating layer 7 ⁇ First electrode 6 Source 81 , Drain 82 And the second capacitor plate 83 Planarization layer 9 , Using a sixth mask to the planarization layer 9 Patterned and formed in the first opening 71 Inside the first electrode 6 Upper second opening 91 .
  • the steps S8 In the use of coating machine in the interlayer insulating layer 7 ⁇ First electrode 6 Source 81 And drain 82 Coated with a planarization layer 9 .
  • the planarization layer 9 The material is organic.
  • step S9 Please refer to the picture 11 , In the planarization layer 9 Form an organic material film and pattern it to form a spacer 10 .
  • the steps S9 Use the coating machine in the flattening layer 9 Coated with organic material film.
  • the present invention TFT Array substrate manufacturing method board uses the first mask to make active patterns 31 And the first capacitor plate 32 , Using the second mask to make the grid 5 , Using the third mask to make the first electrode 6 , Using the fourth mask to make interlayer insulation 7 Gate insulating layer 4 The first opening on the 71 , The first via 72 , Second via 73 And the third opening 74 , Using the fifth mask to make the source 81 , Drain 82 And the second capacitor plate 83 , Using the sixth mask to make the planarization layer 9 Second opening 91 , Using the seventh mask to make spacers 10 , A total of 7 Road mask, compared to the existing technology 9 Road mask can be completed TFT For the manufacture of array substrates, the present invention requires a small number of photomasks and a simple process, which can effectively improve production efficiency and reduce product costs.
  • the present invention also provides a TFT Array substrate manufacturing method TFT Array substrate, including substrate substrate 1 ⁇ Set on the base substrate 1 Active pattern 31 ⁇ Set on the base substrate 1 And active patterns 31 Gate insulating layer 4 ⁇ Set in the gate insulating layer 4 On the active pattern 31 Upper gate 5 ⁇ Set in the gate insulating layer 4 Upper and active patterns 31 First electrodes spaced apart in the horizontal direction 6 , Located on the first electrode 6 Gate 5 Gate insulating layer 4 Interlayer insulation 7 And interlayer insulation 7 Upper and spaced source 81 And drain 82 .
  • the gate 5 Active pattern exposed 31 Both ends.
  • the interlayer insulating layer 7 At the first electrode 6 There is a first opening above 71 .
  • the interlayer insulating layer 7 Gate insulating layer 4 Active pattern 31 There are first vias above the two ends of 72 And the second via 73 .
  • Source 81 And drain 82 Via the first via 72 And the second via 73 With active pattern 31 Both ends of the contact.
  • Source 81 Close to the first electrode 6 Through the first opening 71 With the first electrode 6 Close to source 81 Touch one end.
  • the TFT The array substrate further includes a base substrate 1 Barrier layer 2 , Set on the barrier layer 2 Upper and active patterns 31 Spaced first capacitor plate 32 ⁇ Insulating layer 7 Up and source 81 And drain 82 Evenly spaced second capacitor plates 83 ⁇ Insulating layer 7 ⁇ First electrode 6 Source 81 , Drain 82 And the second capacitor plate 83 Planarization layer 9 , Located on the planarization layer 9 Spacer 10 .
  • the active pattern 31 On the barrier layer 2 Upper, gate insulating layer 4 Set in active pattern 31 , Barrier layer 2 And the first capacitor plate 32 on.
  • the first electrode 6 With the first capacitor plate 32 Spaced apart in the horizontal direction, the planarization layer 9 At the first opening 71 Inner first electrode 6 With a second opening above 91 .
  • the interlayer insulating layer 7 On the first capacitor plate 32 Gate insulating layer 4 Third opening formed above 74 .
  • the second capacitor plate 83 Located on the first capacitor plate 32 Above, the second capacitor plate 83 Cover the third opening 74 .
  • the barrier layer 2 It is a silicon oxide layer, a silicon nitride layer, or a stacked structure of a silicon oxide layer and a silicon nitride layer.
  • the active pattern 31 And the second capacitor plate 83 Of the materials are all polysilicon, and the active pattern 31 Gated 5 Exposed ends and second capacitor plate 83 All undergo ion doping.
  • the gate insulating layer 4 It is a silicon oxide layer, a silicon nitride layer, or a stacked structure of a silicon oxide layer and a silicon nitride layer.
  • the gate 5 The structure is one of a single-layer molybdenum film, a single-layer chromium film, a single-layer molybdenum tungsten film, a two-layer titanium film sandwiching a layer of aluminum film, and a two-layer molybdenum film sandwiching a layer of aluminum film.
  • the first electrode 6 The structure is a stacked structure of two layers of indium tin oxide film sandwiched by an aluminum film or a single layer of indium tin oxide film, a single layer of aluminum film and a single layer of indium zinc oxide film.
  • the interlayer insulating layer 7 It is a silicon oxide layer, a silicon nitride layer, or a stacked structure of a silicon oxide layer and a silicon nitride layer.
  • the source 81 , Drain 82 And the second capacitor plate 83 The structure is that two layers of titanium film sandwich a layer of aluminum film or two layers of molybdenum film sandwich a layer of aluminum film.
  • the planarization layer 9 The material is organic.
  • the active pattern 31 Included with gate 5 Opposite channel 311 And in the channel 311 Source contact area at both ends 312 Drain contact area 313 .
  • the first via 72 And the second via 73 Source contact area 312 Drain contact area 313 Above.
  • Source 81 And drain 82 Via the first via 72 And the second via 73 Contact area with source 312 Drain contact area 313 .
  • the present invention TFT
  • the array substrate uses the above TFT Manufactured by the manufacturing method of the array substrate, during the manufacturing, the first mask is used to make the active pattern 31 And the first capacitor plate 32 , Using the second mask to make the grid 5 , Using the third mask to make the first electrode 6 , Using the fourth mask to make interlayer insulation 7 Gate insulating layer 4 The first opening on the 71 , The first via 72 , Second via 73 And the third opening 74 , Using the fifth mask to make the source 81 , Drain 82 And the second capacitor plate 83 , Using the sixth mask to make the planarization layer 9 Second opening 91 , Using the seventh mask to make spacers 10 , A total of need to complete the production 7 Road mask, compared to the existing technology 9 Road mask can be completed TFT
  • the present invention requires a small number of photomasks and a simple process, which can effectively improve production efficiency and reduce product costs.
  • the present invention also provides a OLED Display panel, including the above TFT Array substrate, no longer right here TFT The structure of the array substrate is repeatedly described.
  • the OLED The display panel also includes a second opening 91 Inside the first electrode 6 Organic light-emitting layer 11 And in the organic light-emitting layer 11 On the second electrode 12 , By the first electrode 6 , Organic light-emitting layer 11 And the second electrode 12 composition OLED Device.
  • the present invention OLED
  • the first mask is used to make the active pattern 31 And the first capacitor plate 32 , Using the second mask to make the grid 5 , Using the third mask to make the first electrode 6 , Using the fourth mask to make interlayer insulation 7 Gate insulating layer 4 The first opening on the 71 , The first via 72 , Second via 73 And the third opening 74 , Using the fifth mask to make the source 81 , Drain 82 And the second capacitor plate 83 , Using the sixth mask to make the planarization layer 9 Second opening 91 , Using the seventh mask to make spacers 10 ,carry out OLED
  • the total production of the display panel is required 7 Road mask, compared to the existing technology 9 Road mask can be completed OLED
  • the present invention requires a small number of photomasks and a simple process, which can effectively improve production efficiency and reduce product costs.
  • the present invention TFT
  • the manufacturing method of the array substrate uses a photomask to make the active pattern, the gate, the first electrode, the interlayer insulating layer, the vias and openings on the gate insulating layer, the source, the drain, and the opening on the planarization layer , And spacers, the required number of masks is small, and the process is simple, which can effectively improve production efficiency and reduce product costs.
  • the invention TFT The array substrate manufacturing requires a small number of photomasks, the manufacturing process is simple, and the product cost is low.
  • the invention OLED The number of photomasks required for the manufacture of the display panel is small, the manufacturing process is simple, and the product cost is low.

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Abstract

本发明提供一种TFT阵列基板及其制作方法与OLED显示面板。本发明的TFT阵列基板的制作方法分别采用一道光罩制作有源图案，栅极，第一电极，层间绝缘层、栅极绝缘层上的过孔、开口，源极、漏极，平坦化层上的开口，以及隔垫物，所需光罩数量少，工艺简单，能够有效提升生产效率，降低产品成本。

Description

TFT阵列基板及其制作方法与OLED显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板及其制作方法与OLED显示面板。
 背景技术
有机发光二极管显示装置（Organic Light Emitting Display，OLED）具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。
OLED按照驱动方式可以分为无源矩阵型OLED（Passive Matrix OLED，PMOLED）和有源矩阵型OLED（Active Matrix OLED，AMOLED）两大类，即直接寻址和薄膜晶体管（TFT）矩阵寻址两类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光效能高，通常用作高清晰度的大尺寸显示装置。
OLED器件通常包括：基板、设于基板上的阳极、设于阳极上的空穴注入层、设于空穴注入层上的空穴传输层、设于空穴传输层上的发光层、设于发光层上的电子传输层、设于电子传输层上的电子注入层及设于电子注入层上的阴极。OLED器件的发光原理为半导体材料和有机发光材料在电场驱动下，通过载流子注入和复合导致发光。具体的，OLED器件通常采用氧化铟锡（ITO）电极和金属电极分别作为器件的阳极和阴极，在一定电压驱动下，电子和空穴分别从阴极和阳极注入到电子传输层和空穴传输层，电子和空穴分别经过电子传输层和空穴传输层迁移到发光层，并在发光层中相遇，形成激子并使发光分子激发，后者经过辐射弛豫而发出可见光。
请参阅图1，现有的一种OLED显示面板包括衬底基板100、设于衬底基板100上的阻隔层200、设于阻隔层200上的有源层300、设于有源层300及阻隔层200上的第一栅极绝缘层410、设于第一栅极绝缘层410上且位于有源层300上方的第一栅极510、设于第一栅极绝缘层410及第一栅极510上的第二栅极绝缘层420、设于第二栅极绝缘层420上且位于第一栅极510上方的第二栅极520、设于第二栅极520及第二栅极绝缘层420上的层间绝缘层600、设于层间绝缘层600上的源极710及漏极720、设于源极710、漏极720及层间绝缘层600上的平坦化层800、设于平坦化层800上的第一电极900、设于第一电极900及平坦化层800上的像素定义层1000、设于第一电极900上的有机发光层1100、设于有机发光层1100上的第二电极1200及设于像素定义层1000上的隔垫物1300。第一栅极绝缘层410、第二栅极绝缘层420及层间绝缘层600设有位于有源层300两端上方的第一过孔411及第二过孔412，源极710及漏极720分别经第一过孔411及第二过孔412与有源层300两端接触，平坦化层800设有位于漏极720上的第三过孔810，第一电极900经第三过孔810与漏极720接触，像素定义层1000设有位于第一电极900上的开口1010，有机发光层1100及第二电极1200均位于开口1010内。第一栅极510及第二栅极520之间形成电容。制作该OLED显示面板需要9道光罩制程，分别用于形成有源层300，第一栅极510，第二栅极520，第一过孔411及第二过孔412，源极710及漏极720，第三过孔810，第一电极900，开口1010，以及隔垫物1300，所需光罩数量较多，制作工艺复杂，使得OLED显示面板的成本增加。
 技术问题
本发明的目的在于提供一种TFT阵列基板的制作方法，所需光罩数量少，工艺简单，能够有效降低产品成本。
本发明的另一目的在于提供一种TFT阵列基板，制作所需光罩数量少，制作工艺简单，产品成本低。
本发明的又一目的在于提供一种OLED显示面板，制作所需光罩数量少，制作工艺简单，产品成本低。
 技术解决方案
为实现上述目的，本发明首先提供一种TFT阵列基板的制作方法，包括如下步骤：
步骤S1、提供衬底基板，在衬底基板上形成半导体材料膜并图案化，形成第一半导体图案；
步骤S2、在第一半导体图案及衬底基板上形成栅极绝缘层；
步骤S3、在栅极绝缘层上形成第一金属膜并图案化，形成位于第一半导体图案上方的栅极；所述栅极暴露出第一半导体图案的两端；
步骤S4、以栅极为遮挡对第一半导体图案进行掺杂，形成有源图案；
步骤S5、在栅极绝缘层上形成导电材料膜并图案化，形成与有源图案在水平方向上相间隔的第一电极；
步骤S6、在第一电极、栅极及栅极绝缘层上形成层间绝缘层；对层间绝缘层及栅极绝缘层进行图案化，在第一电极上方形成第一开口，在有源图案的两端上方分别形成第一过孔及第二过孔；
步骤S7、在第一电极及层间绝缘层上形成第二金属膜并图案化，形成间隔的源极及漏极；源极及漏极分别经第一过孔及第二过孔与有源图案的两端接触；源极靠近第一电极的一端经第一开口与第一电极靠近源极的一端接触。
所述步骤S1中，在衬底基板上形成半导体材料膜之前还在衬底基板上形成阻隔层，所述半导体材料膜形成在阻隔层上；
所述步骤S2中栅极绝缘层形成在第一半导体图案及阻隔层上；
所述的TFT阵列基板的制作方法还包括：
步骤S8、在层间绝缘层、第一电极、源极及漏极上形成平坦化层，对所述平坦化层进行图案化，形成于第一开口内位于第一电极上方的第二开口；
步骤S9、在平坦化层上形成有机材料膜并图案化，形成隔垫物。
所述步骤S1中在对半导体材料膜图案化形成第一半导体图案的同时还形成与第一半导体图案间隔的第二半导体图案；
所述步骤S2中栅极绝缘层还形成在第二半导体图案上；
所述步骤S4中，以栅极为遮挡对第一半导体图案进行掺杂形成有源图案的同时，还对第二半导体图案进行掺杂形成第一电容极板；
所述步骤S5形成的第一电极与第一电容极板在水平方向上相间隔；
所述步骤S6中，对层间绝缘层及栅极绝缘层进行图案化形成第一开口、第一过孔及第二过孔的同时，还在第一电容极板上的栅极绝缘层上方形成第三开口；
所述步骤S7中，在对第二金属膜图案化形成源极及漏极的同时还形成与源极及漏极间隔的第二电容极板；所述第二电容极板位于第一电容极板上方，所述第二电容极板覆盖第三开口。
所述有源图案包括与栅极相对的沟道及分别位于沟道两端的源极接触区及漏极接触区；
所述第一过孔及第二过孔分别位于源极接触区及漏极接触区上方；源极及漏极分别经第一过孔及第二过孔与源极接触区及漏极接触区。
所述步骤S1中采用等离子体增强化学气相沉积的方式在衬底基板上形成阻隔层；所述阻隔层为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构；
所述半导体材料膜为多晶硅膜，所述步骤S1中在阻隔层上形成半导体材料膜的具体过程为：采用等离子体增强化学气相沉积的方式在阻隔层上形成单晶硅膜并对单晶硅膜进行准分子激光退火处理形成多晶硅膜；
所述步骤S2中采用等离子体增强化学气相沉积的方式在第一半导体图案及阻隔层上形成栅极绝缘层；所述栅极绝缘层为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构；
所述步骤S3中采用物理气相沉积的方式在栅极绝缘层上形成第一金属膜；所述第一金属膜为单层钼膜、单层铬膜、单层钨化钼膜、两层钛膜夹一层铝膜及两层钼膜夹一层铝膜中的一种；
所述步骤S5中采用物理气相沉积的方式在栅极绝缘层上形成导电材料膜；所述导电材料膜为两层氧化铟锡膜夹一层铝膜或单层氧化铟锡膜、单层铝膜及单层氧化铟锌膜的叠层结构；
所述步骤S6中采用等离子体增强化学气相沉积的方式在第一电极、栅极及栅极绝缘层上形成层间绝缘层；所述层间绝缘层为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构；
所述步骤S7中采用物理气相沉积的方式在第一电极及层间绝缘层上形成第二金属膜；所述第二金属膜为两层钛膜夹一层铝膜或两层钼膜夹一层铝膜；
所述步骤S8中利用涂布机在层间绝缘层、第一电极、源极及漏极上涂布平坦化层；所述平坦化层的材料为有机材料。
所述步骤S9中利用涂布机在平坦化层上涂布有机材料膜。
本发明还提供一种TFT阵列基板，包括衬底基板、设于衬底基板上的有源图案、设于衬底基板及有源图案上的栅极绝缘层、设于栅极绝缘层上且位于有源图案上方的栅极、设于栅极绝缘层上且与有源图案间隔的第一电极、设于第一电极、栅极及栅极绝缘层上的层间绝缘层以及设于层间绝缘层上且间隔的源极及漏极；
所述栅极暴露出有源图案的两端；所述层间绝缘层在第一电极上方设有第一开口；所述层间绝缘层及栅极绝缘层在有源图案的两端上方分别设有第一过孔及第二过孔；源极及漏极分别经第一过孔及第二过孔与有源图案的两端接触；源极靠近第一电极的一端经第一开口与第一电极靠近源极的一端接触。
所述TFT阵列基板还包括设于衬底基板上的阻隔层、设于阻隔层上与有源图案间隔的第一电容极板、设于层间绝缘层上且与源极及漏极均间隔的第二电容极板、设于层间绝缘层、第一电极、源极、漏极及第二电容极板上的平坦化层、设于平坦化层上的隔垫物；
所述有源图案设于阻隔层上，栅极绝缘层设于有源图案、阻隔层及第一电容极板上；所述第一电极与第一电容极板在水平方向上相间隔；所述平坦化层于第一开口内在第一电极上方设有第二开口；所述层间绝缘层在第一电容极板上的栅极绝缘层上方形成第三开口；所述第二电容极板位于第一电容极板上方，所述第二电容极板覆盖第三开口。
所述阻隔层为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构；
所述有源图案及第二电容极板的材料均为多晶硅，且有源图案被栅极暴露的两端及第二电容极板均经过离子掺杂；
所述栅极绝缘层为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构；
所述栅极的结构为单层钼膜、单层铬膜、单层钨化钼膜、两层钛膜夹一层铝膜及两层钼膜夹一层铝膜中的一种；
所述第一电极的结构为两层氧化铟锡膜夹一层铝膜或单层氧化铟锡膜、单层铝膜及单层氧化铟锌膜的叠层结构；
所述层间绝缘层为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构；
所述源极、漏极及第二电容极板的结构均为两层钛膜夹一层铝膜或两层钼膜夹一层铝膜；
所述平坦化层的材料为有机材料。
所述有源图案包括与栅极相对的沟道及分别位于沟道两端的源极接触区及漏极接触区；
所述第一过孔及第二过孔分别位于源极接触区及漏极接触区上方；源极及漏极分别经第一过孔及第二过孔与源极接触区及漏极接触区。
本发明还提供一种OLED显示面板，包括上述的TFT阵列基板。
 有益效果
本发明的有益效果：本发明的TFT阵列基板的制作方法分别采用一道光罩制作有源图案，栅极，第一电极，层间绝缘层、栅极绝缘层上的过孔、开口，源极、漏极，平坦化层上的开口，以及隔垫物，所需光罩数量少，工艺简单，能够有效提升生产效率，降低产品成本。本发明的TFT阵列基板制作所需光罩数量少，制作工艺简单，产品成本低。本发明的OLED显示面板制作所需光罩数量少，制作工艺简单，产品成本低。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的一种OLED显示面板的结构示意图；
图2为本发明的TFT阵列基板的制作方法的流程图；
图3为本发明的TFT阵列基板的制作方法的步骤S1的示意图；
图4为本发明的TFT阵列基板的制作方法的步骤S2的示意图；
图5为本发明的TFT阵列基板的制作方法的步骤S3的示意图；
图6为本发明的TFT阵列基板的制作方法的步骤S4的示意图；
图7为本发明的TFT阵列基板的制作方法的步骤S5的示意图；
图8为本发明的TFT阵列基板的制作方法的步骤S6的示意图；
图9为本发明的TFT阵列基板的制作方法的步骤S7的示意图；
图10为本发明的TFT阵列基板的制作方法的步骤S8的示意图；
图11为本发明的TFT阵列基板的制作方法的步骤S9的示意图暨本发明的TFT阵列基板的结构示意图；
图12为本发明的OLED显示面板的结构示意图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图 2 ，本发明提供一种 TFT 阵列基板的制作方法，包括如下步骤：
步骤 S1 、请参阅图 3 ，提供衬底基板 1 ，在衬底基板 1 上形成半导体材料膜并利用第一道光罩进行图案化，同时形成间隔的第一半导体图案 38 及第二半导体图案 39 。
具体地，所述步骤 S1 中，在衬底基板 1 上形成半导体材料膜之前还在衬底基板 1 上形成阻隔层 2 ，所述半导体材料膜形成在阻隔层 2 上。
具体地，所述步骤 S1 中采用等离子体增强化学气相沉积（ PECVD ）的方式在衬底基板 1 上形成阻隔层 2 。所述阻隔层 2 为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构。
具体地，所述半导体材料膜为多晶硅膜，所述步骤 S1 中在阻隔层 2 上形成半导体材料膜的具体过程为：采用等离子体增强化学气相沉积的方式在阻隔层 2 上形成单晶硅膜并对单晶硅膜进行准分子激光退火处理对其进行多晶化形成多晶硅膜。
步骤 S2 、请参阅图 4 ，在第一半导体图案 38 、第二半导体图案 39 及衬底基板 1 上形成栅极绝缘层 4 。
具体地，所述步骤 S2 中栅极绝缘层 4 形成在第一半导体图案 38 、第二半导体图案 39 及阻隔层 2 上。
具体地，所述步骤 S2 中采用等离子体增强化学气相沉积的方式在第一半导体图案 38 、第二半导体图案 39 及阻隔层 2 上形成栅极绝缘层 4 。所述栅极绝缘层 4 为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构。
步骤 S3 、请参阅图 5 ，在栅极绝缘层 4 上形成第一金属膜并利用第二道光罩进行图案化，形成位于第一半导体图案 38 上方的栅极 5 。所述栅极 5 暴露出第一半导体图案 38 的两端。
具体地，所述步骤 S3 中采用物理气相沉积（ PVD ）的方式在栅极绝缘层 4 上形成第一金属膜。所述第一金属膜为单层钼（ Mo ）膜、单层铬（ Cr ）膜、单层钨化钼（ MoW ）膜、两层钛（ Ti ）膜夹一层铝（ Al ）膜及两层钼膜夹一层铝膜中的一种。
步骤 S4 、请参阅图 6 。采用自对准的方式，以栅极 5 为遮挡对第一半导体图案 38 进行掺杂，形成有源图案 31 ，同时还对第二半导体图案 39 进行掺杂形成第一电容极板 32 。
具体地，所述有源图案 31 包括与栅极 5 相对的沟道 311 及分别位于沟道 311 两端的源极接触区 312 及漏极接触区 313 。
步骤 S5 、请参阅图 7 ，在栅极绝缘层 4 上形成导电材料膜并利用第三道光罩进行图案化，形成与有源图案 31 在水平方向上相间隔的第一电极 6 。
具体地，所述步骤 S5 形成的第一电极 6 与第一电容极板 32 在水平方向上也相间隔。
具体地，所述步骤 S5 中采用物理气相沉积的方式在栅极绝缘层 4 上形成导电材料膜。所述导电材料膜为两层氧化铟锡膜夹一层铝膜或单层氧化铟锡膜、单层铝膜及单层氧化铟锌（ IZO ）膜的叠层结构。
步骤 S6 、请参阅图 8 ，在第一电极 6 、栅极 5 及栅极绝缘层 4 上形成层间绝缘层 7 。利用第四道光罩对层间绝缘层 7 及栅极绝缘层 4 进行图案化，在第一电极 6 上方形成第一开口 71 ，在有源图案 31 的两端上方分别形成第一过孔 72 及第二过孔 73 ，在第一电容极板 32 上的栅极绝缘层 4 上方形成第三开口 74 。
具体地，所述步骤 S6 中，所述第一过孔 72 及第二过孔 73 分别位于源极接触区 312 及漏极接触区 313 上方。
具体地，所述步骤 S6 中采用等离子体增强化学气相沉积的方式在第一电极 6 、栅极 5 及栅极绝缘层 4 上形成层间绝缘层 7 。所述层间绝缘层 7 为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构。
步骤 S7 、请参阅图 9 ，在第一电极 6 及层间绝缘层 7 上形成第二金属膜并利用第五道光罩进行图案化，形成间隔的源极 81 、漏极 82 及第二电容极板 83 ，源极 81 及漏极 82 分别经第一过孔 72 及第二过孔 73 与有源图案 31 的两端接触，源极 81 靠近第一电极 6 的一端经第一开口 71 与第一电极 6 靠近源极 81 的一端接触，所述第二电容极板 83 位于第一电容极板 32 上方，所述第二电容极板 83 覆盖第三开口 74 。
具体地，所述源极 81 及漏极 82 分别经第一过孔 72 及第二过孔 73 与源极接触区 312 及漏极接触区 313 。
具体地，所述步骤 S7 中采用物理气相沉积的方式在第一电极 6 及层间绝缘层 7 上形成第二金属膜。所述第二金属膜为两层钛膜夹一层铝膜或两层钼膜夹一层铝膜。
步骤 S8 、请参阅图 10 ，在层间绝缘层 7 、第一电极 6 、源极 81 、漏极 82 及第二电容极板 83 上形成平坦化层 9 ，利用第六道光罩对所述平坦化层 9 进行图案化，形成于第一开口 71 内位于第一电极 6 上方的第二开口 91 。
所述步骤 S8 中利用涂布机在层间绝缘层 7 、第一电极 6 、源极 81 及漏极 82 上涂布平坦化层 9 。所述平坦化层 9 的材料为有机材料。
步骤 S9 、请参阅图 11 ，在平坦化层 9 上形成有机材料膜并图案化，形成隔垫物 10 。
具体地，所述步骤 S9 中利用涂布机在平坦化层 9 上涂布有机材料膜。
需要说明的是，本发明的 TFT 阵列基板的制作方法板采用第一道光罩制作有源图案 31 及第一电容极板 32 ，采用第二道光罩制作栅极 5 ，采用第三道光罩制作第一电极 6 ，采用第四道光罩制作层间绝缘层 7 及栅极绝缘层 4 上的第一开口 71 、第一过孔 72 、第二过孔 73 及第三开口 74 ，采用第五道光罩制作源极 81 、漏极 82 及第二电容极板 83 ，采用第六道光罩制作平坦化层 9 上的第二开口 91 ，采用第七道光罩制作隔垫物 10 ，总共需要 7 道光罩，相比于现有技术需要采用 9 道光罩才能完成 TFT 阵列基板的制作，本发明所需光罩数量少，工艺简单，能够有效提升生产效率，降低产品成本。
请参阅图 11 ，基于同一发明构思，本发明还提供一种采用上述的 TFT 阵列基板制作方法制得的 TFT 阵列基板，包括衬底基板 1 、设于衬底基板 1 上的有源图案 31 、设于衬底基板 1 及有源图案 31 上的栅极绝缘层 4 、设于栅极绝缘层 4 上且位于有源图案 31 上方的栅极 5 、设于栅极绝缘层 4 上且与有源图案 31 在水平方向上相间隔的第一电极 6 、设于第一电极 6 、栅极 5 及栅极绝缘层 4 上的层间绝缘层 7 以及设于层间绝缘层 7 上且间隔的源极 81 及漏极 82 。
所述栅极 5 暴露出有源图案 31 的两端。所述层间绝缘层 7 在第一电极 6 上方设有第一开口 71 。所述层间绝缘层 7 及栅极绝缘层 4 在有源图案 31 的两端上方分别设有第一过孔 72 及第二过孔 73 。源极 81 及漏极 82 分别经第一过孔 72 及第二过孔 73 与有源图案 31 的两端接触。源极 81 靠近第一电极 6 的一端经第一开口 71 与第一电极 6 靠近源极 81 的一端接触。
具体地，所述 TFT 阵列基板还包括设于衬底基板 1 上的阻隔层 2 、设于阻隔层 2 上与有源图案 31 间隔的第一电容极板 32 、设于层间绝缘层 7 上且与源极 81 及漏极 82 均间隔的第二电容极板 83 、设于层间绝缘层 7 、第一电极 6 、源极 81 、漏极 82 及第二电容极板 83 上的平坦化层 9 、设于平坦化层 9 上的隔垫物 10 。所述有源图案 31 设于阻隔层 2 上，栅极绝缘层 4 设于有源图案 31 、阻隔层 2 及第一电容极板 32 上。所述第一电极 6 与第一电容极板 32 在水平方向上相间隔，所述平坦化层 9 于第一开口 71 内在第一电极 6 上方设有第二开口 91 。所述层间绝缘层 7 在第一电容极板 32 上的栅极绝缘层 4 上方形成第三开口 74 。所述第二电容极板 83 位于第一电容极板 32 上方，所述第二电容极板 83 覆盖第三开口 74 。从而由栅极 5 、有源图案 31 、源极 81 及漏极 82 组成 TFT 器件，由第一电容极板 31 及第二电容极板 83 组成存储电容。
具体地，所述阻隔层 2 为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构。所述有源图案 31 及第二电容极板 83 的材料均为多晶硅，且有源图案 31 被栅极 5 暴露的两端及第二电容极板 83 均经过离子掺杂。所述栅极绝缘层 4 为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构。所述栅极 5 的结构为单层钼膜、单层铬膜、单层钨化钼膜、两层钛膜夹一层铝膜及两层钼膜夹一层铝膜中的一种。所述第一电极 6 的结构为两层氧化铟锡膜夹一层铝膜或单层氧化铟锡膜、单层铝膜及单层氧化铟锌膜的叠层结构。所述层间绝缘层 7 为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构。所述源极 81 、漏极 82 及第二电容极板 83 的结构均为两层钛膜夹一层铝膜或两层钼膜夹一层铝膜。所述平坦化层 9 的材料为有机材料。
具体地，所述有源图案 31 包括与栅极 5 相对的沟道 311 及分别位于沟道 311 两端的源极接触区 312 及漏极接触区 313 。所述第一过孔 72 及第二过孔 73 分别位于源极接触区 312 及漏极接触区 313 上方。源极 81 及漏极 82 分别经第一过孔 72 及第二过孔 73 与源极接触区 312 及漏极接触区 313 。
需要说明的是，本发明的 TFT 阵列基板采用上述的 TFT 阵列基板的制作方法制得，在制作时，采用第一道光罩制作有源图案 31 及第一电容极板 32 ，采用第二道光罩制作栅极 5 ，采用第三道光罩制作第一电极 6 ，采用第四道光罩制作层间绝缘层 7 及栅极绝缘层 4 上的第一开口 71 、第一过孔 72 、第二过孔 73 及第三开口 74 ，采用第五道光罩制作源极 81 、漏极 82 及第二电容极板 83 ，采用第六道光罩制作平坦化层 9 上的第二开口 91 ，采用第七道光罩制作隔垫物 10 ，完成制作总共需要 7 道光罩，相比于现有技术需要采用 9 道光罩才能完成 TFT 阵列基板的制作，本发明所需光罩数量少，工艺简单，能够有效提升生产效率，降低产品成本。
请参阅图 12 ，基于同一发明构思，本发明还提供一种 OLED 显示面板，包括上述的 TFT 阵列基板，在此不再对 TFT 阵列基板的结构进行重复性描述。该 OLED 显示面板还包括于第二开口 91 内位于第一电极 6 上的有机发光层 11 及位于有机发光层 11 上的第二电极 12 ，由第一电极 6 、有机发光层 11 及第二电极 12 组成 OLED 器件。
需要说明的是，本发明的 OLED 显示面板在制作时，采用第一道光罩制作有源图案 31 及第一电容极板 32 ，采用第二道光罩制作栅极 5 ，采用第三道光罩制作第一电极 6 ，采用第四道光罩制作层间绝缘层 7 及栅极绝缘层 4 上的第一开口 71 、第一过孔 72 、第二过孔 73 及第三开口 74 ，采用第五道光罩制作源极 81 、漏极 82 及第二电容极板 83 ，采用第六道光罩制作平坦化层 9 上的第二开口 91 ，采用第七道光罩制作隔垫物 10 ，完成 OLED 显示面板的制作总共需要 7 道光罩，相比于现有技术需要采用 9 道光罩才能完成 OLED 显示面板的制作，本发明所需光罩数量少，工艺简单，能够有效提升生产效率，降低产品成本。
综上所述，本发明的 TFT 阵列基板的制作方法分别采用一道光罩制作有源图案，栅极，第一电极，层间绝缘层、栅极绝缘层上的过孔、开口，源极、漏极，平坦化层上的开口，以及隔垫物，所需光罩数量少，工艺简单，能够有效提升生产效率，降低产品成本。本发明的 TFT 阵列基板制作所需光罩数量少，制作工艺简单，产品成本低。本发明的 OLED 显示面板制作所需光罩数量少，制作工艺简单，产品成本低。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种TFT阵列基板的制作方法，包括如下步骤：
    步骤S1、提供衬底基板，在衬底基板上形成半导体材料膜并图案化，形成第一半导体图案；
    步骤S2、在第一半导体图案及衬底基板上形成栅极绝缘层；
    步骤S3、在栅极绝缘层上形成第一金属膜并图案化，形成位于第一半导体图案上方的栅极；所述栅极暴露出第一半导体图案的两端；
    步骤S4、以栅极为遮挡对第一半导体图案进行掺杂，形成有源图案；
    步骤S5、在栅极绝缘层上形成导电材料膜并图案化，形成与有源图案在水平方向上相间隔的第一电极；
    步骤S6、在第一电极、栅极及栅极绝缘层上形成层间绝缘层；对层间绝缘层及栅极绝缘层进行图案化，在第一电极上方形成第一开口，在有源图案的两端上方分别形成第一过孔及第二过孔；
    步骤S7、在第一电极及层间绝缘层上形成第二金属膜并图案化，形成间隔的源极及漏极；源极及漏极分别经第一过孔及第二过孔与有源图案的两端接触；源极靠近第一电极的一端经第一开口与第一电极靠近源极的一端接触。
  2. 如权利要求1所述的TFT阵列基板的制作方法，其中，所述步骤S1中，在衬底基板上形成半导体材料膜之前还在衬底基板上形成阻隔层，所述半导体材料膜形成在阻隔层上；
    所述步骤S2中栅极绝缘层形成在第一半导体图案及阻隔层上；
    所述的TFT阵列基板的制作方法还包括：
    步骤S8、在层间绝缘层、第一电极、源极及漏极上形成平坦化层，对所述平坦化层进行图案化，形成于第一开口内位于第一电极上方的第二开口；
    步骤S9、在平坦化层上形成有机材料膜并图案化，形成隔垫物。
  3. 如权利要求1所述的TFT阵列基板的制作方法，其中，所述步骤S1中在对半导体材料膜图案化形成第一半导体图案的同时还形成与第一半导体图案间隔的第二半导体图案；
    所述步骤S2中栅极绝缘层还形成在第二半导体图案上；
    所述步骤S4中，以栅极为遮挡对第一半导体图案进行掺杂形成有源图案的同时，还对第二半导体图案进行掺杂形成第一电容极板；
    所述步骤S5形成的第一电极与第一电容极板在水平方向上相间隔；
    所述步骤S6中，对层间绝缘层及栅极绝缘层进行图案化形成第一开口、第一过孔及第二过孔的同时，还在第一电容极板上的栅极绝缘层上方形成第三开口；
    所述步骤S7中，在对第二金属膜图案化形成源极及漏极的同时还形成与源极及漏极间隔的第二电容极板；所述第二电容极板位于第一电容极板上方，所述第二电容极板覆盖第三开口。
  4. 如权利要求1所述的TFT阵列基板的制作方法，其中，所述有源图案包括与栅极相对的沟道及分别位于沟道两端的源极接触区及漏极接触区；
    所述第一过孔及第二过孔分别位于源极接触区及漏极接触区上方；源极及漏极分别经第一过孔及第二过孔与源极接触区及漏极接触区。
  5. 如权利要求2所述的TFT阵列基板的制作方法，其中，所述步骤S1中采用等离子体增强化学气相沉积的方式在衬底基板上形成阻隔层；所述阻隔层为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构；
    所述半导体材料膜为多晶硅膜，所述步骤S1中在阻隔层上形成半导体材料膜的具体过程为：采用等离子体增强化学气相沉积的方式在阻隔层上形成单晶硅膜并对单晶硅膜进行准分子激光退火处理形成多晶硅膜；
    所述步骤S2中采用等离子体增强化学气相沉积的方式在第一半导体图案及阻隔层上形成栅极绝缘层；所述栅极绝缘层为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构；
    所述步骤S3中采用物理气相沉积的方式在栅极绝缘层上形成第一金属膜；所述第一金属膜为单层钼膜、单层铬膜、单层钨化钼膜、两层钛膜夹一层铝膜及两层钼膜夹一层铝膜中的一种；
    所述步骤S5中采用物理气相沉积的方式在栅极绝缘层上形成导电材料膜；所述导电材料膜为两层氧化铟锡膜夹一层铝膜或单层氧化铟锡膜、单层铝膜及单层氧化铟锌膜的叠层结构；
    所述步骤S6中采用等离子体增强化学气相沉积的方式在第一电极、栅极及栅极绝缘层上形成层间绝缘层；所述层间绝缘层为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构；
    所述步骤S7中采用物理气相沉积的方式在第一电极及层间绝缘层上形成第二金属膜；所述第二金属膜为两层钛膜夹一层铝膜或两层钼膜夹一层铝膜；
    所述步骤S8中利用涂布机在层间绝缘层、第一电极、源极及漏极上涂布平坦化层；所述平坦化层的材料为有机材料；
    所述步骤S9中利用涂布机在平坦化层上涂布有机材料膜。
  6. 一种TFT阵列基板，包括衬底基板、设于衬底基板上的有源图案、设于衬底基板及有源图案上的栅极绝缘层、设于栅极绝缘层上且位于有源图案上方的栅极、设于栅极绝缘层上且与有源图案在水平方向上相间隔的第一电极、设于第一电极、栅极及栅极绝缘层上的层间绝缘层以及设于层间绝缘层上且间隔的源极及漏极；
    所述栅极暴露出有源图案的两端；所述层间绝缘层在第一电极上方设有第一开口；所述层间绝缘层及栅极绝缘层在有源图案的两端上方分别设有第一过孔及第二过孔；源极及漏极分别经第一过孔及第二过孔与有源图案的两端接触；源极靠近第一电极的一端经第一开口与第一电极靠近源极的一端接触。
  7. 如权利要求6所述的TFT阵列基板，还包括设于衬底基板上的阻隔层、设于阻隔层上与有源图案间隔的第一电容极板、设于层间绝缘层上且与源极及漏极均间隔的第二电容极板、设于层间绝缘层、第一电极、源极、漏极及第二电容极板上的平坦化层、设于平坦化层上的隔垫物；
    所述有源图案设于阻隔层上，栅极绝缘层设于有源图案、阻隔层及第一电容极板上；所述第一电极与第一电容极板在水平方向上相间隔，所述平坦化层于第一开口内在第一电极上方设有第二开口；所述层间绝缘层在第一电容极板上的栅极绝缘层上方形成第三开口；所述第二电容极板位于第一电容极板上方，所述第二电容极板覆盖第三开口。
  8. 如权利要求7所述的TFT阵列基板，其中，
    所述阻隔层为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构；
    所述有源图案及第二电容极板的材料均为多晶硅，且有源图案被栅极暴露的两端及第二电容极板均经过离子掺杂；
    所述栅极绝缘层为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构；
    所述栅极的结构为单层钼膜、单层铬膜、单层钨化钼膜、两层钛膜夹一层铝膜及两层钼膜夹一层铝膜中的一种；
    所述第一电极的结构为两层氧化铟锡膜夹一层铝膜或单层氧化铟锡膜、单层铝膜及单层氧化铟锌膜的叠层结构；
    所述层间绝缘层为氧化硅层、氮化硅层或氧化硅层与氮化硅层的叠层结构；
    所述源极、漏极及第二电容极板的结构均为两层钛膜夹一层铝膜或两层钼膜夹一层铝膜；
    所述平坦化层的材料为有机材料。
  9. 如权利要求6所述的TFT阵列基板，其中，所述有源图案包括与栅极相对的沟道及分别位于沟道两端的源极接触区及漏极接触区；
    所述第一过孔及第二过孔分别位于源极接触区及漏极接触区上方；源极及漏极分别经第一过孔及第二过孔与源极接触区及漏极接触区。
  10. 一种OLED显示面板，包括如权利要求6所述的TFT阵列基板。
PCT/CN2019/075633 2018-12-18 2019-02-21 Tft阵列基板及其制作方法与oled显示面板 Ceased WO2020124774A1 (zh)

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