WO2020124347A1

WO2020124347A1 - Fpga chip and electronic device having said fpga chip

Info

Publication number: WO2020124347A1
Application number: PCT/CN2018/121705
Authority: WO
Inventors: 孙辉; 庹伟; 陈星�; 麻军平
Original assignee: 深圳市大疆创新科技有限公司
Priority date: 2018-12-18
Filing date: 2018-12-18
Publication date: 2020-06-25
Also published as: CN111279313A

Abstract

An FPGA chip and an electronic device having said FPGA chip, the FPGA chip comprising: an internal memory unit (1), the internal memory unit (1) comprising a data write interface (11), and the internal memory unit (1) having multiple memory sub-cells (12), each memory sub-cell (12) comprising an enable terminal (121); and a resource management module (2), the resource management module (2) being electrically coupled to the data write interface (11) and electrically coupled to the enable terminal (121) of each memory cell (12); the resource management module (2) being capable of acquiring a current use state of an electronic device via the data write interface (11), and according to the current use state of the electronic device, outputting a first enable signal, so as to trigger enabling of one or more memory sub-cells (12) in the internal memory unit (1). The present FPGA chip has functionality of dynamic application of internal memory resources, ensuring that a minimum of internal memory resources are used in every scenario, minimizing FPGA chip power consumption.

Description

FPGA chip and electronic device with the FPGA chip

Technical field

The invention relates to the field of FPGA chips (Field-Programmable Gate Array), in particular to an FPGA chip and electronic equipment with the FPGA chip.

Background technique

In the field of electronic equipment, FPGA chips are more and more used for their customizable design and short development cycle. However, the flexible design of FPGA chips also brings the disadvantage of higher power consumption than ASIC devices. For electronic devices with high power consumption requirements, FPGA low power design needs to be considered.

The conventional low-power design of FPGA chips is realized by turning off some functional modules by the gated clock. There are usually two methods for inserting the gated clock: manually adding in the FPGA chip design, and automatically adding through the tool. The former is suitable for application in long-term shut-off function modules, while the latter depends on the algorithm of the design tool. In the FPGA chip, the power consumption of the memory unit occupies a large proportion of power consumption. Because the read and write logic of the memory unit is very different, it is difficult for the tool to automatically insert 100% to identify, and the manual insertion workload is too large. The insertion method is difficult to accurately control the power consumption of the memory unit.

Summary of the invention

The invention provides an FPGA chip and an electronic device with the FPGA chip.

Specifically, the present invention is achieved through the following technical solutions:

According to a first aspect of the present invention, an FPGA chip is provided, and the FPGA chip is applied to an electronic device; the FPGA chip includes:

A memory unit, the memory unit includes a data writing interface, and the memory unit has a plurality of storage subunits, and each storage subunit includes an enabling terminal; and

A resource management module, the resource management module is electrically coupled to the data writing interface, and is electrically coupled to the enable end of each storage unit;

The resource management module can obtain the current use state of the electronic device through the data writing interface, and output a first enable signal according to the current use state of the electronic device to trigger one of the memory units Or multiple memory subunits are enabled.

According to a second aspect of the invention, an electronic device is provided, the electronic device comprising:

Data acquisition module and/or data storage module; and

The FPGA chip includes a memory unit and a resource management module. The memory unit includes a data writing interface, and the memory unit has a plurality of storage subunits. Each storage subunit includes an enabling terminal. The resource management module and the resource management module The data writing interface is electrically coupled and connected to the enable terminal of each storage unit;

The data writing interface is electrically coupled to the data acquisition module and/or data storage module;

The data collection module is used to collect data and send the collected data to the data writing interface and/or the data storage module to send the data stored by the data storage module to the data writing interface;

According to a third aspect of the present invention, an FPGA chip is provided, and the FPGA chip is applied to an electronic device; the FPGA chip includes:

After detecting that the data writing interface receives the data to be written, the resource management module outputs an enable signal according to the size of the data to be written to trigger one or more storages in the memory unit The subunit is enabled.

According to a fourth aspect of the present invention, there is provided an electronic device, the electronic device comprising:

Data acquisition module and/or data storage module; and

It can be seen from the technical solutions provided by the above embodiments of the present invention that when the FPGA chip of the present invention is packaged, the memory unit is divided, and the memory unit is divided into a plurality of storage subunits. When in use, it can be based on the current use of electronic equipment The size of the data to be written on the state or data writing interface triggers the enablement of one or more storage subunits in the memory unit, realizing the dynamic application of memory resources, ensuring that the smallest memory resources are used in each scenario, the largest The limit reduces the power consumption of the FPGA chip, so that the FPGA chip can meet the electronic equipment with higher power consumption requirements; and, the method for reducing the power consumption of the FPGA chip of the present invention has strong flexibility.

BRIEF DESCRIPTION

In order to more clearly explain the technical solutions in the embodiments of the present invention, the drawings required in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without paying any creative labor, other drawings can also be obtained based on these drawings.

Figure 1 is a schematic diagram of the structure of the FPGA chip in the related art;

2 is a schematic structural diagram of an FPGA chip in an embodiment of the present invention;

3 is a schematic structural diagram of an FPGA chip in another embodiment of the present invention;

4 is a schematic diagram of the specific structure of the FPGA chip of the embodiment shown in FIG. 3;

FIG. 5 is another schematic diagram of the FPGA chip of the embodiment shown in FIG. 3;

6 is a schematic structural diagram of an FPGA chip in another embodiment of the present invention;

7 is a schematic structural view of an electronic device in an embodiment of the invention;

8 is a schematic structural diagram of another electronic device in an embodiment of the present invention.

Reference signs: 10: data acquisition module; 20: data storage module; 30: FPGA chip; 1: memory unit; 11: data writing interface; 12: storage subunit; 121: enable terminal; 13: data reading Interface; 2: resource management module; 21: first detection terminal; 22: first output terminal; 23: third detection terminal; 3: forward detection module; 31: second detection terminal; 32: second output terminal; 33: Write address judgment module; 34: Frame data detection module; 4: First logic circuit; 5: Second logic circuit.

detailed description

The technical solutions in the embodiments of the present invention will be described clearly and completely in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present invention.

The FPGA chip of the present invention and the electronic device with the FPGA chip will be described in detail below with reference to the drawings. The features in the following examples and implementations can be combined with each other without conflict.

In the related art, when designing FPGA chips with low power consumption, refer to Figure 1, and manually add a gated clock to shut down some functional modules (such as memory cells) in the FPGA chip. This method is suitable for shutting down the design for a long time. For example, the FPGA chip includes module A, module B, and module C. In scenario 1, only module A is turned on; in scenario 2, only module B is turned on; in scenario 3, only module C is turned on. To achieve the goal of reducing the power consumption of the FPGA chip, module B and module C can be turned off by the gated clock in scenario 1; module A and module C can be turned off by the gated clock in scenario 2; Control the clock to turn off module A and module B. It should be noted that scenario 1, scenario 2, and scenario 3 can be divided according to the usage scenario of the electronic device where the FPGA chip is currently located, or can also be divided into tasks currently performed by the FPGA chip. However, if the functional modules that can be turned off are scattered throughout the design (for example, a large number of submodules D are scattered in module A, module B, and module C), a large number of gated clocks need to be instantiated manually, and the workload Great.

Another way to reduce the power consumption of the FPGA chip is to use software to add the gated clock. This method depends heavily on the software algorithm; in addition, if there is a design that depends on the function to switch (such as dynamic storage application), the software will It is difficult to identify and cannot achieve the effect of reducing the power consumption of the FPGA chip.

Referring also to FIG. 1, in the related art, after receiving the write request, the FPGA chip will enable the entire memory unit regardless of whether the current data to be written is large or small (referring to the size of the data capacity), and then the current chip to be written Data is written to the enabled memory unit. If the current data to be written is small, enabling the entire memory unit will cause waste of power consumption of the FPGA chip, which is not conducive to the low power consumption requirement of the FPGA chip.

For this, the FPGA chip of the embodiment of the present invention divides the memory unit when it is packaged, and when it is used, it can be enabled according to the current use state of the electronic device or the size of the data to be written to the memory unit currently written The corresponding storage subunit ensures that the minimum memory resources are used in various scenarios, and the power consumption of the FPGA chip is reduced to the maximum extent, so that the FPGA chip can meet the electronic devices with higher power consumption requirements.

The FPGA chip of the embodiment of the present invention will be described in detail below with reference to the drawings.

Referring to FIG. 2, an embodiment of the present invention provides an FPGA chip. The FPGA chip 30 may include a memory unit 1 and a resource management module 2, wherein the memory unit 1 includes a data writing interface 11 and the memory unit 1 has a plurality of storage elements In the unit 12, each storage sub-unit 12 includes an enable terminal 121. The FPGA chip 30 may include one or more memory units 1, and each memory unit 1 includes a plurality of storage subunits 12 respectively.

Optionally, the memory unit 1 is RAM (random access memory, random access memory). It can be understood that the memory unit 1 is not limited to RAM, but may also be other storage spaces capable of storing data.

After the capacity of the memory unit 1 is determined, the smaller the capacity of the storage subunit 12 is, the more the number of storage subunits 12 constituting the memory unit 1 is, and the larger the granularity of the memory unit 1 is, the easier it is to optimize power consumption. However, the smaller the capacity, the more difficult the production of the storage subunit 12 and the higher the production cost. Therefore, considering the power consumption optimization requirements and the production difficulty and cost of the storage subunit 12, a storage subunit suitable for the size and number of capacities can be selected 12Package to form memory unit 1.

Optionally, the multiple storage subunits 12 of the memory unit 1 are equal in size, which facilitates the dynamic application of memory resources. Of course, the multiple storage units of the memory unit 1 may not be completely equal. In this embodiment, the size of the plurality of storage sub-units 12 is taken as an example for further description. When packaging the FPGA chip 30, the design specification (capacity size) of the memory unit 1 and the current use status of the electronic device, etc. may be selected to select the memory unit 1 The size of each storage subunit 12 in the storage system is optional. In an embodiment, according to the capacity of the memory unit 1, a plurality of storage subunits 12 of equal size are selected to form a memory unit 1, such as 5 2K ( Capacity unit: kilobytes) of the storage sub-unit 12, packaged to form a 10K memory unit 1. In another embodiment, according to the current use status of the electronic device, a plurality of storage subunits 12 of equal size are selected to form a memory unit 1, for example, when the shooting device needs 8K of memory to work when shooting, and the shooting device performs video playback Only requires 1080p memory to work, so four 2K memory subunits 12 can be selected and packaged to form an 8K memory unit 1.

The FPGA chip 30 of this embodiment may be applied to an electronic device. The electronic device may include a front-end module and a back-end module. The front-end module sends data to the FPGA chip 30, and the FPGA chip 30 stores the received data in the memory unit 1. In the middle (cache), the data is read from the memory unit 1 by the back-end module for other processing. The electronic device in this embodiment may be a shooting device, such as a hand-held gimbal camera or a camera mounted on a drone. The electronic device may include a shooting state and/or a video playback state and other usage states. The front-end module may be a data acquisition module 10, a data storage module 20, or other.

The resource management module 2 of this embodiment is electrically coupled to the data writing interface 11 and electrically coupled to the enable terminal 121 of each storage unit. In this embodiment, the resource management module 2 can obtain the current use status of the electronic device through the data writing interface 11, and output a first enable signal according to the current use status of the electronic device to trigger one of the memory units 1 or Multiple storage sub-units 12 are enabled. For example, the memory unit 1 includes four storage subunits 12, and when the shooting device is in a shooting state, the first output terminal 22 electrically coupled to the enable terminals 121 of the four storage subunits 12 all output a first enable signal , Triggering the four storage subunits 12 to be enabled to meet the memory resource requirements required in the shooting state; when the shooting device is in the video playback state, the first electrically coupled connection to the enabling terminals 121 of the four storage subunits 12 One of the output terminals 22 outputs the first enable signal to enable one of the storage subunits 12 to meet the memory resource requirements required for the video playback state.

Optionally, the resource management module 2 outputs the first enable signal according to the size of the data to be written corresponding to the current use status of the electronic device. For example, when the shooting device needs 8K of memory to work when shooting, the memory unit 1 includes five 2K storage subunits 12, and when the resource management module 2 acquires that the shooting device is in a shooting state, four of the first output terminals 22 output the first The enable signal triggers four 2K memory subunits 12 to be enabled.

The FPGA chip 30 of the embodiment of the present invention divides the memory unit 1 when it is packaged, divides the memory unit 1 into a plurality of storage subunits 12, and when in use, triggers the memory unit 1 according to the current use state of the electronic device The one or more storage subunits 12 are enabled, which realizes the dynamic application of memory resources, ensures that the minimum memory resources are used in various scenarios, and minimizes the power consumption of the FPGA chip 30, so that the FPGA chip 30 can meet the function Electronic devices that require higher power consumption; and, the method for reducing the power consumption of the FPGA chip 30 in the embodiments of the present invention is highly flexible.

It should be noted that, in the embodiment of the present invention, enabling the storage subunit 12 refers to switching the storage subunit 12 from the reset state to the working state. The storage sub-unit 12 can store data in the working state, but cannot store data in the reset state. In this embodiment, the memory sub-unit 12 consumes the lowest power in the reset state.

Wherein, when the electronic device is powered on, the enable terminal 121 of each storage subunit 12 is in a reset state, and at this time, the FPGA chip 30 has the lowest power consumption. After detecting that the enabling terminals 121 of all the storage subunits 12 are in the reset state, the resource management module 2 of this embodiment outputs a first enable signal according to the current use state of the electronic device to trigger one of the memory units 1 or The multiple storage subunits 12 are enabled to maximize the power consumption of the FPGA chip 30.

Referring again to FIG. 2, the resource management module 2 of this embodiment may include a first detection terminal 21 and a first output terminal 22. The first detection terminal 21 is electrically coupled to the data writing interface 11, and the first output terminal 22 is connected to each The enable terminal 121 of the memory cell is electrically coupled and connected.

In an embodiment, the first output terminal 22 is directly electrically coupled to the enable terminal 121 of each memory subunit 12, and the signal output by the first output terminal 22 is directly input to the enable terminal 121 of the corresponding memory subunit 12. Optionally, each memory subunit 12 is enabled when the enable terminal 121 of the memory subunit 12 is at a high level, and each memory subunit 12 is enabled at a low power level at the enable terminal 121 of the memory subunit 12 Usually in the reset state. In this embodiment, when the first output terminal 22 outputs a high level, the corresponding storage subunit 12 is enabled.

In another embodiment, the first output terminal 22 is indirectly electrically coupled to the enable terminal 121 of each memory subunit 12, and whether the enable terminal 121 of the memory subunit 12 is enabled not only needs to consider whether the first output terminal 22 To output the first enable signal, the signals output by other modules must also be considered.

Referring to FIG. 3, the FPGA chip 30 further includes a forward detection module 3. The forward detection module 3 is electrically coupled to the data writing interface 11 and electrically connected to the enable terminal 121 of each storage subunit 12. Wherein, the resource management module 2 outputs a first enable signal according to the size of the data to be written corresponding to the current usage state of the electronic device, to trigger one or more storage subunits 12 in the memory unit 1 to be in the to-be-enabled state. After detecting that the data writing interface 11 receives the data to be written, the forward detection module 3 outputs a second enable signal to enable the storage subunit 12 to be enabled. In this embodiment, when the electronic device is working, the resource management module 2 estimates the size of the data to be written in the memory unit 1 under the usage state according to the current usage state of the electronic device, and the One or more storage sub-units 12 are set to a state to be enabled (herein, storage sub-units 12 in a state to be enabled are also referred to as storage sub-units 12 to be enabled). Before the forward detection module 3 detects that there is valid data in the data writing interface 11, the storage subunit 12 to be enabled is in a reset state until the forward detection module 3 detects that there is valid data on the data writing interface 11. Then, the storage subunit 12 to be enabled is enabled to avoid that the data writing interface 11 does not receive valid data, but the power consumption caused by enabling the storage subunit 12 is wasted.

3, the forward detection module 3 of this embodiment may include a second detection terminal 31 and a second output terminal 32, wherein the second detection terminal 31 is electrically coupled to the data writing interface 11 and the second output terminal 32 It is electrically coupled to the enable terminal 121 of each memory cell. In this embodiment, the conditions for enabling the enable terminal 121 of the storage subunit 12 include: a first output terminal 22 electrically coupled to the storage subunit 12 outputs a first enable signal, and electrically connected to the storage subunit 12 The coupled second output terminal 32 outputs the second enable signal, which ensures that the minimum memory resources are used in various scenarios and the power consumption of the FPGA chip 30 is reduced to the maximum.

Referring to FIG. 4, the FPGA chip 30 of this embodiment may further include a first logic circuit 4, and the resource management module 2 and the forward detection module 3 are electrically coupled to the enable terminal 121 of each memory subunit 12 through the first logic circuit 4 connection. Specifically, the first logic circuit 4 includes a first input terminal, a second input terminal, and a third output terminal, the first output terminal 22 is electrically coupled to the first input terminal, and the second output terminal 32 is electrically coupled to the second input terminal The third output terminal is electrically coupled to the enable terminal 121 of each memory subunit 12. The first logic circuit 4 may include at least one of OR operation, AND operation, XOR operation, and NOT operation. As a feasible implementation manner, the first logic circuit 4 includes an AND logic device, and the signal output by the first output terminal 22 and the signal output by the second output terminal 32 are output to the storage subunit 12 after being ANDed with the logic device的使端121。 The enable end 121. For example, when the memory subunit 12 is enabled when its enable terminal 121 is at a high level, the signal output from the first output terminal 22 and the signal from the second output terminal 32 are both at a high level, and the logic device can output a high power When the enable terminal 121 of the memory sub-unit 12 is at a high level.

In some embodiments, there are multiple storage subunits 12 to be enabled, and after detecting that the data writing interface 11 receives the data to be written, the forward detection module 3 according to the row address information of the data to be written per frame , Sequentially enabling a plurality of memory subunits 12 to be enabled, so that the currently enabled memory subunit 12 to be enabled is enabled after writing the row data of the last enabled memory subunit 12 to be enabled. For example, the memory unit 1 includes four 1K storage sub-units 12, and after detecting valid data to be written, the FPGA chip 30 sequentially enables the four storage sub-units 12, when the first storage sub-unit 12 is full After that, the second, third, and fourth memory sub-units 12 are turned on in sequence to further reduce the power consumption of the FPGA chip 30.

In some embodiments, referring to FIG. 5, the forward detection module 3 may include a write address judgment module 33. The write address judgment module 33 is electrically coupled to the data write interface 11 and is connected to the enable terminal of each storage subunit 12. 121 is electrically coupled. The write address judgment module 33 of this embodiment is used to judge the row address information of the data to be written in the current frame on the data writing interface 11, and output the second enable signal to the storage corresponding to the row address information according to the row address information The enabling end 121 of the subunit 12 can ensure that under different resolution input conditions, the corresponding number of storage subunits 12 are turned on. If the data to be written is 8K resolution, 4 2K storages are enabled Sub-unit 12; the data to be written has a resolution of 2K, so that a 2K storage sub-unit 12 is enabled. In this embodiment, the write address judgment module 33 is electrically coupled to the enable terminal 121 of each storage subunit 12 via a logic judgment unit.

For example, when the write address judgment module 33 judges that the address information of the data to be written is between 0 and 2K, it outputs a second enable signal through a logic judgment unit electrically coupled to the first storage subunit 12 to enable the first Storage subunit 12; when the write address judgment module 33 judges that the address information of the data to be written is in the range of 2K to 4K, it outputs the second enable signal through the logic judgment unit electrically coupled to the second storage subunit 12 to enable The second storage subunit 12; when the write address judgment module 33 judges that the address information of the data to be written is between 4K and 6K, it outputs the second enable signal through the logic judgment unit electrically coupled to the third storage subunit 12 To enable the third storage subunit 12; when the write address judgment module 33 judges that the address information of the data to be written is between 6K and 8K, it outputs the second through a logic judgment unit electrically coupled to the fourth storage subunit 12 The enable signal enables the fourth storage sub-unit 12.

Further, in some embodiments, the write address judgment module 33 is directly electrically coupled to the enable terminal 121 of each storage subunit 12. Optionally, each memory subunit 12 is enabled when the enable terminal 121 of the memory subunit 12 is at a high level, and each memory subunit 12 is enabled at a low power level at the enable terminal 121 of the memory subunit 12 Usually in the reset state. In this embodiment, when the first output terminal 22 outputs a high level and the write address judgment module 33 outputs a second enable signal, the corresponding storage subunit 12 is enabled.

In other embodiments, the write address judgment module 33 is indirectly electrically coupled to the enable terminal 121 of each storage subunit 12, and whether the enable terminal 121 of the storage subunit 12 is enabled not only needs to consider whether the first output terminal 22 The output of the first enable signal and whether the write address judgment module 33 outputs the second enable signal also needs to consider the signals output by other modules.

For example, referring to FIG. 5, the forward detection module 3 may further include a frame data detection module 34 that is electrically coupled to the data writing interface 11 and electrically coupled to the enable terminal 121 of each storage subunit 12 connection. In this embodiment, the data on the data writing interface 11 may include valid data (data to be written) and invalid data (non-data to be written). Among them, the valid data includes a specific frame header identifier and a specific frame tail identifier. There may be invalid data between adjacent two frames of valid data. The invalid data does not have the frame header identifier and the frame trailer identifier, or the frame header identifier of the invalid data is different from the frame header identifier of the valid data, and the frame identifier of the invalid data is valid. The end of frame identification of the data is also different. The identification bits (including the frame header identification and the frame end identification) in the data are logic levels, and after receiving the data, the FPGA chip 30 converts the identification bits into internal logic levels (1 or 0). The frame data detection module 34 is used to detect the frame header identifier and the frame trailer identifier of the data to be written on the data writing interface 11. Specifically, the frame data detection module 34 detects whether a specific frame header identifier and a specific frame trailer identifier are detected or According to the detected logic level corresponding to the specific frame header identifier and the specific frame trailer identifier, it is determined whether the data is valid data. The frame data detection module 34 of this embodiment releases all the enabled storage subunits 12 when detecting the specific frame end flag, so that the enable terminals 121 of all the enabled storage subunits 12 are in a reset state to prevent invalidation The data is stored in the memory unit 1, and the power consumption of the FPGA chip 30 is reduced. Moreover, after the frame data detection module 34 detects the current specific frame tail flag and before the next frame header flag, regardless of whether the signal output by the write address judgment module 33 is the second enable signal, all the storage subunits 12 are in Reset state. Specifically, the configuration register can be used to ensure that after a certain time (such as 10ms) at the end of the current frame of valid data and until the beginning of the next frame of valid data, the write address judgment module 33 cannot trigger the storage subunit 12 to be enabled, thereby maintaining memory Unit 1 is reset.

After the frame data detection module 34 detects the frame header identifier of the next frame, if the write address judgment module 33 outputs the second enable signal, the corresponding storage subunit 12 is enabled, that is, the frame data detection module 34 detects the next frame After the frame header is identified, the write address judgment module 33 can trigger the released storage subunit 12 to be re-enabled. In this embodiment, the valid data in the next frame will overwrite the invalid data previously on the data writing interface 11, After the write address judgment module 33 re-enables the released storage subunit 12, the data stored in the storage subunit 12 are all valid data.

The write address judgment module 33 and the frame data detection module 34 of this embodiment are electrically coupled to the data write interface 11 through the first detection terminal 21, as shown in FIG. 5.

Referring again to FIG. 5, the FPGA chip 30 may further include a second logic circuit 5, and the write address judgment module 33 and the frame data detection module 34 are electrically coupled to the enable terminal 121 of each storage subunit 12 through the second logic circuit 5. Optionally, the second logic circuit 5 includes at least one of OR operation, AND operation, XOR operation, and NOT operation. As a feasible implementation manner, the second logic circuit 5 includes an AND logic device, and the signal output from the write address judgment module 33 and the signal output from the frame data detection module 34 are output to the storage subunit 12 after being ANDed with the logic device的使端121。 The enable end 121. For example, the storage subunit 12 is enabled when its enable terminal 121 is at a high level, and the frame data detection module 34 outputs a low level between the detection of the end of the frame of the current frame data and the detection of the frame header of the next frame So that the second logic device outputs a low level to all the enabled storage sub-units 12 so that all the enabled storage sub-units 12 are in a reset state; after detecting the frame header identification of the next frame, the frame data detection module 34 , Output high level, trigger the released memory sub-unit 12 to re-enable. In this embodiment, when the frame data detection module 34 outputs a high level and the write address judgment module 33 outputs a second enable signal, the corresponding storage subunit 12 is enabled.

In this embodiment, after the resource management module 2 outputs a first enable signal according to the current usage state of the electronic device to trigger the enable of one or more storage subunits 12 in the memory unit 1, the data write interface 11 is used The data to be written is written into the enabled one or more storage subunits 12, and the data to be written is cached in the storage subunit 12.

Further, the resource management module 2 of the FPGA chip 30 of this embodiment has the function of dynamically releasing memory in addition to the function of dynamically applying memory. Specifically, the resource management module 2 may implement storage according to a set release mechanism. The dynamic release of the subunit 12, after the release, the storage subunit 12 is in a reset state, to further avoid the waste of power consumption of the FPGA.

2 and 3, the memory unit 1 may further include a data reading interface 13, and the resource management module 2 is electrically coupled to the data reading interface 13. Specifically, the resource management module 2 further includes a third detection terminal 23 that is electrically coupled to the data reading interface 13. In this embodiment, after the data writing interface 11 writes the data to be written into the enabled one or more storage subunits 12, the resource management module 2 detects each enabled storage subunit through the data reading interface 13 The data read status of unit 12. In addition, when the resource management module 2 determines that the enabled storage sub-unit 12 satisfies the preset resource release strategy according to the data reading status of each enabled storage sub-unit 12, it releases the enabled The storage sub-unit 12 makes the enable terminal 121 of the enabled storage sub-unit 12 in a reset state.

Different strategies can be used to determine whether the currently read data storage subunit 12 meets the preset resource release strategy. For example, in some examples, the resource management module 2 detects the row of read data on the data read interface 13 Address information, and when it is determined that the row address information of the read data on the data reading interface 13 does not contain the row address information of the data stored in the currently enabled storage subunit 12, the currently enabled storage subunit is determined 12 Meet the preset resource release strategy. In this embodiment, the release mechanism is to release the content of the storage subunit 12 when it is read empty.

In another embodiment, the resource management module 2 detects the row address information of the read data on the data reading interface 13 and determines that the row address information of the read data on the data reading interface 13 does not contain the current enable After the row address information of the data stored in the storage sub-unit 12 of the storage subunit 12, it is further detected that the data writing interface 11 has not received new data to be written for a period longer than a preset time period, or that the data writing interface 11 is further detected The row address information of the data to be written does not include the row address information of the data stored in the currently enabled storage subunit 12 is longer than the preset duration, and it is determined that the currently enabled storage subunit 12 satisfies the preset resource release Strategy. In this embodiment, the release mechanism of the currently enabled storage subunit 12 is that the content of the currently enabled storage subunit 12 is read empty and there is no new data to be written within the preset time period after the content is read empty The written data is written to the interface 11, or the content of the currently enabled storage subunit 12 is read empty and the preset duration after the content is read empty. The data to be written on the data writing interface 11 does not include writing to the The data of the storage subunit 12 that is currently enabled. Among them, the preset duration can be set according to needs, such as 10 seconds, 20 seconds, 30 seconds or other.

After releasing the currently enabled storage subunit 12, the resource management module 2 re-enables the released storage subunit 12 if it detects that the data writing interface 11 receives new data to be written. For example, when the shooting device shoots, when the storage subunit 12 is enabled, a line of data is stored, and then this line of data is read again. Before receiving new data, the storage subunit 12 can be reset to reduce power consumption. Until the FPGA receives new data to be written, the released storage subunit 12 will be enabled again, and the new data to be written will be stored in the storage subunit 12.

In a specific embodiment, referring to FIG. 6, the FPGA chip 30 is used in a camera. The FPGA chip 30 includes a RAM 100 with a size of 8K. The RAM 100 includes a 2K RAM 101, a 2K RAM 102, a 2K RAM 103, and a 2K RAM 104. When the camera is in the shooting state, 8K of memory resources are required, and RAM101, RAM102, RAM103, and RAM104 are all enabled; when the camera is in the video playback state, 1080P of memory resources are required, and RAM101 is enabled.

Under certain usage scenarios, compared with the unoptimized FPGA chip 30, the power consumption of the optimized FPGA chip 30 is reduced by 30%.

In an alternative embodiment, the FPGA chip includes a resource management module 2 but no forward detection module 3. In this alternative embodiment, after detecting that the data writing interface 11 receives the data to be written, the resource management module 2 outputs an enable signal according to the size of the data to be written to trigger one or more of the memory unit 1 The storage subunit 12 is enabled. Different from the FPGA chip 30 of the above embodiment, after determining that there is valid data to be written, the resource management module 2 of the alternative embodiment directly enables one of the plurality of storage subunits 12 according to the size of the data to be written或 Multiple storage subunits 12. For example, the memory unit 1 includes four 2K storage subunits 12. When the data to be written currently received by the data writing interface 11 is 8K in size, the enable terminals 121 of the four storage subunits 12 are electrically coupled to the first An output terminal 22 outputs an enable signal, triggering the four storage subunits 12 to be enabled, and storing 8K data to be written into the four storage subunits 12; when the data writing interface 11 currently receives the write to be received If the data is 1080P, one of the first output terminals 22 electrically coupled to the enable terminals 121 of the four memory subunits 12 outputs an enable signal, so that one of the memory subunits 12 is enabled, and the 1080P size The data to be written is stored in the enabled storage sub-unit 12.

The other parts of the alternative embodiment are similar to the FPGA chip 30 of the above embodiment.

The FPGA chip of this alternative embodiment divides the memory unit 1 when it is packaged, divides the memory unit 1 into a plurality of storage subunits 12, and in use, according to the size of the data to be written on the data writing interface 11 , Triggering the enablement of one or more storage subunits 12 in the memory unit 1 to realize the dynamic application of memory resources, ensuring that the minimum memory resources are used in various scenarios, and maximally reducing the power consumption of the FPGA chip, making the FPGA The chip can meet the electronic equipment with high power consumption requirements; moreover, the method for reducing the power consumption of the FPGA chip of the present invention has strong flexibility.

An embodiment of the present invention further provides an electronic device. The electronic device may include an acquisition module and/or a data storage module 20 and the FPGA chip 30 described in Embodiment 1 or Embodiment 2 above.

The data writing interface 11 is electrically coupled to the data collection module 10 and/or the data storage module 20. The data collection module 10 is used to collect data and send the collected data to the data writing interface 11 and/or the data storage module 20 The data stored in the data storage module 20 is sent to the data writing interface 11.

In an embodiment, referring to FIG. 7, the electronic device includes a data collection module 10 and an FPGA chip 30, and the data collection module 10 is electrically coupled to the FPGA chip 30. Taking an electronic device as a shooting device as an example, in this embodiment, a shooting device is used for shooting (the shooting device is in a shooting state), and the data collection module 10 is an image acquisition device of the shooting device. The image acquisition device captures an image and sends the image to The FPGA chip 30, the FPGA chip 30 caches the image in the memory unit 1. Further, the electronic device may further include a back-end module, and the back-end module may be an image processing module or a data storage module 20 (SD card or solid state drive SSD). The image processing module can read the image cached in the memory unit 1 and perform image processing, and the data storage module 20 can read the image cached in the memory unit 1 and store it.

In another embodiment, referring to FIG. 8, the electronic device includes a data storage module 20 and an FPGA chip 30, and the data storage module 20 is electrically coupled to the FPGA chip 30. Taking an electronic device as a shooting device as an example, in this embodiment, a historical display image (such as an LCD display) is used to play back the historically captured images (the shooting device is in a video playback state), and the data storage module 20 is the shooting device. The data storage module 20 sends the image stored in the data storage module 20 to the FPGA chip 30, and the FPGA chip 30 caches the image in the memory unit 1. Further, the electronic device may further include a back-end module, and the back-end module may be a display drive module, which may read the image in the memory unit 1 and display it through the display screen of the shooting device.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations There is any such actual relationship or order. The terms "include", "include", or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device that includes a series of elements includes not only those elements, but also others that are not explicitly listed Elements, or also include elements inherent to such processes, methods, objects, or equipment. Without further restrictions, the element defined by the sentence "include one..." does not exclude that there are other identical elements in the process, method, article or equipment that includes the element.

The FPGA chip provided by the embodiment of the present invention and the electronic device provided with the FPGA chip have been described in detail above. Specific examples are used in this article to explain the principle and implementation of the present invention. The description of the above embodiment is only for help Understand the method of the present invention and its core idea; meanwhile, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation and application scope. In summary, the content of this specification is not It should be understood as a limitation to the present invention.

Claims

An FPGA chip, which is used in electronic equipment; characterized in that the FPGA chip includes:

A memory unit, the memory unit includes a data writing interface, and the memory unit has a plurality of storage subunits, and each storage subunit includes an enabling terminal; and

A resource management module, the resource management module is electrically coupled to the data writing interface, and is electrically coupled to the enable end of each storage unit;

The resource management module can obtain the current use state of the electronic device through the data writing interface, and output a first enable signal according to the current use state of the electronic device to trigger one of the memory units Or multiple memory subunits are enabled.
The FPGA chip according to claim 1, wherein the plurality of storage subunits are equal in size.
The FPGA chip according to claim 1, wherein the electronic device is a camera, and the use state includes at least one of the following:

Shooting status, video playback status.
The FPGA chip according to claim 1, wherein the resource management module includes a first detection terminal and a first output terminal, the first detection terminal is electrically coupled to the data writing interface, and the first An output terminal is electrically coupled to the enable terminal of each memory cell.
The FPGA chip according to claim 1 or 4, wherein the resource management module outputs a first enable signal according to the size of the data to be written corresponding to the current use status of the electronic device.
The FPGA chip according to claim 5, wherein the FPGA further comprises a forward detection module, the forward detection module is electrically coupled to the data writing interface and connected to each storage subunit Energy-end electrical coupling connection;

The resource management module outputs a first enable signal according to the size of the data to be written corresponding to the current use state of the electronic device, to trigger one or more storage subunits in the memory unit to be in the enable state ;

After detecting that the data writing interface receives the data to be written, the forward detection module outputs a second enable signal to enable the storage subunit to be enabled.
The FPGA chip according to claim 6, wherein the FPGA chip further includes a first logic circuit, and the resource management module and the forward detection module communicate with each storage subunit through the first logic circuit The enable terminal is electrically coupled.
The FPGA chip according to claim 7, wherein the first logic circuit includes at least one of an OR operation, an AND operation, an XOR operation, and a NOT operation.
The FPGA chip according to claim 6, wherein there are multiple storage subunits to be enabled;

After detecting that the data writing interface receives the data to be written, the forward detection module sequentially enables the plurality of storage subunits to be enabled according to the row address information of the data to be written in each frame, Therefore, the currently enabled memory subunit to be enabled is enabled after the writing of row data of the last enabled memory subunit to be enabled is completed.
The FPGA chip according to claim 9, wherein the forward detection module includes a write address judgment module, the write address judgment module is electrically coupled to the data write interface, and is connected to each storage subunit The electrical connection of the enable end of the;

The write address judgment module is used to judge the row address information of the data to be written in the current frame on the data writing interface, and according to the row address information, output a second enable signal to the storage corresponding to the row address information The enable end of the subunit.
The FPGA chip according to claim 10, wherein the forward detection module further comprises a frame data detection module, the frame data detection module is electrically coupled to the data writing interface and connected to each storage sub The enable end of the unit is electrically coupled;

The frame data detection module is used to detect a frame header identifier and a frame trailer identifier of the data to be written in the current frame on the data writing interface;

The frame data detection module releases all the enabled storage subunits when detecting the specific frame end flag, so that the enabled terminals of all the enabled storage subunits are in a reset state;

After the frame data detection module detects the specific frame header identifier, if the write address judgment module outputs the second enable signal, the corresponding storage subunit is enabled.
The FPGA chip according to claim 11, wherein the FPGA chip further includes a second logic circuit, and the write address judgment module and the frame data detection module communicate with each storage sub via the second logic circuit The enable terminal of the unit is electrically coupled and connected.
The FPGA chip according to claim 12, wherein the second logic circuit includes at least one of an OR operation, an AND operation, an XOR operation, and a NOT operation.
The FPGA chip according to claim 1, wherein the resource management module outputs the first enable according to the current use state of the electronic device after detecting that the enable terminals of all the storage subunits are in the reset state Signal to trigger one or more storage subunits in the memory unit to be enabled.
The FPGA chip according to claim 1, wherein the resource management module outputs a first enable signal according to the current use state of the electronic device to trigger one or more storages in the memory unit After the subunit is enabled, the data to be written is written into the enabled one or more storage subunits through the data writing interface.
The FPGA chip according to claim 15, wherein the memory unit further includes a data reading interface, and the resource management module is electrically coupled to the data reading interface;

After the data writing interface writes the data to be written into the enabled one or more storage subunits, the resource management module detects each enabled storage through the data reading interface The data reading status of the subunit;

In addition, the resource management module releases the enabled storage when it is determined that the enabled storage subunit satisfies the preset resource release strategy according to the data reading status of each enabled storage subunit The subunit, so that the enabled end of the enabled storage subunit is in a reset state.
The FPGA chip according to claim 16, wherein the resource management module detects row address information of the read data on the data read interface and determines the read data on the data read interface When the row address information does not include the row address information of the data stored in the currently enabled storage subunit, it is determined that the currently enabled storage subunit satisfies the preset resource release strategy.
The FPGA chip according to claim 17, wherein the resource management module determining that the currently enabled storage subunit satisfies a preset resource release strategy further comprises:

The resource management module detects the row address information of the read data on the data reading interface, and determines that the row address information of the read data on the data reading interface does not contain the currently enabled storage sub After the row address information of the data stored in the cell,

Further detecting that the data writing interface has not received new data to be written for a period of time greater than a preset period of time, or,

It is further detected that the row address information of the data to be written on the data writing interface does not include the row address information of the data stored in the currently enabled storage subunit is longer than the preset duration.
The FPGA chip according to claim 16, wherein after the resource management module releases the currently enabled storage subunit, if it is detected that the data writing interface receives new data to be written , Then re-enable the released storage subunit.
The FPGA chip according to claim 1, wherein the memory unit is a RAM.
An electronic device, characterized in that the electronic device includes:

Data acquisition module and/or data storage module; and

The FPGA chip includes a memory unit and a resource management module. The memory unit includes a data writing interface, and the memory unit has a plurality of storage subunits. Each storage subunit includes an enabling terminal. The resource management module and the resource management module The data writing interface is electrically coupled and connected to the enable terminal of each storage unit;

The data writing interface is electrically coupled to the data acquisition module and/or data storage module;

The data collection module is used to collect data and send the collected data to the data writing interface and/or the data storage module to send the data stored by the data storage module to the data writing interface;

The resource management module can obtain the current use state of the electronic device through the data writing interface, and output a first enable signal according to the current use state of the electronic device to trigger one of the memory units Or multiple memory subunits are enabled.
The electronic device according to claim 21, wherein the plurality of storage subunits are equal in size.
The electronic device according to claim 21, wherein the electronic device is a camera, and the use state includes at least one of the following:

Shooting status, video playback status.
The electronic device according to claim 21, wherein the resource management module includes a first detection terminal and a first output terminal, the first detection terminal is electrically coupled to the data writing interface, and the first An output terminal is electrically coupled to the enable terminal of each memory cell.
The electronic device according to claim 21 or 24, wherein the resource management module outputs a first enable signal according to the size of the data to be written corresponding to the current use status of the electronic device.
The electronic device according to claim 25, wherein the FPGA further comprises a forward detection module, the forward detection module is electrically coupled to the data writing interface and connected to each storage subunit Energy-end electrical coupling connection;

The resource management module outputs a first enable signal according to the size of the data to be written corresponding to the current use state of the electronic device, to trigger one or more storage subunits in the memory unit to be in the enable state ;

After detecting that the data writing interface receives the data to be written, the forward detection module outputs a second enable signal to enable the storage subunit to be enabled.
The electronic device according to claim 26, wherein the FPGA chip further includes a first logic circuit, and the resource management module and the forward detection module communicate with each storage subunit through the first logic circuit The enable terminal is electrically coupled.
The electronic device according to claim 27, wherein the first logic circuit includes at least one of an OR operation, an AND operation, an XOR operation, and a NOT operation.
The electronic device according to claim 26, wherein there are multiple storage subunits to be enabled;

After detecting that the data writing interface receives the data to be written, the forward detection module sequentially enables the plurality of storage subunits to be enabled according to the row address information of the data to be written in each frame, Therefore, the currently enabled memory subunit to be enabled is enabled after the writing of row data of the last enabled memory subunit to be enabled is completed.
The electronic device according to claim 29, wherein the forward detection module includes a write address judgment module, the write address judgment module is electrically coupled to the data write interface, and is connected to each storage subunit The electrical connection of the enable end of the;

The write address judgment module is used to judge the row address information of the data to be written in the current frame on the data writing interface, and according to the row address information, output a second enable signal to the storage corresponding to the row address information The enable end of the subunit.
The electronic device according to claim 30, wherein the forward detection module further comprises a frame data detection module, the frame data detection module is electrically coupled to the data writing interface and connected to each storage sub The enable end of the unit is electrically coupled;

The frame data detection module is used to detect a frame header identifier and a frame trailer identifier of the data to be written in the current frame on the data writing interface;

The frame data detection module releases all the enabled storage subunits when detecting the specific frame end flag, so that the enabled terminals of all the enabled storage subunits are in a reset state;

After the frame data detection module detects the specific frame header identifier, if the write address judgment module outputs the second enable signal, the corresponding storage subunit is enabled.
The electronic device according to claim 31, wherein the FPGA chip further includes a second logic circuit, and the write address determination module and the frame data detection module communicate with each storage sub via the second logic circuit The enable terminal of the unit is electrically coupled and connected.
The electronic device according to claim 32, wherein the second logic circuit includes at least one of an OR operation, an AND operation, an XOR operation, and a NOT operation.
The electronic device according to claim 21, wherein the resource management module outputs the first enable according to the current use state of the electronic device after detecting that the enable terminals of all the storage subunits are in the reset state Signal to trigger one or more storage subunits in the memory unit to be enabled.
The electronic device according to claim 21, wherein the resource management module outputs a first enable signal according to the current usage state of the electronic device to trigger one or more storages in the memory unit After the subunit is enabled, the data to be written is written into the enabled one or more storage subunits through the data writing interface.
The electronic device according to claim 35, wherein the memory unit further includes a data reading interface, and the resource management module is electrically coupled to the data reading interface;

After the data writing interface writes the data to be written into the enabled one or more storage subunits, the resource management module detects each enabled storage through the data reading interface The data reading status of the subunit;

In addition, the resource management module releases the enabled storage when it is determined that the enabled storage subunit satisfies the preset resource release strategy according to the data reading status of each enabled storage subunit The subunit, so that the enabled end of the enabled storage subunit is in a reset state.
The electronic device according to claim 36, wherein the resource management module detects row address information of the read data on the data read interface and determines the read data on the data read interface When the row address information does not include the row address information of the data stored in the currently enabled storage subunit, it is determined that the currently enabled storage subunit satisfies the preset resource release strategy.
The electronic device according to claim 37, wherein the resource management module determining that the currently enabled storage subunit satisfies a preset resource release policy further comprises:

The resource management module detects the row address information of the read data on the data reading interface, and determines that the row address information of the read data on the data reading interface does not contain the currently enabled storage sub After the row address information of the data stored in the cell,

Further detecting that the data writing interface has not received new data to be written for a period of time greater than a preset period of time, or,

It is further detected that the row address information of the data to be written on the data writing interface does not include the row address information of the data stored in the currently enabled storage subunit is longer than the preset duration.
The electronic device according to claim 36, characterized in that, after releasing the currently enabled storage subunit, the resource management module detects that the data writing interface receives new data to be written , Then re-enable the released storage subunit.
The electronic device according to claim 21, wherein the memory unit is a RAM.
An FPGA chip, which is used in electronic equipment; characterized in that the FPGA chip includes:

A memory unit, the memory unit includes a data writing interface, and the memory unit has a plurality of storage subunits, and each storage subunit includes an enabling terminal; and

A resource management module, the resource management module is electrically coupled to the data writing interface, and is electrically coupled to the enable end of each storage unit;

After detecting that the data writing interface receives the data to be written, the resource management module outputs an enable signal according to the size of the data to be written to trigger one or more storages in the memory unit The subunit is enabled.
The FPGA chip according to claim 41, wherein the plurality of storage subunits are equal in size.
The FPGA chip according to claim 41, wherein the resource management module includes a first detection terminal and a first output terminal, the first detection terminal is electrically coupled to the data writing interface, and the first An output terminal is electrically coupled to the enable terminal of each memory cell.
The FPGA chip according to claim 41, wherein the resource management module outputs an enable signal according to the size of the data to be written after detecting that the enable terminals of all storage subunits are in a reset state, To trigger the enabling of one or more storage subunits in the memory unit.
The FPGA chip according to claim 41, wherein the resource management module outputs an enable signal according to the size of the data to be written to trigger one or more storage subunits in the memory unit After being enabled, the data to be written is written into the enabled one or more storage subunits through the data writing interface.
The FPGA chip according to claim 45, wherein the memory unit further includes a data reading interface, and the resource management module is electrically coupled to the data reading interface;

After the data writing interface writes the data to be written into the enabled one or more storage subunits, the resource management module detects each enabled storage through the data reading interface The data reading status of the subunit;

In addition, the resource management module releases the enabled storage when it is determined that the enabled storage subunit satisfies the preset resource release strategy according to the data reading status of each enabled storage subunit The subunit, so that the enabled end of the enabled storage subunit is in a reset state.
The FPGA chip according to claim 45, wherein the resource management module detects row address information of the read data on the data read interface and determines the read data on the data read interface When the row address information does not include the row address information of the data stored in the currently enabled storage subunit, it is determined that the currently enabled storage subunit satisfies the preset resource release strategy.
The FPGA chip according to claim 47, wherein the resource management module determining that the currently enabled storage subunit satisfies a preset resource release strategy further comprises:

The resource management module detects the row address information of the read data on the data reading interface, and determines that the row address information of the read data on the data reading interface does not contain the currently enabled storage sub After the row address information of the data stored in the cell,

Further detecting that the data writing interface has not received new data to be written for a period of time greater than a preset period of time, or,

It is further detected that the row address information of the data to be written on the data writing interface does not include the row address information of the data stored in the currently enabled storage subunit is longer than the preset duration.
The FPGA chip according to claim 46, wherein after releasing the currently enabled storage subunit, the resource management module detects that the data writing interface receives new data to be written , Then re-enable the released storage subunit.
The FPGA chip according to claim 41, wherein the memory unit is a RAM.
An electronic device, characterized in that the electronic device includes:

Data acquisition module and/or data storage module; and

The FPGA chip includes a memory unit and a resource management module. The memory unit includes a data writing interface, and the memory unit has a plurality of storage subunits. Each storage subunit includes an enabling terminal. The resource management module and the resource management module The data writing interface is electrically coupled and connected to the enable terminal of each storage unit;

The data writing interface is electrically coupled to the data acquisition module and/or data storage module;

The data collection module is used to collect data and send the collected data to the data writing interface and/or the data storage module to send the data stored by the data storage module to the data writing interface;

After detecting that the data writing interface receives the data to be written, the resource management module outputs an enable signal according to the size of the data to be written to trigger one or more storages in the memory unit The subunit is enabled.
The electronic device according to claim 51, wherein the plurality of storage subunits are equal in size.
The electronic device according to claim 51, wherein the resource management module includes a first detection terminal and a first output terminal, the first detection terminal is electrically coupled to the data writing interface, and the first An output terminal is electrically coupled to the enable terminal of each memory cell.
The electronic device according to claim 51, wherein the resource management module outputs an enable signal according to the size of the data to be written after detecting that the enable terminals of all storage subunits are in a reset state, To trigger the enabling of one or more storage subunits in the memory unit.
The electronic device according to claim 51, wherein the resource management module outputs an enable signal according to the size of the data to be written to trigger one or more storage subunits in the memory unit After being enabled, the data to be written is written into the enabled one or more storage subunits through the data writing interface.
The electronic device according to claim 55, wherein the memory unit further includes a data reading interface, and the resource management module is electrically coupled to the data reading interface;

After the data writing interface writes the data to be written into the enabled one or more storage subunits, the resource management module detects each enabled storage through the data reading interface The data reading status of the subunit;

In addition, the resource management module releases the enabled storage when it is determined that the enabled storage subunit satisfies the preset resource release strategy according to the data reading status of each enabled storage subunit The subunit, so that the enabled end of the enabled storage subunit is in a reset state.
The electronic device according to claim 55, wherein the resource management module detects row address information of the read data on the data read interface and determines the read data on the data read interface When the row address information does not include the row address information of the data stored in the currently enabled storage subunit, it is determined that the currently enabled storage subunit satisfies the preset resource release strategy.
The electronic device according to claim 57, wherein the resource management module determining that the currently enabled storage subunit satisfies the preset resource release policy further comprises:

The resource management module detects the row address information of the read data on the data reading interface, and determines that the row address information of the read data on the data reading interface does not contain the currently enabled storage sub After the row address information of the data stored in the cell,

Further detecting that the data writing interface has not received new data to be written for a period of time greater than a preset period of time, or,

It is further detected that the row address information of the data to be written on the data writing interface does not include the row address information of the data stored in the currently enabled storage subunit is longer than the preset duration.
The electronic device according to claim 56, characterized in that, after releasing the currently enabled storage subunit, the resource management module detects that the data writing interface receives new data to be written , Then re-enable the released storage subunit.
The electronic device according to claim 51, wherein the memory unit is a RAM.