CN116298811B - Chip packaging detection system based on FPGA and packaging method thereof - Google Patents

Chip packaging detection system based on FPGA and packaging method thereof Download PDF

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CN116298811B
CN116298811B CN202310340182.6A CN202310340182A CN116298811B CN 116298811 B CN116298811 B CN 116298811B CN 202310340182 A CN202310340182 A CN 202310340182A CN 116298811 B CN116298811 B CN 116298811B
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chip packaging
image
image data
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CN116298811A (en
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吴佳
李礼
吴叶楠
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Shanghai V&g Information Technology Co ltd
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    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract

The invention relates to the technical field of product detection, in particular to a chip packaging detection system based on an FPGA and a packaging method thereof, wherein the chip packaging detection system comprises a deployment layer, a data processing layer and an evaluation layer: the processing stations of the chip packaging equipment are recorded through a deployment layer, a system end user selects the installation position of the detection equipment in the deployment layer according to the processing stations of the chip packaging equipment, meanwhile, the detection equipment is installed, and the detection equipment installed on the processing stations of the chip packaging equipment is subjected to operation logic debugging; the system can detect the surface of the chip in a mode of image data acquisition and analysis, ensures that dust is not attached to the surface of the packaged chip, enables the packaged chip to meet the use standard, and can detect the packaging environment of the chip in the image analysis stage, so that the system can realize the chip packaging safety judgment and evaluate the qualified condition of the chip packaging batch.

Description

Chip packaging detection system based on FPGA and packaging method thereof
Technical Field
The invention relates to the technical field of product detection, in particular to a chip packaging detection system based on an FPGA and a packaging method thereof.
Background
The shell for mounting semiconductor integrated circuit chip plays roles of placing, fixing, sealing, protecting chip and enhancing electrothermal performance, and is also a bridge for communicating the world inside the chip with external circuits, the joints on the chip are connected to pins of the package shell by wires, and the pins are connected with other devices by wires on the printed board. Thus, packaging plays an important role for the chip.
However, in the process of chip packaging, if dust exists on the surface of the chip packaging, the subsequent operation of the chip can be directly affected, so that people can package the chip in a dust-free environment to solve the problem, but a small amount of dust still exists in the dust-free environment, and therefore, a small amount of defective products often appear on chips produced in the same batch on the chip packaging equipment.
Disclosure of Invention
Technical problem to be solved
Aiming at the defects in the prior art, the invention provides a chip packaging detection system based on an FPGA and a packaging method thereof, which solve the technical problems in the background art.
Technical proposal
In order to achieve the above purpose, the invention is realized by the following technical scheme:
in a first aspect, an FPGA-based chip package inspection system includes a deployment layer, a data processing layer, and an evaluation layer:
the processing stations of the chip packaging equipment are recorded through a deployment layer, a system end user selects the installation position of the detection equipment in the deployment layer according to the processing stations of the chip packaging equipment, meanwhile, the detection equipment is installed, and the detection equipment installed on the processing stations of the chip packaging equipment is subjected to operation logic debugging;
the data processing layer comprises a storage module, an identification module and a setting module, wherein the storage module is used for receiving operation logic obtained by operation of the module to which the deployment layer belongs, and the identification module is used for identifying the number of dust existing on the surface of a chip image in image data acquired by the detection equipment and setting a chip packaging safety threshold;
when the identification module identifies the number of dust existing on the surface of the chip image or the filter screen module image in the image data, the identification module calculates the dust by the following formula:
wherein: lambda is the number of dust existing on the chip image or the filter screen module image area pixel points in the traversed image data; m is M i The image is segmented, and the segmented area contains the number of pixels of the chip image or the filter screen module image; mu dust example image data; s is S li Image chromaticity weight for dust example; ζ is an image disturbance factor; TY (TY) c Counting a permissible deviation coefficient for the number of dust set by a user;
the evaluation layer comprises a judging module and a marking module, wherein the judging module judges whether the number of dust existing on the surface of a chip image or a filter screen module image in the image data calculated by the data processing layer is in a chip packaging safety threshold set by the setting module, and the marking module is used for marking a chip packaging time stamp.
Still further, the in-deployment layer detection apparatus includes: the camera module and the closed fan unit are both arranged at the position where the processing stations of the chip packaging equipment are mutually bordered, and the camera module is integrated by a high-definition high-speed camera and is used for collecting chip images transmitted in real time on the processing stations of the chip packaging equipment; the closed fan unit is composed of a closed shell and a fan unit, and the closed fan unit performs closed treatment on a treatment station of the chip packaging equipment and performs air circulation on the environment of the treatment station of the chip packaging equipment.
Still further, the fan group output of sealed fan group all is provided with the filter screen module for intercept the dust that exists in the fan group transmission gas, the filter screen module that fan group output set up all is provided with the camera module, the camera module gathers the processing station operation rate looks adaptation of frequency and chip encapsulation equipment when the chip image data of real-time collection of operation, and the camera module is in the synchronous triggering of collection chip image data at every turn and is sealed fan group operation, and sealed fan group stops the operation when the chip arrives chip encapsulation equipment last processing station next time.
Further, when the closed fan set is started and stopped in the system, in the stage that the camera module operates and collects chip image data, image data collection and judgment are carried out through the following formula, operation is triggered after the judgment is completed, and the judgment formula is that;
wherein:is a judgment coefficient; a is that eb The residence time of the chip in a processing station on the chip packaging equipment is given; v (V) tar The transmission speed of a processing station on chip packaging equipment is the transmission speed; s is a processing station where a chip transmitted on the chip packaging equipment is located; omega is the traction time of a transmission chip on a processing station of the chip packaging equipment; s is S tar A next target processing station for chip transfer on the chip packaging apparatus;
after the judgment formula is calculated, when the judgment coefficient is larger than 1, the judgment result and parameters used by formula calculation are synchronously fed back to a deployment layer, the deployment layer transmits received data to a camera module and a closed fan set, and the camera module and the closed fan set perform setting of operation logic according to the received data; and the judgment coefficient is smaller than or equal to 1, and the chip packaging equipment is triggered to run again to transmit the chip so as to provide data support for formula rerun.
Further, all modules included in the deployment layer before the data processing layer and the evaluation layer are operated at least once, and the data processing layer and the evaluation layer include modules which are manually confirmed to be permitted to operate by a system end user.
Furthermore, when the identification module operates to identify and count the number of dust existing on the chip image or the image surface of the filter screen module in the image data, defogging processing is synchronously performed on the image data, and the image data is calculated and processed through the following functions to obtain defogged image data, wherein the formula is as follows:
wherein: j (x) is the original image; i (x) is a hazy image: t is t 0 Is an image exposure threshold; t (x) is transmittance; a is the intensity of ambient atmosphere.
Furthermore, the chip package safety threshold set by the setting module and the operation logic stored by the storage module are mutually configured, the setting module is manually edited by a system end user to set, and the content of the chip package safety threshold set by the setting module is the ratio of the designated unit area to the dust number.
Furthermore, the evaluation layer judging module operates continuously through the operation frequency set by the system end user, two groups of chip packaging safety thresholds set by the setting module in the data processing layer are respectively applied to the chip images and the filter screen module images in the image data, the judging module in the evaluation layer judges the chip packaging safety thresholds corresponding to the image data of the image filter screen module, when the judging result is negative, the chip packaging equipment stops operating, and the system end user sorts the time stamps marked by the packaged chips according to the marking module.
Still further, there are camera module and closed fan group through medium electric connection on the chip packaging equipment, the filter screen module is installed to closed fan group's output, camera module and closed fan group have the storage module through medium electric connection, the storage module has identification module and settlement module through medium electric connection, settlement module has the judgement module through medium electric connection, the judgement module passes through medium electric and marks the module interconnection.
In a second aspect, a chip packaging method based on FPGA includes the steps of:
step 1: the method comprises the steps that a camera module and a closed fan set are arranged on chip packaging equipment, and image data of chips transmitted and processed on the chip packaging equipment and a filter screen module arranged at the output end of the closed fan set are collected through the camera module;
step 2: analyzing the image data acquired in the step 1, and identifying chip images in the image data and the quantity of dust in a filter screen module arranged at the output end of the closed fan unit;
step 3: setting a chip packaging safety threshold, and judging whether the chip transmitted on the current chip packaging equipment is qualified or not according to the chip packaging safety threshold;
step 4: and further packaging the qualified chips through chip packaging equipment.
Advantageous effects
Compared with the known public technology, the technical scheme provided by the invention has the following beneficial effects:
1. the invention provides a chip packaging detection system based on an FPGA, which can detect the surface of a chip in a mode of image data acquisition and analysis, ensure that dust is not attached to the surface of the packaged chip, ensure that the packaged chip meets the use standard, and can detect the packaging environment of the chip in the stage of image analysis, thereby realizing the safety judgment of chip packaging and evaluating the qualified condition of chip packaging batches.
2. When the system is operated, the arrangement of the closed fan unit further brings a maintenance effect to chip packaging equipment when packaging chips, dust existing in a chip packaging environment is reduced to a certain extent, and the system can be suitable for chip packaging detection of different signals in a data storage mode, so that the operation applicability of the system is further improved.
3. The invention provides a chip packaging method based on an FPGA, which can further maintain the stability of system operation in the invention by executing the steps in the method, and further provides packaging logic when chip packaging equipment packages chips in the step execution process of the method, so that a system end user can more conveniently and rapidly complete chip packaging operation through the technical scheme.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a chip package inspection system based on an FPGA;
fig. 2 is a flow chart of a chip packaging method based on FPGA.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention is further described below with reference to examples.
Example 1
The chip package detection system based on the FPGA of this embodiment, as shown in fig. 1, includes a deployment layer, a data processing layer, and an evaluation layer:
the processing stations of the chip packaging equipment are recorded through a deployment layer, a system end user selects the installation position of the detection equipment in the deployment layer according to the processing stations of the chip packaging equipment, meanwhile, the detection equipment is installed, and the detection equipment installed on the processing stations of the chip packaging equipment is subjected to operation logic debugging;
the data processing layer comprises a storage module, an identification module and a setting module, wherein the storage module is used for receiving operation logic obtained by operation of the module to which the deployment layer belongs, and the identification module is used for identifying the number of dust existing on the surface of a chip image in image data acquired by the detection equipment and setting a chip packaging safety threshold;
when the identification module identifies the number of dust existing on the surface of the chip image or the filter screen module image in the image data, the identification module calculates the dust by the following formula:
wherein: lambda is the number of dust existing on the chip image or the filter screen module image area pixel points in the traversed image data; m is M i The image is segmented, and the segmented area contains the number of pixels of the chip image or the filter screen module image; mu dust example image data; s is S li Image chromaticity weight for dust example; ζ is an image disturbance factor; TY (TY) c Counting a permissible deviation coefficient for the number of dust set by a user;
through the calculation of the formula, the system can conduct specific analysis of dust number on each item of collected image data, and further serve as a standard for judging whether a chip is safe or not, and basic data support is provided for system operation.
The evaluation layer comprises a judging module and a marking module, wherein the judging module judges whether the number of dust on the surface of a chip image or a filter screen module image in the image data calculated by the data processing layer is in a chip packaging safety threshold set by the setting module, and the marking module is used for marking a chip packaging time stamp;
a chip packaging method based on FPGA comprises the following steps:
step 1: the method comprises the steps that a camera module and a closed fan set are arranged on chip packaging equipment, and image data of chips transmitted and processed on the chip packaging equipment and a filter screen module arranged at the output end of the closed fan set are collected through the camera module;
step 2: analyzing the image data acquired in the step 1, and identifying chip images in the image data and the quantity of dust in a filter screen module arranged at the output end of the closed fan unit;
step 3: setting a chip packaging safety threshold, and judging whether the chip transmitted on the current chip packaging equipment is qualified or not according to the chip packaging safety threshold;
step 4: and further packaging the qualified chips through chip packaging equipment.
Example 2
On the basis of embodiment 1, this embodiment further specifically describes, with reference to fig. 1, an FPGA-based chip package inspection system in embodiment 1:
the detection device in the deployment layer comprises: the camera module and the closed fan unit are both arranged at the position where the processing stations of the chip packaging equipment are mutually bordered, and the camera module is integrated by a high-definition high-speed camera and is used for collecting chip images transmitted in real time on the processing stations of the chip packaging equipment; the closed fan unit is composed of a closed shell and a fan unit, and is used for performing closed treatment on a treatment station of the chip packaging equipment and performing air circulation on the environment of the treatment station of the chip packaging equipment;
the output ends of the fan units of the closed fan units are provided with filter screen modules for intercepting dust in the gas transmitted by the fan units, the filter screen modules arranged at the output ends of the fan units are provided with camera modules, the acquisition frequency of the camera modules is matched with the operation speed of the processing stations of the chip packaging equipment when the camera modules acquire chip image data in real time in operation, the camera modules synchronously trigger the operation of the closed fan units when the chip image data are acquired each time, and the closed fan units stop operating when the chip reaches the next processing station of the chip packaging equipment;
when the closed fan set is started and stopped in the system, in the stage of acquiring chip image data in the operation of the camera module, image data acquisition judgment is carried out through the following formula, the operation is triggered after the judgment is completed, and the judgment formula is as follows;
wherein:is a judgment coefficient; a is that eb Stopping processing station for chip on chip packaging equipmentA time is reserved; v (V) tar The transmission speed of a processing station on chip packaging equipment is the transmission speed; s is a processing station where a chip transmitted on the chip packaging equipment is located; omega is the traction time of a transmission chip on a processing station of the chip packaging equipment; s is S tar A next target processing station for chip transfer on the chip packaging apparatus;
after the judgment formula is calculated, when the judgment coefficient is larger than 1, the judgment result and parameters used by formula calculation are synchronously fed back to a deployment layer, the deployment layer transmits received data to a camera module and a closed fan set, and the camera module and the closed fan set perform setting of operation logic according to the received data; and the judgment coefficient is smaller than or equal to 1, and the chip packaging equipment is triggered to run again to transmit the chip so as to provide data support for formula rerun.
Through the formula calculation, the data obtained by the system operation can be further selected, so that the data obtained by the system operation is safer and more effective when being applied further.
Example 3
On the basis of embodiment 1, this embodiment further specifically describes, with reference to fig. 1, an FPGA-based chip package inspection system in embodiment 1:
all modules contained in the deployment layer before the data processing layer and the evaluation layer are operated at least once, and the data processing layer and the evaluation layer contain the modules which are manually confirmed to permit operation by a system end user.
When the identification module operates to identify and count the number of dust existing on the surface of a chip image or a filter screen module image in the image data, defogging processing is synchronously carried out on the image data, the image data is calculated and processed through the following functions to obtain defogged image data, and the formula is as follows:
wherein: j (x) is the original image; i (x) is a hazy image: t is t 0 Is an image exposure threshold;t (x) is transmittance; a is the intensity of ambient atmosphere;
the chip packaging safety threshold set by the setting module and the operation logic stored by the storage module are mutually configured, the setting module manually edits and sets the chip packaging safety threshold set by the setting module, and the content of the chip packaging safety threshold set by the setting module is the ratio of the designated unit area to the dust number;
the evaluation layer judging module operates continuously through the operation frequency set by a system end user, two groups of chip packaging safety thresholds set by the setting module in the data processing layer are respectively applied to chip images and filter screen module images in the image data, the judging module in the evaluation layer judges the chip packaging safety thresholds corresponding to the image data of the image filter screen module, when the judging result is negative, the chip packaging equipment stops operating, and the system end user sorts the time stamps marked by the packaged chips according to the marking module;
the chip packaging equipment is electrically connected with a camera module and a closed fan unit through a medium, the output end of the closed fan unit is provided with a filter screen module, the camera module and the closed fan unit are electrically connected with a storage module through the medium, the storage module is electrically connected with an identification module and a setting module through the medium, the setting module is electrically connected with a judging module through the medium, and the judging module is interconnected with the marking module through the medium.
In summary, in the above embodiment, the system can detect the surface of the chip by means of image data acquisition and analysis, so as to ensure that no dust adheres to the surface of the packaged chip, and enable the packaged chip to meet the use standard, and can detect the packaging environment of the chip in the stage of image analysis, thereby enabling the system to realize the chip packaging safety judgment and evaluate the qualified condition of the chip packaging batch at the same time; meanwhile, when the system is in operation, the arrangement of the closed fan unit further brings a maintenance effect to chip packaging equipment when packaging chips, dust existing in a chip packaging environment is reduced to a certain extent, and the system can be suitable for chip packaging detection of different signals in a data storage mode, so that the operation applicability of the system is further improved;
on the other hand, the method described in the embodiment can further stabilize the system operation, and further provide the packaging logic when the chip packaging device packages the chip in the step execution process of the method, so that the system end user can more conveniently complete the chip packaging operation through the technical scheme.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. The chip packaging detection system based on the FPGA is characterized by comprising a deployment layer, a data processing layer and an evaluation layer:
the processing stations of the chip packaging equipment are recorded through a deployment layer, a system end user selects the installation position of the detection equipment in the deployment layer according to the processing stations of the chip packaging equipment, meanwhile, the detection equipment is installed, and the detection equipment installed on the processing stations of the chip packaging equipment is subjected to operation logic debugging;
the data processing layer comprises a storage module, an identification module and a setting module, wherein the storage module is used for receiving operation logic obtained by operation of the module to which the deployment layer belongs, and the identification module is used for identifying the number of dust existing on the surface of a chip image in image data acquired by the detection equipment and setting a chip packaging safety threshold;
when the identification module identifies the number of dust existing on the surface of the chip image or the filter screen module image in the image data, the identification module calculates the dust by the following formula:
；
wherein:the number of dust existing on the pixel points of the chip image or the filter screen module image area in the traversed image data; />The image is segmented, and the segmented area contains the number of pixels of the chip image or the filter screen module image; />Dust example image data; />Image chromaticity weight for dust example; />Is an image interference factor; />Counting a permissible deviation coefficient for the number of dust set by a user;
the evaluation layer comprises a judging module and a marking module, wherein the judging module judges whether the number of dust existing on the surface of a chip image or a filter screen module image in the image data calculated by the data processing layer is in a chip packaging safety threshold set by the setting module, and the marking module is used for marking a chip packaging time stamp.
2. The FPGA-based chip package inspection system of claim 1, wherein the in-deployment layer inspection apparatus comprises: the camera module and the closed fan unit are both arranged at the position where the processing stations of the chip packaging equipment are mutually bordered, and the camera module is integrated by a high-definition high-speed camera and is used for collecting chip images transmitted in real time on the processing stations of the chip packaging equipment; the closed fan unit is composed of a closed shell and a fan unit, and the closed fan unit performs closed treatment on a treatment station of the chip packaging equipment and performs air circulation on the environment of the treatment station of the chip packaging equipment.
3. The chip packaging detection system based on the FPGA, according to claim 2, wherein the fan set output ends of the closed fan set are all provided with filter screen modules for intercepting dust existing in the air transmitted by the fan set, the filter screen modules arranged at the fan set output ends are all provided with camera modules, the acquisition frequency of the camera modules is adapted to the operation speed of the processing station of the chip packaging equipment when the camera modules acquire chip image data in real time, the camera modules synchronously trigger the operation of the closed fan set every time the chip image data is acquired, and the closed fan set stops operating when the chip reaches the next processing station on the chip packaging equipment.
4. The chip packaging detection system based on the FPGA as claimed in claim 3, wherein when the closed fan set is started and stopped in the system, in the stage that the camera module operates and collects chip image data, image data collection judgment is carried out by the following formula, and the operation is triggered after the judgment is completed, wherein the judgment formula is as follows;
；
wherein:is a judgment coefficient; />The residence time of the chip in a processing station on the chip packaging equipment is given; />The transmission speed of a processing station on chip packaging equipment is the transmission speed; />The processing station is used for processing chips transmitted on the chip packaging equipment; />The traction time for transmitting the chip on a processing station of the chip packaging equipment; />A next target processing station for chip transfer on the chip packaging apparatus;
after the judgment formula is calculated, when the judgment coefficient is larger than 1, the judgment result and parameters used by formula calculation are synchronously fed back to a deployment layer, the deployment layer transmits received data to a camera module and a closed fan set, and the camera module and the closed fan set perform setting of operation logic according to the received data; and the judgment coefficient is smaller than or equal to 1, and the chip packaging equipment is triggered to run again to transmit the chip so as to provide data support for formula rerun.
5. The FPGA-based chip package inspection system of claim 1, wherein all modules included in the pre-run deployment layer of the data processing layer and the evaluation layer are run at least once, the data processing layer and the evaluation layer including modules manually confirming approval of the run by a system end user.
6. The FPGA-based chip packaging and detecting system according to claim 1, wherein when the identification module operates to identify and count the number of dust existing on the chip image or the surface of the filter screen module image in the image data, the image data is defogged synchronously, and the image data is calculated and processed by the following function to obtain defogged image data, where the formula is:
；
wherein:is the original image; />Is a foggy image: />Is an image exposure threshold; />Is transmittance; a is the intensity of ambient atmosphere.
7. The FPGA-based chip packaging inspection system according to claim 1, wherein the chip packaging security threshold set by the setting module and the operation logic stored in the storage module are mutually configured, the setting module is manually edited by a user at the system end to set, and the content of the chip packaging security threshold set by the setting module is a ratio of a specified unit area to a specified dust number.
8. The chip packaging detection system based on the FPGA according to claim 1, wherein the judging module in the evaluation layer runs continuously through the running frequency set by a system end user, two groups of chip packaging safety thresholds set by the setting module in the data processing layer are respectively applied to the chip images and the filter screen module images in the image data, the judging module in the evaluation layer judges the chip packaging safety thresholds corresponding to the image filter screen module image data, when the judging result is no, the chip packaging equipment stops running, and the system end user sorts the time stamps marked by the packaged chips according to the marking module.
9. The chip packaging detection system based on the FPGA according to claim 1, wherein the chip packaging equipment is electrically connected with a camera module and a closed fan unit through a medium, the output end of the closed fan unit is provided with a filter screen module, the camera module and the closed fan unit are electrically connected with a storage module through the medium, the storage module is electrically connected with an identification module and a setting module through the medium, the setting module is electrically connected with a judging module through the medium, and the judging module is electrically connected with the marking module through the medium.
10. An FPGA-based chip packaging method implemented by the FPGA-based chip packaging detection system according to any one of claims 1 to 9, comprising the steps of:
step 1: the method comprises the steps that a camera module and a closed fan set are arranged on chip packaging equipment, and image data of chips transmitted and processed on the chip packaging equipment and a filter screen module arranged at the output end of the closed fan set are collected through the camera module;
step 2: analyzing the image data acquired in the step 1, and identifying chip images in the image data and the quantity of dust in a filter screen module arranged at the output end of the closed fan unit;
step 3: setting a chip packaging safety threshold, and judging whether the chip transmitted on the current chip packaging equipment is qualified or not according to the chip packaging safety threshold;
step 4: and further packaging the qualified chips through chip packaging equipment.
CN202310340182.6A 2023-03-31 2023-03-31 Chip packaging detection system based on FPGA and packaging method thereof Active CN116298811B (en)

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