WO2020118748A1 - 一种显示面板和显示装置 - Google Patents

一种显示面板和显示装置 Download PDF

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Publication number
WO2020118748A1
WO2020118748A1 PCT/CN2018/122224 CN2018122224W WO2020118748A1 WO 2020118748 A1 WO2020118748 A1 WO 2020118748A1 CN 2018122224 W CN2018122224 W CN 2018122224W WO 2020118748 A1 WO2020118748 A1 WO 2020118748A1
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WIPO (PCT)
Prior art keywords
signal
source driver
bus
timing controller
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/122224
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English (en)
French (fr)
Inventor
赵文勤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Application filed by HKC Co Ltd, Chongqing HKC Optoelectronics Technology Co Ltd filed Critical HKC Co Ltd
Priority to US17/042,180 priority Critical patent/US11488514B2/en
Publication of WO2020118748A1 publication Critical patent/WO2020118748A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a display device.
  • Flat panel displays include thin film transistor liquid crystal displays (Thin Film Transistor-Liquid Crystal (TFT-LCD) and organic light-emitting diode (Organic Light-Emitting Diode, OLED) displays, etc.
  • TFT-LCD Thi Film Transistor-Liquid Crystal
  • OLED Organic Light-Emitting Diode
  • the thin film transistor liquid crystal display controls the rotation direction of the liquid crystal molecules to refract the light of the backlight module to generate a picture, which has many advantages such as thin body, power saving, no radiation and so on.
  • the organic light emitting diode display is made of organic electroluminescent diodes, and has many advantages such as self-luminescence, short response time, high definition and contrast, flexible display and large-area full-color display.
  • the purpose of the present application is to provide a display panel and a display device to reduce the cost of the display device.
  • the present application provides a display device including a display panel and a panel driving circuit that drives the display of the display panel;
  • the panel driving circuit includes a source driver that drives the data lines of the display panel, and a driver that drives the display panel A gate driver of the scanning line, a timing controller and a bus for driving the source driver and the gate driver, and the timing controller is respectively connected to the source driver and the gate driver through the bus;
  • the timing controller transmits signals to the source driver and the gate driver through the bus, respectively.
  • the bus includes:
  • a data transmission line the timing controller transmits data signals to the gate driver and the source driver through the data transmission line respectively;
  • a plurality of chip selection signal lines, the timing controller is connected to the source driver through the chip selection signal line; the chip selection signal line is connected to the source driver in one-to-one correspondence;
  • the source driver When the source driver receives the chip selection signal corresponding to the chip selection signal line, it reads the data signal from the data transmission line.
  • the panel driving circuit further includes a control circuit board and a flexible circuit board
  • the timing controller is located on the control circuit board
  • the source driver and the gate driver are located on the flexible circuit board
  • the bus and all Part of the bus connected to the timing controller is on the control circuit board
  • the branch points generated by connecting the bus to the source driver and the gate driver are on the flexible circuit board.
  • the panel driving circuit further includes a memory that stores data, and the memory is connected to the timing controller.
  • the present application also discloses a display device, which includes a display panel and a panel driving circuit that drives the display of the display panel;
  • the panel driving circuit includes: a control circuit board, a flexible circuit board, a source driver, a gate driver, a timing controller, a memory, and a bus;
  • the source driver which drives the data line of the display panel, is located on the flexible circuit board;
  • the gate driver which drives the scanning lines of the display panel, is located on the flexible circuit board;
  • Timing controller located on the control circuit board
  • the memory stores data and is connected to a timing controller.
  • the timing controller reads data signals and chip select signals from the memory;
  • a part of the bus connected to the timing controller is on the control circuit board, and the branch points generated by the bus connected to the source driver and the gate driver are on the flexible circuit board;
  • the bus includes:
  • a data transmission line the timing controller transmits data signals to the gate driver and the source driver through the data transmission line respectively;
  • Chip select signal line the timing controller is connected to the source driver through the chip select signal line; the chip select signal line is connected to the source driver in one-to-one correspondence;
  • the source driver When the source driver receives the chip selection signal corresponding to the chip selection signal line, it reads the data signal from the data transmission line.
  • the present application also discloses a driving method of a display device.
  • the display device includes:
  • the panel driving circuit includes:
  • a source driver to drive the data line of the display panel
  • the gate driver drives the scan line of the display panel
  • Timing controller to drive and control the source driver and the gate driver
  • the timing controller is respectively connected to the source driver and the gate driver through the bus;
  • the timing controller transmits signals to the source driver and the gate driver through the bus, respectively.
  • the driving method includes the steps of:
  • Timing controller transmits the data signal to the bus
  • Signal receiving step the source driver and the gate driver receive the data signal from the bus.
  • the bus includes:
  • a data transmission line the timing controller transmits data signals to the gate driver and the source driver through the data transmission line respectively;
  • a plurality of chip selection signal lines, the timing controller is connected to the source driver through the chip selection signal line; the chip selection signal line is connected to the source driver in one-to-one correspondence;
  • the source driver When the source driver receives a chip selection signal corresponding to the chip selection signal line, it reads the data signal from the data transmission line.
  • the panel driving circuit further includes a control circuit board and a flexible circuit board
  • the timing controller is located on the control circuit board
  • the source driver and the gate driver are located on the flexible circuit board.
  • a part of the bus connecting the bus to the timing controller is on the control circuit board, and the branch points generated when the bus is respectively connected to the source driver and the gate driver are on the flexible circuit board.
  • the panel driving circuit further includes a memory that stores data, and the memory is connected to the timing controller.
  • the bus includes a data transmission line and a chip select signal line;
  • the signal transmission step includes: the timing controller transmits a data signal to the data transmission line, and transmits a chip selection signal to the chip selection signal line;
  • the signal receiving step includes the source driver and the gate driver receiving the data signal from the data transmission line according to the chip select signal.
  • the timing controller reads the data signal and the chip select signal from the memory.
  • the data signal includes a first data signal and a second data signal
  • the signal transmission step includes: the timing controller sends the first data signal to the source driver to decode to generate a second data signal; the source driver transmits the second data signal to the bus;
  • the signal receiving step includes the gate driver receiving the second data signal from the bus.
  • the first data signal includes a source driving signal and a gate driving signal
  • the source driver decodes the gate driving signal, and sends the decoded gate driving signal to the bus.
  • this application receives the signal sent by the timing controller through the shared bus of the source driver and the gate driver, so the signal transmission method of the shared bus saves
  • the pins of the chip reduce the cost of packaging, and at the same time save space for the layout of the printed circuit board (PCB) and provide convenience.
  • FIG. 1 is a schematic diagram of a display device according to an embodiment of this application.
  • FIG. 2 is a schematic diagram of a display device according to one embodiment of the present application.
  • FIG. 3 is a schematic diagram of Part A of one embodiment of the present application.
  • FIG. 4 is a schematic diagram of steps of a driving method according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of steps of a driving method according to an embodiment of the present application.
  • connection should be understood in a broad sense, for example, it can be fixed connection or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • installation should be understood in a broad sense, for example, it can be fixed connection or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • the present application discloses a display device in an embodiment, including: a display panel 200; a panel driving circuit 100 that drives a display of the display panel 200; the panel driving circuit 100 includes: a source driver 110 , Driving the data lines of the display panel 200; the gate driver 120, driving the scanning lines of the display panel 200; the timing controller 130, driving and controlling the source driver 110 and the gate driver 120; the bus 140, the timing controller 130 through the bus 140 respectively
  • the source driver 110 and the gate driver 120 are connected; the timing controller 130 transmits signals to the source driver 110 and the gate driver 120 through the bus 140, respectively.
  • the source driver 110 and the gate driver 120 share the bus 140 to receive the signals from the timing controller 130.
  • the shared bus 140 performs signal transmission, which saves the pins of the chip and reduces the cost of packaging.
  • the layout of the printed circuit board (PCB) saves space and provides convenience.
  • a plurality of source drivers 110 are provided; the bus 140 includes:
  • the data transmission line 141, the timing controller 130 transmits data signals to the gate driver 120 and the source driver 110 through the data transmission line 141, respectively;
  • the timing controller 130 is connected to the source driver 110 through the chip select signal lines 142; the chip select signal lines 142 are connected in a one-to-one correspondence with the source driver 110; when the source driver 110 receives the corresponding chip select When the chip select signal of the signal line 142 is used, the data signal is read from the data transmission line 141.
  • each chip select signal line 142 controls the reading and writing of the signals of each source driver 110, so that at the same time, only one source driver 110 receives the data signal on the bus 140, and there will not be more than one at the same time.
  • the source driver 110 receives data signals on the bus 140 at the same time, that is, it does not occur that different source drivers 110 receive uncorresponding data signals. This is achieved by receiving data signals on the bus 140 through chip selection signal control. In one embodiment, there are two data transmission lines 141.
  • two data transmission lines 141 can perform data serial input and output, one data transmission line 141 inputs data signals, and the other data transmission line 141 outputs data signals, without affecting each other, and simultaneously, improving efficiency.
  • the panel driving circuit 100 further includes a control circuit board 160 and a flexible circuit board 150
  • the timing controller 130 is located on the control circuit board 160
  • the source driver 110 and the gate driver 120 are located on the flexible circuit board 150
  • the bus A part of the bus 140 connected to the timing controller 130 is on the control circuit board 160
  • the branch point generated by the bus 140 being respectively connected to the source driver 110 and the gate driver 120 is on the flexible circuit board 150.
  • the bus 140 is only connected to the timing controller 130 on the control circuit board 160, and is connected to the source driver 110 and the gate driver 120 on the flexible circuit board 150 respectively.
  • the wiring on the flexible circuit board 150 is convenient. The overall layout of the circuit board has little effect.
  • the panel driving circuit 100 further includes a memory 170 for storing data, and the memory 170 is connected to the timing controller 130.
  • the state where the source driver 110 needs to be set is stored in the memory 170, and the timing controller 130 reads the data of the memory 170 at power-on and writes the data to the source driver 110 to make the source
  • the working state of the driver 110 is matched with the panel.
  • the drive mode needs to be adjusted, only the data stored in the memory 170 needs to be modified.
  • a display device including a display panel 200; a panel driving circuit 100 that drives the display of the display panel 200;
  • the panel driving circuit 100 includes a control circuit board 160, a flexible circuit board 150, a plurality of source drivers 110 on the flexible circuit board 150, a gate driver 120 on the control circuit board 160, a timing controller 130, and a memory 170;
  • the source driver 110 drives the data lines of the display panel 200;
  • the gate driver 120 drives the scan lines of the display panel 200;
  • the timing controller 130 drives and controls the source driver 110 and the gate driver 120;
  • the memory 170 stores data and the timing controller 130 connection;
  • the timing controller 130 reads data signals and chip select signals from the memory 170; part of the bus 140 connected to the timing controller 130 is on the control circuit board 160, and the bus 140 is connected to the source driver 110 and the gate driver 120 respectively The bifurcation point is on the flexible circuit board 150;
  • the bus 140 includes: a data transmission line 141, and the timing controller 130 transmits data signals to the gate driver 120 and the source driver 110 through the data transmission line 141, respectively;
  • the timing controller 130 is connected to the source driver 110 through the chip select signal lines 142;
  • the chip selection signal line 142 is connected to the source driver 110 in a one-to-one correspondence; when the source driver 110 receives the chip selection signal corresponding to the chip selection signal line 142, the data signal is read from the data transmission line 141.
  • each source driver 110 and the gate driver 120 share the bus 140 to receive the signal sent by the timing controller 130, each A chip select signal line 142 controls the reading and writing of the signals of each source driver 110, so that at the same time, only one source driver 110 receives the data signal on the bus 140, and multiple source drivers 110 do not appear at the same time at the same time Receiving the data signal on the bus 140, that is, no different source driver 110 receives the uncorresponding data signal. It realizes that the data signal is received on the bus 140 through the chip selection signal control. In this way, the common bus 140 is used for signal transmission, which saves the pins of the chip, reduces the cost of packaging, and saves the layout of the printed circuit board (PCB). Space provides convenience.
  • PCB printed circuit board
  • a driving method of a display device including:
  • S41 Signal transmission step: The timing controller 130 transmits the data signal to the bus 140;
  • S42 Signal receiving step: the source driver 110 and the gate driver 120 receive data signals from the bus 140.
  • the bus 140 includes a data transmission line 141 and a chip select signal line 142;
  • the signal transmission step includes: the timing controller 130 transmits the data signal to the data transmission line 141, and transmits the chip selection signal to the chip selection signal line 142;
  • the signal receiving step includes the source driver 110 and the gate driver 120 receiving the data signal from the data transmission line 141 according to the chip selection signal.
  • the timing controller 130 performs signal transmission on the source driver 110 connected to one chip select signal line 142 through the data transmission line 141. Only one chip select signal has predetermined logic at the same time.
  • each chip select signal line 142 controls the reading and writing of the signals of each source driver 110, so that at the same time, only one source driver 110 receives the data signal on the bus 140, and there will not be more than one at the same time.
  • the source driver 110 receives data signals on the bus 140 at the same time, that is, it does not occur that different source drivers 110 receive uncorresponding data signals. This is achieved by receiving data signals on the bus 140 through chip selection signal control.
  • the timing controller 130 reads the data signal and the chip select signal from the memory 170.
  • the state where the source driver 110 needs to be set is stored in the memory 170, and the timing controller 130 reads the data of the memory 170 at power-on and writes the data to the source driver 110 to make the source
  • the working state of the driver 110 matches the need of the panel.
  • the drive mode needs to be adjusted, only the data stored in the memory 170 needs to be modified.
  • the data signal includes a first data signal and a second data signal
  • the signal transmission steps include: S51: the timing controller 130 sends the first data signal to the source driver 110 for decoding to generate a second data signal; S52: the source driver 110 transmits the second data signal to the bus 140;
  • the signal receiving step includes: S53: The gate driver 120 receives the second data signal from the bus 140.
  • the data signal sent by the timing controller 130 to the gate driver 120 can be decoded by the source driver 110, and then sent by the source driver 110 to the gate driver 120, which can reduce multiple gate drivers
  • the time delay caused by 120 and the source driver 110 cannot share the data transmission line 141 at the same time.
  • the panel of this application may be a TN panel (full name Twisted Nematic, namely twisted nematic panel), IPS panel (In-Plane Switching, plane switching), VA panel (Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology), of course , Can also be other types of panels, just apply.
  • TN panel full name Twisted Nematic, namely twisted nematic panel
  • IPS panel In-Plane Switching, plane switching
  • VA panel Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology

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Abstract

一种显示装置及其驱动方法，显示装置包括显示面板(200)和驱动显示面板(200)的面板驱动电路(100)；面板驱动电路(100)包括：源极驱动器(110)，驱动显示面板(200)的数据线；栅极驱动器(120)，驱动显示面板(200)的扫描线；时序控制器(130)，驱动控制源极驱动器(110)和栅极驱动器(120)；总线(140)，时序控制器(130)通过总线(140)分别连接源极驱动器(110)、栅极驱动器(120)；时序控制器(130)通过总线(140)将信号分别传输至源极驱动器(110)和栅极驱动器(120)。

Description

一种显示面板和显示装置
本申请要求于2018年12月13日提交中国专利局、申请号为CN201811522216.9、发明名称为“一种显示装置及其驱动方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板和显示装置。
背景技术
应当理解的是，这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着科技的发展和进步，平板显示器由于具备机身薄、省电和辐射低等热点而成为显示器的主流产品，得到了广泛应用。平板显示器包括薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)显示器等。其中，薄膜晶体管液晶显示器通过控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面，具有机身薄、省电、无辐射等众多优点。有机发光二极管显示器是利用有机电致发光二极管制成，具有自发光、响应时间短、清晰度与对比度高、可实现柔性显示与大面积全色显示等诸多优点。
显示面板中使用的各种材料增多，以及需要各种技术增多，造成了显示面板成本较高的问题。
技术解决方案
本申请的目的在于提供一种显示面板和显示装置，以降低显示装置的成本。
为实现上述目的，本申请提供了一种显示装置，包括显示面板、驱动所述显示面板显示的面板驱动电路；所述面板驱动电路包括驱动显示面板的数据线的源极驱动器、驱动显示面板的扫描线的栅极驱动器、驱动控制源极驱动器和栅极驱动器的时序控制器和总线，所述时序控制器通过所述总线分别连接所述源极驱动器和所述栅极驱动器；
所述时序控制器通过所述总线将信号分别传输至所述源极驱动器和栅极驱动器。
可选的，所述源级驱动器设置有多个；所述总线包括：
数据传输线，所述时序控制器通过所述数据传输线分别向所述栅极驱动器和所述源极驱动器传输数据信号；
多条片选信号线，所述时序控制器通过所述片选信号线与源极驱动器连接；所述片选信号线与所述源极驱动器一一对应连接；
当源极驱动器接收到对应片选信号线的片选信号时，从所述数据传输线读取数据信号。
可选的，所述数据传输线为两条。
可选的，所述面板驱动电路还包括控制电路板和柔性电路板，所述时序控制器位于控制电路板上，所述源极驱动器和栅极驱动器位于柔性电路板上，所述总线与所述时序控制器连接的部分总线在所述控制电路板上，所述总线分别与所述源极驱动器和栅极驱动器连接产生的分叉点在所述柔性电路板上。
可选的，所述面板驱动电路还包括储存数据的存储器，所述存储器与时序控制器连接。
本申请还公开了一种显示装置，包括显示面板、驱动所述显示面板显示的面板驱动电路；
所述面板驱动电路包括：控制电路板、柔性电路板、源极驱动器、栅极驱动器、时序控制器、存储器和总线；
源极驱动器，驱动显示面板的数据线，位于柔性电路板上；
栅极驱动器，驱动显示面板的扫描线，位于柔性电路板上；
时序控制器，驱动控制源极驱动器和栅极驱动器，位于控制电路板上；
存储器，储存数据，与时序控制器连接，在控制电路板上，所述时序控制器从存储器中读取数据信号和片选信号；
总线与所述时序控制器连接的部分总线在所述控制电路板上，总线分别与所述源极驱动器和栅极驱动器连接产生的分叉点在所述柔性电路板上；
所述总线包括：
数据传输线，所述时序控制器通过所述数据传输线分别向所述栅极驱动器和所述源极驱动器传输数据信号；
片选信号线，所述时序控制器通过所述片选信号线与源极驱动器连接；所述片选信号线与所述源极驱动器一一对应连接；
当源极驱动器接收到对应片选信号线的片选信号时，从所述数据传输线读取数据信 号。
本申请还公开了一种显示装置的驱动方法，所述显示装置包括：
显示面板；
面板驱动电路，驱动所述显示面板；
所述面板驱动电路包括：
源极驱动器，驱动所述显示面板的数据线；
栅极驱动器，驱动所述显示面板的扫描线；
时序控制器，驱动控制所述源极驱动器和栅极驱动器；
总线，传输信号；
所述时序控制器通过所述总线分别连接所述源极驱动器和所述栅极驱动器；
所述时序控制器通过所述总线将信号分别传输至所述源极驱动器和栅极驱动器。
所述驱动方法包括步骤：
信号传输步骤：所述时序控制器将数据信号传输到所述总线上；
信号接收步骤：所述源极驱动器和栅极驱动器从所述总线中接收所述数据信号。
可选的，所述源级驱动器设置有多个；
所述总线包括：
数据传输线，所述时序控制器通过所述数据传输线分别向所述栅极驱动器和所述源极驱动器传输数据信号；
多条片选信号线，所述时序控制器通过所述片选信号线与源极驱动器连接；所述片选信号线与所述源极驱动器一一对应连接；
当所述源极驱动器接收到对应所述片选信号线的片选信号时，从所述数据传输线读取数据信号。
可选的，，所述数据传输线为两条。
可选的，所述面板驱动电路还包括控制电路板和柔性电路板，所述时序控制器位于所述控制电路板上，所述源极驱动器和栅极驱动器位于所述柔性电路板上，所述总线与所述时序控制器连接的部分总线在所述控制电路板上，所述总线分别与所述源极驱动器和栅极驱动器连接产生的分叉点在所述柔性电路板上。
可选的，所述面板驱动电路还包括储存数据的存储器，所述存储器与所述时序控制器连接。
可选的，所述总线包括数据传输线和片选信号线；
所述信号传输步骤包括：所述时序控制器将数据信号传输到所述数据传输线上，将片选信号传输到所述片选信号线上；
所述信号接收步骤包括：所述源极驱动器和栅极驱动器根据所述片选信号从所述数据传输线中接收所述数据信号。
可选的，所述信号传输步骤中，所述时序控制器从存储器中读取所述数据信号和片选信号。
可选的，所述数据信号包括第一数据信号和第二数据信号；
所述信号传输步骤包括：所述时序控制器将第一数据信号发送到源极驱动器中解码，生成第二数据信号；源极驱动器将第二数据信号传输到所述总线上；
所述信号接收步骤包括：所述栅极驱动器从总线中接收所述第二数据信号。
可选的，所述第一数据信号包括源级驱动信号和栅极驱动信号，所述源级驱动器对所述栅极驱动信号解码，将解码后的栅极驱动信号发送到所述总线上。
相对于使用较多连线，使得各芯片引脚数量较多的方案；本申请通过源极驱动器和栅极驱动器共用总线接收时序控制器发出的信号，这样共用总线进行信号传输的方式，节约了芯片的管脚，降低了封装的成本，同时为印刷电路板(PCB)的布局节省了空间，提供了方便。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请其中一个实施例的显示装置的示意图；
图2是本申请其中一个实施例的显示装置的示意图；
图3是本申请其中一个实施例局部A的示意图；
图4是本申请其中一个实施例的驱动方法的步骤示意图；
图5是本申请其中一个实施例的驱动方法的步骤示意图。
本申请的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方 位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和较佳的实施例对本申请作进一步说明。
参考图1至图3所示，本申请在一实施例中公布了一种显示装置，包括：显示面板200；面板驱动电路100，驱动显示面板200显示；面板驱动电路100包括：源极驱动器110，驱动显示面板200的数据线；栅极驱动器120，驱动显示面板200的扫描线；时序控制器130，驱动控制源极驱动器110和栅极驱动器120；总线140，时序控制器130通过总线140分别连接源极驱动器110、栅极驱动器120；时序控制器130通过总线140将信号分别传输至源极驱动器110和栅极驱动器120。
本方案中，源极驱动器110和栅极驱动器120共用总线140接收时序控制器130发出的信号，这样共用总线140进行信号传输的方式，节约了芯片的管脚，降低了封装的成本，同时为印刷电路板(PCB)的布局节省了空间，提供了方便。
在一实施例中，源级驱动器110设置有多个；总线140包括：
数据传输线141，时序控制器130通过数据传输线141分别向栅极驱动器120和源极驱动器110传输数据信号；
多条片选信号线142，时序控制器130通过片选信号线142与源极驱动器110连接；片选信号线142与源极驱动器110一一对应连接；当源极驱动器110接收到对应片选信号线142的片选信号时，从数据传输线141读取数据信号。
本方案中，每一个片选信号线142控制每一个源极驱动器110的信号的读写，使得在同一时间，只有一个源极驱动器110接收总线140上的数据信号，不会出现同一时间多个源极驱动器110同时接收总线140上的数据信号，也就是不会出现不同的源极驱动器110接收到不对应的数据信号。实现在通过片选信号控制在总线140上接收数据信号。在一实施例中，数据传输线141为两条。
本方案中，两条数据传输线141可以进行数据串行输入输出，一条数据传输线141进行输入数据信号，另一条数据传输线141进行输出数据信号，互不影响，同时进行，提高效率。
在一实施例中，面板驱动电路100还包括控制电路板160和柔性电路板150，时序控制器130位于控制电路板160上，源极驱动器110和栅极驱动器120位于柔性电路板150上，总线140与时序控制器130连接的部分总线在控制电路板160上，总线140分别与源极驱动器110和栅极驱动器120连接产生的分叉点在柔性电路板150上。
本方案中，总线140在控制电路板160上只与时序控制器130相连，而到了柔性电路板150上分别与源极驱动器110和栅极驱动器120相连，在柔性电路板150上布线方便，对电路板的整体布局影响小。
在一实施例中，面板驱动电路100还包括储存数据的存储器170，存储器170与时序控制器130连接。
本方案中，源极驱动器110需要设定的状态被储存在存储器170中，在上电的时候时序控制器130读取存储器170的数据，并将数据写给源极驱动器110，来使得源极驱动器110工作状态与面板所需匹配。当需要调整驱动方式时，只需修改存储器170里存储的数据。
在一实施例中，参考图1至图3所示，公开了一种显示装置，包括显示面板200；驱动显示面板200显示的面板驱动电路100；
面板驱动电路100包括控制电路板160、柔性电路板150、位于柔性电路板150上的多个源极驱动器110、位于控制电路板160上的栅极驱动器120、时序控制器130和存储器170；
源极驱动器110驱动显示面板200的数据线；栅极驱动器120驱动显示面板200的扫描线；时序控制器130驱动控制源极驱动器110和栅极驱动器120；存储器170储存数据，与时序控制器130连接；
时序控制器130从存储器170中读取数据信号和片选信号；总线140与时序控制器130连接的部分总线在控制电路板160上，总线140分别与源极驱动器110和栅极驱动器120连接产生的分叉点在柔性电路板150上；
总线140包括：数据传输线141，时序控制器130通过数据传输线141分别向栅极驱动器120和源极驱动器110传输数据信号；
多条片选信号线142，时序控制器130通过片选信号线142与源极驱动器110连接；
片选信号线142与源极驱动器110一一对应连接；当源极驱动器110接收到对应片选信号线142的片选信号时，从数据传输线141读取数据信号。
本方案中，如图2和图3所述，包括3个源级驱动器，对应有三条片选信号线；源极驱动器110和栅极驱动器120共用总线140接收时序控制器130发出的信号，每一个片选信号线142控制每一个源极驱动器110的信号的读写，使得在同一时间，只有一个源极驱动器110接收总线140上的数据信号，不会出现同一时间多个源极驱动器110同时接收总线140上的数据信号，也就是不会出现不同的源极驱动器110接收到不对应的数据信号。实现在通过片选信号控制在总线140上接收数据信号，这样共用总线140进行信号传输的方式，节约了芯片的管脚，降低了封装的成本，同时为印刷电路板(PCB)的布局节省了空间，提供了方便。
在一实施例中，参考图4至图5所示，公开了一种显示装置的驱动方法，包括：
S41:信号传输步骤：时序控制器130将数据信号传输到总线140上；
S42:信号接收步骤：源极驱动器110和栅极驱动器120从总线140中接收数据信号。
本方案中，所有的数据信号都通过总线140传输到各个源极驱动器和栅极驱动器120，只需要一根总线140即可将时序控制器130、栅极驱动器120和源极驱动器110连接起来，节省了芯片的引脚，进而节省了芯片的封装成本。
在一实施例中，总线140包括数据传输线141和片选信号线142；
信号传输步骤包括：时序控制器130将数据信号传输到数据传输线141上，将片选信号传输到片选信号线142上；
信号接收步骤包括：源极驱动器110和栅极驱动器120根据片选信号从数据传输线141中接收所述数据信号。
信号接收步骤中，每一条片选信号线142上的片选信号出现预定逻辑时，时序控制器130对与一个片选信号线142相连的源极驱动器110通过数据传输线141进行信号传输，所有的片选信号同一时刻仅有一个片选信号出现预定逻辑。
本方案中，每一个片选信号线142控制每一个源极驱动器110的信号的读写，使得在同一时间，只有一个源极驱动器110接收总线140上的数据信号，不会出现同一时间 多个源极驱动器110同时接收总线140上的数据信号，也就是不会出现不同的源极驱动器110接收到不对应的数据信号。实现在通过片选信号控制在总线140上接收数据信号。
在一实施例中，信号传输步骤中，时序控制器130从存储器170中读取数据信号和片选信号。
本方案中，源极驱动器110需要设定的状态被储存在存储器170中，在上电的时候时序控制器130读取存储器170的数据，并将数据写给源极驱动器110，来使得源极驱动器110工作状态与面板所需匹配。当需要调整驱动方式时，只需修改存储器170里存储的数据。
在一实施例中，数据信号包括第一数据信号和第二数据信号；
信号传输步骤包括：S51:时序控制器130将第一数据信号发送到源极驱动器110中解码，生成第二数据信号；S52:源极驱动器110将第二数据信号传输到所述总线140上；
信号接收步骤包括：S53:栅极驱动器120从总线140中接收第二数据信号。
本方案中，由时序控制器130发送给栅极驱动器120的数据信号可以通过源极驱动器110解码出数据信号，然后由源极驱动器110发送给栅极驱动器120，这样可以减少多个栅极驱动器120和源极驱动器110不能在同一时间需要共用数据传输线141导致的时间延迟。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
本申请的面板可以是TN面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS面板(In-PlaneSwitching，平面转换)、VA面板(Multi-domain Vertical Alignment，多象限垂直配向技术)，当然，也可以是其他类型的面板，适用即可。
以上内容是结合具体的优选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (17)

  1. 一种显示装置，包括：
    显示面板；
    面板驱动电路，驱动所述显示面板；
    所述面板驱动电路包括：
    源极驱动器，驱动所述显示面板的数据线；
    栅极驱动器，驱动所述显示面板的扫描线；
    时序控制器，驱动控制所述源极驱动器和栅极驱动器；
    总线，传输信号；
    所述时序控制器通过所述总线分别连接所述源极驱动器和所述栅极驱动器；
    所述时序控制器通过所述总线将信号分别传输至所述源极驱动器和栅极驱动器。
  2. 如权利要求1所述的一种显示装置，其中，所述源级驱动器设置有多个；
    所述总线包括：
    数据传输线，所述时序控制器通过所述数据传输线分别向所述栅极驱动器和所述源极驱动器传输数据信号；
    多条片选信号线，所述时序控制器通过所述片选信号线与源极驱动器连接；所述片选信号线与所述源极驱动器一一对应连接；
    当所述源极驱动器接收到对应所述片选信号线的片选信号时，从所述数据传输线读取数据信号。
  3. 如权利要求2所述的一种显示装置，其中，所述数据传输线为两条。
  4. 如权利要求1所述的一种显示装置，其中，所述面板驱动电路还包括控制电路板和柔性电路板，所述时序控制器位于所述控制电路板上，所述源极驱动器和栅极驱动器位于所述柔性电路板上，所述总线与所述时序控制器连接的部分总线在所述控制电路板上，所述总线分别与所述源极驱动器和栅极驱动器连接产生的分叉点在所述柔性电路板上。
  5. 如权利要求1所述的一种显示装置，其中，所述面板驱动电路还包括储存数据的存储器，所述存储器与所述时序控制器连接。
  6. 一种显示装置，包括：
    显示面板；
    面板驱动电路，驱动所述显示面板显示；
    所述面板驱动电路包括：
    控制电路板；
    柔性电路板；
    多个源极驱动器，驱动所述显示面板的数据线，位于所述柔性电路板上；
    栅极驱动器，驱动所述显示面板的扫描线，位于所述柔性电路板上；
    时序控制器，驱动控制所述源极驱动器和栅极驱动器，位于所述控制电路板上；
    存储器，储存数据，与所述时序控制器连接，在所述控制电路板上，所述时序控制器从所述存储器中读取数据信号和片选信号；
    总线与所述时序控制器连接的部分总线在所述控制电路板上，总线分别与所述源极驱动器和栅极驱动器连接产生的分叉点在所述柔性电路板上；
    所述总线包括：
    数据传输线，所述时序控制器通过所述数据传输线分别向所述栅极驱动器和所述源极驱动器传输数据信号；
    多条片选信号线，所述时序控制器通过所述片选信号线与源极驱动器连接；所述片选信号线与所述源极驱动器一一对应连接；
    当所述源极驱动器接收到对应所述片选信号线的片选信号时，从所述数据传输线读取数据信号。
  7. 一种显示装置的驱动方法，所述显示装置包括：
    显示面板；
    面板驱动电路，驱动所述显示面板；
    所述面板驱动电路包括：
    源极驱动器，驱动所述显示面板的数据线；
    栅极驱动器，驱动所述显示面板的扫描线；
    时序控制器，驱动控制所述源极驱动器和栅极驱动器；
    总线，传输信号；
    所述时序控制器通过所述总线分别连接所述源极驱动器和所述栅极驱动器；
    所述时序控制器通过所述总线将信号分别传输至所述源极驱动器和栅极驱动器。
    所述驱动方法包括步骤：
    信号传输步骤：所述时序控制器将数据信号传输到所述总线上；
    信号接收步骤：所述源极驱动器和栅极驱动器从所述总线中接收所述数据信号。
  8. 如权利要求7所述的一种显示装置的驱动方法，其中，
    所述数据信号包括第一数据信号和第二数据信号；
    所述信号传输步骤包括：所述时序控制器将第一数据信号发送到源极驱动器中解码，生成第二数据信号；源极驱动器将第二数据信号传输到所述总线上；
    所述信号接收步骤包括：所述栅极驱动器从总线中接收所述第二数据信号。
  9. 如权利要求8所述的一种显示装置的驱动方法，其中，所述第一数据信号包括源级驱动信号和栅极驱动信号，所述源级驱动器对所述栅极驱动信号解码，将解码后的栅极驱动信号发送到所述总线上。
  10. 如权利要求7所述的一种显示装置的驱动方法，其中，所述源级驱动器设置有多个；
    所述总线包括：
    数据传输线，所述时序控制器通过所述数据传输线分别向所述栅极驱动器和所述源极驱动器传输数据信号；
    多条片选信号线，所述时序控制器通过所述片选信号线与源极驱动器连接；所述片选信号线与所述源极驱动器一一对应连接；
    当所述源极驱动器接收到对应所述片选信号线的片选信号时，从所述数据传输线读取数据信号。
  11. 如权利要求10所述的一种显示装置的驱动方法，其中，所述数据传输线为两条。
  12. 如权利要求7所述的一种显示装置的驱动方法，其中，所述面板驱动电路还包括控制电路板和柔性电路板，所述时序控制器位于所述控制电路板上，所述源极驱动器和栅极驱动器位于所述柔性电路板上，所述总线与所述时序控制器连接的部分总线在所述控制电路板上，所述总线分别与所述源极驱动器和栅极驱动器连接产生的分叉点在所述柔性电路板上。
  13. 如权利要求7所述的一种显示装置的驱动方法，其中，所述面板驱动电路还包括储存数据的存储器，所述存储器与所述时序控制器连接。
  14. 如权利要求7所述的一种显示装置的驱动方法，其中，所述总线包括数据传输线和片选信号线；
    所述信号传输步骤包括：所述时序控制器将数据信号传输到所述数据传输线上，将片选信号传输到所述片选信号线上；
    所述信号接收步骤包括：所述源极驱动器和栅极驱动器根据所述片选信号从所述数据传输线中接收所述数据信号。
  15. 如权利要求14所述的一种显示装置的驱动方法，其中，
    所述信号传输步骤中，所述时序控制器从存储器中读取所述数据信号和片选信号。
  16. 如权利要求10所述的一种显示装置的驱动方法，其中，
    所述数据信号包括第一数据信号和第二数据信号；
    所述信号传输步骤包括：所述时序控制器将第一数据信号发送到源极驱动器中解码，生成第二数据信号；源极驱动器将第二数据信号传输到所述总线上；
    所述信号接收步骤包括：所述栅极驱动器从总线中接收所述第二数据信号。
  17. 如权利要求16所述的一种显示装置的驱动方法，其中，所述第一数据信号包括源级驱动信号和栅极驱动信号，所述源级驱动器对所述栅极驱动信号解码，将解码后的栅极驱动信号发送到所述总线上。
PCT/CN2018/122224 2018-12-13 2018-12-20 一种显示面板和显示装置 Ceased WO2020118748A1 (zh)

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