WO2020114127A1 - 低通匹配式大动态常数相位的数控衰减电路 - Google Patents

低通匹配式大动态常数相位的数控衰减电路 Download PDF

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Publication number
WO2020114127A1
WO2020114127A1 PCT/CN2019/112619 CN2019112619W WO2020114127A1 WO 2020114127 A1 WO2020114127 A1 WO 2020114127A1 CN 2019112619 W CN2019112619 W CN 2019112619W WO 2020114127 A1 WO2020114127 A1 WO 2020114127A1
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series
attenuation
transistor
low
node
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PCT/CN2019/112619
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English (en)
French (fr)
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盖川
李垚
夏冬
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南京米乐为微电子科技有限公司
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Publication of WO2020114127A1 publication Critical patent/WO2020114127A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/24—Frequency-independent attenuators
    • H03H11/245—Frequency-independent attenuators using field-effect transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/28—Impedance matching networks

Definitions

  • the invention relates to the technical field of variable attenuation circuits, in particular to a low-pass matching type digitally controlled attenuation circuit with large dynamic constant phase.
  • Variable attenuation circuits are widely used in radar signal simulators, signal generators, automatic gain controllers, phased array systems, electronic countermeasure systems, and communication systems to achieve control of signal amplitude.
  • the variable attenuation circuit has the disadvantages of a large phase difference between the attenuation states and low attenuation accuracy in a large dynamic attenuation range, which limits the application of the variable attenuation circuit in the current system, or increases the complexity of the application system.
  • Attenuation circuits with consistent phase shift of each attenuation state, attenuation accuracy in a large dynamic range, high consistency, and temperature stability enable the application system to save calibration work and reduce the complexity of the application system.
  • the technical problem to be solved by the present invention is to provide a low-pass matching type large dynamic constant phase numerical control attenuation circuit, which can realize ultra-low additional phase shift and excellent attenuation under the application requirements of ultra-wideband and high dynamic range Precision.
  • the present invention provides a low-pass matching type large-dynamic constant-phase numerical control attenuation circuit, including: an input node and an output node, a reference path and an attenuation path are connected between the input node and the output node, and the input node receives To attenuate the signal, the output node outputs the attenuated signal.
  • the reference path includes a first series transistor, several parallel transistors, and several series reactance elements; the first parallel transistor is connected to the first series transistor, and several parallel transistors are connected in series by series reactance; the first control voltage is applied to the first A bias node of a series transistor, the second control voltage is applied to the bias nodes of all parallel transistors in the reference path.
  • the attenuation path includes a second series transistor, several parallel transistors, several series reactance elements and an attenuation network;
  • the second series transistor is connected to the input node through a reactance element, the second parallel transistor is connected to the second series transistor, and several parallel
  • the series reactance elements are connected in series between the transistors, and the attenuation network is set at the symmetric center of several cascade connected parallel transistors and series reactance elements;
  • the third control voltage is applied to the bias node of the second series transistor, and the fourth control voltage is applied At the bias node of all several parallel transistors in the attenuation path.
  • the channel width of the first series transistor in the reference path is larger than the channel width of the second series transistor in the attenuation path.
  • a reactive element is connected in series between the pre-stage circuit and the circuit input node, and a reactive element is connected in series between the circuit output node and the input port of the post-stage circuit to enhance the matching characteristics of the circuit.
  • several series reactance elements use inductive devices or high characteristic impedance transmission lines.
  • the attenuation network is implemented by an improved T-type resistance network, and a reactive element is connected in series between the common node of the T-type network and the grounding resistance, and the reactive element is used to adjust the high-frequency attenuation accuracy.
  • the attenuation network is implemented by an improved ⁇ -type resistance network, and a reactive element is connected in series between the output node of the ⁇ -type network and the grounding resistance, and the reactive element is used to adjust the high-frequency attenuation accuracy.
  • a circuit architecture that switches the reference path and the attenuation path can achieve a constant phase characteristic while satisfying a high dynamic attenuation range;
  • the improved T-type or ⁇ -type resistance network can further improve the attenuation accuracy.
  • FIG. 1 is a schematic diagram of a circuit structure of the present invention.
  • FIG. 2 is a schematic diagram of the improved T-type and improved ⁇ -type resistance network of the present invention.
  • FIG. 3 is a schematic diagram of the circuit principle of an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of an equivalent circuit principle of an attenuation circuit in a reference state according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of an equivalent circuit principle of an attenuation circuit in an attenuation state according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of simulation results of insertion loss, attenuation characteristics, and additional phase shift according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of simulation results of input return loss in a reference state and an attenuation state according to an embodiment of the present invention.
  • the low-pass matching type large dynamic constant phase numerical control attenuation circuit can realize a large attenuation dynamic range on the premise of low insertion loss and low additional phase shift.
  • the numerical control attenuation circuit includes an RF input node Ie and an RF output node Oe, and this embodiment adopts a symmetric structure with respect to the input and output nodes. Both the input node Ie and the output node Oe are connected to the reference path Pref and the attenuation path Patt.
  • the attenuation circuit contains switching elements for switching the signal to the reference path or the attenuation path. The lower the reference path loss, the better, but due to the limited quality factor of the device, insertion loss is inevitable. Therefore, the actual attenuation of the attenuation circuit is the difference between the loss of the signal through the reference path Pref and the signal through the attenuation path Patt.
  • the low-pass matching type large-dynamic constant-phase numerical control attenuation circuit includes: an input node and an output node, a reference path and an attenuation path are connected between the input node and the output node, the input node receives the signal to be attenuated, and the output node outputs the attenuation signal.
  • the reference path includes a first series transistor, several parallel transistors, and several series reactance elements; the first parallel transistor is connected to the first series transistor, and the several parallel transistors are connected in series by series reactance; the first control voltage is applied to the first series transistor , The second control voltage is applied to the bias nodes of all several parallel transistors in the reference path.
  • the attenuation path includes a second series transistor, several parallel transistors, several series reactance elements, and an attenuation network; the second series transistor is connected to the input node through a reactance element, and the second parallel transistor is connected to the second series transistor , Several series-connected transistors are connected in series by series reactance elements, and the attenuation network is set at the symmetrical center position of several series-connected parallel-connected transistors and series reactance elements; the third control voltage is applied to the bias node of the second series transistor, and the fourth The control voltage is applied to the bias node of all several parallel transistors in the attenuation path.
  • the attenuation network is implemented with an improved T-type resistance network.
  • a reactive element is connected in series between the common node of the T-type network and the grounding resistance. The reactive element is used to adjust the high-frequency attenuation accuracy.
  • the attenuation network is implemented with an improved ⁇ -type resistance network.
  • a reactive element is connected in series between the output node of the ⁇ -type network and the grounding resistance. The reactive element is used to adjust the high-frequency attenuation accuracy.
  • the attenuation circuit includes a double-pole double-throw (DPDT) switching structure.
  • the double pole double throw structure consists of two single pole double throw (SPDT) structures at the input and output.
  • the switch structure is composed of series transistors and several transistors in parallel; in this embodiment, one transistor in series and one transistor in parallel are selected for verification, that is, the input pole single-pole double-throw structure includes the first series transistor T11 and the first in the reference path Pref
  • the parallel transistor T12 also includes a second series transistor T21 and a second parallel transistor T22 in the attenuation path Patt.
  • the single pole double throw structure at the output includes the first series transistor T11' and the first parallel transistor T12' in the reference path Pref, and the second series transistor T21' and the second parallel transistor T22' in the attenuation path Patt.
  • the first series transistor T11 and the first parallel transistor T12 are connected in cascade, and the first parallel transistor T12 is grounded.
  • the gates of the first series transistor T11 and the first parallel transistor T12 are respectively connected to bias nodes through resistors R11 and R12, and the control voltages at the bias nodes of T11 and T12 are V1 and V2, respectively.
  • the first series transistor T11' is cascade-connected with the first parallel transistor T12', and the first parallel transistor T12' is grounded.
  • the gates of the first series transistor T11' and the first parallel transistor T12' are connected to bias nodes through resistors R11' and R12', respectively, and the control voltages at the bias nodes of T11' and T12' are V1 and V2, respectively.
  • R11 and R12 select 2.5k resistors to reduce RF signal leakage and maintain the working speed of the attenuation circuit.
  • the channel width of the first series transistor is moderately selected. On the one hand, a larger channel width can reduce the on-resistance of the transistor and reduce the insertion loss of the attenuation circuit; on the other hand, an excessively large channel width will increase the transistor If the switch-off capacitor is too large, the switch-off characteristic of the reference path will be deteriorated, resulting in the mutual influence of the reference path and the attenuation path signal.
  • the series inductance L11+L11' is connected in cascade between the first parallel transistors, the first parallel transistor is equivalent to a small capacitor when the signal passes through the reference path, and the inductance L11+L11' together with T12 and T12' form a third-order low-pass network .
  • the second series transistor T21 and the second parallel transistor T22 are connected in cascade, and the second parallel transistor T22 is grounded.
  • the gates of the second series transistor T21 and the second parallel transistor T22 are respectively connected to bias nodes through resistors R21 and R22, and the control voltages at the bias nodes of T21 and T22 are V2 and V1, respectively.
  • the second series transistor T21' is cascade-connected with the second parallel transistor T22', and the second parallel transistor T22' is grounded.
  • the gates of the second series transistor T21' and the second parallel transistor T22' are respectively connected to the bias nodes through resistors R21' and R22', and the control voltages at the bias nodes of T21' and T22' are V2 and V1, respectively.
  • the first series transistor and the second parallel transistor apply the same bias voltage V1 at the bias node, and the second series transistor and the first parallel transistor apply the same bias voltage V2 at the bias node.
  • the channel width of the second series transistor is generally smaller than the channel width of the first series transistor, which can increase the isolation of the two paths.
  • the attenuation network adopts an improved T-shaped structure, which is composed of resistors R1, R2, R3 and a high-impedance transmission line TL0.
  • the resistance elements R1, R2, R3 are used to attenuate the signal
  • the high resistance transmission line TL0 is used to improve the attenuation accuracy of the high frequency band
  • the improved T-type attenuation network composed of them has little effect on the phase characteristics of the attenuation path.
  • a transmission line TL21 is cascaded between the input node Ie and the second series transistor T11 as a series reactance element.
  • a section of transmission line TL22 is cascaded between the second parallel transistor T22 and the attenuation network as a series reactance element.
  • a section of transmission line TL21' is cascaded between the output node Oe and the second series transistor T11' as a series reactance element.
  • a section of transmission line TL22' is cascaded between the second parallel transistor T22' and the attenuation network as a series reactance element.
  • the two third-order low-pass networks on the attenuation path balance the phase characteristics of the path while achieving broadband matching, so that the phase of the attenuation path is consistent with the reference path.
  • Table 1 is the channel width of the switching transistor used in this embodiment and the equivalent circuit parameters in the on/off state.
  • Table 1 The channel width of the switching transistor and the equivalent circuit parameters in the on/off state
  • a reactive element is connected in series between the output node Si and the input node Ie of the preceding stage, and the output node Oe and the output node of the latter stage.
  • a section of high-impedance transmission lines TLi and TLo is used for further circuit matching To reduce the standing wave ratio of the input and output ports.
  • Table 2 shows the circuit parameter values of other circuit elements used in this embodiment.
  • the first series transistor T11 and the first parallel transistor T12 are respectively equivalent to the series resistance R11 and the parallel capacitor C12, and the high-impedance transmission lines TLi and TLo of the input and output can be approximately equivalent to the series Inductance Li and Lo; and for the attenuation path, the second series transistor T21 and the second parallel transistor T22 are equivalent to a small series capacitance and a small parallel resistance, respectively, so the attenuation circuit has little effect; the attenuation circuit is equivalent to 5th order low-pass filter structure, as shown in Fig.
  • the second series transistor T21 and the second parallel transistor T22 are equivalent to a series resistance R21 and a parallel capacitor C22, respectively.
  • the resistance transmission lines TLi and TLo can be approximately equivalent to the series inductances Li and Lo; and for the reference circuit, the first series transistor T11 and the first parallel transistor T12 are equivalent to a small series capacitance and a small parallel resistance, respectively, so the reference circuit There is almost no effect, and other high-impedance transmission lines are still approximately equivalent to inductive components.
  • the first series transistor T11' and the first parallel transistor T12' are respectively equivalent to the series resistance R11' and the parallel capacitor C12', and the input and output high-impedance transmission lines TLi and TLo can be approximately equivalent to Series inductances Li and Lo; and for the attenuation path, the second series transistor T21' and the second parallel transistor T22' are equivalent to small series capacitance and small parallel resistance, respectively, so the attenuation circuit has little effect; at this time, the attenuation circuit Equivalent to the 5th-order low-pass filter structure, as shown in Figure 4; when the switch structure is switched to the attenuation path, the second series transistor T21' and the second parallel transistor T22' are equivalent to a series resistance R21' and a parallel capacitor, respectively C22', the input and output high-impedance transmission lines TLi and TLo can be approximately equivalent to the series inductances Li and Lo; and for the reference path, the first series transistor T11' and the
  • FIG. 6 is a schematic diagram of simulation results of attenuation accuracy, attenuation additional phase shift, and insertion loss of an embodiment.
  • an ultra-low attenuation additional phase shift of ⁇ 2° can be achieved;
  • the insertion loss of the attenuation circuit is less than 1.4dB in the frequency range.
  • FIG. 7 shows the standing wave characteristics in the reference state and the attenuation state of the embodiment. In the frequency range of DC-20 GHz, a good match better than -10 dB is achieved.

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Abstract

本发明公开了一种低通匹配式大动态常数相位的数控衰减电路，包括：输入节点和输出节点，输入节点和输出节点之间连接有参考路径和衰减路径，输入节点接收待衰减信号，输出节点输出衰减信号。本发明的有益效果为：（1）采用切换参考路径和衰减路径的电路架构，可以在满足高动态衰减范围的同时，实现常数相位特性；（2）非对称开关结构，串联电抗元件，构成低通匹配结构，可以在在较宽的频率范围内实现大动态高精度低插损低附加相移的特性；（3）采用改进的T型或者π型电阻网络，能够进一步提高衰减精度。

Description

低通匹配式大动态常数相位的数控衰减电路 技术领域
本发明涉及可变衰减电路技术领域，尤其是一种低通匹配式大动态常数相位的数控衰减电路。
 背景技术
可变衰减电路广泛应用于雷达信号模拟器、信号发生器、自动增益控制器、相控阵系统、电子对抗系统和通信系统等，实现对信号幅度的控制。当前，可变衰减电路存在个衰减态之间相位差较大和大动态衰减范围时衰减精度低的不足，限制了可变衰减电路在现今系统中应用，或是增加了应用系统的复杂度。各衰减态相移一致、大动态范围内的衰减精度、高度一致性和温度稳定性的衰减电路能使应用系统省去校准工作，降低应用系统复杂度。
 技术问题
本发明所要解决的技术问题在于，提供一种低通匹配式大动态常数相位的数控衰减电路，可以在满足超宽带带和高动态范围的应用需求下，实现超低附加相移以及优异的衰减精度。
 技术解决方案
为解决上述技术问题，本发明提供一种低通匹配式大动态常数相位的数控衰减电路，包括：输入节点和输出节点，输入节点和输出节点之间连接有参考路径和衰减路径，输入节点接收待衰减信号，输出节点输出衰减信号。
优选的，参考路径包括第一串联晶体管、若干并联晶体管和若干串联电抗元件；第一并联晶体管与第一串联晶体管连接，若干并联晶体管之间通过串联电抗逐级连接；第一控制电压施加于第一串联晶体管的偏置节点，第二控制电压施加于参考路径中所有若干并联晶体管的偏置节点上。
优选的，衰减路径包括第二串联晶体管、若干并联晶体管、若干串联电抗元件和衰减网络；第二串联晶体管与输入节点之间通过电抗元件连接，第二并联晶体管与第二串联晶体管连接，若干并联晶体管之间采用串联电抗元件逐级连接，衰减网络设置于若干级联连接并联晶体管和串联电抗元件的对称中心位置；第三控制电压施加于第二串联晶体管的偏置节点，第四控制电压施加于衰减路径中所有若干并联晶体管的偏置节点上。
优选的，参考路径中第一串联晶体管的沟道宽度大于衰减路径中第二串联晶体管的沟道宽度。
优选的，在前级电路与电路输入节点间串联电抗元件，在电路输出节点和后级电路输入端口之间串联电抗元件，增强电路的匹配特性。
优选的，若干串联电抗元件采用电感器件或者高特征阻抗的传输线。
优选的，衰减网络采用改进的T型电阻网络实现，在T型网络的公共节点与接地电阻之间串联电抗性元件，电抗性元件用于调节高频衰减精度。
优选的，衰减网络采用改进的π型电阻网络实现，在π型网络的输出节点与接地电阻之间串联电抗性元件，电抗性元件用于调节高频衰减精度。
 有益效果
本发明的有益效果为：（1）采用切换参考路径和衰减路径的电路架构，可以在满足高动态衰减范围的同时，实现常数相位特性；（2）非对称开关结构，串联电抗元件，构成低通匹配结构，可以在在较宽的频率范围内实现大动态高精度低插损低附加相移的特性；（3）采用改进的T型或者π型电阻网络，能够进一步提高衰减精度。
 附图说明
[0006] 图1为本发明的电路结构示意图。
图2为本发明改进T型和改进π型电阻网络示意图。
图3为本发明的实施例电路原理示意图。
图4为本发明实施例参考态下的衰减电路等效电路原理示意图。
图5为本发明实施例衰减态下的衰减电路等效电路原理示意图。
图6为本发明实施例插入损耗、衰减特性和附加相移的仿真结果示意图。
图7为本发明实施例参考态和衰减态下输入回波损耗的仿真结果示意图。
 本发明的实施方式
本发明所提供的低通匹配式大动态常数相位的数控衰减电路，可以在低插入损耗和低附加相移的前提下，实现大的衰减动态范围。如图1所示，数控衰减电路包含RF输入节点Ie和RF输出节点Oe，本实施例采用关于输入输出节点对称的结构。输入节点Ie和输出节点Oe均与参考路径Pref和衰减路径Patt连接。衰减电路包含开关元件，用于切换信号到参考路径或者衰减路径。参考路径损耗越低越好，但由于器件有限的品质因数，插损不可避免，因此，实际的衰减电路衰减量为信号通过参考路径Pref和信号通过衰减路径Patt的损耗差值。
低通匹配式大动态常数相位的数控衰减电路，包括：输入节点和输出节点，输入节点和输出节点之间连接有参考路径和衰减路径，输入节点接收待衰减信号，输出节点输出衰减信号。
参考路径包括第一串联晶体管、若干并联晶体管和若干串联电抗元件；第一并联晶体管与第一串联晶体管连接，若干并联晶体管之间通过串联电抗逐级连接；第一控制电压施加于第一串联晶体管的偏置节点，第二控制电压施加于参考路径中所有若干并联晶体管的偏置节点上。
如图2所示，衰减路径包括第二串联晶体管、若干并联晶体管、若干串联电抗元件和衰减网络；第二串联晶体管与输入节点之间通过电抗元件连接，第二并联晶体管与第二串联晶体管连接，若干并联晶体管之间采用串联电抗元件逐级连接，衰减网络设置于若干级联连接并联晶体管和串联电抗元件的对称中心位置；第三控制电压施加于第二串联晶体管的偏置节点，第四控制电压施加于衰减路径中所有若干并联晶体管的偏置节点上。
衰减网络采用改进的T型电阻网络实现，在T型网络的公共节点与接地电阻之间串联电抗性元件，电抗性元件用于调节高频衰减精度。衰减网络采用改进的π型电阻网络实现，在π型网络的输出节点与接地电阻之间串联电抗性元件，电抗性元件用于调节高频衰减精度。
如图3所示，衰减电路电路包含一个双刀双掷（DPDT）切换结构。该双刀双掷结构由输入端和输出端两个单刀双掷（SPDT）结构组成。开关结构由串联晶体管和并联若干晶体管组成；在本实施例中，选取串联1支晶体管，并联1支晶体管进行验证，即输入端单刀双掷结构包含参考路径Pref中第一串联晶体管T11和第一并联晶体管T12，同时包含衰减路径Patt中第二串联晶体管T21和第二并联晶体管T22。输出端单刀双掷结构包含参考路径Pref中第一串联晶体管T11＇和第一并联晶体管T12＇，同时包含衰减路径Patt中第二串联晶体管T21＇和第二并联晶体管T22＇。
参考路径Pref中，第一串联晶体管T11与第一并联晶体管T12级联连接，第一并联晶体管T12接地。第一串联晶体管T11和第一并联晶体管T12的栅极各自通过电阻R11和R12连接偏置节点，T11和T12的偏置节点处控制电压分别为V1与V2。第一串联晶体管T11＇与第一并联晶体管T12＇级联连接，第一并联晶体管T12＇接地。第一串联晶体管T11＇和第一并联晶体管T12＇的栅极各自通过电阻R11＇和R12＇连接偏置节点， T11＇和T12＇的偏置节点处控制电压分别为V1与V2。其中，R11和R12选取2.5k电阻，以减小射频信号泄露并保持衰减电路的工作速度。第一串联晶体管的沟道宽度选择适中，一方面较大的沟道宽度可以减小晶体管的开启电阻，实现降低衰减电路插入损耗的目的；另一方面，过大的沟道宽度将增大晶体管的关闭电容，过大的关闭电容会恶化参考路径的开关特性，从而造成参考路径和衰减路径信号的互相影响。第一并联晶体管之间串联电感L11+L11＇进行级联连接，第一并联晶体管在信号通过参考路径时等效为小电容，电感L11+L11＇连同T12、T12＇共同组成三阶低通网络。
衰减路径Patt中，第二串联晶体管T21与第二并联晶体管T22级联连接，第二并联晶体管T22接地。第二串联晶体管T21和第二并联晶体管T22的栅极各自通过电阻R21和R22连接偏置节点，T21和T22的偏置节点处控制电压分别为V2与V1。第二串联晶体管T21＇与第二并联晶体管T22＇级联连接，第二并联晶体管T22＇接地。第二串联晶体管T21＇和第二并联晶体管T22＇的栅极各自通过电阻R21＇和R22＇连接偏置节点，T21＇和T22＇的偏置节点处控制电压分别为V2与V1。第一串联晶体管和第二并联晶体管在偏置节点处施加相同的偏置电压V1，第二串联晶体管和第一并联晶体管在偏置节点处施加相同的偏置电压V2。第二串联晶体管的沟道宽度选择一般小于第一串联晶体管的沟道宽度，这样可以增加两个路径的隔离度。衰减网络采用改进的T型结构，由电阻R1、R2、R3以及高阻传输线TL0构成。其中，电阻元件R1、R2、R3用于对信号进行衰减，高阻传输线TL0用于改进高频段的衰减精度，由它们组成的改进的T型衰减网络对衰减路径的相位特性影响较小。输入节点Ie与第二串联晶体管T11之间级联一段传输线TL21，作为串联电抗元件。第二并联晶体管T22与衰减网络之间级联一段传输线TL22，作为串联电抗元件。输出节点Oe与第二串联晶体管T11＇之间级联一段传输线TL21＇，作为串联电抗元件。第二并联晶体管T22＇与衰减网络之间级联一段传输线TL22＇，作为串联电抗元件。衰减路径上的两个三阶低通网络，在实现宽带匹配的同时，平衡路径的相位特性，使得衰减路径与参考路径的相位一致。表1为本实施例中所采用的开关晶体管的沟道宽度以及开/关状态下等效电路参数。
表1   开关晶体管的沟道宽度以及开/关状态下等效电路参数
  T11 T12 T12＇ T11＇ T21 T22 T22＇ T21＇
沟道宽度 300um 100um 100um 300um 100um 200um 200um 100um
开启等效电阻 4Ω 13Ω 13Ω 5Ω 13Ω 7Ω 7Ω 13Ω
关闭等效电容 0.1pF 0.04pF 0.04pF 0.1pF 0.04pF 0.06pF 0.06pF 0.04pF
进一步地，在前级输出节点Si与输入节点Ie、后级输入节点So与输出节点Oe之间，串联一电抗元件，本实施例中采用了一段高阻传输线TLi和TLo，用于进一步电路匹配，降低输入输出端口的驻波比。表2为本实施例中所采用的其它电路元件的电路参数值。
表2   其它电路元件的电路参数值
传输线 TLi TL21 TL22 TL22＇ TL21＇ TLo TL0
特征阻抗 90Ω 90Ω 90Ω 90Ω 90Ω 90Ω 90Ω
电长度@10GHz 13° 7° 2.9° 2.9° 7° 13° 5°
电感元件 L11 L11＇          
电感值 0.13nH 0.13nH          
此时，当开关结构切换到参考路径时，第一串联晶体管T11和第一并联晶体管T12分别等效为串联电阻R11和并联电容C12，输入输出的高阻传输线TLi和TLo可以近似等效与串联电感Li和Lo；而对于衰减路径而言，第二串联晶体管T21和第二并联晶体管T22分别等效为串联小电容和并联小电阻，因此衰减路电路几乎没有影响；此时衰减电路等效于5阶低通滤波器结构，如图4所示；当开关结构切换到衰减路径时，第二串联晶体管T21和第二并联晶体管T22分别等效为串联电阻R21和并联电容C22，输入输出的高阻传输线TLi和TLo可以近似等效与串联电感Li和Lo；而对于参考路而言，第一串联晶体管T11和第一并联晶体管T12分别等效为串联小电容和并联小电阻，因此参考路电路几乎没有影响，其它高阻传输线仍近似等效于电感元件。当开关结构切换到参考路径时，第一串联晶体管T11＇和第一并联晶体管T12＇分别等效为串联电阻R11＇和并联电容C12＇，输入输出的高阻传输线TLi和TLo可以近似等效与串联电感Li和Lo；而对于衰减路径而言，第二串联晶体管T21＇和第二并联晶体管T22＇分别等效为串联小电容和并联小电阻，因此衰减路电路几乎没有影响；此时衰减电路等效于5阶低通滤波器结构，如图4所示；当开关结构切换到衰减路径时，第二串联晶体管T21＇和第二并联晶体管T22＇分别等效为串联电阻R21＇和并联电容C22＇，输入输出的高阻传输线TLi和TLo可以近似等效与串联电感Li和Lo；而对于参考路而言，第一串联晶体管T11＇和第一并联晶体管T12＇分别等效为串联小电容和并联小电阻，因此参考路电路几乎没有影响，其它高阻传输线仍近似等效于电感元件。衰减电路等效于两个3阶低通网络之间串联T型衰减网络，如图5所示。
图6为实施例的衰减精度、衰减附加相移以及插入损耗的仿真结果示意图，在DC-20GHz的频率范围内，保持20dB的衰减精度，能够实现±2°的超低衰减附加相移；于此同时，在频率范围内，衰减电路的插入损耗小于1.4dB。图7为实施例参考态和衰减态下驻波特性，在DC-20GHz的频率范围内，实现好于-10dB的良好匹配。

Claims (8)

  1. 低通匹配式大动态常数相位的数控衰减电路，其特征在于，包括：输入节点和输出节点，输入节点和输出节点之间连接有参考路径和衰减路径，输入节点接收待衰减信号，输出节点输出衰减信号。
  2. 如权利要求1所述的低通匹配式大动态常数相位的数控衰减电路，其特征在于，参考路径包括第一串联晶体管、若干并联晶体管和若干串联电抗元件；第一并联晶体管与第一串联晶体管连接，若干并联晶体管之间通过串联电抗逐级连接；第一控制电压施加于第一串联晶体管的偏置节点，第二控制电压施加于参考路径中所有若干并联晶体管的偏置节点上。
  3. 如权利要求1所述的低通匹配式大动态常数相位的数控衰减电路，其特征在于，衰减路径包括第二串联晶体管、若干并联晶体管、若干串联电抗元件和衰减网络；第二串联晶体管与输入节点之间通过电抗元件连接，第二并联晶体管与第二串联晶体管连接，若干并联晶体管之间采用串联电抗元件逐级连接，衰减网络设置于若干级联连接并联晶体管和串联电抗元件的对称中心位置；第三控制电压施加于第二串联晶体管的偏置节点，第四控制电压施加于衰减路径中所有若干并联晶体管的偏置节点上。
  4. 如权利要求2或3所述的低通匹配式大动态常数相位的数控衰减电路，其特征在于，参考路径中第一串联晶体管的沟道宽度大于衰减路径中第二串联晶体管的沟道宽度。
  5. 如权利要求1所述的低通匹配式大动态常数相位的数控衰减电路，其特征在于，在前级电路与电路输入节点间串联电抗元件，在电路输出节点和后级电路输入端口之间串联电抗元件。
  6. 如权利要求2或3所述的低通匹配式大动态常数相位的数控衰减电路，其特征在于，若干串联电抗元件采用电感器件或者高特征阻抗的传输线。
  7. 如权利要求3所述的低通匹配式大动态常数相位的数控衰减电路，其特征在于，衰减网络采用改进的T型电阻网络实现，在T型网络的公共节点与接地电阻之间串联电抗性元件。
  8. 如权利要求3所述的低通匹配式大动态常数相位的数控衰减电路，其特征在于，衰减网络采用改进的π型电阻网络实现，在π型网络的输出节点与接地电阻之间串联电抗性元件。
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