WO2020108589A1 - 高速链路系统的测试装置及方法 - Google Patents

高速链路系统的测试装置及方法 Download PDF

Info

Publication number
WO2020108589A1
WO2020108589A1 PCT/CN2019/121842 CN2019121842W WO2020108589A1 WO 2020108589 A1 WO2020108589 A1 WO 2020108589A1 CN 2019121842 W CN2019121842 W CN 2019121842W WO 2020108589 A1 WO2020108589 A1 WO 2020108589A1
Authority
WO
WIPO (PCT)
Prior art keywords
test
transmission
signal
crosstalk
test signal
Prior art date
Application number
PCT/CN2019/121842
Other languages
English (en)
French (fr)
Inventor
刘春伟
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2020108589A1 publication Critical patent/WO2020108589A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/20—Monitoring; Testing of receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/30—Monitoring; Testing of propagation channels
    • H04B17/309—Measuring or estimating channel quality parameters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
    • H04L27/04—Modulator circuits; Transmitter circuits

Definitions

  • the present disclosure relates to the field of communication technology, for example, to a testing device and method for a high-speed link system.
  • the exchange capacity and processing capacity of the communication system are increasing, the transmission rate of the communication signal is getting higher and higher, and the loss of the communication signal directly affects the correct transmission of the signal and affects the entire system.
  • Designers must understand the loss of communication signals in order to make correct judgments and evaluations.
  • the high-speed communication system is evaluated by the communication signal loss test.
  • Some test methods have a single test item, and there are large errors in the test conclusion; some test methods have complicated operation steps.
  • the present disclosure proposes a test device and method for a high-speed link system, to solve the problems of low precision and complicated operation steps for the insertion loss crosstalk test of high-speed transmission signals in the related art.
  • the present disclosure provides a test device for a high-speed link system, including: a chip test device, a transmission insertion loss ISI attenuation device, a crosstalk ISI attenuation device, and a crosstalk XTK test device;
  • the chip test device is configured to transmit the generated transmission test signal to the transmission ISI attenuation device, and transmit the generated crosstalk test signal to the crosstalk ISI attenuation device;
  • the transmission ISI attenuation device is configured to attenuate the received transmission test signal and transmit the attenuated transmission test signal to the XTK test device;
  • the crosstalk ISI attenuation device is configured to attenuate the received crosstalk test signal and transmit the attenuated crosstalk test signal to the XTK test device;
  • the XTK test device is configured to form the received attenuated crosstalk test signal in the received attenuated transmission test signal to form a crosstalk signal, and transmit the attenuated transmission test signal carrying the crosstalk signal to all Describe the chip test device;
  • the chip test device is further configured to test and evaluate the quality parameters of the attenuated transmission test signal carrying the crosstalk signal.
  • the present disclosure also provides a test method, including:
  • test parameters include: the attenuation parameter of the transmission test signal and the attenuation parameter of the crosstalk test signal;
  • the attenuated crosstalk test signal is formed into a crosstalk signal in the attenuated transmission test signal
  • the test evaluates the bit error rate of the transmitted test signal carrying the attenuated crosstalk signal.
  • FIG. 1 is a schematic structural diagram of a test device for a high-speed link system according to the first embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a test device of a high-speed link system according to a second embodiment of the present disclosure
  • FIG. 3 is a flowchart of a test method of a high-speed link system according to the third and fourth embodiments of the present disclosure.
  • the high-speed communication system is evaluated by performing communication signal loss testing in the following two ways: method one, measuring the eye diagrams of a communication signal of one rate under two different channels, and extracting the amplitude parameters from the eye diagrams , And then take the absolute value of the parameters extracted from the same eye diagram and add them to obtain two sums.
  • the two sums are averaged to obtain the amplitude value; because the characteristics of each channel are inconsistent, each channel All parameters need to be individually configured to adjust the quality of the communication signals it transmits to ensure good communication effects, increase the difficulty of product research and development, and extend the research and development cycle; method two, according to the wiring of the board (including line width and spacing, Elements that affect the insertion loss, such as trace level and plate type), use computer simulation to calculate the insertion loss per unit length, and then calculate the length of the two board traces. After multiplying the two, the total number of multiple signal bits is obtained.
  • Insertion loss value by calculating the transmission length of the high-speed channel, and then calculating the attenuation of the signal according to the transmission length, and then adjusting the pre-emphasis or equalization parameters; by adjusting the pre-emphasis or equalization parameters to output the estimated channel characteristics, but the output
  • the estimated channel characteristics still need to be tested.
  • the test environment of scheme 1 is simple but only for the test results of the eye diagram of a signal at a certain rate.
  • the test item is single, and the test conclusion has a large error; the scheme 2 is for single board wiring
  • the situation and the test situation of insertion loss need to simulate and then look up the table, and then calculate the insertion loss value, the operation steps are cumbersome.
  • the first embodiment of the present disclosure provides a test device for a high-speed link system. As shown in FIG. 1, it includes the following components:
  • Chip test device 100 transmission insertion loss (Insertion, ISI) attenuation device 200, crosstalk ISI attenuation device 300, and crosstalk XTK (crosstalk) test device 400;
  • ISI Transmission insertion loss
  • crosstalk ISI attenuation device 300
  • crosstalk XTK crosstalk
  • the chip test device 100 is configured to transmit the generated transmission test signal to the transmission ISI attenuation device 200, and transmit the generated crosstalk test signal to the crosstalk ISI attenuation device 300;
  • the transmission ISI attenuation device 200 is set to attenuate the received transmission test signal and transmit the attenuated transmission test signal to the XTK test device 400;
  • the crosstalk ISI attenuation device 300 is configured to attenuate the received crosstalk test signal and transmit the attenuated crosstalk test signal to the XTK test device 400;
  • the XTK test device 400 is configured to form the received attenuated crosstalk test signal in the received attenuated transmission test signal to form a crosstalk signal, and transmit the attenuated transmission test signal carrying the crosstalk signal to the chip test device 100 ;
  • the chip test device 100 is further configured to test and evaluate the quality parameters of the attenuated transmission test signal carrying the crosstalk signal.
  • the format of the transmission test signal includes one of the following signals: a pseudo-random binary sequence (Pseudo-Random Binary Sequence, PRBS) code signal, and a non-return-to-zero (NRZ) code signal
  • PRBS pseudo-random binary sequence
  • NRZ non-return-to-zero
  • the format of the crosstalk test signal includes one of the following signals: PRBS code signal, NRZ code signal, etc.; wherein, the transmission test signal may be a signal having the same format as the crosstalk test signal or a different format from the crosstalk test signal signal.
  • the manner in which the transmission ISI attenuation device 200 attenuates the received transmission test signal is not limited, and it may be that the received transmission test signal is attenuated to a set value, or it may be a preset time The interval sequentially attenuates the received transmission test signal to multiple set values.
  • the manner in which the crosstalk ISI attenuation device 300 attenuates the received crosstalk test signal is not limited, and it may be that the received crosstalk test signal is attenuated to a set value, or it may be a preset time The interval sequentially attenuates the received crosstalk test signal to multiple set values.
  • the quality parameter is not limited, and may be a bit error rate, or may be a parameter such as transmission insertion loss.
  • the chip test device 100 is configured to: generate a transmission test signal based on the received transmission signal control instruction and send the transmission test signal to the transmission ISI attenuation device 200; generate based on the received crosstalk signal control instruction The crosstalk test signal is sent to the crosstalk ISI attenuation device 300.
  • a high-speed link system test device and method disclosed in the present disclosure effectively improve the accuracy of the insertion loss crosstalk test for high-speed transmission signals; simplify the insertion loss crosstalk test steps for high-speed transmission signals, and improve the performance of high-speed transmission signals Insertion loss crosstalk test efficiency.
  • the device described in the first embodiment of the present disclosure effectively improves the accuracy of test error evaluation of transmission test signals carrying crosstalk signals, and avoids the test of error rate of transmission test signals carrying crosstalk signals through computer simulation Defects in evaluation; simplifies the bit error rate test and evaluation steps for transmission test signals carrying crosstalk signals, improves the efficiency of bit error rate test and evaluation for transmission test signals carrying crosstalk signals, and avoids the preparation of multiple different high-speed chains
  • the test circuit of the road system tests and evaluates the bit error rate of the transmission test signal carrying the crosstalk signal, resulting in defects such as cumbersome test steps and long test period.
  • the second embodiment of the present disclosure provides a test device for a high-speed link system. As shown in FIG. 2, it includes the following components:
  • Chip test device 100 transmission ISI attenuation device 200, crosstalk ISI attenuation device 300 and XTK test device 400;
  • the chip test device 100 is configured to transmit the generated transmission test signal to the transmission ISI attenuation device 200, and transmit the generated crosstalk test signal to the crosstalk ISI attenuation device 300;
  • the transmission ISI attenuation device 200 is configured to perform an insertion loss gradient scan on the received transmission test signal to attenuate the transmission test signal through the corresponding insertion loss gradient channel and transmit the attenuated transmission test signal to the XTK test device 400 ;
  • the crosstalk ISI attenuation device 300 is configured to perform an insertion loss gradient scan on the received crosstalk test signal to attenuate the crosstalk test signal through the corresponding insertion loss gradient channel, and transmit the attenuated crosstalk test signal to the XTK test device 400 ;
  • the XTK test device 400 is configured to form the received attenuated crosstalk test signal in the received attenuated transmission test signal to form a crosstalk signal, and transmit the attenuated transmission test signal carrying the crosstalk signal to the chip test device 100 ;
  • the chip test device 100 is further configured to test and evaluate the quality parameters of the attenuated transmission test signal carrying the crosstalk signal.
  • the chip test device 100 includes: a clock chip 101, a control management device 102, and a serializer/deserializer (SERializer/ DESerializer, SerDes) test chip 103;
  • SERializer/ DESerializer, SerDes serializer/deserializer
  • control management device 102 is configured to send a clock control instruction to the clock chip 101, and send a test signal control instruction to the SerDes test chip 103;
  • the clock chip 101 is set to generate a clock signal of a set frequency under the control of a clock control instruction, and transmit the clock signal to the SerDes test chip 103;
  • the SerDes test chip 103 is configured to generate a transmission test signal and a crosstalk test signal based on the clock signal under the control of the test signal control instruction; test and evaluate the bit error rate of the received transmission test signal after the attenuation of the crosstalk signal .
  • the SerDes test chip 103 is set to: when the format of the transmission test signal is the NRZ format, the result of testing and evaluating the bit error rate of the received transmission test signal after the attenuation of the crosstalk signal is: :
  • n is the number of transmission test signal transmission bits after attenuation of the crosstalk signal
  • k is the number of error codes of the transmission test signal after attenuation of the crosstalk signal
  • p is the attenuated transmission test signal carrying crosstalk signal Bit error rate
  • the transmission rate range for transmitting test signals is: [10Gbps, 25Gbps].
  • the SerDes test chip 103 is configured to: when the format of the transmission test signal is a 4 pulse amplitude modulation (4 Pulse Amplitude ModulaTIon, PAM4) format, attenuated the transmission test signal carrying the crosstalk signal received
  • the results of testing and evaluation of the bit error rate are:
  • x is the number of transmission test signal transmission bits after attenuation of the crosstalk signal
  • ⁇ is the number of error codes of the transmission test signal after attenuation of the crosstalk signal
  • ⁇ is the attenuation of the transmission test signal carrying crosstalk signal Bit error rate
  • the transmission rate range for transmitting test signals is [50Gbps, 56Gbps].
  • the chip test device 100 further includes: a first test probe 104, a second test probe 105, a third test probe 106, and a printed circuit board (Printed Circuit Board, PCB) board 107;
  • a printed circuit board Printed Circuit Board, PCB
  • the PCB board 107 is provided with a first signal transmission line 1071, a second signal transmission line 1072 and a third signal transmission line 1073;
  • the first signal transmission line 1071 is configured to transmit the transmission test signal output from the first signal output pin of the SerDes test chip 103 to the first test probe 104;
  • the second signal transmission line 1072 is configured to transmit the crosstalk test signal output from the second signal output pin of the SerDes test chip 103 to the second test probe 105;
  • the third signal transmission line 1073 is configured to transmit the transmission test signal carrying the crosstalk signal received by the third test probe 106 to the test pin of the SerDes test chip 103;
  • the first test probe 104 is configured to transmit the transmission test signal to the transmission ISI attenuation device 200 through the transmission cable;
  • the second test probe 105 is configured to transmit the crosstalk test signal to the crosstalk ISI attenuation device 300 through the transmission cable;
  • the third test probe 106 is configured to receive the attenuated transmission test signal carrying the crosstalk signal transmitted by the XTK test device 400 through the transmission cable.
  • the first test probe 104, the second test probe 105, and the third test probe 106 are not limited, and may be the same test probe or different test probes; wherein, the first test probe 104, the second test probe 105, and the third test probe 106 are one or more of the following test probes: Shape Memory Alloy (SMA) test probe, MCX test probe, and BCN test probe.
  • SMA Shape Memory Alloy
  • the first signal transmission line 1071 is configured to transmit the first signal output pin of the SerDes test chip 103 from the first PRBS code signal output by the fan-out via of the ball grid array (BGA) to the first SMA Test probe 104;
  • the second signal transmission line 1072 is configured to transmit the second PRBS code signal output from the second signal output pin of the SerDes test chip 103 from the BGA fan-out via to the second SMA test probe 105;
  • the third signal transmission line 1073 is configured to transmit the first PRBS code signal carrying the crosstalk signal received by the third SMA test probe 106 to the BGA fan-out via of the test pin of the SerDes test chip 103.
  • a test transmission line 111 is also provided on the PCB board 107; the quality parameters of the transmission test signal further include: the insertion loss of the transmission test signal transmitted on the test transmission line 111 provided on the PCB board 107; the SerDes test chip 103 is also set For: under the control of the test signal control instruction, a plurality of transmission test signals of a set frequency are generated based on the clock signal; control the plurality of transmission test signals of a set frequency to be respectively transmitted on the test transmission line 111 provided on the PCB 107, In order to obtain the insertion loss of the transmission test signal of each set frequency transmitted on the test transmission line 111 provided on the PCB 107.
  • the length of the test transmission line 111 is not limited, and can be set according to engineering experience, or can be set according to the requirement of the PCB board in the high-speed link system to transmit high-speed link signals.
  • the length of the test transmission line 111 is not limited, and can be set according to engineering experience, or can be set according to the requirement of the PCB board in the high-speed link system to transmit high-speed link signals.
  • test cost is too high; at the same time, it avoids the shortcomings of the test and evaluation of the insertion loss of the high-speed link signal through the computer simulation of the high-speed link system PCB board, and the test results are inaccurate, effectively improving the high-speed link signal in the PCB Transmission insertion loss test accuracy.
  • a plurality of transmission test signals of a set frequency can be separately tested on a test transmission line 111 provided on the PCB 107, and the obtained insertion loss is prepared as a table to facilitate each set frequency
  • the transmitted test signal is transmitted on the test transmission line 111 provided on the PCB 107, and the obtained insertion loss is compared.
  • the PCB board 107 includes: a plurality of PCB boards 107 of a set material; wherein each PCB board 107 of a set material is provided with the same test transmission line 111; the quality parameters of the transmission test signal further include: transmission The insertion loss of the test signal transmitted on the test transmission line 111 provided on the PCB 107 of each set material; the SerDes test chip 103 is also set to: under the control of the test signal control instruction, generate multiple settings based on the clock signal Fixed frequency transmission test signals; control multiple set frequency transmission test signals to be transmitted on the test transmission line 111 provided on the PCB board 107 of each set material to obtain each set frequency transmission test signal The insertion loss transmitted on the test transmission line 111 provided on the PCB 107 of each set material.
  • the transmission loss of each set frequency transmission test signal in the test transmission line 111 is obtained, which effectively simplifies
  • the insertion loss test procedure for the test transmission line 111 provided on the PCB board 107 avoids the complicated steps caused by multiple preparations of high-speed link system PCB test boards of different materials to test the insertion loss of high-speed link signals, and the test cost is too high
  • it avoids the disadvantages of testing and evaluating the insertion loss of high-speed link signals on high-speed link system PCB boards of different materials through computer simulation, and the test results are inaccurate, which effectively improves the high-speed link signals on PCB boards of different materials. Insertion loss test accuracy for transmission in.
  • PCB board 107 includes: FR4 (a number of heat-resistant material grade) PCB board 107, M4 (Megtron4) PCB board 107, and M6 (Megtron6) PCB board 107; each of which The PCB board 107 of the material is provided with the same test transmission line 111; the quality parameters of the transmission test signal also include: the insertion loss of the transmission test signal transmitted on the test transmission line 111 provided on the PCB board 107 of each material; the SerDes test chip 103.
  • FR4 a number of heat-resistant material grade
  • the transmission test signal is transmitted on the test transmission line 111 provided on the PCB board 107 of each set material to obtain the transmission test signal of each set frequency set on the PCB board 107 of each set material Test the insertion loss of transmission on the transmission line 111 (as shown in Table 2).
  • the insertion loss of the FR4 PCB board at the frequency of 5GHz has reached -34.8dB, and the M4 PCB board is at 10GHz
  • the insertion loss of the frequency point is -36.7dB.
  • the M4 PCB is under the same length of transmission line, and the signal transmission is lower at higher frequencies.
  • the M6 PCB is at 20GHz.
  • the insertion loss at the frequency point is -33.9dB.
  • the M6 material PCB board is more suitable for high-speed links.
  • the PCB board 107 is also provided with a plurality of test transmission lines 111 with different set lengths; the quality parameters for transmitting test signals further include: a plurality of test transmission lines with different set lengths set on the PCB board 107 Insertion loss transmitted on 111; SerDes test chip 103 is also set to: control transmission test signals to be transmitted on a plurality of test transmission lines 111 of different set lengths set on the PCB board 107 to obtain transmission test signals The insertion loss of a test transmission line 111 of a set length.
  • Test transmission lines 111 of different lengths on the PCB board 107 are transmitted by transmitting test signals to obtain insertion loss of the test transmission lines 111 of the test transmission lines 111 of different lengths, which effectively simplifies the test transmission line 111 provided on the PCB board 107
  • the insertion loss test procedure avoids the tedious steps caused by the high-speed link system PCB test board that prepares test transmission lines of different lengths to test the insertion loss of high-speed link signals many times, and the test cost is too high; at the same time, it avoids the passing Computer simulation of high-speed link system PCB boards that test transmission lines of different lengths tests and evaluates the insertion loss of high-speed link signals.
  • the shortcomings of inaccurate test results effectively improve the high-speed link signals in the PCB boards of test transmission lines of different lengths.
  • the accuracy of the insertion loss test for transmission is performed by transmitting test signals to obtain insertion loss of the test transmission lines 111 of the test transmission lines 111 of different lengths, which effectively simplifies the test transmission line 111 provided on the PC
  • the FR4, M4, and M6 PCB materials 107 are provided with a test transmission line 111 of 0.4m length, a test transmission line 111 of 0.5m length, a test transmission line 111 of 0.7m length, and a test transmission line 111 of 1.2m length.
  • the quality parameters of the transmission test signal also include: the transmission test signal is set on the PCB 107 of the set length of the test transmission line Insertion loss transmitted on 111; the SerDes test chip 103 is also set to: control transmission test signals to be transmitted on each set length transmission line 111 provided on the PCB 107 to obtain transmission test signals in each type of setting The insertion loss of transmission on the fixed-length transmission line 111 (as shown in Table 3).
  • the signal transmission line length of the PCB board of the high-speed link system is evaluated at a rate of 10Gbps SerDes and an insertion loss of -13dB.
  • the same frequency point of 10GHz the PCB board 107 of FR4 material is used
  • the length of the signal transmission line is only 0.4m
  • the length of the signal transmission line of the PCB board 107 made of M4 material is 0.9m
  • the length of the signal transmission line of the PCB board 107 made of M6 material is 1.2m.
  • the quality parameters of the transmitted test signal further include: the insertion loss of the test signal transmitted on the test transmission line 111 provided on the PCB 107 at each preset temperature; the SerDes test chip 103 is also set to: Under the preset temperature, the transmission test signal is controlled to be transmitted on the test transmission line 111 provided on the PCB board 107 to obtain the insertion loss of the test signal transmitted on the test transmission line 111 provided on the PCB board 107 at each preset temperature .
  • Test transmission lines 111 of different lengths on the PCB board 107 at different temperatures by transmitting test signals to perform transmission tests to obtain transmission test signals to test the insertion loss of the transmission line 111 at different temperatures, effectively simplifying the PCB board 107 at different temperatures
  • the insertion loss test procedure of the test transmission line 111 provided above avoids the cumbersome steps caused by the multiple times of testing the insertion loss of the high-speed link system PCB test board that prepares test transmission lines of different lengths for high-speed link signals, and the test cost is too high At the same time, it avoids the disadvantage of being unable to test and evaluate the insertion loss of the high-speed link signal on the PCB board of the high-speed link system at different temperatures through computer simulation, and effectively improves the test transmission line of the high-speed link signal on the PCB board at different temperatures. Insertion loss test accuracy for transmission in.
  • the PCB board 107 includes: a PCB board 107 processed by a variety of setting processes; each PCB board 107 processed by the setting process is provided with a test transmission line 111; the quality parameters for transmitting the test signal further include: transmitting the test signal The insertion loss transmitted on the test transmission line 111 provided on the PCB board 107 processed by each set process; the SerDes test chip 103 is also set to: control the transmission test signal to be set on the PCB board 107 processed by each set process The test transmission line 111 is transmitted to obtain the insertion loss of the transmission test signal transmitted on the test transmission line 111 provided on the PCB board 107 processed by each set process.
  • Test transmission line 111 on PCB board 107 prepared by different processing processes is transmitted by transmitting test signals to obtain insertion loss of transmission test signal in test transmission line 111, which effectively simplifies PCB board 107 prepared under different processing processes
  • the insertion loss test steps of the test transmission line 111 provided above avoid the tedious steps caused by multiple preparations of high-speed link system PCB test boards of different processing technologies to test the insertion loss of high-speed link signals, and the defects of excessive test cost ; At the same time, it avoids the disadvantage of being unable to test and evaluate the insertion loss of the high-speed link signal on the PCB board of the high-speed link system with different processing technologies through computer simulation, and effectively improves the transmission of the high-speed link signal in the test transmission line of the PCB board. Insertion loss test accuracy.
  • the format of the transmission test signal includes one of the following signals: PRBS code signal, NRZ code signal, etc.;
  • the format of the crosstalk test signal includes one of the following signals: PRBS code signal, NRZ code signal, etc.; wherein, the transmission test The signal may be a signal having the same format as the crosstalk test signal or a signal having a different format from the crosstalk test signal.
  • the manner in which the transmission ISI attenuation device 200 attenuates the received transmission test signal is not limited, and it may be that the received transmission test signal is attenuated to a set value, or it may be a preset time The interval sequentially attenuates the received transmission test signal to multiple set values.
  • the manner in which the crosstalk ISI attenuation device 300 attenuates the received crosstalk test signal is not limited, and it may be that the received crosstalk test signal is attenuated to a set value, or it may be a preset time The interval sequentially attenuates the received crosstalk test signal to multiple set values.
  • the quality parameter is not limited, and may be a bit error rate, or may be a parameter such as transmission insertion loss.
  • the chip test device 100 is configured to: generate a transmission test signal based on the received transmission signal control instruction and send the transmission test signal to the transmission ISI attenuation device 200; generate based on the received crosstalk signal control instruction The crosstalk test signal is sent to the crosstalk ISI attenuation device 300.
  • the device described in the second embodiment of the present disclosure effectively improves the accuracy of testing and evaluating the quality parameter of the transmission test signal carrying the crosstalk signal, and avoids the testing and evaluation of the quality parameter of the transmission test signal carrying the crosstalk signal through computer simulation. Defects; Simplifies the testing and evaluation of the quality parameters of the transmission test signals carrying crosstalk signals, improves the efficiency of testing and evaluating the quality parameters of the transmission test signals carrying crosstalk signals, and avoids the preparation of multiple different high-speed link system test circuits , Test and evaluate the quality parameters of the transmission test signal carrying the crosstalk signal, resulting in the defects of cumbersome test steps and long test cycle; at the same time, the transmission test signals of different frequencies are transmitted through the test transmission line on the PCB board, or in different The test transmission line of the material PCB board transmits the test signal, or the test transmission line of the PCB board of different processing technology transmits the test signal, or the test transmission line of the PCB board of different processing technology transmits the test signal, or the PCB at different temperatures
  • test result is inaccurate, which effectively improves the high-speed link signal in the test transmission line PCB board Transmission insertion loss test accuracy.
  • the third embodiment of the present disclosure provides a test method for a high-speed link system. As shown in FIG. 3, the test method includes S3010 to S3030.
  • S3010 Attenuate the transmission test signal and the crosstalk test signal separately according to the preset test parameters.
  • the test parameters include: attenuation parameters of the transmission test signal, and attenuation parameters of the crosstalk test signal.
  • the attenuation parameter of the transmission test signal is not limited, and it may be that the transmission test signal is attenuated to a set value, or that the transmission test signal is attenuated by a set attenuation amplitude value, or that the transmission test signal is transmitted Attenuation amplitude value for gradient attenuation.
  • the attenuation parameter of the crosstalk test signal is not limited, and it may be that the crosstalk test signal is attenuated to a set value, or that the crosstalk test signal is attenuated by a set amplitude value, or that the crosstalk test signal Attenuation amplitude value for gradient attenuation.
  • the transmission test signal and the crosstalk test signal are respectively attenuated according to the attenuation parameters of the signal, including one of the following methods:
  • Method 1 According to the preset test parameters, the transmission test signal and the crosstalk test signal are respectively attenuated to the set signal amplitude value;
  • Method 2 According to the preset test parameters, set the attenuation amplitude value for the transmission test signal and the crosstalk test signal respectively;
  • Method 3 According to the preset test parameters, the transmission test signal and the crosstalk test signal are respectively subjected to gradient attenuation.
  • the format of the transmission test signal includes one of the following signals: PRBS code signal, NRZ code signal, etc.;
  • the format of the crosstalk test signal includes one of the following signals: PRBS code signal, NRZ code signal, etc.; wherein, the transmission test The signal may be a signal having the same format as the crosstalk test signal or a signal having a different format from the crosstalk test signal.
  • the attenuated crosstalk test signal is formed into a crosstalk signal in the attenuated transmission test signal.
  • the attenuated crosstalk test signal in the attenuated transmission test signal to form a crosstalk signal to control the crosstalk test signals of different amplitude values to form a crosstalk signal in the transmission test signals of different amplitude values
  • crosstalk of various amplitude values is achieved
  • the test signal forms a crosstalk signal in the transmission test signals of various amplitude values, which effectively improves the accuracy of testing and evaluating the bit error rate of the transmission test signal carrying the crosstalk signal, and avoids the crosstalk test signal that can only test and evaluate one amplitude value.
  • a crosstalk signal formed in a transmission test signal of an amplitude value but a crosstalk signal formed by a crosstalk test signal of another amplitude value cannot be tested and evaluated in a transmission test signal of the amplitude value, or a crosstalk test signal of the amplitude value cannot be tested and evaluated
  • the crosstalk signal formed in the transmission test signals of other amplitude values improves the efficiency of test evaluation and also improves the accuracy of test evaluation.
  • S3030 Test and evaluate the bit error rate of the transmitted test signal after the attenuation of the crosstalk signal.
  • the method described in the third embodiment of the present disclosure effectively improves the accuracy of test error evaluation of transmission test signals carrying crosstalk signals, and avoids the test of error rate of transmission test signals carrying crosstalk signals through computer simulation
  • the shortcomings of the evaluation it simplifies the bit error rate test and evaluation steps of the transmission test signal carrying the crosstalk signal, and improves the efficiency of the bit error rate test and evaluation of the transmission test signal carrying the crosstalk signal.
  • the fourth embodiment of the present disclosure provides a test method for a high-speed link system. As shown in FIG. 3, the test method includes S3010 to S3030.
  • S3010 Attenuate the transmission test signal and the crosstalk test signal separately according to the preset test parameters.
  • the test parameters include: attenuation parameters of the transmission test signal, and attenuation parameters of the crosstalk test signal.
  • S3010 includes:
  • the format of the transmission test signal includes one of the following signals: PRBS code signal, NRZ code signal, etc.;
  • the format of the crosstalk test signal includes one of the following signals: PRBS code signal, NRZ code signal, etc.; wherein, the transmission test The signal may be a signal having the same format as the crosstalk test signal or a signal having a different format from the crosstalk test signal.
  • the attenuated crosstalk test signal is formed into a crosstalk signal in the attenuated transmission test signal.
  • the attenuated crosstalk test signal in the attenuated transmission test signal to form a crosstalk signal to control the crosstalk test signals of different amplitude values to form a crosstalk signal in the transmission test signals of different amplitude values
  • crosstalk of various amplitude values is achieved
  • the test signal forms a crosstalk signal in the transmission test signals of various amplitude values, which effectively improves the accuracy of testing and evaluating the bit error rate of the transmission test signal carrying the crosstalk signal, and avoids the crosstalk test signal that can only test and evaluate one amplitude value.
  • a crosstalk signal formed in a transmission test signal of an amplitude value but a crosstalk signal formed by a crosstalk test signal of another amplitude value cannot be tested and evaluated in a transmission test signal of the amplitude value, or a crosstalk test signal of the amplitude value cannot be tested and evaluated
  • the crosstalk signal formed in the transmission test signals of other amplitude values improves the efficiency of test evaluation and also improves the accuracy of test evaluation.
  • S3030 Test and evaluate the bit error rate of the transmitted test signal after the attenuation of the crosstalk signal.
  • S3030 includes: when the format of the transmission test signal is the NRZ format, the result of the test evaluation of the bit error rate of the attenuated transmission test signal carrying the crosstalk signal is:
  • n is the number of transmission test signal transmission bits after attenuation of the crosstalk signal
  • k is the number of error codes of the transmission test signal after attenuation of the crosstalk signal
  • p is the attenuated transmission test signal carrying crosstalk signal Bit error rate
  • the transmission rate range for transmitting test signals is: [10Gbps, 25Gbps].
  • Pn(k) is the bit error rate when the number of bit errors is the number of bit errors.
  • S3030 includes: when the format of the transmission test signal is the PAM4 format, the result of the test evaluation of the attenuated transmission error rate of the transmission test signal carrying the crosstalk signal is the PAM4 format.
  • the bit error rate of the transmission test signal after attenuation; the transmission rate range of the transmission test signal is [50Gbps, 56Gbps].
  • g(x) is the bit error rate when the number of transmitted bits is x.
  • the test parameters also include one or more of the following parameters: the length of the test transmission line provided on the PCB board, the material of the PCB board, the processing technology of the PCB board, and the test temperature; the method further includes S304, Among them, S304 includes: testing the insertion loss of the transmission test signal transmitted on the test transmission line provided on the PCB according to the test parameters.
  • S304 includes one or more of the following ways:
  • Method 1 Control the transmission test signals of multiple set frequencies to be respectively transmitted on the test transmission line set on the PCB board to obtain the insertion loss of each set frequency transmission test signal transmitted on the test transmission line set on the PCB board .
  • Method 2 Control the transmission test signal of each set frequency to be transmitted on the test transmission line provided on the PCB board of each set material to obtain the transmission test signal of each set frequency in each set material The insertion loss of the test transmission line set on the PCB board.
  • Method 3 Control transmission test signals to be transmitted on multiple transmission lines of different set lengths on PCBs of various set materials to obtain insertion of transmission test signals transmitted on each set length of the transmission line loss.
  • Method four under multiple preset temperatures, respectively control the transmission of test signals on the test transmission line set on the PCB board to obtain the transmission of the test signals transmitted on the test transmission line set on the PCB board at each preset temperature Insertion loss.
  • Method five Control transmission test signals to be transmitted on test transmission lines set on multiple PCBs processed by a set process to obtain transmission test signals to be transmitted on test transmission lines set on PCBs processed by a set process Insertion loss.
  • the execution order of S304 is not limited, and may be executed before S3030 or after S3030.
  • the method described in the fourth embodiment of the present disclosure effectively improves the accuracy of the test error evaluation of the transmission test signal carrying the crosstalk signal, and avoids the test of the error rate of the transmission test signal carrying the crosstalk signal through computer simulation
  • the shortcomings of the evaluation it simplifies the bit error rate test and evaluation steps of the transmission test signal carrying the crosstalk signal, and improves the efficiency of the bit error rate test and evaluation of the transmission test signal carrying the crosstalk signal.
  • a fifth embodiment of the present disclosure is based on the above-mentioned embodiments and takes a test method as an example to introduce an application example of the present disclosure.
  • the line card BGA pad and fan-out vias are connected to the line card orthogonal connector and Footprint (pin) through the signal transmission line of the PCB board, and to the switch board orthogonal connector and Footprint, line
  • the card BGA pad and fan-out via are connected to the BGA pad and fan-out via of the PCB board signal transmission line.
  • This test environment directly simulates the high-speed link system.
  • the high-speed SerDes of the main chip of the test board can support 10.3125Gbps, 25.78125Gbps or 53.125Gbps.
  • S601 in the case of a fixed 50Gbps rate and a signal transmission line of the PCB board, evaluate the system insertion loss crosstalk, and perform insertion loss traversal on the same channel.
  • the channel insertion loss gradient is 2dB@12.5GHz.
  • S602 Perform crosstalk traversal on different channels, the crosstalk gradient is 0.5mv, and link training (link negotiation) is enabled.
  • the test results in a table of insertion loss and crosstalk.
  • a graph can be drawn to visually see the bit error rate corresponding to different insertion loss and different crosstalk; according to the above evaluation method, it can be evaluated at 10G/25G Whether the bit error rate at /50G rate is a better bit error situation.
  • a sixth embodiment of the present disclosure is based on the above-mentioned embodiment and takes a test method as an example to introduce an application example of the present disclosure.
  • the line card BGA pad and fan-out vias are connected to the line card orthogonal connector and Footprint through the signal transmission line of the PCB board, and to the switchboard orthogonal connector and Footprint, line card BGA pad And the fan-out vias are connected to the BGA pad of the switch board and the fan-out vias through the signal transmission line of the PCB board.
  • S702 Perform insertion loss traversal on the same channel; wherein, the insertion loss gradient of the channel is 2dB@12.5GHz.
  • a seventh embodiment of the present disclosure is based on the above-mentioned embodiment and takes a test method as an example to introduce an application example of the present disclosure.
  • the line card BGA pad and fan-out vias are connected to the line card orthogonal connector and Footprint through the signal transmission line of the PCB board, and to the switchboard orthogonal connector and Footprint, line card BGA pad And the fan-out vias are connected to the BGA pad of the switch board and the fan-out vias through the signal transmission line of the PCB board.
  • the simulation result shows that the insertion loss increases by 1.7dB when the system temperature rises by 40 degrees.
  • insertion loss within 30dB is a tolerable temperature rise, which can be used to evaluate the temperature rise of line cards and switch boards of different systems and achieve simulation results. It is verified that the simulation result is that the insertion loss of the high-temperature system increases by 1.4dB under the condition that the insertion loss of the normal temperature system is 25.3dB@13.28GHz.
  • An eighth embodiment of the present disclosure is based on the above-mentioned embodiment and takes a test method as an example to introduce an application example of the present disclosure.
  • the entire channel of the system link consists of line card BGA pads and fan-out vias. It connects the line card orthogonal connector and Footprint through the signal transmission line of the PCB board, and connects the switch board orthogonal connector and Footprint, and passes the signal transmission line of the PCB board. Connected to the BGA pad of the exchange board and the fan-out via.
  • S901 Perform system evaluation on demo boards of different processing technologies at a fixed 50Gbps rate.
  • S902 Perform insertion loss traversal on the same channel; wherein, the insertion loss gradient of the channel is 2dB@12.5GHz.
  • demo board's main chip supports 30dB insertion loss, it is undesirable for the processing technology that exceeds the insertion loss standard, and can realize the evaluation of the processing technology of line cards and exchange boards of different systems.
  • the terms "including”, “comprising” or other variations thereof are intended to cover non-exclusive inclusions such that a process, method, article or device that includes a series of elements includes not only those elements, It also includes other elements that are not explicitly listed, or include elements inherent to such processes, methods, objects, or devices. Without more restrictions, the element defined by the sentence "include one" does not exclude that there are other identical elements in the process, method, article or device that includes the element.
  • the method of the above embodiments may be implemented by means of software plus a necessary general hardware platform, or may be implemented by hardware.
  • the technical solution of the present disclosure can be embodied in the form of a software product that is stored in a storage medium (such as read-only memory/random access memory (Read-Only Memory/Random Access Memory, ROM/RAM), magnetic disk , CD), including one or more instructions to enable a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to perform the methods described in multiple embodiments of the present disclosure.
  • a storage medium such as read-only memory/random access memory (Read-Only Memory/Random Access Memory, ROM/RAM), magnetic disk , CD
  • a terminal which may be a mobile phone, computer, server, air conditioner, or network device, etc.

Abstract

本公开提出了一种高速链路系统的测试装置，包括：芯片测试器件、传输插入损耗ISI衰减器件、串扰ISI衰减器件和串扰XTK测试器件；所述XTK测试器件，设置为将接收到的衰减后的串扰测试信号在接收到的衰减后的传输测试信号中形成串扰信号，并将承载所述串扰信号的衰减后的传输测试信号传输至所述芯片测试器件；所述芯片测试器件，还设置为对承载所述串扰信号的衰减后的传输测试信号的质量参数进行测试评估。本文还公开了一种高速链路系统的测试方法。

Description

高速链路系统的测试装置及方法
本申请要求在2018年11月29日提交中国专利局、申请号为201811445288.8的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本公开涉及通信技术领域，例如涉及一种高速链路系统的测试装置及方法。
背景技术
通信系统的交换能力以及处理能力越来越大，通信信号的传输速率越来越高，通信信号损耗直接影响信号正确传输，并影响整个系统。设计者必须了解通信信号损耗状况，以便做出正确的判断及评估。
相关技术中通过通信信号损耗测试来评估高速通信系统有的测试方式测试项单一，测试结论存在较大的误差；有的测试方式操作步骤繁琐。
发明内容
本公开提出了一种高速链路系统的测试装置及方法，用以解决相关技术中对高速传输信号的插损串扰测试精度低、操作步骤繁琐的问题。
本公开提供一种高速链路系统的测试装置，包括：芯片测试器件、传输插入损耗ISI衰减器件、串扰ISI衰减器件和串扰XTK测试器件；
所述芯片测试器件，设置为将生成的传输测试信号传输至所述传输ISI衰减器件，并将生成的串扰测试信号传输至所述串扰ISI衰减器件；
所述传输ISI衰减器件，设置为对接收到的所述传输测试信号进行衰减，并将衰减后的传输测试信号传输至所述XTK测试器件；
所述串扰ISI衰减器件，设置为对接收到的所述串扰测试信号进行衰减，并将衰减后的串扰测试信号传输至所述XTK测试器件；
所述XTK测试器件，设置为将接收到的衰减后的串扰测试信号在接收到的衰减后的传输测试信号中形成串扰信号，并将承载所述串扰信号的衰减后的传输测试信号传输至所述芯片测试器件；
所述芯片测试器件，还设置为对承载所述串扰信号的衰减后的传输测试信号的质量参数进行测试评估。
本公开还提供一种测试方法，包括：
根据预置的测试参数，对传输测试信号和串扰测试信号分别进行衰减；其 中，所述测试参数包括：所述传输测试信号的衰减参数，以及所述串扰测试信号的衰减参数；
将衰减后的串扰测试信号在衰减后的传输测试信号中形成串扰信号；
测试评估承载所述串扰信号的衰减后的传输测试信号的误码率。
附图说明
图1为本公开第一实施例所述的高速链路系统的测试装置组成结构示意图；
图2为本公开第二实施例所述的高速链路系统的测试装置组成结构示意图；
图3为本公开第三和第四实施例所述的高速链路系统的测试方法流程图。
具体实施方式
为阐述本公开为达成预定目的所采取的技术手段及功效，以下结合附图及可选实施例，对本公开进行说明。
在一实施例中，通过以下两种方式进行通信信号损耗测试来评估高速通信系统：方式一，测量一种速率的通信信号在两个不同通道下的眼图，并从眼图中提取幅度参数，然后分别对同一眼图中提取到的参数取绝对值做加法运算，得到两个和值，最后将两个和值做平均值运算，得到幅度值；由于每个通道特性不一致，每个通道都需要单独配置其参数才能调整其传输的通信信号质量，来确保良好的通信效果，增加了产品研发的难度，延长研发周期；方式二，根据板卡的走线情况(包括线宽线距、走线层面和板材型号等影响插损的要素)，使用计算机仿真计算出单位长度的插损，再把两个板卡走线长度统计出来，两者相乘后得出多个信号位的总插入损耗值；通过对高速通道的传输长度进行计算，再根据传输长度计算信号的衰减，然后调整预加重或均衡参数；通过调整预加重或均衡参数以输出预估的通道特性，但是，输出的预估的通道特性还需要测试。其中，方案一测试环境简单但是只针对一种信号在某一种速率下的眼图得出的测试结果，测试项单一，测试结论存在较大的误差；方案二中针对的是单板走线情况与插损的测试情况，需要仿真再查表，然后统计出插损值，操作步骤繁琐。
本公开第一实施例提供了一种高速链路系统的测试装置，如图1所示，包括以下组成部分：
芯片测试器件100、传输插入损耗(Insertion，ISI)衰减器件200、串扰ISI衰减器件300和串扰XTK(crosstalk)测试器件400；
芯片测试器件100，设置为将生成的传输测试信号传输至传输ISI衰减器件200，并将生成的串扰测试信号传输至串扰ISI衰减器件300；
传输ISI衰减器件200，设置为对接收到的传输测试信号进行衰减，并将衰减后的传输测试信号传输至XTK测试器件400；
串扰ISI衰减器件300，设置为对接收到的串扰测试信号进行衰减，并将衰减后的串扰测试信号传输至XTK测试器件400；
XTK测试器件400，设置为将接收到的衰减后的串扰测试信号在接收到的衰减后的传输测试信号中形成串扰信号，并将承载串扰信号的衰减后的传输测试信号传输至芯片测试器件100；
芯片测试器件100，还设置为对承载串扰信号的衰减后的传输测试信号的质量参数进行测试评估。
在本实施例中，传输测试信号的格式包括以下信号之一：伪随机二进制序列(Pseudo-Random Binary Sequence，PRBS)码信号，不归零码(Non-Return-to-Zero，NRZ)码信号等；串扰测试信号的格式包括以下信号之一：PRBS码信号，NRZ码信号等；其中，传输测试信号可以是与串扰测试信号具有相同格式的信号，也可以是与串扰测试信号具有不同格式的信号。
在本实施例中，对传输ISI衰减器件200对接收到的传输测试信号进行衰减的方式不做限定，可以是将接收到的传输测试信号衰减至设定值，也可以是以预设的时间间隔将接收到的传输测试信号依次衰减至多个设定值。
在本实施例中，对串扰ISI衰减器件300对接收到的串扰测试信号进行衰减的方式不做限定，可以是将接收到的串扰测试信号衰减至设定值，也可以是以预设的时间间隔将接收到的串扰测试信号依次衰减至多个设定值。
在本实施例中，对质量参数不做限定，可以是误码率，也可以是传输插入损耗等参数。
可选地，芯片测试器件100，是设置为：基于接收到的传输信号控制指令，生成传输测试信号，并将传输测试信号发送至传输ISI衰减器件200；基于接收到的串扰信号控制指令，生成串扰测试信号，并将串扰测试信号发送至串扰ISI衰减器件300。
本公开所述一种高速链路系统的测试装置及方法，有效提高了对高速传输信号的插损串扰测试精度；简化了对高速传输信号的插损串扰测试步骤，提高了对高速传输信号的插损串扰测试效率。
本公开第一实施例所述的装置，有效提高了对承载串扰信号的传输测试信号的误码率测试评估精度，避免了通过计算机仿真带来的承载串扰信号的传输测试信号的误码率测试评估的缺陷；简化了对承载串扰信号的传输测试信号的误码率测试评估步骤，提高了对承载串扰信号的传输测试信号的误码率测试评估效率，避免了通过制备多个不同的高速链路系统测试电路，对承载串扰信号 的传输测试信号的误码率进行测试评估，导致的测试步骤繁琐，测试周期过长的缺陷。
本公开第二实施例提供了一种高速链路系统的测试装置，如图2所示，包括以下组成部分：
芯片测试器件100、传输ISI衰减器件200、串扰ISI衰减器件300和XTK测试器件400；
芯片测试器件100，设置为将生成的传输测试信号传输至传输ISI衰减器件200，并将生成的串扰测试信号传输至串扰ISI衰减器件300；
传输ISI衰减器件200，设置为对接收到的传输测试信号进行插损梯度扫描，以通过对应的插损梯度通道对传输测试信号进行衰减，并将衰减后的传输测试信号传输至XTK测试器件400；
串扰ISI衰减器件300，设置为对接收到的串扰测试信号进行插损梯度扫描，以通过对应的插损梯度通道对串扰测试信号进行衰减，并将衰减后的串扰测试信号传输至XTK测试器件400；
XTK测试器件400，设置为将接收到的衰减后的串扰测试信号在接收到的衰减后的传输测试信号中形成串扰信号，并将承载串扰信号的衰减后的传输测试信号传输至芯片测试器件100；
芯片测试器件100，还设置为对承载串扰信号的衰减后的传输测试信号的质量参数进行测试评估。
可选地，在传输测试信号的质量参数包括：传输测试信号的误码率的情况下，芯片测试器件100包括：时钟芯片101，控制管理器件102，及串行器/解串器(SERializer/DESerializer，SerDes)测试芯片103；
其中，控制管理器件102，设置为将时钟控制指令发送至时钟芯片101，并将测试信号控制指令发送至SerDes测试芯片103；
时钟芯片101，设置为在时钟控制指令的控制下，生成设定频率的时钟信号，并将时钟信号传输至SerDes测试芯片103；
SerDes测试芯片103，设置为在测试信号控制指令的控制下，基于时钟信号生成传输测试信号，及串扰测试信号；对接收到的承载串扰信号的衰减后的传输测试信号的误码率进行测试评估。
可选地，SerDes测试芯片103，是设置为：在传输测试信号的格式为NRZ格式的情况下，对接收到的承载串扰信号的衰减后的传输测试信号的误码率进行测试评估的结果为：
Figure PCTCN2019121842-appb-000001
其中，n为承载串扰信号的衰减后的传输测试信号的传输比特个数；k为承载串扰信号的衰减后的传输测试信号的误码个数；p为承载串扰信号的衰减后的传输测试信号的误码率；传输测试信号的传输速率范围为：[10Gbps，25Gbps]。
可选地，SerDes测试芯片103，是设置为：在传输测试信号的格式为4脉冲幅度调制(4Pulse Amplitude ModulaTIon，PAM4)格式的情况下，对接收到的承载串扰信号的衰减后的传输测试信号的误码率进行测试评估的结果为：
Figure PCTCN2019121842-appb-000002
其中，x为承载串扰信号的衰减后的传输测试信号的传输比特个数；μ为承载串扰信号的衰减后的传输测试信号的误码个数；σ为承载串扰信号的衰减后的传输测试信号的误码率；传输测试信号的传输速率范围为[50Gbps,56Gbps]。
在本实施例中，芯片测试器件100，还包括：第一测试探头104，第二测试探头105，第三测试探头106及印制电路板(Printed Circuit Board，PCB)板107；
其中，PCB板107上设置有第一信号传输线1071、第二信号传输线1072和第三信号传输线1073；
第一信号传输线1071，设置为将SerDes测试芯片103的第一信号输出管脚输出的传输测试信号传输至第一测试探头104；
第二信号传输线1072，设置为将SerDes测试芯片103的第二信号输出管脚输出的串扰测试信号传输至第二测试探头105；
第三信号传输线1073，设置为将第三测试探头106接收到的承载串扰信号的传输测试信号传输至SerDes测试芯片103的测试管脚；
第一测试探头104，设置为将传输测试信号通过传输线缆传输至传输ISI衰减器件200；
第二测试探头105，设置为将串扰测试信号通过传输线缆传输至串扰ISI衰减器件300；
第三测试探头106，设置为通过传输线缆接收XTK测试器件400传输的承载串扰信号的衰减后的传输测试信号。
在本实施例中，对第一测试探头104，第二测试探头105，及第三测试探头106不做限定，可以是相同的测试探头，也可以是不同的测试探头；其中，第一测试探头104，第二测试探头105，及第三测试探头106为以下测试探头中的一种或多种：形状记忆合金(Shape Memory Alloys，SMA)测试探头，MCX测试探头，及BCN测试探头。
例如：第一信号传输线1071，设置为将SerDes测试芯片103的第一信号输出管脚从焊球阵列封装(Ball Grid Array，BGA)扇出过孔输出的第一PRBS码信号传输至第一SMA测试探头104；
第二信号传输线1072，设置为将SerDes测试芯片103的第二信号输出管脚从BGA扇出过孔输出的第二PRBS码信号传输至第二SMA测试探头105；
第三信号传输线1073，设置为将第三SMA测试探头106接收到的携带串扰信号的第一PRBS码信号传输至SerDes测试芯片103的测试管脚的BGA扇出过孔。
通过不同的第一信号传输线1071、第二信号传输线1072和第三信号传输线1073的测试组合，对对应的第一PRBS码信号、第二PRBS码信号和携带串扰信号的第一PRBS码信号进行传输测试，如表1所示：
表1：
Figure PCTCN2019121842-appb-000003
可选地，PCB板107上还设置有测试传输线111；传输测试信号的质量参数还包括：传输测试信号在PCB板107上设置的测试传输线111上传输的插入损耗；SerDes测试芯片103，还设置为：在测试信号控制指令的控制下，基于时钟信号生成多个设定频率的传输测试信号；控制多个设定频率的传输测试信号分别在PCB板107上设置的测试传输线111上进行传输，以获取每一个设定频率的传输测试信号在PCB板107上设置的测试传输线111上传输的插入损耗。
在本实施例中，对测试传输线111长度不做限定，可以根据工程经验进行设置，也可以根据高速链路系统中PCB板传输高速链路信号的需求进行设置。通过生成多个设定频率的传输测试信号分别在PCB板107上设置的测试传输线111进行传输，以分别获取每一种设定频率的传输测试信号在PCB板107上设置的测试传输线111上传输的插入损耗，有效简化了对PCB板107上设置的测试传输线111的插入损耗测试步骤，避免了多次制备高速链路系统PCB测试板对高速链路信号的插入损耗进行测试导致的步骤繁琐，测试成本过高的缺陷；同时避免了通过计算机仿真高速链路系统PCB板对高速链路信号的插入损耗进行测试评估，测试结果不精确的弊端，有效提高了高速链路信号在PCB板中进行传输的插入损耗测试精度。
在本实施例中，可以将多个设定频率的传输测试信号分别在PCB板107上 设置的测试传输线111上进行传输测试，得到的插入损耗制备为表格，以方便对每一种设定频率的传输测试信号在PCB板107上设置的测试传输线111上进行传输，得到的插入损耗进行对比。
可选地，PCB板107包括：多种设定材质的PCB板107；其中，每一种设定材质的PCB板107均设置有相同的测试传输线111；传输测试信号的质量参数还包括：传输测试信号在每一种设定材质的PCB板107上设置的测试传输线111上传输的插入损耗；SerDes测试芯片103，还设置为：在测试信号控制指令的控制下，基于时钟信号生成多个设定频率的传输测试信号；控制多个设定频率的传输测试信号分别在每一种设定材质的PCB板107上设置的测试传输线111上进行传输，以获取每一个设定频率的传输测试信号在每一种设定材质的PCB板107上设置的测试传输线111上传输的插入损耗。
通过控制多个设定频率的传输测试信号分别在不同材质的PCB板107上的测试传输线111进行传输测试，以得到每一个设定频率的传输测试信号在测试传输线111的插入损耗，有效简化了对PCB板107上设置的测试传输线111的插入损耗测试步骤，避免了多次制备不同材质的高速链路系统PCB测试板对高速链路信号的插入损耗进行测试导致的步骤繁琐，测试成本过高的缺陷；同时避免了通过计算机仿真进行不同材质高速链路系统PCB板对高速链路信号的插入损耗进行测试评估，测试结果不精确的弊端，有效提高了高速链路信号在不同材质的PCB板中进行传输的插入损耗测试精度。
例如：PCB板107包括：FR4(一种耐热材料等级的编号)材质的PCB板107，M4(Megtron4)材质的PCB板107，及M6(Megtron6)材质的PCB板107；其中，每一种材质的PCB板107均设置有相同的测试传输线111；传输测试信号的质量参数还包括：传输测试信号在每一种材质的PCB板107上设置的测试传输线111上传输的插入损耗；SerDes测试芯片103，还设置为：在测试信号控制指令的控制下，基于时钟信号生成多个设定频率(1GHz、2GHz、3GHz、5GHz、10GHz、14GHz和20GHz)的传输测试信号；控制每一个设定频率的传输测试信号在每一种设定材质的PCB板107上设置的测试传输线111上进行传输，以获取每一个设定频率的传输测试信号在每一种设定材质的PCB板107上设置的测试传输线111上传输的插入损耗(如表2所示)。
表2：
  1GHz 2GHz 3GHz 5GHz 10GHz 14GHz 20GHz
FR4 -7.5 -13.3 -19.9 -34.8      
M4 -4.9 -7.7 -10.2 -14.8 -26.3 -36.7  
M6 -4.14 -6.08 -8 -10.8 -19 -25 -33.9
根据表2中FR4、M4和M6这三种材质的PCB板能容忍的插入损耗情况，FR4材质的PCB板在5GHz频点的插入损耗就已经达到了-34.8dB，M4材质的PCB板在10GHz频点的插入损耗值为-36.7dB，相比FR4材质的PCB，M4材质 的PCB板在同样长度的传输线下，信号传输在更高频的插入损耗更小，而M6材质的PCB板在20GHz频点的插入损耗为-33.9dB，相比FR4材质的PCB板和M4材质的PCB板，在同样长度的情况下，M6材质的PCB板更适用于高速链路。
可选地，PCB板107上还设置有多个不同设定长度的测试传输线111；传输测试信号的质量参数还包括：传输测试信号在PCB板107上设置的多个不同设定长度的测试传输线111上传输的插入损耗；SerDes测试芯片103，还设置为：控制传输测试信号分别在PCB板107上设置的多个不同设定长度的测试传输线111上进行传输，以获取传输测试信号在每一种设定长度的测试传输线111上传输的插入损耗。
通过传输测试信号分别在PCB板107上的不同长度的测试传输线111进行传输测试，以得到传输测试信号在不同长度的测试传输线111的插入损耗，有效简化了对PCB板107上设置的测试传输线111的插入损耗测试步骤，避免了多次制备不同长度的测试传输线的高速链路系统PCB测试板对高速链路信号的插入损耗进行测试导致的步骤繁琐，测试成本过高的缺陷；同时避免了通过计算机仿真进行不同长度测试传输线的高速链路系统PCB板对高速链路信号的插入损耗进行测试评估，测试结果不精确的弊端，有效提高了高速链路信号在不同长度的测试传输线的PCB板中进行传输的插入损耗测试精度。
例如，FR4、M4和M6这三种材质的PCB板107上分别设置有0.4m长度的测试传输线111、0.5m长度的测试传输线111、0.7m长度的测试传输线111、1.2m长度的测试传输线111、1.6m长度的测试传输线111、2.1m长度的测试传输线111和3.1m长度的测试传输线111；传输测试信号的质量参数还包括：传输测试信号在PCB板107上设置的设定长度的测试传输线111上传输的插入损耗；SerDes测试芯片103，还设置为：控制传输测试信号在PCB板107上设置的每一种设定长度的传输线111上进行传输，以获取传输测试信号在每一种设定长度传输线111上传输的插入损耗(如表3所示)。
表3：
  1GHz 2GHz 3GHz 5GHz 10GHz 14GHz 20GHz
FR4 1.6 1 0.7 0.4      
M4 2.7 1.7 1.3 0.9 0.5 0.4  
M6 3.1 2.1 1.6 1.2 0.7 0.5 0.4
根据已有的表3，以10Gbps SerDes速率，插损为-13dB，来评估高速链路系统的PCB板的信号传输线长度，在表3对应相同的10GHz的频点，FR4材质的PCB板107的信号传输线长度只有0.4m，M4材质的PCB板107的信号传输线长度为0.9m，M6材质的PCB板107的信号传输线长度为1.2m。
可选地，传输测试信号的质量参数还包括：每个预设温度下传输测试信号 在PCB板107上设置的测试传输线111上传输的插入损耗；SerDes测试芯片103，还设置为：在多个预设温度下，分别控制传输测试信号在PCB板107上设置的测试传输线111上进行传输，以获取每个预设温度下传输测试信号在PCB板107上设置的测试传输线111上传输的插入损耗。
通过传输测试信号分别在不同温度下的PCB板107上的不同长度测试传输线111进行传输测试，以得到传输测试信号在不同温度下测试传输线111的插入损耗，有效简化了对不同温度下PCB板107上设置的测试传输线111的插入损耗测试步骤，避免了多次制备不同长度的测试传输线的高速链路系统PCB测试板对高速链路信号的插入损耗进行测试导致的步骤繁琐，以及测试成本过高的缺陷；同时避免了无法通过计算机仿真在不同温度下高速链路系统PCB板对高速链路信号的插入损耗进行测试评估的弊端，有效提高了不同温度下高速链路信号在PCB板的测试传输线中进行传输的插入损耗测试精度。
可选地，PCB板107包括：多种设定工艺加工的PCB板107；每一种设定工艺加工的PCB板107均设置有测试传输线111；传输测试信号的质量参数还包括：传输测试信号在每种设定工艺加工的PCB板107上设置的测试传输线111上传输的插入损耗；SerDes测试芯片103，还设置为：控制传输测试信号在每一种设定工艺加工的PCB板107上设置的测试传输线111上进行传输，以获取传输测试信号在每一设定工艺加工的PCB板107上设置的测试传输线111上传输的插入损耗。
通过传输测试信号分别在不同加工工艺下制备的PCB板107上的测试传输线111进行传输测试，以得到传输测试信号在测试传输线111的插入损耗，有效简化了对不同加工工艺下制备的PCB板107上设置的测试传输线111的插入损耗测试步骤，避免了多次制备不同加工工艺的高速链路系统PCB测试板对高速链路信号的插入损耗进行测试导致的步骤繁琐，以及测试成本过高的缺陷；同时避免了无法通过计算机仿真在不同加工工艺的高速链路系统PCB板对高速链路信号的插入损耗进行测试评估的弊端，有效提高了高速链路信号在PCB板的测试传输线中进行传输的插入损耗测试精度。
在本实施例中，传输测试信号的格式包括以下信号之一：PRBS码信号，NRZ码信号等；串扰测试信号的格式包括以下信号之一：PRBS码信号，NRZ码信号等；其中，传输测试信号可以是与串扰测试信号具有相同格式的信号，也可以是与串扰测试信号具有不同格式的信号。
在本实施例中，对传输ISI衰减器件200对接收到的传输测试信号进行衰减的方式不做限定，可以是将接收到的传输测试信号衰减至设定值，也可以是以预设的时间间隔将接收到的传输测试信号依次衰减至多个设定值。
在本实施例中，对串扰ISI衰减器件300对接收到的串扰测试信号进行衰减的方式不做限定，可以是将接收到的串扰测试信号衰减至设定值，也可以是以预设的时间间隔将接收到的串扰测试信号依次衰减至多个设定值。
在本实施例中，对质量参数不做限定，可以是误码率，也可以是传输插入损耗等参数。
可选地，芯片测试器件100，是设置为：基于接收到的传输信号控制指令，生成传输测试信号，并将传输测试信号发送至传输ISI衰减器件200；基于接收到的串扰信号控制指令，生成串扰测试信号，并将串扰测试信号发送至串扰ISI衰减器件300。
本公开第二实施例所述的装置，有效提高了对承载串扰信号的传输测试信号的质量参数测试评估精度，避免了通过计算机仿真带来的承载串扰信号的传输测试信号的质量参数测试评估的缺陷；简化了对承载串扰信号的传输测试信号的质量参数测试评估步骤，提高了对承载串扰信号的传输测试信号的质量参数测试评估效率，避免了通过制备多个不同的高速链路系统测试电路，对承载串扰信号的传输测试信号的质量参数进行测试评估，导致的测试步骤繁琐，测试周期过长的缺陷；同时，通过在PCB板上的测试传输线传输不同频率的传输测试信号，或者在不同材质的PCB板上的测试传输线传输测试信号，或者在不同加工工艺的PCB板上的测试传输线传输测试信号，或者在不同加工工艺的PCB板上的测试传输线传输测试信号，或者在不同温度下PCB板上的测试传输线传输测试信号，以获取PCB板上的测试传输线传输测试信号的插入损耗，有效提高了PCB板上的测试传输线传输测试信号的插入损耗测试效率，避免了多次制备高速链路系统PCB测试板对高速链路信号的插入损耗进行测试导致的步骤繁琐，以及测试成本过高的缺陷；同时避免了无法通过计算机仿真高速链路系统PCB板对高速链路信号的插入损耗进行测试评估的弊端，或者避免了通过计算机仿真高速链路系统PCB板对高速链路信号的插入损耗进行测试评估，测试结果不精确的弊端，有效提高了高速链路信号在测试传输线的PCB板中进行传输的插入损耗测试精度。
本公开第三实施例提供了一种高速链路系统的测试方法，如图3所示，该测试方法包括S3010至S3030。
S3010，根据预置的测试参数，对传输测试信号和串扰测试信号分别进行衰减。
其中，测试参数包括：传输测试信号的衰减参数，以及串扰测试信号的衰减参数。
在本实施例中，对传输测试信号的衰减参数不做限定，可以是将传输测试信号衰减至设定值，也可以是将传输测试信号衰减设定衰减幅度值，也可以是将传输测试信号进行梯度衰减的衰减幅度值。
在本实施例中，对串扰测试信号的衰减参数不做限定，可以是将串扰测试信号衰减至设定值，也可以是将串扰测试信号衰减设定衰减幅度值，也可以是将串扰测试信号进行梯度衰减的衰减幅度值。在本实施例中，根据信号的衰减 参数，对传输测试信号和串扰测试信号分别进行衰减的方式，包括以下方式之一：
方式一，根据预置的测试参数，对传输测试信号和串扰测试信号分别衰减至设定信号幅度值；
方式二，根据预置的测试参数，对传输测试信号和串扰测试信号分别衰减设定衰减幅度值；
方式三，根据预置的测试参数，对传输测试信号和串扰测试信号分别进行梯度衰减。
在本实施例中，传输测试信号的格式包括以下信号之一：PRBS码信号，NRZ码信号等；串扰测试信号的格式包括以下信号之一：PRBS码信号，NRZ码信号等；其中，传输测试信号可以是与串扰测试信号具有相同格式的信号，也可以是与串扰测试信号具有不同格式的信号。
S3020，将衰减后的串扰测试信号在衰减后的传输测试信号中形成串扰信号。
通过将衰减后的串扰测试信号在衰减后的传输测试信号中形成串扰信号，以控制不同幅度值的串扰测试信号在不同幅度值的传输测试信号中形成串扰信号，实现了多种幅度值的串扰测试信号在多种幅度值的传输测试信号中形成串扰信号，有效提高了测试评估承载串扰信号的传输测试信号的误码率的精度，避免了只能测试评估一种幅度值的串扰测试信号在一种幅度值的传输测试信号中形成的串扰信号，而不能测试评估其他幅度值的串扰测试信号在该幅度值的传输测试信号中形成的串扰信号，或者不能测试评估该幅度值的串扰测试信号在其他幅度值的传输测试信号中形成的串扰信号，提高了测试评估效率，也提高了测试评估的精度。
S3030，测试评估承载串扰信号的衰减后的传输测试信号的误码率。
本公开第三实施例所述的方法，有效提高了对承载串扰信号的传输测试信号的误码率测试评估精度，避免了通过计算机仿真带来的承载串扰信号的传输测试信号的误码率测试评估的缺陷；简化了对承载串扰信号的传输测试信号的误码率测试评估步骤，提高了对承载串扰信号的传输测试信号的误码率测试评估效率。
本公开第四实施例提供了一种高速链路系统的测试方法，如图3所示，该测试方法包括S3010至S3030。
S3010，根据预置的测试参数，对传输测试信号和串扰测试信号分别进行衰减。
其中，测试参数包括：传输测试信号的衰减参数，以及串扰测试信号的衰 减参数。
可选地，S3010，包括：
对所述传输测试信号进行插损梯度扫描，以通过对应的插损梯度通道对所述传输测试信号进行衰减；以及
对所述串扰测试信号进行插损梯度扫描，以通过对应的插损梯度通道对所述串扰测试信号进行衰减。。
在本实施例中，传输测试信号的格式包括以下信号之一：PRBS码信号，NRZ码信号等；串扰测试信号的格式包括以下信号之一：PRBS码信号，NRZ码信号等；其中，传输测试信号可以是与串扰测试信号具有相同格式的信号，也可以是与串扰测试信号具有不同格式的信号。
S3020，将衰减后的串扰测试信号在衰减后的传输测试信号中形成串扰信号。
通过将衰减后的串扰测试信号在衰减后的传输测试信号中形成串扰信号，以控制不同幅度值的串扰测试信号在不同幅度值的传输测试信号中形成串扰信号，实现了多种幅度值的串扰测试信号在多种幅度值的传输测试信号中形成串扰信号，有效提高了测试评估承载串扰信号的传输测试信号的误码率的精度，避免了只能测试评估一种幅度值的串扰测试信号在一种幅度值的传输测试信号中形成的串扰信号，而不能测试评估其他幅度值的串扰测试信号在该幅度值的传输测试信号中形成的串扰信号，或者不能测试评估该幅度值的串扰测试信号在其他幅度值的传输测试信号中形成的串扰信号，提高了测试评估效率，也提高了测试评估的精度。
S3030，测试评估承载串扰信号的衰减后的传输测试信号的误码率。
可选地，S3030，包括：在传输测试信号的格式为NRZ格式的情况下，对承载串扰信号的衰减后的传输测试信号的误码率进行测试评估的结果为：
Figure PCTCN2019121842-appb-000004
其中，n为承载串扰信号的衰减后的传输测试信号的传输比特个数；k为承载串扰信号的衰减后的传输测试信号的误码个数；p为承载串扰信号的衰减后的传输测试信号的误码率；传输测试信号的传输速率范围为：[10Gbps，25Gbps]。Pn(k)为误码个数为误码个数为k时的误码率。
可选地，S3030，包括：在传输测试信号的格式为PAM4格式的情况下，对承载所述串扰信号的衰减后的传输测试信号的误码率进行测试评估的结果为：
Figure PCTCN2019121842-appb-000005
其中，x为承载所述串扰信号的衰减后的传输测试信号的传输比特个数；μ 为承载所述串扰信号的衰减后的传输测试信号的误码个数；σ为承载所述串扰信号的衰减后的传输测试信号的误码率；所述传输测试信号的传输速率范围为[50Gbps,56Gbps]。g(x)为传输比特个数为x时的误码率。
在本实施例中，测试参数还包括以下参数中的一种或多种：PCB板上设置的测试传输线长度，PCB板的材质，PCB板的加工工艺，以及测试温度；该方法还包括S304，其中，S304，包括：根据测试参数，测试传输测试信号在PCB板上设置的测试传输线上传输的插入损耗。
在本实施例中，S304，包括以下方式中的一种或多种：
方式一，控制多个设定频率的传输测试信号分别在PCB板上设置的测试传输线上进行传输，以获取每一个设定频率的传输测试信号在PCB板上设置的测试传输线上传输的插入损耗。
方式二，控制每一个设定频率的传输测试信号在每一种设定材质的PCB板上设置的测试传输线上进行传输，以获取每一个设定频率的传输测试信号在每一种设定材质的PCB板上设置的测试传输线上传输的插入损耗。
方式三，控制传输测试信号分别在多种设定材质的PCB板上设置的多个不同设定长度的传输线上进行传输，以获取传输测试信号在每一种设定长度的传输线上传输的插入损耗。
方式四，在多个预设温度下，分别控制传输测试信号在PCB板上设置的测试传输线上进行传输，以获取每个预设温度下传输测试信号在PCB板上设置的测试传输线上传输的插入损耗。
方式五，控制传输测试信号分别在多个设定工艺加工的PCB板上设置的测试传输线上进行传输，以获取传输测试信号在每一种设定工艺加工的PCB板上设置的测试传输线上传输的插入损耗。
在本实施例中，对S304的执行顺序不做限定，可以在S3030之前执行，也可以在S3030之后执行。
本公开第四实施例所述的方法，有效提高了对承载串扰信号的传输测试信号的误码率测试评估精度，避免了通过计算机仿真带来的承载串扰信号的传输测试信号的误码率测试评估的缺陷；简化了对承载串扰信号的传输测试信号的误码率测试评估步骤，提高了对承载串扰信号的传输测试信号的误码率测试评估效率。
本公开第五实施例，本实施例是在上述实施例的基础上，以一种测试方法为例，介绍一个本公开的应用实例。
系统链路整个通道中，线卡BGA焊盘及扇出过孔，通过PCB板的信号传输线连接线卡正交连接器及Footprint(管脚)，并连接交换板正交连接器及 Footprint，线卡BGA焊盘及扇出过孔通过PCB板的信号传输线连接交换板BGA焊盘及扇出过孔。这个测试环境直接模拟高速链路系统，测试板主芯片的高速SerDes可支持10.3125Gbps、25.78125Gbps或53.125Gbps的速率。
S601，在固定50Gbps速率和PCB板的信号传输线的情况下，对系统插损串扰进行评估，对同一通道进行插损遍历。
其中，通道插损梯度为2dB@12.5GHz。
S602，对不同通道进行串扰遍历，串扰梯度为0.5mv，启用linktraining(链路协商)。
S603，对不同系统链路插损对应的不同串扰的多个情况(case)进行误码测试，以开前向纠错(Forward Error Correction，FEC)12个小时，framer error不超过15个为无误码标准。
通过上述测试方法，测试得出插损与串扰的表格，根据表格可以绘制曲线图，可以直观的看出不同插损，不同串扰对应的误码率；根据上述评估方法，可以评估在10G/25G/50G速率下的误码率是否为较优误码情况。
本公开第六实施例，本实施例是在上述实施例的基础上，以一种测试方法为例，介绍一个本公开的应用实例。
系统链路整个通道中，线卡BGA焊盘及扇出过孔，通过PCB板的信号传输线连接线卡正交连接器及Footprint，并连接交换板正交连接器及Footprint，线卡BGA焊盘及扇出过孔通过PCB板的信号传输线连接交换板BGA焊盘及扇出过孔。
S701，以50Gbps速率，通过改变PCB板的信号传输线长度，对系统链路插损进行测试评估。
S702，对同一通道进行插损遍历；其中，通道插损梯度为2dB@12.5GHz。
S703，在将插损梯度都遍历后，根据上述测试评估方法，会得出一个表格，由于此测试(demo)板主芯片支持-30dB的插损，因此在30dB以内的插损都是可以容忍的线长，进而可以实现对不同系统的走线长度进行评估。
本公开第七实施例，本实施例是在上述实施例的基础上，以一种测试方法为例，介绍一个本公开的应用实例。
系统链路整个通道中，线卡BGA焊盘及扇出过孔，通过PCB板的信号传输线连接线卡正交连接器及Footprint，并连接交换板正交连接器及Footprint，线卡BGA焊盘及扇出过孔通过PCB板的信号传输线连接交换板BGA焊盘及扇出过孔。
S801，以固定50Gbps速率和PCB板的信号传输线的情况下，改变温度，得到系统链路插损温升增量计算表格；
仿真结果为系统温升40度插损增加1.7dB。
S802，对系统高温插损进行验证，对同一通道进行插损遍历；其中，通道插损梯度为2dB@12.5GHz。
S803，在将插损梯度都遍历后，得到系统高温插损测试表格。
由于此demo板主芯片支持-30dB的插损，因此在30dB以内的插损都是可以容忍的温升，进而可以实现对不同系统的线卡、交换板的温升评估并实现对仿真结果的验证，仿真结果为在常温系统插损最大25.3dB@13.28GHz的情况下，高温系统插损增大1.4dB。
本公开第八实施例，本实施例是在上述实施例的基础上，以一种测试方法为例，介绍一个本公开的应用实例。
系统链路整个通道由线卡BGA焊盘及扇出过孔，通过PCB板的信号传输线连接线卡正交连接器及Footprint；并连接交换板正交连接器及Footprint，通过PCB板的信号传输线连接交换板BGA焊盘及扇出过孔组成。
S901，以固定50Gbps速率，对不同加工工艺的demo板进行系统评估。
S902，对同一通道，进行插损遍历；其中，通道插损梯度为2dB@12.5GHz。
S903，将插损梯度都遍历后，得到系统评估插损测试表格。
由于此demo板主芯片支持30dB的插损，因此对于超出插损标准要求的加工工艺都是不可取的，并可以实现对不同系统的线卡、交换板的加工工艺的评估。
在一实施例中，在本文中，术语“包括”、“包含”或者其其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
通过以上的实施方式的描述上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，也可以通过硬件实现。本公开的技术方案可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如只读存储器/随机存取存储器(Read-Only Memory/Random Access Memory，ROM/RAM)、磁碟、光盘)中，包括一个或多个指令用以使得一台终端(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本公开多个实施例所述的方法。

Claims (17)

  1. 一种高速链路系统的测试装置，包括：芯片测试器件、传输插入损耗ISI衰减器件、串扰ISI衰减器件和串扰XTK测试器件；
    所述芯片测试器件，设置为将生成的传输测试信号传输至所述传输ISI衰减器件，并将生成的串扰测试信号传输至所述串扰ISI衰减器件；
    所述传输ISI衰减器件，设置为对接收到的所述传输测试信号进行衰减，并将衰减后的传输测试信号传输至所述XTK测试器件；
    所述串扰ISI衰减器件，设置为对接收到的所述串扰测试信号进行衰减，并将衰减后的串扰测试信号传输至所述XTK测试器件；
    所述XTK测试器件，设置为将接收到的衰减后的串扰测试信号在接收到的衰减后的传输测试信号中形成串扰信号，并将承载所述串扰信号的衰减后的传输测试信号传输至所述芯片测试器件；
    所述芯片测试器件，还设置为对承载所述串扰信号的衰减后的传输测试信号的质量参数进行测试评估。
  2. 根据权利要求1所述的装置，其中，所述传输ISI衰减器件，是设置为：对接收到的所述传输测试信号进行插损梯度扫描，以通过对应的插损梯度通道对所述传输测试信号进行衰减。
  3. 根据权利要求1或2所述的装置，其中，所述串扰ISI衰减器件，是设置为：对接收到的所述串扰测试信号进行插损梯度扫描，以通过对应的插损梯度通道对所述串扰测试信号进行衰减。
  4. 根据权利要求1所述的装置，其中，所述传输测试信号的质量参数包括：所述传输测试信号的误码率；
    所述芯片测试器件，包括：时钟芯片，控制管理器件，及串行器/解串器SerDes测试芯片；
    所述控制管理器件，设置为将时钟控制指令发送至所述时钟芯片，并将测试信号控制指令发送至所述SerDes测试芯片；
    所述时钟芯片，设置为在所述时钟控制指令的控制下，生成设定频率的时钟信号，并将所述时钟信号传输至所述SerDes测试芯片；
    所述SerDes测试芯片，设置为在所述测试信号控制指令的控制下，基于所述时钟信号生成所述传输测试信号，及所述串扰测试信号；对接收到的承载所述串扰信号的衰减后的传输测试信号的误码率进行测试评估。
  5. 根据权利要求4所述的装置，其中，所述SerDes测试芯片，是设置为：
    在所述传输测试信号的格式为不归零码NRZ格式的情况下，对接收到的承载所述串扰信号的衰减后的传输测试信号的误码率进行测试评估的结果为：
    Figure PCTCN2019121842-appb-100001
    其中，所述n为承载所述串扰信号的衰减后的传输测试信号的传输比特个数；所述k为承载所述串扰信号的衰减后的传输测试信号的误码个数；所述p为承载所述串扰信号的衰减后的传输测试信号的误码率；所述传输测试信号的传输速率范围为：[10千兆比特每秒Gbps，25Gbps]。
  6. 根据权利要求4所述的装置，其中，所述SerDes测试芯片，是设置为：
    在所述传输测试信号的格式为脉冲幅度调制PAM4格式的情况下，对接收到的承载所述串扰信号的衰减后的传输测试信号的误码率进行测试评估的结果为：
    Figure PCTCN2019121842-appb-100002
    其中，所述x为承载所述串扰信号的衰减后的传输测试信号的传输比特个数；所述μ为承载所述串扰信号的衰减后的传输测试信号的误码个数；所述σ为承载所述串扰信号的衰减后的传输测试信号的误码率；所述传输测试信号的传输速率范围为[50Gbps，56Gbps]。
  7. 根据权利要求4所述的装置，其中，所述芯片测试器件，还包括：第一测试探头，第二测试探头，第三测试探头及印刷电路板PCB板；
    所述PCB板上设置有第一信号传输线、第二信号传输线和第三信号传输线；
    所述第一信号传输线，设置为将所述SerDes测试芯片的第一信号输出管脚输出的所述传输测试信号传输至所述第一测试探头；
    所述第二信号传输线，设置为将所述SerDes测试芯片的第二信号输出管脚输出的所述串扰测试信号传输至所述第二测试探头；
    所述第三信号传输线，设置为将所述第三测试探头接收到的承载所述串扰信号的传输测试信号传输至所述SerDes测试芯片的测试管脚；
    所述第一测试探头，设置为将所述传输测试信号通过传输线缆传输至所述传输ISI衰减器件；
    所述第二测试探头，设置为将所述串扰测试信号通过传输线缆传输至所述串扰ISI衰减器件；
    所述第三测试探头，设置为通过传输线缆接收所述XTK测试器件传输的承载所述串扰信号的衰减后的传输测试信号。
  8. 根据权利要求7所述的装置，其中，所述PCB板上还设置有测试传输线；所述传输测试信号的质量参数还包括：所述传输测试信号在所述PCB板上设置的测试传输线上传输的插入损耗；
    所述SerDes测试芯片，还设置为：
    在所述测试信号控制指令的控制下，基于所述时钟信号生成多个设定频率的所述传输测试信号；
    控制所述多个设定频率的所述传输测试信号分别在所述PCB板上设置的测试传输线上进行传输，以获取每一个设定频率的所述传输测试信号在所述PCB板上设置的测试传输线上传输的插入损耗。
  9. 根据权利要求7所述的装置，其中，所述PCB板包括：多种设定材质的PCB板；其中，每一种设定材质的PCB板均设置有相同的测试传输线；所述传输测试信号的质量参数还包括：所述传输测试信号在每一种设定材质的PCB板上设置的测试传输线上传输的插入损耗；
    所述SerDes测试芯片，还设置为：
    在所述测试信号控制指令的控制下，基于所述时钟信号生成多个设定频率的所述传输测试信号；
    控制所述多个设定频率的所述传输测试信号分别在每一种设定材质的PCB板上设置的测试传输线上进行传输，以获取每一种设定频率的所述传输测试信号在每一种设定材质的PCB板上设置的测试传输线上传输的插入损耗。
  10. 根据权利要求7所述的装置，其中，所述PCB板上还设置有多个不同设定长度的测试传输线；所述传输测试信号的质量参数还包括：所述传输测试信号在所述PCB板上设置的多个不同设定长度的测试传输线上传输的插入损耗；
    所述SerDes测试芯片，还设置为：
    控制所述传输测试信号分别在所述PCB板上设置的多个不同设定长度的测试传输线上进行传输，以获取所述传输测试信号在每一种设定长度的测试传输线上传输的插入损耗。
  11. 根据权利要求7所述的装置，其中，所述传输测试信号的质量参数还包括：每个预设温度下所述传输测试信号在所述PCB板上设置的测试传输线上传输的插入损耗；
    所述SerDes测试芯片，还设置为：
    在多个预设温度下，分别控制所述传输测试信号在所述PCB板上设置的测试传输线上进行传输，以获取每个预设温度下所述传输测试信号在所述PCB板上设置的测试传输线上传输的插入损耗。
  12. 根据权利要求7所述的装置，其中，所述PCB板包括：多种设定工艺加工的PCB板；每一种设定工艺加工的PCB板均设置有测试传输线；
    所述传输测试信号的质量参数还包括：所述传输测试信号在每种设定工艺加工的PCB板上设置的测试传输线上传输的插入损耗；
    所述SerDes测试芯片，还设置为：
    控制所述传输测试信号在每一种设定工艺加工的PCB板上设置的测试传输线上进行传输，以获取所述传输测试信号在每一种设定工艺加工的PCB板上设置的测试传输线上传输的插入损耗。
  13. 一种高速链路系统的测试方法，包括：
    根据预置的测试参数，对传输测试信号和串扰测试信号分别进行衰减；其中，所述测试参数包括：所述传输测试信号的衰减参数，以及所述串扰测试信号的衰减参数；
    将衰减后的串扰测试信号在衰减后的传输测试信号中形成串扰信号；
    测试评估承载所述串扰信号的衰减后的传输测试信号的误码率。
  14. 根据权利要求13所述的方法，其中，所述对传输测试信号和串扰测试信号分别进行衰减，包括：
    对所述传输测试信号进行插损梯度扫描，以通过对应的插损梯度通道对所述传输测试信号进行衰减；以及
    对所述串扰测试信号进行插损梯度扫描，以通过对应的插损梯度通道对所述串扰测试信号进行衰减。
  15. 根据权利要求13所述的方法，其中，所述测试评估承载所述串扰信号的衰减后的传输测试信号的误码率，包括：
    在所述传输测试信号的格式为不归零码NRZ格式的情况下，对承载所述串扰信号的衰减后的传输测试信号的误码率进行测试评估的结果为：
    Figure PCTCN2019121842-appb-100003
    其中，所述n为承载所述串扰信号的衰减后的传输测试信号的传输比特个数；所述k为承载所述串扰信号的衰减后的传输测试信号的误码个数；所述p为承载所述串扰信号的衰减后的传输测试信号的误码率；所述传输测试信号的传输速率范围为：[10千兆比特每秒Gbps，25Gbps]。
  16. 根据权利要求13所述的方法，其中，所述测试评估承载所述串扰信号的传输测试信号的误码率，包括：
    在所述传输测试信号的格式为脉冲幅度调制PAM4格式的情况下，对承载所述串扰信号的衰减后的传输测试信号的误码率进行测试评估的结果为：
    Figure PCTCN2019121842-appb-100004
    其中，所述x为承载所述串扰信号的衰减后的传输测试信号的传输比特个数；所述μ为承载所述串扰信号的衰减后的传输测试信号的误码个数；所述σ为 承载所述串扰信号的衰减后的传输测试信号的误码率；所述传输测试信号的传输速率范围为[50Gbps，56Gbps]。
  17. 根据权利要求13所述的方法，其中，所述测试参数还包括以下参数中的一种或多种：印刷电路板PCB板上设置的测试传输线长度，所述PCB板的材质，所述PCB板的加工工艺，以及测试温度；所述方法还包括：
    根据所述测试参数，测试所述传输测试信号在所述PCB板上设置的测试传输线上传输的插入损耗。
PCT/CN2019/121842 2018-11-29 2019-11-29 高速链路系统的测试装置及方法 WO2020108589A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811445288.8 2018-11-29
CN201811445288.8A CN111245530B (zh) 2018-11-29 2018-11-29 一种高速链路系统的测试装置及方法

Publications (1)

Publication Number Publication Date
WO2020108589A1 true WO2020108589A1 (zh) 2020-06-04

Family

ID=70854363

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/121842 WO2020108589A1 (zh) 2018-11-29 2019-11-29 高速链路系统的测试装置及方法

Country Status (2)

Country Link
CN (1) CN111245530B (zh)
WO (1) WO2020108589A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114221719A (zh) * 2020-09-04 2022-03-22 安立股份有限公司 误码率测量装置及误码率测量方法
CN115291075A (zh) * 2022-06-24 2022-11-04 杭州未名信科科技有限公司 一种高速信号质量的测试方法和测试装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1921327A (zh) * 2005-08-03 2007-02-28 安捷伦科技有限公司 外来串扰测试信号单元的互连和控制
CN101543027A (zh) * 2007-03-22 2009-09-23 罗德施瓦兹两合股份有限公司 用于对移动无线终端进行交替测试的开关设备
CN103026637A (zh) * 2010-06-01 2013-04-03 电缆感测有限公司 用于识别端口间的线缆连接的信号处理设备和方法
US20170012718A1 (en) * 2015-07-10 2017-01-12 Broadcom Corporation Device and method for detecting and measuring alien crosstalk in greater than 1000base-t operations

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7072415B2 (en) * 1999-10-19 2006-07-04 Rambus Inc. Method and apparatus for generating multi-level reference voltage in systems using equalization or crosstalk cancellation
CN101068118A (zh) * 2007-06-27 2007-11-07 中兴通讯股份有限公司 测量线缆串扰、长度以及线路衰减的方法及系统
CN101673317B (zh) * 2009-10-23 2012-02-29 中兴通讯股份有限公司 一种高速串行通道预加重调整方法及装置
CN105043718B (zh) * 2015-04-30 2017-11-21 哈尔滨工程大学 一种光学偏振器件分布式偏振串扰测量的噪声抑制装置与抑制方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1921327A (zh) * 2005-08-03 2007-02-28 安捷伦科技有限公司 外来串扰测试信号单元的互连和控制
CN101543027A (zh) * 2007-03-22 2009-09-23 罗德施瓦兹两合股份有限公司 用于对移动无线终端进行交替测试的开关设备
CN103026637A (zh) * 2010-06-01 2013-04-03 电缆感测有限公司 用于识别端口间的线缆连接的信号处理设备和方法
US20170012718A1 (en) * 2015-07-10 2017-01-12 Broadcom Corporation Device and method for detecting and measuring alien crosstalk in greater than 1000base-t operations

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114221719A (zh) * 2020-09-04 2022-03-22 安立股份有限公司 误码率测量装置及误码率测量方法
CN115291075A (zh) * 2022-06-24 2022-11-04 杭州未名信科科技有限公司 一种高速信号质量的测试方法和测试装置

Also Published As

Publication number Publication date
CN111245530B (zh) 2022-07-19
CN111245530A (zh) 2020-06-05

Similar Documents

Publication Publication Date Title
US8793541B2 (en) Link equalization tester
WO2020108589A1 (zh) 高速链路系统的测试装置及方法
CN106155950A (zh) 参数处理方法及装置
CN106443086B (zh) 一种测试基板
US9940294B2 (en) Method, apparatus, and system for configuring high-speed serial bus parameter
CN110728108A (zh) 一种超高速SerDes电路系统参数配置方法
CN108254652B (zh) 一种背板连接器的测试装置
CN101834679A (zh) 端口测试的方法、装置和系统
CN103970699A (zh) 一种调试fpga预加重均衡的方法
US11074384B1 (en) Method for simulating signal integrity of hybrid model
US9673941B2 (en) Frequency-domain high-speed bus signal integrity compliance model
CN107506540B (zh) 一种混合模型信号完整性仿真方法
CN114636919A (zh) Pcie差分信号链路的多梯度衰减测试系统、方法和电子设备
US9733305B2 (en) Frequency-domain high-speed bus signal integrity compliance model
CN107943641A (zh) 一种生成多端口s参数文档的方法及装置
Win et al. A frequency-domain high-speed bus signal integrity compliance model: Design methodology and implementation
CN112286744A (zh) 一种中央处理器物理信号电气特性测试装置、系统及方法
CN117391021A (zh) 一种仿真模型的准确性校验方法和系统
Cocchini et al. Time-domain simulation of system interconnect using convolution and Newton-Raphson iteration methods
Qi et al. MPLEG: A Multi-mode Physical Layer Error Generator for Link Layer Fault Tolerance Test
Decrock et al. DesignCon 2016
de Paulis A Novel Approach to 224 Gb/s Reference Receiver Design Using Raised Cosine Response for Noise Mitigation
Arora et al. SERDES external loopback test using production parametric-test hardware
CN116506028A (zh) 基于OpenVPX架构的电信号完整性评估测试夹具
Yao et al. Simulation Method of 32Gbps Signal Transmission Considering Xtalk Impact Using Probability Density Function

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19891490

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 04/11/2021)

122 Ep: pct application non-entry in european phase

Ref document number: 19891490

Country of ref document: EP

Kind code of ref document: A1