WO2020107597A1 - 显示面板、像素充电方法和计算机可读存储介质 - Google Patents

显示面板、像素充电方法和计算机可读存储介质 Download PDF

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Publication number
WO2020107597A1
WO2020107597A1 PCT/CN2018/123358 CN2018123358W WO2020107597A1 WO 2020107597 A1 WO2020107597 A1 WO 2020107597A1 CN 2018123358 W CN2018123358 W CN 2018123358W WO 2020107597 A1 WO2020107597 A1 WO 2020107597A1
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WIPO (PCT)
Prior art keywords
integrated circuit
gate integrated
time period
scan line
target
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/123358
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English (en)
French (fr)
Inventor
杨艳娜
宋振莉
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HKC Co Ltd
Original Assignee
HKC Co Ltd
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Filing date
Publication date
Application filed by HKC Co Ltd filed Critical HKC Co Ltd
Priority to US17/044,239 priority Critical patent/US11341885B2/en
Publication of WO2020107597A1 publication Critical patent/WO2020107597A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present application relates to the technical field of display devices, and in particular, to a display panel, a pixel charging method, and a computer-readable storage medium.
  • the display panel usually has a thin film transistor (Thin Film Transisitor, TFT) array substrate.
  • TFT Thin Film Transisitor
  • a plurality of scanning lines and a plurality of data lines are formed on the TFT array substrate, and each sub-pixel respectively receives scanning signals through corresponding scanning lines, and receives data signals through corresponding data lines to display images.
  • the data signal is transmitted from the opposite end of the data source (source end) to the source end through the data line. Due to the presence of the resistance and capacitance of the data line and other loads on the panel, the transmission of the data signal from the source end to the source side will occur Deformation causes the pixel TFT switch corresponding to the scan line to turn on with delay.
  • each gate integrated circuit (Gate IC)
  • the scan lines controlled by the same open time, that is, the set charging time of each pixel is the same, resulting in different Gate
  • the pixels corresponding to the scan lines controlled by the IC are insufficiently charged, causing problems such as uneven brightness of the entire display panel and low picture quality.
  • the main purpose of the present application is to provide a display panel, a pixel charging method and a computer-readable storage medium, aiming to solve the problems caused by insufficient pixel charging, resulting in the problem of uneven brightness of the entire display panel and low picture quality.
  • a pixel charging method provided by the present application includes the following steps:
  • the preset charging duration and the current time point are obtained, wherein the thin film transistor substrate is provided with a plurality of horizontally arranged scanning lines and a plurality of vertically arranged The data line, using the scan line with the largest relative distance from the data transmission end of the data line as the target scan line, and using the gate integrated circuit that controls the opening of the target scan line as the first gate integrated circuit;
  • Controlling the thin film transistor switches corresponding to the scan lines of each target gate integrated circuit to turn on during the pre-charge time period and the actual charging time period corresponding to the scan lines, so as to carry out the pixels corresponding to the scan lines Charging, wherein the voltage polarity of each pixel electrode corresponding to the data line on the thin film transistor substrate is the same.
  • the present application also provides a display panel, the display panel includes at least one processor, and a storage device, wherein,
  • the memory device stores computer-executable instructions executable by the at least one processor, and when the computer-executable instructions are executed by the at least one processor, causes one processor to perform the following steps:
  • the preset charging duration and the current time point are obtained, wherein the thin film transistor substrate is provided with a plurality of horizontally arranged scanning lines and a plurality of vertically arranged The data line, using the scan line with the largest relative distance from the data transmission end of the data line as the target scan line, and using the gate integrated circuit that controls the opening of the target scan line as the first gate integrated circuit;
  • Controlling the thin film transistor switches corresponding to the scan lines of each target gate integrated circuit to turn on during the pre-charge time period and the actual charging time period corresponding to the scan lines, so as to carry out the pixels corresponding to the scan lines Charging, wherein the voltage polarity of each pixel electrode corresponding to the data line on the thin film transistor substrate is the same.
  • the present application further provides a computer-readable storage medium storing computer-executable instructions executable by the at least one processor, the computer-executable instructions being When at least one processor executes, it causes one processor to perform the following steps:
  • the preset charging duration and the current time point are obtained, wherein the thin film transistor substrate is provided with a plurality of horizontally arranged scanning lines and a plurality of vertically arranged The data line, using the scan line with the largest relative distance from the data transmission end of the data line as the target scan line, and using the gate integrated circuit that controls the opening of the target scan line as the first gate integrated circuit;
  • Controlling the thin film transistor switches corresponding to the scan lines of each target gate integrated circuit to turn on during the pre-charge time period and the actual charging time period corresponding to the scan lines, so as to carry out the pixels corresponding to the scan lines Charging, wherein the voltage polarity of each pixel electrode corresponding to the data line on the thin film transistor substrate is the same.
  • the display panel, pixel charging method and computer readable storage medium provided by the present application, when the first gate integrated circuit on the opposite end of the source integrated circuit on the thin film transistor substrate is turned on, obtain the current time point and the preset charging duration to determine The pre-charge time period and the actual charging time period of the scan lines controlled by the gate integrated circuits except the first gate integrated circuit on the thin film transistor substrate, thereby controlling the thin film transistors corresponding to the scan lines of each gate integrated circuit
  • the switch is turned on during the precharge period and actual charging period corresponding to the scan line to charge the pixels corresponding to the scan line; the pixels corresponding to the scan line can be precharged in advance, ensuring the voltage of the pixels corresponding to each scan line
  • the set voltage value can be reached, thereby ensuring the uniformity of the overall brightness of the display panel, and the picture quality of the display panel is high.
  • FIG. 1 is a schematic diagram of the hardware structure of a display panel involved in an embodiment of the present application
  • FIG. 2 is a schematic flowchart of an embodiment of a pixel charging method according to this application.
  • FIG. 3 is a schematic flowchart of another embodiment of a pixel charging method according to this application.
  • FIG. 4 is a schematic flowchart of another embodiment of a pixel charging method according to this application.
  • 5A is a schematic diagram of pixel charging in an exemplary technology
  • 5B is a schematic diagram of charging a pixel in another embodiment of the present application.
  • 5C is a schematic diagram of yet another pixel charging in another embodiment of the present application.
  • FIG. 6 is a schematic flowchart of another embodiment of a pixel charging method according to this application.
  • the main solution of the embodiment of the present application is: when it is detected that the first gate integrated circuit on the thin film transistor substrate is opened, the preset charging duration and the current time point are obtained, wherein the thin film transistor substrate is provided with a plurality of horizontal arrangements Scan lines and multiple vertically arranged data lines, the scan line with the largest relative distance from the data transmission end of the data line is used as the target scan line, and the gate integrated circuit that controls the opening of the target scan line is used as the target
  • the first gate integrated circuit according to the preset charging duration and the current time point, determine corresponding to each target gate integrated circuit on the thin film transistor substrate except the first gate integrated circuit A precharge time period and an actual charging time period of the scan line; controlling the thin film transistor switches corresponding to the scan lines of each target gate integrated circuit, the precharge time period and the actual charging time corresponding to the scan line
  • the segment is turned on to charge the pixels corresponding to the scan lines, wherein the voltage polarities of the pixel electrodes corresponding to the data lines on the thin film transistor substrate are the
  • the pixels corresponding to the scan lines on the display panel can be pre-charged in advance, the voltage of the pixels corresponding to the respective scan lines can reach the set voltage value, thereby ensuring the uniformity of the overall brightness of the display panel, the display panel High quality.
  • the display panel may be as shown in FIG. 1.
  • the solution of the embodiment of the present application relates to a display panel.
  • the display panel includes: a processor 1001, such as a CPU, a memory 1002, and a communication bus 1003.
  • the communication bus 1003 is configured to implement connection communication between these components.
  • the memory 1002 may be a high-speed RAM memory or a non-volatile memory (non-volatile memory), such as a disk memory.
  • the memory 1003 as a computer storage medium may include a pixel charging program; and the processor 1001 may be configured to call the pixel charging program stored in the memory 1002 and execute the pixel charging method corresponding to the following embodiment.
  • FIG. 2 is an embodiment of a pixel charging method of the present application.
  • the pixel charging method includes the following steps:
  • Step S10 when it is detected that the first gate integrated circuit on the thin film transistor substrate is turned on, the preset charging duration and the current time point are obtained, wherein the thin film transistor substrate is provided with a plurality of horizontally arranged scanning lines and a plurality of vertical The data lines arranged in the direction, the scan line with the largest relative distance from the data transmission end of the data line is used as the target scan line, and the gate integrated circuit that controls the opening of the target scan line is integrated as the first gate Circuit
  • the thin-film transistor substrate of the display panel includes a plurality of scan lines and data lines, and the pixels on the thin-film transistor substrate receive scan signals through the scan lines and data signals through the data lines; When charging, the voltage polarities of the corresponding pixel electrodes on the data line are the same.
  • the thin film transistor substrate is provided with a plurality of gate integrated circuits, namely Gate IC, Gate
  • the IC controls the opening and closing of the scanning signal of the scanning line, and there are a plurality of source integrated circuits on the thin film transistor substrate, that is, Source IC, Source
  • the IC controls the opening and closing of the data signals of the data lines; the scanning lines are arranged laterally on the thin film transistor substrate, and the data lines are arranged vertically on the thin film transistor substrate.
  • Source The scan lines on the opposite side of the IC are sequentially turned on to turn on the pixel TFTs corresponding to the scan lines to charge the pixels.
  • the opening order of each Gate IC on the thin film transistor substrate is: distance Source The farther the scan line corresponding to the Gate IC on the IC side, the earlier it turns on, that is, the farther away the scan line from the data transmission end of the data line, the sooner the scan line opens, each Gate The opening time and closing time of the IC are connected end to end.
  • the display panel When the display panel detects that the first gate integrated circuit on the thin film transistor substrate is turned on, it obtains the preset charging duration and the current time point.
  • the first gate integrated circuit is the gate integrated circuit that is turned on first in a frame scan, and The first gate integrated circuit is located at the opposite end of the source integrated circuit, that is, the thin film transistor substrate is provided with a plurality of horizontally arranged scanning lines and a plurality of vertically arranged data lines, which will be relatively away from the data transmission end of the data line The largest scan line is used as the scan line, and the gate integrated circuit that controls the opening of the scan line is used as the first gate integrated circuit.
  • the preset charging duration refers to the charging duration set by the pixels in the display panel.
  • Step S20 determine the actual charging time of the scan line corresponding to each target gate integrated circuit on the thin film transistor substrate except the first gate integrated circuit segment;
  • Step S30 Determine the precharge period of the scan line corresponding to each target gate integrated circuit; when the first gate integrated circuit is turned on, the corresponding thin film transistor switches on the scan line controlled by the gate integrated circuit will all turn on. Since the data signal first enters the pixel corresponding to the scan line controlled by the first gate integrated circuit, the resistance and capacitance have little effect on the switching delay of the thin film transistor, so there is no need to precharge the pixel corresponding to the first gate integrated circuit, only All other gate integrated circuits except the first gate integrated circuit need to be precharged. In this application, each other gate integrated circuit is used as the target gate integrated circuit.
  • the actual charging time period refers to the originally planned charging time period of each pixel.
  • the set time periods of the scan lines corresponding to each gate integrated circuit are connected end to end, and the preset charging duration corresponding to each scan line is the same, so the first gate can be integrated according to the current time point and the preset charging duration
  • the actual charging time period of the scanning line corresponding to the circuit is determined by the actual charging time period of the scanning line corresponding to the first gate integrated circuit.
  • the actual charging time period of the scan line corresponding to the target gate integrated circuit is determined by the actual charging time period of the scanning line corresponding to the target gate integrated circuit.
  • the current time is 8:30 minutes and 0 seconds
  • the preset charging time is 10 seconds
  • the actual charging time period of the scan line corresponding to the first gate integrated circuit is 8:30 minutes 0 seconds and 8:30 minutes 10 Second
  • the actual charging period of the scan line corresponding to the second gate integrated circuit (the first and second gate integrated circuits are named according to the order in which the gate integrated circuits are turned on) is 8:30:10-10:00 30 minutes and 20 seconds, and so on, to obtain the actual charging time period of the scanning line controlled by each gate integrated circuit.
  • each target gate integrated circuit is provided with a precharge period, and the target gate integrated circuit corresponds to the precharge period
  • the end time point is earlier than or equal to the start time point of the actual charging time period of the target gate integrated circuit. Due to the delay of the pixel TFT switching, the pixel is insufficiently charged, so only the time corresponding to the maximum delay needs to be determined, which is the precharge time corresponding to the precharge time period, and the precharge time corresponding to the pre-stored time period corresponding to each target gate integrated circuit Both can be the time corresponding to the maximum delay in the pixel TFT switch.
  • the duration corresponding to the precharge period can be determined according to the opening sequence number of the target gate integrated circuit on the thin film transistor substrate. The higher the opening sequence number, the longer the duration.
  • the precharge time period can be integrated with the actual charging time period, that is, the end time point of the target precharge time period is consistent with the start time point of the actual charging time period.
  • Step S40 Control the thin film transistor switches corresponding to the scan lines of each target gate integrated circuit, and turn on the pre-charge time period and the actual charging time period corresponding to the scan lines to correspond to the scan lines Pixels are charged, wherein each pixel electrode corresponding to the data line on the thin film transistor substrate has the same voltage polarity;
  • the thin film transistor switch corresponding to the scan line of each target gate integrated circuit can be controlled, and the precharge time corresponding to the scan line The period and the actual charging time period are turned on to charge the pixels.
  • a gate integrated circuit can control multiple scan lines, controlled by the same gate integrated circuit
  • the current time point and the preset charging duration are acquired to determine the first The pre-charge period and the actual charging period of the scan lines controlled by the gate integrated circuits other than the gate integrated circuits, so as to control the thin film transistor switches corresponding to the scan lines of each gate integrated circuit.
  • the precharge period and the actual charging period are turned on to charge the pixels corresponding to the scan lines; the pixels corresponding to the scan lines can be precharged in advance, ensuring that the voltage of the pixels corresponding to the scan lines can reach the set voltage value
  • the uniformity of the overall brightness of the display panel is ensured, and the picture quality of the display panel is high.
  • FIG. 3 is another embodiment of the pixel charging method of the present application. Based on an embodiment, the step S30 includes:
  • Step S31 taking each of the target gate integrated circuits as the current gate integrated circuit in turn, and determining the number of gate integrated circuits that were opened before the current gate integrated circuit;
  • Step S32 Determine each precharge period of the scan line corresponding to the current gate integrated circuit according to the number of gate integrated circuits opened before the current gate integrated circuit, wherein, according to the current gate integrated circuit The greater the number of previously opened gate integrated circuits, the greater the number of target gate integrated circuits corresponding to the precharge time period;
  • a pre-charge duration can be set, which is A precharge period can be characterized. The closer to the gate integrated circuit at the end of the data transmission, the greater the number of precharge periods corresponding to the scan lines.
  • the sequence of opening the gate integrated circuits on the thin film transistor substrate is in accordance with the source IC opposite side to the source IC side, so the number of gate circuits opened before the current gate integrated circuit can be used to characterize the distance between the scanning line controlled by the current gate integrated circuit and the data transmission end of the data line.
  • the greater the number, the current gate integration The closer the scan line corresponding to the circuit is to the data transmission end of the data line, it can be understood that the display panel can determine each of the scan lines corresponding to the current gate integrated circuit according to the number of gate circuits opened before the current gate integrated circuit Precharge time period.
  • the start time of each precharge time period corresponding to the current gate integrated circuit is later than the opening time point of the first gate integrated circuit, and the precharge duration corresponding to the precharge time period can be any suitable The value of is preferably less than the charging duration of the actual charging period.
  • the display panel treats each target gate integrated circuit as the current gate integrated circuit in turn, thereby determining the number of gate integrated circuits that are turned on before the current gate integrated circuit, and then determining the current gate according to the number
  • Each precharge period of the scan line corresponding to the polar integrated circuit avoids the detection of the delay time of the pixel TFT switch, and reduces the cost of the display panel while ensuring the uniformity of the display screen.
  • FIG. 4 is another embodiment of a pixel charging method of the present application. Based on an embodiment, the step S30 includes:
  • step S33 each of the target gate integrated circuits is used as the current gate integrated circuit in turn, and the actual charging time period of the scan line corresponding to each gate integrated circuit opened before the current gate integrated circuit is determined as The actual charging time period to be processed;
  • Step S34 Use each of the set charging time periods to be processed as each of the precharge time periods of the scan lines corresponding to the current gate integrated circuit.
  • the precharge time period of the target gate integrated circuit is determined according to the actual charging time period corresponding to the target gate integrated circuit; and in this embodiment, the precharge time of the target gate integrated circuit The segment is determined according to the actual charging time period of each gate integrated circuit.
  • the display panel sequentially uses each target gate integrated circuit as the current gate integrated circuit, and then determines that the current gate integrated circuit
  • the actual charging time period of the scanning line corresponding to each gate integrated circuit opened before the circuit to take these actual charging time periods as the actual charging time period to be processed, and these actual charging time periods to be processed can be integrated as the current gate The precharge period of the circuit.
  • the precharge duration can be determined according to these actual charging time periods to be processed.
  • the precharge duration is the corresponding length of the precharge time period, for example, there are 2 set charging durations to be processed, each of which sets charging If the duration is 10s, then the precharge duration is 20s, so the precharge period is determined according to the current gate integrated circuit opening time and the precharge duration, and the end of the precharge period is the current gate integrated circuit. The starting point of the actual charging period.
  • precharge time periods can be integrated into one precharge time period.
  • the display panel can sequentially obtain the precharge time period of each target gate integrated circuit according to the above process.
  • the pre-charge time period corresponding to each scan line can refer to the following steps:
  • the start time point and end time point of the actual charging time period of each scanning line of the same gate integrated circuit are connected end to end, that is, each scanning line has a corresponding opening sequence number.
  • FIGS. 5A-5C are gate integrated circuits, where GA is the first gate integrated circuit, and the gate integrated circuit controls two scan lines (such as GA1 and GA2 are the first Scanning lines controlled by a gate integrated circuit), the gate integrated circuits in FIGS. 5A-5C are only provided as examples, and do not limit the thin film transistor substrate in the present application to only five gate integrated circuits, and do not limit a gate
  • the polar integrated circuit controls two scanning lines.
  • FIG. 5A is a schematic diagram of pixel charging in another exemplary technology, and the signal fluctuation period is the actual charging time period corresponding to the scan line.
  • the high level indicated by the dotted line in FIGS. 5B and 5C is the precharge period, and the realized high level is the actual charging period.
  • 5B is a schematic diagram of charging a pixel in the third embodiment of the present application.
  • each gate circuit For the determination of the actual charging time period, please refer to the relevant descriptions in the first and second embodiments, which will not be repeated here one by one), and then determine the control of each gate integrated circuit opened before the current gate integrated circuit Scan to set the open sequence number first; then, according to the actual charging time period of the scan line with the same setting open sequence number, determine each precharge time period of the current scan line of the same set open sequence number in the gate integrated circuit.
  • each actual charging time period to be processed with the same set open sequence number can be used as a scan of the same set open sequence number in the current gate integrated circuit
  • the precharge period of the line for example, each gate integrated circuit controls three scan lines, and the current gate integrated circuit is the third open, then, the current gate integrated circuit is set to open the second scan
  • the pre-charge time period of the line is: the actual charging time period of the scan line whose open sequence number is set as the second in the first gate integrated circuit, and the scan whose second open sequence number is set in the second gate integrated circuit The actual charging period of the line.
  • the pre-charge time period of the target scan line is determined according to the open time point and the pre-charge time length, where the open time point is the end time point of the pre-charge time period.
  • each gate integrated circuit controls three scan lines, and the current gate integrated circuit is the third to be turned on. Then, the current gate integrated circuit is set to open the scan line with the second scan line precharge period as : Integration of the actual charging time period of the scanning line with the opening sequence number second in the first gate integrated circuit, and integration of the actual charging time period of the scanning line with the opening sequence number second set in the second gate integrated circuit As a result, the end time point of the precharge period is the opening time point of the scan line.
  • the precharge time period corresponding to each scan line in the current gate integrated circuit is determined, so as to determine the precharge time period corresponding to all scan lines of the target gate integrated circuit.
  • the display panel treats each target gate integrated circuit as the current gate integrated circuit in turn, and determines the actual charging time of the scan line corresponding to each gate integrated circuit that was turned on before the current gate integrated circuit To be used as the actual charging time period to be processed, and then each set charging time period to be processed as each pre-charge time period of the scan line corresponding to the current gate integrated circuit, so that the pixels on each scan line are all Can get enough voltage to ensure the brightness uniformity of the display panel.
  • FIG. 6 is still another embodiment of the pixel charging method of the present application. Based on an embodiment, the step S30 includes:
  • Step S35 determining the location of each target gate integrated circuit on the thin film transistor substrate
  • Step S36 Determine the precharge duration of the scan line corresponding to the target gate integrated circuit according to the position, where the closer the scan line corresponding to the target gate integrated circuit is to the data transmission end of the data line, the The longer the pre-charging time;
  • Step S37 Determine the precharge time period of the scan line corresponding to the target gate integrated circuit according to the precharge time period and the current time point, where the start time point of the precharge time period is later than or equal to The current time point;
  • the display panel stores the mapping relationship between the position of each target gate integrated circuit on the thin film transistor and the precharge duration.
  • the precharge time period of the polar integrated circuit, the duration corresponding to the precharge time period is the precharge duration, and the start time point corresponding to the precharge time period is later than or equal to the current time point.
  • the position of the gate integrated circuit on the thin film transistor is used to determine the precharge time period of the scanning line corresponding to the gate integrated circuit, which can save the computing resources of the display panel,
  • the present application also provides a display panel including at least one processor and a storage device, wherein,
  • the memory device stores computer-executable instructions executable by the at least one processor, and when the computer-executable instructions are executed by the at least one processor, causes the one processor to perform the following steps:
  • the preset charging duration and the current time point are obtained, wherein the thin film transistor substrate is provided with a plurality of horizontally arranged scanning lines and a plurality of vertically arranged The data line, using the scan line with the largest relative distance from the data transmission end of the data line as the target scan line, and using the gate integrated circuit that controls the opening of the target scan line as the first gate integrated circuit;
  • Controlling the thin film transistor switches corresponding to the scan lines of each target gate integrated circuit to turn on during the pre-charge time period and the actual charging time period corresponding to the scan lines, so as to carry out the pixels corresponding to the scan lines Charging, wherein the voltage polarity of each pixel electrode corresponding to the data line on the thin film transistor substrate is the same.
  • the present application also provides a computer-readable storage medium storing computer-executable instructions executable by the at least one processor, the computer-executable instructions being executed by the at least one processor When, make a processor perform the following steps:
  • the preset charging duration and the current time point are obtained, wherein the thin film transistor substrate is provided with a plurality of horizontally arranged scanning lines and a plurality of vertically arranged The data line, using the scan line with the largest relative distance from the data transmission end of the data line as the target scan line, and using the gate integrated circuit that controls the opening of the target scan line as the first gate integrated circuit;
  • Controlling the thin film transistor switches corresponding to the scan lines of each target gate integrated circuit to turn on during the pre-charge time period and the actual charging time period corresponding to the scan lines, so as to carry out the pixels corresponding to the scan lines Charging, wherein the voltage polarity of each pixel electrode corresponding to the data line on the thin film transistor substrate is the same.
  • the methods in the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware, but in many cases the former is better Implementation.
  • the technical solution of the present application can essentially be embodied in the form of software products, and the computer software products are stored in a storage medium (such as ROM/RAM) as described above , Magnetic disk, optical disk), including several instructions to make a terminal device (which can be a mobile phone, computer, server, air conditioner, or network equipment, etc.) to perform the method described in each embodiment of the present application.

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Abstract

一种像素充电方法，显示面板和计算机可读存储介质，其中像素充电方法包括：在第一颗栅极集成电路打开时，获取预设充电时长以及当前时间点；根据预设充电时长以及当前时间点，确定薄膜晶体管基板各个目标栅极集成电路控制的扫描线的预充时间段与实际充电时间段；控制各个目标栅极集成电路的扫描线对应的薄膜晶体管开关，在扫描线的预充时间段以及实际充电时间段打开，以对像素进行充电，从而解决充电不足引起的显示面板整体亮度不均、画面品质低下的问题。

Description

显示面板、像素充电方法和计算机可读存储介质
相关申请
本申请要求2018年11月27日申请的，申请号为201811429900.2，名称为“显示面板、像素充电方法和计算机可读存储介质”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及显示设备技术领域，尤其涉及一种显示面板、像素充电方法和计算机可读存储介质。
背景技术
显示面板通常具有一薄膜晶体管（Thin Film Transisitor，TFT）阵列基板。TFT阵列基板上形成有多条扫描线及多条数据线，每一子像素分别通过对应的扫描线来接收扫描信号，通过对应的数据线来接收数据信号，以显示影像。数据信号由数据源端（source端）对侧经数据线传输到source端，由于数据线本身的电阻电容的存在及面板上其他负载的影响，数据信号从source端对侧传输到source端会发生变形，使得扫描线对应的像素TFT开关延迟打开。而每个栅极集成电路（Gate IC）所控制的扫描线打开时长相同，即每个像素的设定的充电时间相同，从而导致不同Gate IC控制的扫描线对应的像素充电不足，引起显示面板整体亮度不均、画面品质低下的问题产生。
发明内容
本申请的主要目的在于提供一种显示面板、像素充电方法和计算机可读存储介质，旨在解决像素充电不足，引起显示面板整体亮度不均、画面品质低下的问题产生的问题。
为实现上述目的，本申请提供的一种像素充电方法，所述像素充电方法包括以下步骤：
在检测到薄膜晶体管基板上第一颗栅极集成电路打开时，获取预设充电时长以及当前时间点，其中，所述薄膜晶体管基板设有多条横向排列的扫描线以及多条竖向排列的数据线，将与所述数据线的数据传输末端相对距离最大的扫描线作为目标扫描线，以将控制所述目标扫描线打开的栅极集成电路作为所述第一颗栅极集成电路；
根据所述预设充电时长以及所述当前时间点，确定所述薄膜晶体管基板上除所述第一颗栅极集成电路之外各个目标栅极集成电路对应的扫描线的实际充电时间段；
确定各个所述目标栅极集成电路对应的扫描线的预充时间段；以及
控制各个所述目标栅极集成电路的扫描线对应的薄膜晶体管开关，在所述扫描线对应的所述预充时间段以及所述实际充电时间段打开，以对所述扫描线对应的像素进行充电，其中，所述薄膜晶体管基板上数据线对应的各个像素电极的电压极性相同。
为实现上述目的，本申请还提供一种显示面板，所述显示面板包括至少一个处理器，以及存储设备，其中，
所述存储器设备存储有可被所述至少一个处理器执行的计算机可执行指令，所述计算机可执行指令被所述至少一个处理器执行时，使得一个处理器执行以下步骤：
在检测到薄膜晶体管基板上第一颗栅极集成电路打开时，获取预设充电时长以及当前时间点，其中，所述薄膜晶体管基板设有多条横向排列的扫描线以及多条竖向排列的数据线，将与所述数据线的数据传输末端相对距离最大的扫描线作为目标扫描线，以将控制所述目标扫描线打开的栅极集成电路作为所述第一颗栅极集成电路；
根据所述当前时间点以及所述预设充电时长，确定所述第一颗栅极集成电路对应的扫描线的实际充电时间段，
根据所述第一颗栅极集成电路对应的扫描线的实际充电时间段，确定各个所述目标栅极集成电路对应的扫描线的实际充电时间段，其中，所述薄膜晶体管基板上各个栅极集成电路对应的扫描线的实际充电时间段首尾相连；
确定各个所述目标栅极集成电路对应的扫描线的预充时间段；以及
控制各个所述目标栅极集成电路的扫描线对应的薄膜晶体管开关，在所述扫描线对应的所述预充时间段以及所述实际充电时间段打开，以对所述扫描线对应的像素进行充电，其中，所述薄膜晶体管基板上数据线对应的各个像素电极的电压极性相同。
为实现上述目的，本申请还提供一种计算机可读存储介质，所述计算机可读存储介质存储有可被所述至少一个处理器执行的计算机可执行指令，所述计算机可执行指令被所述至少一个处理器执行时，使得一个处理器执行以下步骤：
在检测到薄膜晶体管基板上第一颗栅极集成电路打开时，获取预设充电时长以及当前时间点，其中，所述薄膜晶体管基板设有多条横向排列的扫描线以及多条竖向排列的数据线，将与所述数据线的数据传输末端相对距离最大的扫描线作为目标扫描线，以将控制所述目标扫描线打开的栅极集成电路作为所述第一颗栅极集成电路；
根据所述预设充电时长以及所述当前时间点，确定所述薄膜晶体管基板上除所述第一颗栅极集成电路之外各个目标栅极集成电路对应的扫描线的实际充电时间段；
确定各个所述目标栅极集成电路对应的扫描线的预充时间段；
控制各个所述目标栅极集成电路的扫描线对应的薄膜晶体管开关，在所述扫描线对应的所述预充时间段以及所述实际充电时间段打开，以对所述扫描线对应的像素进行充电，其中，所述薄膜晶体管基板上数据线对应的各个像素电极的电压极性相同。
本申请提供的显示面板、像素充电方法和计算机可读存储介质，在薄膜晶体管基板上源极集成电路对端的第一颗栅极集成电路打开时，获取当前时间点以及预设充电时长，以确定薄膜晶体管基板上除第一颗栅极集成电路之外的各个栅极集成电路所控制的扫描线的预充时间段以及实际充电时间段，从而控制各个栅极集成电路的扫描线对应的薄膜晶体管开关，在扫描线对应的预充时间段以及实际充电时间段打开，以对扫描线对应的像素进行充电；因扫描线对应的像素能够提前进行预充电，确保了各个扫描线对应的像素的电压能够达到设定的电压值，从而保证了显示面板的整体亮度的均匀性，显示面板的画面品质高。
附图说明
图1为本申请实施例涉及的显示面板的硬件结构示意图；
图2为本申请像素充电方法一实施例的流程示意图；
图3为本申请像素充电方法又一实施例的流程示意图；
图4为本申请像素充电方法另一实施例的流程示意图；
图5A为示例性技术中的像素充电示意图；
图5B为本申请另一实施例中一像素充电示意图；
图5C为本申请另一实施例中又一像素充电示意图；
图6为本申请像素充电方法再一实施例的流程示意图；
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不设置为限定本申请。
本申请实施例的主要解决方案是：在检测到薄膜晶体管基板上第一颗栅极集成电路打开时，获取预设充电时长以及当前时间点，其中，所述薄膜晶体管基板设有多条横向排列的扫描线以及多条竖向排列的数据线，将与所述数据线的数据传输末端相对距离最大的扫描线作为目标扫描线，以将控制所述目标扫描线打开的栅极集成电路作为所述第一颗栅极集成电路；根据所述预设充电时长以及所述当前时间点，确定所述薄膜晶体管基板上除所述第一颗栅极集成电路之外各个目标栅极集成电路对应的扫描线的预充时间段以及实际充电时间段；控制各个所述目标栅极集成电路的扫描线对应的薄膜晶体管开关，在所述扫描线对应的所述预充时间段以及所述实际充电时间段打开，以对所述扫描线对应的像素进行充电，其中，所述薄膜晶体管基板上数据线对应的各个像素电极的电压极性相同。
由于显示面板上的扫描线对应的像素能够提前进行预充电，确保了各个扫描线对应的像素的电压能够达到设定的电压值，从而保证了显示面板的整体亮度的均匀性，显示面板的画面品质高。
作为一种实现方案，显示面板可以如图1所示。
本申请实施例方案涉及的是显示面板，显示面板包括：处理器1001，例如CPU，存储器1002，通信总线1003。其中，通信总线1003设置为实现这些组件之间的连接通信。
存储器1002可以是高速RAM存储器，也可以是稳定的存储器（non-volatilememory），例如磁盘存储器。如图1所示，作为一种计算机存储介质的存储器1003中可以包括像素充电程序；而处理器1001可以设置为调用存储器1002中存储的像素充电程序，并执行以下实施例对应的像素充电方法的各个步骤。
基于上述硬件构架，提出本申请像素充电方法的实施例。
参照图2，图2为本申请像素充电方法的一实施例，所述像素充电方法包括以下步骤：
步骤S10，在检测到薄膜晶体管基板上第一颗栅极集成电路打开时，获取预设充电时长以及当前时间点，其中，所述薄膜晶体管基板设有多条横向排列的扫描线以及多条竖向排列的数据线，将与所述数据线的数据传输末端相对距离最大的扫描线作为目标扫描线，以将控制所述目标扫描线打开的栅极集成电路作为所述第一颗栅极集成电路；
在本申请中，显示面板的薄膜晶体管基板上包括多条扫描线以及数据线，薄膜晶体管基板上的像素通过扫描线来接收扫描信号，通过数据线来接收数据信号；在同一帧扫描线对像素进行充电时，数据线上对应的各个像素电极的电压极性相同。
薄膜晶体管基板上设有多颗栅极集成电路，也即Gate IC，Gate IC控制扫描线的扫描信号的打开以及关闭，薄膜晶体管基板上还设有多颗源极集成电路，也即Source IC，Source IC控制数据线的数据信号的打开以及关闭；扫描线在薄膜晶体管基板上横向排列，数据线则在薄膜晶体管基板上竖向排列。
在薄膜晶体管基板的像素进行充电时，Source IC对侧的扫描线依次打开，以将扫描线对应的像素TFT打开，从而对像素进行充电，可以理解的是，薄膜晶体管基板上各个Gate IC的打开顺序为：距离Source IC侧越远的Gate IC对应的扫描线，越早打开，也即距离数据线的数据传输末端越远的扫描线越早打开，各个Gate IC的打开时间点以及关闭时间点首尾相连。
由于数据信号是由Source IC对侧通过数据线传输到Source IC端，由于数据线本身的电阻电容以及显示面板上其他负载的影响，会使得薄膜晶体管开关的开启延迟，从而造成像素的充电不足，且越靠近Source IC端的薄膜晶体管开关的延迟越严重。基于此，对各个像素进行预充电。
显示面板在检测到薄膜晶体管基板上第一颗栅极集成电路打开时，获取预设充电时长以及当前时间点，第一颗栅极集成电路为一帧扫描中首先打开的栅极集成电路，且第一颗栅极集成电路位于源极集成电路的对端，也即薄膜晶体管基板设有多条横向排列的扫描线以及多条竖向排列的数据线，将与数据线的数据传输末端相对距离最大的扫描线作为扫描线，以将控制扫描线打开的栅极集成电路作为第一颗栅极集成电路。预设充电时长指的是，显示面板中像素设定的充电时长。
步骤S20，根据所述预设充电时长以及所述当前时间点，确定所述薄膜晶体管基板上除所述第一颗栅极集成电路之外各个目标栅极集成电路对应的扫描线的实际充电时间段；
步骤S30，确定各个所述目标栅极集成电路对应的扫描线的预充时间段；第一颗栅极集成电路打开时，该栅极集成电路所控制的扫描线上对应的薄膜晶体管开关均会打开。因数据信号先进入第一颗栅极集成电路所控制的扫描线对应的像素，电阻电容对薄膜晶体管开关延迟影响很小，故无需对第一颗栅极集成电路对应的像素进行预充电，只需对除第一颗栅极集成电路之外的各个其他栅极集成电路进行预充电，在本申请中，将每一个其他栅极集成电路作为目标栅极集成电路。
实际充电时间段指的是各个像素原计划的充电时间段。而各个栅极集成电路对应的扫描线的设定时间段首尾相连，而每一条扫描线对应的预设充电时长均相同，故可以根据当前时间点以及预设充电时长来第一颗栅极集成电路对应的扫描线的实际充电时间段，由于各个栅极电路对应的扫描线的实际充电时间段首尾相连，故可以根据第一颗栅极集成电路对应的扫描先的实际充电时间段来确定各个目标栅极集成电路对应的扫描线的实际充电时间段。例如，当前时间点为8点30分0秒，预设充电时长为10秒，第一颗栅极集成电路对应的扫描线的实际充电时间段为8点30分0秒-8点30分10秒，第二颗栅极集成电路（第一、第二栅极集成电路的按照栅极集成电路的先后打开顺序命名）对应的扫描线的实际充电时间段为8点30分10秒-8点30分20秒，以此类推，得到各个栅极集成电路所控制的扫描线的实际充电时间段。
除第一颗栅极集成电路之外的各个目标栅极集成电路均需要预充电，也即各个目标栅极集成电路均设有预充时间段，目标栅极集成电路对应的预充时间段的结束时间点，早于或等于该目标栅极集成电路的实际充电时间段的开始时间点。由于像素TFT开关延迟，使得像素充电不足，故只需确定最大延迟对应的时长，时长即为预充时间段对应的预充电时长，每一个目标栅极集成电路对应的预存时间段的预充电时长均可为像素TFT开关中最大延迟对应的时长。
另外，预充时间段对应的时长可以根据目标栅极集成电路在薄膜晶体管基板上的打开序号来确定，打开序号越靠前，时长越长。另外，可将预充时间段与实际充电时间段整合，也即目标预充时间段的结束时间点与实际充电时间段的开始时间点一致。
当然，可确定打开序号最后的扫描线对应的薄膜晶体管开关的延时时长，并将该延时时长作为各个扫描线的预充时间段对应的预充时长；然后再确定各个扫描线实际充电时间段的打开时间点，以将其打开时间点作为该扫描线对应的预充时间段的结束时间点，从而确定了预充时间段。
步骤S40，控制各个所述目标栅极集成电路的扫描线对应的薄膜晶体管开关，在所述扫描线对应的所述预充时间段以及所述实际充电时间段打开，以对所述扫描线对应的像素进行充电，其中，所述薄膜晶体管基板上数据线对应的各个像素电极的电压极性相同；
在确定各个目标栅极集成电路对应的扫描线的预充时间段以及实际充电时间段后，可以控制各个目标栅极集成电路的扫描线对应的薄膜晶体管开关，在该扫描线对应的预充时间段以及实际充电时间段打开，以对像素进行充电。
另外，一颗栅极集成电路可以控制多条扫描线，由同一栅极集成电路控
在本实施例提供的技术方案中，在薄膜晶体管基板上源极集成电路对端的第一颗栅极集成电路打开时，获取当前时间点以及预设充电时长，以确定薄膜晶体管基板上除第一颗栅极集成电路之外的各个栅极集成电路所控制的扫描线的预充时间段以及实际充电时间段，从而控制各个栅极集成电路的扫描线对应的薄膜晶体管开关，在扫描线对应的预充时间段以及实际充电时间段打开，以对扫描线对应的像素进行充电；因扫描线对应的像素能够提前进行预充电，确保了各个扫描线对应的像素的电压能够达到设定的电压值，从而保证了显示面板的整体亮度的均匀性，显示面板的画面品质高。
参照图3，图3为本申请像素充电方法的又一实施例，基于一实施例，所述步骤S30包括：
步骤S31，将各个所述目标栅极集成电路中依次作为当前栅极集成电路，并确定所述当前栅极集成电路之前打开的栅极集成电路的数量；
步骤S32，根据所述当前栅极集成电路之前打开的栅极集成电路的数量，确定所述当前栅极集成电路对应的扫描线的各个预充时间段，其中，根据所述当前栅极集成电路之前打开的栅极集成电路的数量越多，所述目标栅极集成电路对应预充时间段的数量越多；
测量像素薄膜晶体管开关的延迟时长需要额外的硬件去测量，显示面板的成本必然会增大。而在像素充电的过程，由于越靠近数据线的数据传输末端的栅极集成电路，对应的扫描线所控制的像素充电量越不足；对此，可设置一预充电时长，该预充电时长即可表征一个预充时间段，越靠近数据传输末端的栅极集成电路，其对应的扫描线的预充时间段的数量也就越多。
薄膜晶体管基板上的各个栅极集成电路打开的顺序，是按照Source IC对侧到Source IC端，故可以用当前栅极集成电路之前打开的栅极电路的数量，来表征当前栅极集成电路所控制的扫描线与数据线的数据传输末端的距离，数量越多，当前栅极集成电路对应的扫描线越靠近数据线的数据传输末端，可以理解的是，显示面板可根据当前栅极集成电路之前打开的栅极电路的数量，来确定当前栅极集成电路对应的扫描线的各个预充时间段。
需要说明的是，当前栅极集成电路对应的各个预充时间段的开始时间点晚于第一颗栅极集成电路打开时间点即可，而预充时间段对应的预充电时长可为任意合适的数值，优选，小于实际充电时间段的充电时长。
在本实施例提供的技术方案中，显示面板将各个目标栅极集成电路依次作为当前栅极集成电路，从而确定当前栅极集成电路之前打开的栅极集成电路的数量，再根据数量确定当前栅极集成电路对应的扫描线的各个预充时间段，避免对像素TFT开关进行延时时长的检测，在保证显示画面的均匀下的情况下，减少了显示面板的成本。
参照图4，图4为本申请像素充电方法的另一实施例，基于一实施例，所述步骤S30包括：
步骤S33，将各个所述目标栅极集成电路中依次作为当前栅极集成电路，并确定所述当前栅极集成电路之前打开的各个栅极集成电路对应的扫描线的实际充电时间段，以作为待处理的实际充电时间段；
步骤S34，将各个所述待处理的设定充电时间段，作为所述当前栅极集成电路对应的扫描线的各个所述预充时间段。
在一实施例中，目标栅极集成电路的预充时间段是根据该目标栅极集成电路对应的实际充电时间段来确定的；而在本实施例中，目标栅极集成电路的预充时间段根据各个栅极集成电路的实际充电时间段确定的。
具体的，显示面板在确定各个目标栅极集成电路以及第一颗栅极集成电路的实际充电时间段后，将各个目标栅极集成电路依次作为当前栅极集成电路，再确定在当前栅极集成电路之前打开的各个栅极集成电路对应的扫描线的实际充电时间段，以将这些实际充电时间段作为待处理的实际充电时间段，可将这些待处理的实际充电时间段作为当前栅极集成电路的预充时间段。
具体的，可以根据这些待处理的实际充电时间段来确定预充电时长，预充电时长即为预充时间段对应的时长，比如，有2个待处理的设定充电时长，每一个设定充电时长为10s，那么预充电时长即为20s，从而根据当前栅极集成电路的打开时间点以及预充电时长来确定预充时间段，预充时间段的结束时间点即为当前栅极集成电路的实际充电时间段的开始时间点。
当然，多个预充时间段可以整合为一个预充时间段。
显示面板可以根据上述流程依次获得各个目标栅极集成电路的预充时间段。
进一步的，一颗栅极集成电路控制多条扫描线，此时，各个扫描线对应的预充时间段可参照以下步骤：
A、确定所述第一颗栅极集成电路以及各个所述目标栅极集成电路中对应的各个扫描线的设定打开序号；
B、将各个所述目标栅极集成电路中依次作为当前栅极集成电路，并确定在所述当前栅极集成电路之前打开的各个栅极集成电路中对应各个扫描线的实际充电时间段，以作为待处理的实际充电时间段；
C、将相同所述设定打开序号的各个所述待处理的实际充电时间段，作为所述当前栅极集成电路中同一所述设定打开序号的扫描线的各个预充时间段；
同一栅极集成电路的各个扫描线的实际充电时间段的开始时间点以及结束时间点首尾相连，也即各个扫描线具有对应的打开序号。
请参照图5A、图5B以及图5C，GA、GB、GC为栅极集成电路，其中，GA为第一颗栅极集成电路，栅极集成电路控制二条扫描线（如GA1与GA2为第一颗栅极集成电路控制的扫描线），图5A-图5C中栅极集成电路仅设置为举例，并不限定本申请中薄膜晶体管基板仅有五颗栅极集成电路，且不限定一颗栅极集成电路控制二条扫描线。图5A为另一示例性技术中的像素充电示意图，信号波动段即为扫描线对应的实际充电时间段。另外，图5B以及图5C中用虚线表征的高电平为预充时间段，实现表征的高电平为实际充电时间段。
图5B为本申请第三实施例中一像素充电示意图，具体的，在确定在当前栅极集成电路之前打开的各个栅极电路所控制的扫描线的实际充电时间段后（各个栅极电路的实际充电时间段的确定可参考第一以及第二实施例中的相关描述，在此不再一一赘述），再确定在当前栅极集成电路之前打开的各个栅极集成电路中所控制的各个扫描先的设定打开序号；然后，根据相同设定打开序号的扫描线对应实际充电时间段，确定当前栅极集成电路中同一设定打开序号的扫描线的各个预充时间段。
图5C为本申请第三实施例中另一像素充电示意图，具体的，可将相同设定打开序号的各个待处理的实际充电时间段，作为当前栅极集成电路中同一设定打开序号的扫描线的预充时间段；例如，每一颗栅极集成电路控制三条扫描线，当前栅极集成电路为第三颗打开的，那么，当前栅极集成电路中设定打开序号为第二的扫描线的预充时间段为：第一颗栅极集成电路中设定打开序号为第二的扫描线的实际充电时间段，以及第二颗栅极集成电路中设定打开序号为第二的扫描线的实际充电时间段。
或者，根据相同设定打开序号的各个待处理的实际充电时间段，确定当前栅极集成电路中同一设定打开序号的目标扫描线的预充电时长；
确定目标扫描线对应的实际充电时间段的打开时间点；
根据打开时间点以及预充电时长，确定目标扫描线的预充时间段，其中，打开时间点为预充时间段的结束时间点。
例如，每一颗栅极集成电路控制三条扫描线，当前栅极集成电路为第三颗打开的，那么，当前栅极集成电路中设定打开序号为第二的扫描线的预充时间段为：第一颗栅极集成电路中设定打开序号为第二的扫描线的实际充电时间段，以及第二颗栅极集成电路中设定打开序号为第二的扫描线的实际充电时间段整合而成，该预充时间段的结束时间点即该扫描线的打开时间点。
以此，来确定当前栅极集成电路中各个扫描线对应的预充时间段，从而确定全部的目标栅极集成电路对应的扫描线的预充时间段。
在本实施提供的技术方案中，显示面板将各个目标栅极集成电路中依次作为当前栅极集成电路，并确定当前栅极集成电路之前打开的各个栅极集成电路对应的扫描线的实际充电时间段，以作为待处理的实际充电时间段，再将各个待处理的设定充电时间段，作为当前栅极集成电路对应的扫描线的各个预充时间段，从而使得各个扫描线上的像素均能够得到足够的电压，保证显示面板的亮度均匀性。
参照图6，图6为本申请像素充电方法的再一实施例，基于一实施例，所述步骤S30包括：
步骤S35，确定各个所述目标栅极集成电路，在所述薄膜晶体管基板上的位置；
步骤S36，根据所述位置确定所述目标栅极集成电路对应的扫描线的预充电时长，其中，所述目标栅极集成电路对应的扫描线越接近所述数据线的数据传输末端，所述预充电时长越长；
步骤S37，根据所述预充电时长以及所述当前时间点，确定所述目标栅极集成电路对应的扫描线的预充时间段，其中，所述预充时间段的开始时间点晚于或等于所述当前时间点；
本实施例中，显示面板存储有，各个目标栅极集成电路在薄膜晶体管上的位置与预充电时长的映射关系，目标栅极集成电路对应的扫描线越接近数据线的数据传输末端，预充电时长越长。故在当第一颗栅极集成电路打开时，即可以根据各个目标栅极集成电路在薄膜晶体管上的位置，来确定对应的预充电时长，然后根据预充电时长以及当前时间点来确定目标栅极集成电路的预充时间段，该预充时间段对应的时长即为预充电时长，预充时间段对应的开始时间点晚于或等于当前时间点即可。
采用栅极集成电路在薄膜晶体管上的位置，来确定栅极集成电路对应的扫描线的预充时间段，可以节省显示面板的计算资源，
本申请还提供一种显示面板，所述显示面板包括至少一个处理器，以及存储设备，其中，
所述存储器设备存储有可被所述至少一个处理器执行的计算机可执行指令，所述计算机可执行指令被所述至少一个处理器执行时，使得一个处理器执行以下的步骤：
在检测到薄膜晶体管基板上第一颗栅极集成电路打开时，获取预设充电时长以及当前时间点，其中，所述薄膜晶体管基板设有多条横向排列的扫描线以及多条竖向排列的数据线，将与所述数据线的数据传输末端相对距离最大的扫描线作为目标扫描线，以将控制所述目标扫描线打开的栅极集成电路作为所述第一颗栅极集成电路；
根据所述预设充电时长以及所述当前时间点，确定所述薄膜晶体管基板上除所述第一颗栅极集成电路之外各个目标栅极集成电路对应的扫描线的实际充电时间段；
确定各个所述目标栅极集成电路对应的扫描线的预充时间段；
控制各个所述目标栅极集成电路的扫描线对应的薄膜晶体管开关，在所述扫描线对应的所述预充时间段以及所述实际充电时间段打开，以对所述扫描线对应的像素进行充电，其中，所述薄膜晶体管基板上数据线对应的各个像素电极的电压极性相同。
本申请还提供一种计算机可读存储介质，所述计算机可读存储介质存储有可被所述至少一个处理器执行的计算机可执行指令，所述计算机可执行指令被所述至少一个处理器执行时，使得一个处理器执行以下步骤：
在检测到薄膜晶体管基板上第一颗栅极集成电路打开时，获取预设充电时长以及当前时间点，其中，所述薄膜晶体管基板设有多条横向排列的扫描线以及多条竖向排列的数据线，将与所述数据线的数据传输末端相对距离最大的扫描线作为目标扫描线，以将控制所述目标扫描线打开的栅极集成电路作为所述第一颗栅极集成电路；
根据所述预设充电时长以及所述当前时间点，确定所述薄膜晶体管基板上除所述第一颗栅极集成电路之外各个目标栅极集成电路对应的扫描线的实际充电时间段；
确定各个所述目标栅极集成电路对应的扫描线的预充时间段；
控制各个所述目标栅极集成电路的扫描线对应的薄膜晶体管开关，在所述扫描线对应的所述预充时间段以及所述实际充电时间段打开，以对所述扫描线对应的像素进行充电，其中，所述薄膜晶体管基板上数据线对应的各个像素电极的电压极性相同。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对示例性技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在如上所述的一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例所述的方法。
以上仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种像素充电方法，其中，所述像素充电方法包括以下步骤：
    在检测到薄膜晶体管基板上第一颗栅极集成电路打开时，获取预设充电时长以及当前时间点，其中，所述薄膜晶体管基板设有多条横向排列的扫描线以及多条竖向排列的数据线，将与所述数据线的数据传输末端相对距离最大的扫描线作为目标扫描线，以将控制所述目标扫描线打开的栅极集成电路作为所述第一颗栅极集成电路；
    根据所述预设充电时长以及所述当前时间点，确定所述薄膜晶体管基板上除所述第一颗栅极集成电路之外各个目标栅极集成电路对应的扫描线的实际充电时间段；
    确定各个所述目标栅极集成电路对应的扫描线的预充时间段；以及
    控制各个所述目标栅极集成电路的扫描线对应的薄膜晶体管开关，在所述扫描线对应的所述预充时间段以及所述实际充电时间段打开，以对所述扫描线对应的像素进行充电，其中，所述薄膜晶体管基板上数据线对应的各个像素电极的电压极性相同。
  2. 如权利要求1所述的像素充电方法，其中，所述确定各个所述目标栅极集成电路对应的扫描线的预充时间段的步骤包括：
    将各个所述目标栅极集成电路中依次作为当前栅极集成电路，并确定所述当前栅极集成电路之前打开的栅极集成电路的数量；
    根据所述当前栅极集成电路之前打开的栅极集成电路的数量，确定所述当前栅极集成电路对应的扫描线的各个预充时间段，其中，根据所述当前栅极集成电路之前打开的栅极集成电路的数量越多，所述目标栅极集成电路对应预充时间段的数量越多。
  3. 如权利要求2所述的像素充电方法，其中，所述预充时间段的预充电时长小于所述实际充电时间点的充电时长。
  4. 如权利要求1所述的像素充电方法，其中，所述确定各个所述目标栅极集成电路对应的扫描线的预充时间段的步骤包括：
    将各个所述目标栅极集成电路中依次作为当前栅极集成电路，并确定所述当前栅极集成电路之前打开的各个栅极集成电路对应的扫描线的实际充电时间段，以作为待处理的实际充电时间段；
    将各个所述待处理的设定充电时间段，作为所述当前栅极集成电路对应的扫描线的各个所述预充时间段。
  5. 如权利要求4所述的像素充电方法，其中，所述确定所述当前栅极集成电路之前打开的各个栅极集成电路对应的扫描线的实际充电时间段，以作为待处理的实际充电时间段的步骤之后，还包括：
    将各个所述待处理的预充时间段整合为一个预充时间段，以作为所述所述当前栅极集成电路对应的扫描线的预充时间段。
  6. 如权利要求1所述的像素充电方法，其中，所述确定各个所述目标栅极集成电路对应的扫描线的预充时间段的步骤包括：
    确定各个所述目标栅极集成电路，在所述薄膜晶体管基板上的位置；
    根据所述位置确定所述目标栅极集成电路对应的扫描线的预充电时长，其中，所述目标栅极集成电路对应的扫描线越接近所述数据线的数据传输末端，所述预充电时长越长；
    根据所述预充电时长以及所述当前时间点，确定所述目标栅极集成电路对应的扫描线的预充时间段，其中，所述预充时间段的开始时间点晚于或等于所述当前时间点。
  7. 如权利要求1所述像素充电方法，其中，所述目所述薄膜晶体管基板上各个栅极集成电路控制多条扫描线，所述确定各个所述目标栅极集成电路对应的扫描线的预充时间段的步骤包括：
    确定所述第一颗栅极集成电路以及各个所述目标栅极集成电路中对应的各个扫描线的设定打开序号；
    将各个所述目标栅极集成电路中依次作为当前栅极集成电路，并确定在所述当前栅极集成电路之前打开的各个栅极集成电路中对应各个扫描线的实际充电时间段，以作为待处理的实际充电时间段；
    将相同所述设定打开序号的各个所述待处理的实际充电时间段，作为所述当前栅极集成电路中同一所述设定打开序号的扫描线的各个预充时间段。
  8. 如权利要求7所述的像素充电方法，其中，所述栅极集成电路控制的多条扫描线的预充电时间段对应的预充电时长相同。
  9. 如权利要求1所述的像素充电方法，其中，所述薄膜晶体管基板中栅极集成电路对应的扫描线与数据线的数据传输末端之间的距离越近，所述栅极集成电路对应的像素的预充电时长越长。
  10. 如权利要求1所述的像素充电方法，其中，所述确定所述薄膜晶体管基板上除所述第一颗栅极集成电路之外各个目标栅极集成电路对应的扫描线的实际充电时间段的步骤包括：
    根据所述当前时间点以及所述预设充电时长，确定所述第一颗栅极集成电路对应的扫描线的实际充电时间段，
    根据所述第一颗栅极集成电路对应的扫描线的实际充电时间段，确定各个所述目标栅极集成电路对应的扫描线的实际充电时间段，其中，所述薄膜晶体管基板上各个栅极集成电路对应的扫描线的实际充电时间段首尾相连。
  11. 如权利要求1所述像素充电方法，其中，所述薄膜晶体管基板上各个栅极集成电路控制多条扫描线，所述栅极集成电路控制的多条扫描线的预充电时长相同。
  12. 如权利要求11所述的像素充电方法，其中，所述预充电时长为最大延迟的所述像素薄膜晶体管开关对应的延迟时长。
  13. 如权利要求1所述的像素充电方法，其中，所述薄膜晶体管基板上的各个栅极集成电路打开顺序为：
    从源极集成电路对端至所述源极集成电路端。
  14. 如权利要求1所述的像素充电方法，其特征在于，所述预设充电时长为所述显示面板中像素设定的充电时长。
  15. 如权利要求1所述的像素充电方法，其特征在于，所述实际充电时间段为所述显示面板中像素设定的充电充电时间段。
  16. 一种显示面板，其中，所述显示面板包括至少一个处理器，以及存储设备，其中，
    所述存储器设备存储有可被所述至少一个处理器执行的计算机可执行指令，所述计算机可执行指令被所述至少一个处理器执行时，使得一个处理器执行以下步骤：
    在检测到薄膜晶体管基板上第一颗栅极集成电路打开时，获取预设充电时长以及当前时间点，其中，所述薄膜晶体管基板设有多条横向排列的扫描线以及多条竖向排列的数据线，将与所述数据线的数据传输末端相对距离最大的扫描线作为目标扫描线，以将控制所述目标扫描线打开的栅极集成电路作为所述第一颗栅极集成电路；
    根据所述当前时间点以及所述预设充电时长，确定所述第一颗栅极集成电路对应的扫描线的实际充电时间段，
    根据所述第一颗栅极集成电路对应的扫描线的实际充电时间段，确定各个所述目标栅极集成电路对应的扫描线的实际充电时间段，其中，所述薄膜晶体管基板上各个栅极集成电路对应的扫描线的实际充电时间段首尾相连；
    确定各个所述目标栅极集成电路对应的扫描线的预充时间段；以及
    控制各个所述目标栅极集成电路的扫描线对应的薄膜晶体管开关，在所述扫描线对应的所述预充时间段以及所述实际充电时间段打开，以对所述扫描线对应的像素进行充电，其中，所述薄膜晶体管基板上数据线对应的各个像素电极的电压极性相同。
  17. 如权利要求16所述的显示面板，其中，所述计算机可执行指令被所述至少一个处理器执行时，使得一个处理器执行以下步骤：
    将各个所述目标栅极集成电路中依次作为当前栅极集成电路，并确定所述当前栅极集成电路之前打开的栅极集成电路的数量；
    根据所述当前栅极集成电路之前打开的栅极集成电路的数量，确定所述当前栅极集成电路对应的扫描线的各个预充时间段，其中，根据所述当前栅极集成电路之前打开的栅极集成电路的数量越多，所述目标栅极集成电路对应预充时间段的数量越多。
  18. 如权利要求16所述的显示面板，其中，所述计算机可执行指令被所述至少一个处理器执行时，使得一个处理器执行以下步骤：
    将各个所述目标栅极集成电路中依次作为当前栅极集成电路，并确定所述当前栅极集成电路之前打开的各个栅极集成电路对应的扫描线的实际充电时间段，以作为待处理的实际充电时间段；
    将各个所述待处理的设定充电时间段，作为所述当前栅极集成电路对应的扫描线的各个所述预充时间段。
  19. 如权利要求16所述的显示面板，其中，所述计算机可执行指令被所述至少一个处理器执行时，使得一个处理器执行以下步骤：
    确定各个所述目标栅极集成电路，在所述薄膜晶体管基板上的位置；
    根据所述位置确定所述目标栅极集成电路对应的扫描线的预充电时长，其中，所述目标栅极集成电路对应的扫描线越接近所述数据线的数据传输末端，所述预充电时长越长；
    根据所述预充电时长以及所述当前时间点，确定所述目标栅极集成电路对应的扫描线的预充时间段，其中，所述预充时间段的开始时间点晚于或等于所述当前时间点。
  20. 一种计算机可读存储介质，其中，所述计算机可读存储介质存储有可被所述至少一个处理器执行的计算机可执行指令，所述计算机可执行指令被所述至少一个处理器执行时，使得一个处理器执行以下步骤：
    在检测到薄膜晶体管基板上第一颗栅极集成电路打开时，获取预设充电时长以及当前时间点，其中，所述薄膜晶体管基板设有多条横向排列的扫描线以及多条竖向排列的数据线，将与所述数据线的数据传输末端相对距离最大的扫描线作为目标扫描线，以将控制所述目标扫描线打开的栅极集成电路作为所述第一颗栅极集成电路；
    根据所述预设充电时长以及所述当前时间点，确定所述薄膜晶体管基板上除所述第一颗栅极集成电路之外各个目标栅极集成电路对应的扫描线的实际充电时间段；
    确定各个所述目标栅极集成电路对应的扫描线的预充时间段；以及
    控制各个所述目标栅极集成电路的扫描线对应的薄膜晶体管开关，在所述扫描线对应的所述预充时间段以及所述实际充电时间段打开，以对所述扫描线对应的像素进行充电，其中，所述薄膜晶体管基板上数据线对应的各个像素电极的电压极性相同。
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