WO2020103123A1 - 一种相位噪声校正方法和相关设备 - Google Patents

一种相位噪声校正方法和相关设备

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Publication number
WO2020103123A1
WO2020103123A1 PCT/CN2018/117155 CN2018117155W WO2020103123A1 WO 2020103123 A1 WO2020103123 A1 WO 2020103123A1 CN 2018117155 W CN2018117155 W CN 2018117155W WO 2020103123 A1 WO2020103123 A1 WO 2020103123A1
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WO
WIPO (PCT)
Prior art keywords
signal
output
synthesized
frequency
reference source
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Application number
PCT/CN2018/117155
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English (en)
French (fr)
Inventor
张烈
田铅柱
李美峰
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2018/117155 priority Critical patent/WO2020103123A1/zh
Publication of WO2020103123A1 publication Critical patent/WO2020103123A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference

Definitions

  • the present application relates to the field of signal processing technology, in particular to a phase noise correction method and related equipment.
  • Phase noise is an important indicator used to measure the frequency stability quality of frequency standard sources (high-stability crystal oscillator, atomic frequency standard, etc.), and it is also a modulation noise in communication systems.
  • frequency standard sources high-stability crystal oscillator, atomic frequency standard, etc.
  • the influence of phase noise is usually reduced by customizing a local oscillator with higher performance.
  • the deterioration of phase noise becomes more and more serious, making the phase noise of the local oscillator that can be obtained in wireless communication systems or microwave communication systems worse, so that the possible modulation methods for the system are becoming more and more limited .
  • the phase noise of the local oscillator is extracted by adopting the phase division method of the local oscillator and the reference source to extract the phase noise of the local oscillator, or the method of amplifying and sampling after the frequency division of the local oscillator is used to obtain the phase noise of the local oscillator to complete the correction of the phase noise of the transmission and reception
  • the present application provides a phase noise correction method and related equipment, which can reduce the frequency division multiple of the frequency divider, improve the phase noise recovery accuracy, effectively remove the interference of the jitter noise on the correction signal, and improve the phase noise correction performance.
  • a phase noise correction method includes: a transmission device synthesizes a first synthesized signal and a second synthesized signal to obtain a jitter noise cancellation signal; and the transmission device performs filter tracking on the jitter noise cancellation signal Obtain a phase noise correction signal; the transmitting device superimposes the baseband signal with the phase noise correction signal to generate a signal to be output; the transmitting device mixes the signal to be output with the first local oscillator signal to generate an output signal The output signal is sent to the receiving device; wherein, the frequency and delay of the first synthesized signal and the second synthesized signal are the same, and the first synthesized signal is obtained after the output signal of the frequency divider passes through the analog-to-digital converter A signal obtained by synthesizing a signal and a first reference source signal, the second synthesized signal is a signal obtained by synthesizing a reference clock output signal through an analog-to-digital converter and a first delayed signal, and the first local oscillator
  • the transmitting device performs analog-to-digital conversion on the signal output from the frequency divider and the signal output from the reference clock at the same time, and obtains the jitter noise cancellation signal through synthesis (ie, jitter noise removal), and thereby obtains the phase noise correction signal, and
  • the correction signal is used to correct the first local oscillator signal, which can effectively remove the interference of the jitter noise on the correction signal and improve the phase noise correction performance.
  • the method before the first synthesized signal and the second synthesized signal are synthesized, the method further includes: the sending device performs analog-to-digital conversion on the reference clock output signal The signal obtained after the receiver is frequency-multiplied to obtain a first clock signal; the sending device makes the reference source generator output a second reference source signal according to the first clock signal, and the second reference source signal is The frequency of the first clock signal is the same.
  • the method further includes: passing the second reference source signal and the frequency divider output signal through The signals obtained after the analog-to-digital converter are synthesized to obtain a third synthesized signal, and the third synthesized signal has the same frequency as the first clock signal; the first clock signal and the third synthesized signal are correlated to obtain a delay Time information, and configure the delay information into the reference source generator, so that the reference source generator outputs the first reference source signal according to the delay information, the first reference source signal The same frequency and delay as the first clock signal; or, the relevant calculation of the first clock signal and the third synthesized signal to obtain delay information, and the delay information is configured to the delay , So that the delayer outputs the first delay signal according to the time delay information, and the frequency and time delay of the first delay signal and the third synthesized signal are the same.
  • the sending device can adjust the frequency of the signal obtained after the output signal of the frequency divider passes through the analog-to-digital converter through the second reference source signal to make it the same frequency as the first clock signal, so that it can A clock signal is related to calculation to obtain delay information.
  • the delay information in the reference source generator or delayer By configuring the delay information in the reference source generator or delayer, the frequency and delay of the resulting first synthesized signal and second synthesized signal are the same, and then Realize the process of eliminating jitter noise.
  • the sending device synthesizes the signal obtained after the second reference source signal and the output signal of the frequency divider through an analog-to-digital converter to obtain a third synthesized signal
  • the method further includes: the sending device filters the output signal of the frequency divider to extract a signal containing phase noise.
  • the transmitting device filters the obtained signal after dividing the first local oscillator signal, thereby ensuring that the signal containing phase noise can be effectively extracted.
  • the first local oscillator signal is a signal output by the local oscillator after receiving the first input signal
  • the first input signal is a phase-locked local oscillator The signal output by the ring after receiving the reference clock signal sent by the reference clock.
  • the method before filtering and tracking the jitter noise cancellation signal, the method further includes: performing a first rate conversion on the jitter noise cancellation signal; and converting the jitter noise After the filtered signal is filtered and tracked, the method further includes: performing a second rate conversion on the dithered noise removed signal.
  • the transmission device can reduce the rate by performing rate conversion on the jitter noise cancellation signal, so that it can reduce the amount of calculation and improve efficiency in the process of filter tracking, etc., and finally increase the rate through rate conversion to ensure Match the launch rate.
  • the sending device converts the signal to be output into an analog signal through a digital-to-analog converter, and mixes the obtained analog signal with the first local oscillator signal .
  • the sending device can convert the digital domain signal into the analog domain signal, to ensure that the signal to be output can be properly mixed with the first local oscillator signal, and the transmission process is completed.
  • a phase noise correction method includes: a receiving device receives a signal to be corrected sent by a transmitting device; the receiving device synthesizes a first synthesized signal and a second synthesized signal to obtain a jitter noise cancellation signal; Filtering and tracking the jitter noise cancellation signal to obtain a phase noise correction signal; using the phase noise correction signal to perform phase noise correction on the signal to be corrected; wherein, the frequencies of the first synthesized signal and the second synthesized signal Same as the time delay, the first synthesized signal is a signal obtained by synthesizing the output signal of the frequency divider through the analog-to-digital converter and the first reference source signal, and the second synthesized signal is the output signal of the reference clock A signal obtained by synthesizing the signal obtained after the analog-to-digital converter and a first delayed signal, the first reference source signal is a signal output by a reference source generator, and the first delayed signal is a signal output by a delayer.
  • the receiving device performs analog-to-digital conversion on the signal output from the frequency divider and the signal output from the reference clock at the same time, and obtains the jitter noise cancellation signal through synthesis (ie, jitter noise removal), and thereby obtains the phase noise correction signal, and
  • the correction signal is used to correct the received signal to be corrected, which can effectively remove the interference of the jitter noise on the correction signal and improve the phase noise correction performance.
  • the method before the first synthesized signal and the second synthesized signal are synthesized, the method further includes: a receiving device performs analog-to-digital conversion on the reference clock output signal The signal obtained after the receiver is frequency-multiplied to obtain a first clock signal; the receiving device makes the reference source generator output a second reference source signal according to the first clock signal, the second reference source signal and the The frequency of the first clock signal is the same.
  • the method further includes: the receiving device outputs the second reference source signal and the frequency divider
  • the signal obtained after the signal passes through the analog-to-digital converter is synthesized to obtain a third synthesized signal, and the third synthesized signal has the same frequency as the first clock signal; the receiving device performs the first clock signal and the third synthesized signal
  • the correlation calculation obtains the delay information, and configures the delay information into the reference source generator, so that the reference source generator outputs the first reference source signal according to the delay information, the first A reference source signal and the first clock signal have the same frequency and delay; or, the receiving device performs correlation calculation on the first clock signal and the third synthesized signal to obtain delay information, and then the delay information It is configured into the delayer, so that the delayer outputs the first delay signal according to the time delay information, and the frequency and time delay of the first delay signal and the third composite signal are the same.
  • the receiving device can adjust the frequency of the signal obtained after the frequency divider output signal passes through the analog-to-digital converter through the second reference source signal to make it the same frequency as the first clock signal, so that it can be the same as the first clock signal.
  • a clock signal is related to calculation to obtain delay information.
  • the receiving device synthesizes the signal obtained after the second reference source signal and the output signal of the frequency divider through an analog-to-digital converter to obtain a third synthesized signal
  • the method further includes: the receiving device filters the output signal of the frequency divider to extract a signal containing phase noise.
  • the receiving device filters the obtained signal after dividing the first local oscillator signal, thereby ensuring that the signal containing phase noise can be effectively extracted.
  • the method further includes: the receiving device compares the signal to be corrected with The first local oscillator signal is mixed to generate a first output signal, and the first local oscillator signal is a signal output by a local oscillator; the receiving device converts the first output signal to a digital signal through an analog-to-digital converter.
  • the first local oscillator signal is a signal output by the local oscillator after receiving the first input signal
  • the first input signal is a local oscillator phase-locked The signal output by the ring after receiving the reference clock signal sent by the reference clock.
  • the method before the receiving device performs filtering and tracking of the jitter noise cancellation signal, the method further includes: the receiving device performs a first rate conversion on the jitter noise cancellation signal; receiving After the device performs filtering and tracking on the jitter noise cancellation signal, the method further includes: the receiving device performs a second rate conversion on the jitter noise cancellation signal.
  • the receiving device can reduce the rate by performing rate conversion on the jitter noise cancellation signal, so that it can reduce the amount of calculation and improve efficiency in the process of filter tracking, etc., and finally increase the rate through rate conversion to ensure Match the receiving rate.
  • a sending device includes:
  • a synthesis unit configured to synthesize the first synthesized signal and the second synthesized signal to obtain a jitter noise cancellation signal
  • a filter tracking unit configured to filter and track the jitter noise cancellation signal to obtain a phase noise correction signal
  • a superimposing unit configured to superimpose the baseband signal and the phase noise correction signal to generate a signal to be output
  • a mixing output unit for mixing the signal to be output with the first local oscillator signal to generate an output signal and sending the output signal to a receiving device
  • the frequency and delay of the first synthesized signal and the second synthesized signal are the same, the first synthesized signal is the signal obtained after the output signal of the frequency divider passes through the analog-to-digital converter and the first reference source signal A synthesized signal, the second synthesized signal is a signal obtained by synthesizing a signal obtained by a reference clock output signal after passing through an analog-to-digital converter, and a first delayed signal, and the first local oscillator signal is a signal output by a local oscillator
  • the first reference source signal is a signal output by a reference source generator, and the first delay signal is a signal output by a delay.
  • a transmission device includes: a transceiver module, a modulator, a local oscillator, an analog-to-digital converter, a frequency divider, a reference source generator, a delayer, a multiplexing module, and a reference clock Modules, where:
  • the local oscillator is used to generate a first local oscillator signal
  • the modulator is configured to mix the signal to be output after the baseband signal and the phase noise correction signal are superimposed with the first local oscillator signal to generate an output signal;
  • the transceiver module is used to send the output signal to a receiving device
  • the frequency divider is used to divide the first local oscillator signal and output a frequency-divided signal
  • the reference clock module is used to provide a reference clock signal
  • the analog-to-digital converter is used to convert the frequency-divided signal and the reference clock signal into digital signals
  • the reference source generator is used to provide a first reference source signal
  • the delayer is used to provide a first delay signal
  • the multiplexing module is used to synthesize the signal obtained after the output signal of the reference clock module passes through the analog-to-digital converter and the first delayed signal to obtain a second synthesized signal, and to combine the first reference source signal with
  • the signal obtained after the frequency divider output signal passes through the analog-to-digital converter is synthesized to obtain a first synthesized signal, which is also used to synthesize the first synthesized signal and the second synthesized signal to obtain a jitter noise cancellation signal ;
  • the frequency and delay of the first synthesized signal and the second synthesized signal are the same.
  • the sending device further includes a frequency multiplier, and the frequency multiplier is configured to pass the output signal of the reference clock module through the analog-to-digital converter. Frequency multiplication processing is performed to obtain a first clock signal; the reference source generator is also used to provide a second reference source signal, and the second reference source signal has the same frequency as the first clock signal.
  • the multiplexing module is further configured to synthesize the signal obtained after the second reference source signal and the frequency-divided signal pass through the analog-to-digital converter Obtaining a third synthesized signal, the third synthesized signal having the same frequency as the first clock signal;
  • the sending device further includes a correlator for correlating the first clock signal with the third synthesized signal Calculate, obtain delay information, and configure the delay information into the reference source generator, so that the reference source generator outputs the first reference source signal according to the delay information, the first A reference source signal has the same frequency and delay as the first clock signal; or, the delay information is configured into the delayer, so that the delayer outputs the delayer according to the delay information A first delayed signal, the first delayed signal and the third synthesized signal have the same frequency and time delay.
  • the sending device further includes a filter for filtering the frequency-divided signal to extract a signal containing phase noise.
  • the sending device further includes a local oscillator phase-locked loop, configured to receive a reference clock signal output by the reference clock module and output a first output signal, so that the The local oscillator outputs the first local oscillator signal according to the first output signal.
  • a local oscillator phase-locked loop configured to receive a reference clock signal output by the reference clock module and output a first output signal, so that the The local oscillator outputs the first local oscillator signal according to the first output signal.
  • the sending device further includes a rate change module, configured to perform a first rate conversion on the jitter noise cancellation signal before the jitter noise cancellation signal undergoes filter tracking, And performing a second rate conversion on the jitter noise cancellation signal after filtering and tracking the jitter noise cancellation signal.
  • the sending device further includes a digital-to-analog converter for converting the signal to be output into an analog signal, and sending the analog signal to the modulator , So that the modulator mixes the analog signal with the first local oscillator signal.
  • a receiving device includes:
  • the receiving unit is used to receive the signal to be corrected sent by the sending device
  • a synthesis unit configured to synthesize the first synthesized signal and the second synthesized signal to obtain a jitter noise cancellation signal
  • a filter tracking unit configured to filter and track the jitter noise cancellation signal to obtain a phase noise correction signal
  • a correction unit configured to perform phase noise correction on the signal to be corrected according to the phase noise correction signal
  • the frequency and delay of the first synthesized signal and the second synthesized signal are the same, the first synthesized signal is the signal obtained after the output signal of the frequency divider passes through the analog-to-digital converter and the first reference source signal A synthesized signal, the second synthesized signal is a signal obtained by synthesizing a reference clock output signal through an analog-to-digital converter and a first delayed signal, and the first reference source signal is output by a reference source generator Signal, the first delayed signal is a signal output by the delay.
  • a receiving device includes a transceiver module, a demodulator, a local oscillator, an analog-to-digital converter, a frequency divider, a reference source generator, a delayer, a multiplexing module, and a reference Clock module, where:
  • the local oscillator is used to generate a first local oscillator signal
  • the transceiver module is used to receive the signal to be corrected sent by the sending device
  • the demodulator is used to mix the signal to be corrected with the first local oscillator signal to generate a first output signal
  • the frequency divider is used to divide the first local oscillator signal and output a frequency-divided signal
  • the reference clock module is used to provide a reference clock signal
  • the analog-to-digital converter is used to convert the frequency-divided signal and the reference clock signal into digital signals
  • the reference source generator is used to provide a first reference source signal
  • the delayer is used to provide a first delay signal
  • the multiplexing module is used to synthesize the signal obtained after the output signal of the reference clock module passes through the analog-to-digital converter and the first delayed signal to obtain a second synthesized signal, and to combine the first reference source signal with
  • the signal obtained after the frequency divider output signal passes through the analog-to-digital converter is synthesized to obtain a first synthesized signal, which is also used to synthesize the first synthesized signal and the second synthesized signal to obtain a jitter noise cancellation signal ;
  • the frequency and delay of the first synthesized signal and the second synthesized signal are the same.
  • the receiving device further includes a frequency multiplier, and the frequency multiplier is configured to obtain a signal obtained by passing the output signal of the reference clock module through the analog-to-digital converter Frequency multiplication processing is performed to obtain a first clock signal; the reference source generator is also used to provide a second reference source signal, and the second reference source signal has the same frequency as the first clock signal.
  • the multiplexing module is further configured to synthesize the signal obtained after the second reference source signal and the frequency-divided signal pass through the analog-to-digital converter Obtaining a third synthesized signal, the third synthesized signal having the same frequency as the first clock signal;
  • the sending device further includes a correlator for correlating the first clock signal with the third synthesized signal Calculate, obtain delay information, and configure the delay information into the reference source generator, so that the reference source generator outputs the first reference source signal according to the delay information, the first A reference source signal has the same frequency and delay as the first clock signal; or, the delay information is configured into the delayer, so that the delayer outputs the delayer according to the delay information A first delayed signal, the first delayed signal and the third synthesized signal have the same frequency and time delay.
  • the receiving device further includes a filter, configured to filter the frequency-divided signal to extract a signal containing phase noise.
  • the receiving device further includes a local oscillator phase-locked loop, and the local oscillator phase-locked loop is configured to receive the reference clock signal output by the reference clock module and output the first Two output signals, so that the local oscillator outputs the first local oscillator signal according to the second output signal; and the analog-to-digital converter is also used to convert the first output signal to a digital signal.
  • the receiving device further includes a rate change module, configured to perform a first rate conversion on the jitter noise cancellation signal before the jitter noise cancellation signal undergoes filter tracking, And performing a second rate conversion on the jitter noise cancellation signal after filtering and tracking the jitter noise cancellation signal.
  • FIG. 1 is a schematic diagram of a scenario architecture provided by an embodiment of this application.
  • FIG. 2 is a schematic flowchart of a phase noise correction method provided by an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of another phase noise correction method provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a sending device according to an embodiment of this application.
  • FIG. 5 is a schematic structural diagram of another sending device according to an embodiment of this application.
  • FIG. 6 is a schematic structural diagram of a receiving device according to an embodiment of this application.
  • FIG. 7 is a schematic structural diagram of another receiving device according to an embodiment of the present application.
  • the technical solutions of the embodiments of the present application can be applied to a long term evolution (LTE) system architecture, and can also be applied to a universal mobile telecommunications system (UMTS) terrestrial wireless access network (UMTS terrestrial radio access) network, UTRAN) architecture, or global mobile communication system (global system for mobile GSM), enhanced data rate GSM evolution (enhanced data for rate GSM evolution, EDGE) system wireless access network (GSM EDGE radio access network, GERAN) architecture .
  • UMTS universal mobile telecommunications system
  • UTRAN universal mobile telecommunications system
  • GSM global system for mobile GSM
  • enhanced data rate GSM evolution enhanced data for rate GSM evolution
  • EDGE enhanced data for rate GSM evolution
  • GSM EDGE radio access network GSM EDGE radio access network
  • GERAN global mobile communication system
  • the technical solutions of the embodiments of the present application may also be applied to other communication systems, such as a public land mobile network (publish land mobile) network (PLMN) system, or
  • the embodiments of the present application relate to a sending device.
  • the sending device may be any device with a wireless transmission function or a chip that can be set in the device.
  • the device includes but is not limited to: evolved Node B (evolved Node B, eNB), radio network controller (radio network controller) , RNC), Node B (Node B, NB), Base Station Controller (BSC), Base Transceiver Station (BTS), Home Base Station (eg, home evolved NodeB, or home Node B, HNB ), Baseband unit (BBU), access point (AP), wireless relay node, wireless backhaul node, transmission point (transmission point) in a wireless fidelity (WIFI) system TP) or transmission and reception points (TRP), etc.
  • 5G such as NR, gNB in the system, or, transmission point (TRP or TP), one or a group of base stations in the 5G system (Including multiple antenna panels)
  • An antenna panel or, may be a network node that constitutes
  • the embodiment of the present application also relates to a receiving device.
  • the receiving device may be any device with a wireless receiving function or a chip that can be installed in the device.
  • the device includes but is not limited to: evolved Node B (evolved Node B, eNB), radio network controller (radio network controller) , RNC), Node B (Node B, NB), Base Station Controller (BSC), Base Transceiver Station (BTS), Home Base Station (eg, home evolved NodeB, or home Node B, HNB ), Baseband unit (BBU), access point (AP), wireless relay node, wireless backhaul node, transmission point (transmission point) in a wireless fidelity (WIFI) system TP) or transmission and reception point (transmission and reception point, TRP), etc.
  • 5G such as NR, gNB in the system, or, transmission point (TRP or TP), one or a group of base stations in the 5G system (Including multiple antenna panels)
  • An antenna panel or, may be a
  • the sending device and / or receiving device may also be a new generation user equipment (new generation UE, gUE).
  • User equipment may also be referred to as terminal equipment (user equipment, UE), access terminal, subscriber unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user Agent or user device.
  • the terminal equipment can be a station (STA) in a wireless local area network (WLAN), a cellular phone, a cordless phone, a session initiation protocol (SIP) phone, and a wireless local loop (wireless local) loop, WLL) station, personal digital processing (personal digital assistant (PDA) device, handheld device with wireless communication function, computing device or other processing device connected to a wireless modem, in-vehicle device, wearable device, and next-generation communication system, For example, terminal equipment in a fifth-generation (5G) network or terminal equipment in a public land mobile network (PLMN) network that evolves in the future, a new radio (NR) communication system Terminal equipment, etc.
  • 5G fifth-generation
  • PLMN public land mobile network
  • NR new radio
  • the terminal device may also be a wearable device.
  • Wearable devices can also be referred to as wearable smart devices. It is a general term for applying wearable technology to intelligently design everyday wear and develop wearable devices, such as glasses, gloves, watches, clothing and shoes.
  • a wearable device is a portable device that is worn directly on the body or integrated into the user's clothes or accessories. Wearable devices are not only a hardware device, but also realize powerful functions through software support, data interaction, and cloud interaction.
  • Generalized wearable smart devices include full-featured, large-sized, complete or partial functions that do not depend on smartphones, such as: smart watches or smart glasses, and only focus on a certain type of application functions, and need to cooperate with other devices such as smartphones Use, such as various smart bracelets and smart jewelry for sign monitoring.
  • the present application provides a phase noise correction method, which can effectively remove the interference of the jitter noise on the correction signal and improve the phase noise correction performance.
  • FIG. 1 is a schematic diagram of a scenario architecture provided by an embodiment of the present application.
  • the architecture includes a sending device 110 and a receiving device 120, and the sending device 110 and the receiving device 120 form a communication system.
  • the transmitting device 110 transmits the data to be transmitted to the receiving device 120 through the high-frequency wireless network by microwave or radio frequency through modulation
  • the receiving device 120 receives the wireless signal transmitted by the transmitting device 110 through the high-frequency wireless network, and Obtain the data carried in it by demodulating it.
  • FIG. 2 is a schematic flowchart of a phase noise correction method provided by an embodiment of the present application.
  • the sending device described in FIG. 2 may correspond to the sending device 110 shown in FIG. 1.
  • the method includes but is not limited to the following steps:
  • the sending device synthesizes the first synthesized signal and the second synthesized signal to obtain a jitter noise cancellation signal.
  • the transmission device synthesizes the first synthesized signal and the second synthesized signal, it is necessary to ensure that the frequency and delay of the first synthesized signal and the second synthesized signal are the same.
  • the first synthesized signal and the second synthesized signal can be passed through a complex number
  • the multiplier performs a complex conjugate operation on it to eliminate jitter noise to obtain a jitter noise cancellation signal.
  • the jitter in the second synthesized signal that is, the signal obtained after analog-to-digital conversion of the clock signal
  • Noise signal to remove the jitter noise signal in the first synthesized signal ie, the signal containing phase noise).
  • the first synthesized signal here refers to the signal obtained by synthesizing the signal obtained by the output signal of the frequency divider through the analog-to-digital converter and the first reference source signal
  • the second synthesized signal refers to the analog-digital conversion of the reference clock output signal The signal obtained after the synthesizer and the first delayed signal are synthesized.
  • the first reference source signal is the signal output by the reference source generator
  • the first delay signal is the signal output by the delayer.
  • the purpose of introducing the reference source generator and the delayer is to ensure that the first synthesized signal and the second The synthesized signal can meet the requirements of frequency and time delay, can perform complex conjugate operation, eliminate jitter noise, and obtain a jitter noise cancellation signal. All the first and second references in the embodiments of the present application are only for distinguishing, and do not constitute a specific limitation.
  • the sending device before the transmitting device synthesizes the first synthesized signal and the second synthesized signal, performs frequency multiplication processing on the signal obtained after the reference clock output signal passes through the analog-to-digital converter to obtain the first
  • the clock signal causes the reference source generator to output a second reference source signal according to the first clock signal, and the second reference source signal has the same frequency as the first clock signal.
  • the reference clock output signal is an analog signal, so it needs to be digitally sampled by an analog-to-digital converter and converted into a digital signal. It can be understood that if the correction of the phase noise signal is completed by an analog device, the requirements for the analog device are high, the cost is too high, and the implementation is complicated and the accuracy is not high.
  • the analog signal is converted into a digital signal by an analog-to-digital converter.
  • the digital device completes the correction of the phase noise, which can avoid the non-ideal effect of analog correction, improve the accuracy and achieve simple, low difficulty.
  • the frequency of the reference clock output signal is relatively low compared to the frequency of the local oscillation signal, etc. Even after it is converted to a digital signal by an analog-to-digital converter, its frequency is still low. In order to increase its frequency, you can After being converted into a digital signal, it is frequency-doubled to increase its frequency.
  • a frequency multiplier to increase its signal frequency, and it can be processed by double frequency, quadruple frequency or other multiples.
  • the specific multiple can be set according to actual needs.
  • the method and specific frequency multiplier are not specifically limited.
  • the analog-to-digital converter will introduce jitter noise in the process of converting the analog signal to a digital signal to simplify the calculation.
  • the reference source generator performs frequency multiplication processing on the reference clock signal After the first clock signal is obtained, a second reference source signal consistent with the frequency of the first clock signal is output, and the second reference source signal is used to adjust the frequency of the frequency divider output signal so that it matches the first clock signal The frequency of the signal is the same, so that subsequent synchronization configuration and adjustment can be performed.
  • the transmitting device synthesizes the signal obtained by the second reference source signal and the frequency divider output signal after passing through the analog-to-digital converter to obtain the first Three combined signals, the third combined signal has the same frequency as the first clock signal.
  • the transmitting device needs to filter the signal output by the frequency divider to extract Phase noise signal.
  • the signal output by the frequency divider contains a phase noise signal.
  • the phase noise signal needs to be extracted to obtain a phase noise correction signal, so the output signal of the frequency divider can be filtered by a band pass filter to extract Phase noise signal.
  • the transmitting device may filter the output signal of the frequency divider before passing through the analog-to-digital converter to extract the signal containing phase noise, or may filter and extract the signal of the frequency divider after passing through the analog-to-digital converter. If the phase noise signal is filtered before passing through the analog-to-digital converter, an analog bandwidth filter needs to be deployed for filtering and extraction. If it is filtered after passing through the analog-to-digital converter, a digital bandwidth filter needs to be deployed for filtering and extraction.
  • the deployment position of the pass filter and the bandwidth selection ie, the filter range) can be set according to actual needs, which is not limited in this application.
  • the frequency divider divides the local oscillator signal, it will attenuate the energy of the local oscillator signal and the phase noise signal it contains.
  • the number of frequency divisions is closely related to the energy of the signal. Every additional frequency division, The corresponding signal energy will be reduced by 6 decibels (dB), for example, at this time, the frequency of the local oscillator signal and the phase noise contained in it is 10 GHz, and the corresponding signal strength is -115 dB, which is divided (divided by two) ,
  • the frequency of the frequency-divided signal output by the frequency divider is 5 GHz, and the corresponding signal energy is -121 dB.
  • phase noise signal of this application is to filter the output signal of the frequency divider by setting a band-pass filter, which can effectively reduce the frequency division multiple of the frequency divider, and ensure that the analog-to-digital converter can correctly digitalize the output signal of the frequency divider Sampling to ensure that the digital signal output contains the phase noise signal that needs to be extracted to improve the accuracy of phase noise recovery.
  • the sending device uses the second reference source signal to adjust the frequency of the signal obtained after the frequency divider output signal passes through the analog-to-digital converter. Since the frequency of the second reference source signal is consistent with the first clock signal, the frequency adjustment , the signal containing phase noise (ie, the third synthesized signal) has the same frequency as the first clock signal.
  • the transmitting device performs correlation calculation on the first clock signal and the third synthesized signal to obtain delay information, and configures the delay information into the reference source generator, so that the reference source generator outputs the first delay information according to the delay information.
  • a reference source signal, or the delay information is configured in the delayer, so that the delayer outputs the first delay signal according to the delay information.
  • the sending device sends the first clock signal and the third synthesized signal to the correlator together for correlation calculation.
  • both the first clock signal and the third synthesized signal are converted into digital signals by the analog-to-digital converter, their time delay Not synchronized, it may be that the third composite signal is leading, the first clock signal is lagging, or it may be that the first clock signal is leading, and the third composite signal is lagging.
  • the correlator can obtain the delay information of the clock synchronization between them after the correlation calculation.
  • the sending device will configure the delay information calculated by the correlator to In the reference source generator, the reference source generator outputs the first reference source signal to adjust the delay of the third synthesized signal (that is, synthesize the third synthesized signal and the first reference source signal to obtain the first synthesized signal), so that Synchronize with the time delay of the first clock signal, at this time, the frequency and delay of the first reference source signal and the first clock signal are also the same, then the frequency and delay of the first composite signal and the first clock signal are also synchronized .
  • the delay configuration of the delayer can be set to 0, then the frequency and time delay of the second synthesized signal and the first clock signal are also the same, thereby realizing the frequency and time of the first synthesized signal and the second synthesized signal
  • the first synthesized signal and the second synthesized signal can be subjected to complex conjugate operations to eliminate jitter noise and obtain a jitter noise cancellation signal.
  • the sending device configures the delay information calculated by the correlator to the delay device, so that the delay device outputs the first delay according to the configured delay information.
  • the delay signal adjusts the time delay of the first clock signal (that is, synthesizes the first clock signal and the first delay signal to obtain a second synthesized signal) to synchronize the delay with the third synthesized signal.
  • the first delayed signal The frequency and delay of the third composite signal are also the same, and the frequency and delay of the second composite signal and the third composite signal are also synchronized.
  • the delay configuration of the reference source generator can be set to 0, and the frequency and delay of the first synthesized signal and the third synthesized signal are also the same, thereby realizing the frequencies of the first synthesized signal and the second synthesized signal Synchronized with the time delay, and further, the first synthesized signal and the second synthesized signal can be subjected to complex conjugate operation to eliminate jitter noise, thereby obtaining a jitter noise cancellation signal.
  • the transmitting device filters and tracks the jitter noise cancellation signal to obtain a phase noise correction signal.
  • the transmission device synthesizes the first synthesized signal and the second synthesized signal to obtain the jitter noise cancellation signal, although the jitter noise is eliminated, the extracted phase noise signal is not pure, and some other noises still exist
  • the signal needs to be further processed to extract a relatively pure phase noise signal.
  • the transmitting device passes the jitter noise cancellation signal through an adaptive filter (such as a Kalman filter) to filter out the interference noise signal therein to obtain a phase noise correction signal.
  • an adaptive filter such as a Kalman filter
  • the transmitting device before the jitter noise cancellation signal is filtered and tracked, performs a first rate conversion on the jitter noise cancellation signal through a rate converter, and after filtering and tracking the jitter noise cancellation signal, The jitter noise cancellation signal undergoes a second rate conversion by a rate converter.
  • the sampling rate corresponding to the jitter noise cancellation signal is relatively high. If it is filtered and tracked directly through the adaptive filter, the calculation amount is relatively large. Therefore, before performing the filter tracking, the rate converter is used to eliminate the jitter noise cancellation signal. Re-sampling to reduce its sampling rate can reduce the amount of calculation. After filtering and tracking (that is, after filtering out other interference noise signals through an adaptive filter), in order to match the transmission rate of the baseband signal, it needs to be re-sampled again by a rate converter to increase its sampling rate.
  • the transmitting device superimposes the baseband signal and the phase noise correction signal to generate a signal to be output.
  • the sending device mixes the signal to be output with the first local oscillator signal to generate an output signal, and sends the output signal to the receiving device.
  • the transmitting device will use the phase noise correction signal to perform phase noise correction on the first local oscillator signal, for example, perform a complex conjugate operation on the phase noise correction signal and the first local oscillator signal to Eliminate and correct the phase noise in the first local oscillator signal.
  • the sending device modulates the baseband signal by using the local oscillator signal that has been corrected for phase noise by sending the signal to be output and the first local oscillator signal into the modulator. Since the frequency of the first local oscillator signal is higher, the The baseband signal can be modulated onto a radio frequency or microwave frequency point to generate an output signal and send the output signal to a receiving device through a transmitting antenna or the like.
  • the first local oscillator signal is a signal output by the local oscillator after receiving the first input signal
  • the first input signal is a reference sent by the local oscillator phase-locked loop after receiving the reference clock The signal output after the clock signal.
  • the reference clock provides a reference clock signal for the local oscillator PLL.
  • the local oscillator PLL After receiving the reference clock signal, the local oscillator PLL outputs a first-level local oscillation signal from a voltage controlled oscillator (VCO).
  • VCO voltage controlled oscillator
  • LO local oscillator
  • the local oscillator receives the first-stage local oscillation signal (that is, the first After an input signal)
  • frequency multiply the first-level local oscillation signal to increase the frequency of the signal.
  • the number of frequency multiplications can be set according to actual needs, which is not limited in this application.
  • the local oscillator outputs the first local oscillator signal after frequency multiplication processing to increase the signal frequency.
  • the sending device before the sending device sends the signal to be output to the modulator and mixes with the first local oscillator signal, the sending device converts the signal to be output into an analog signal through a digital-to-analog converter. The analog signal is mixed with the first local oscillator signal.
  • the transmission device obtains a digital signal after superimposing the baseband signal and the phase noise correction signal, and the first local oscillator signal is an analog signal.
  • the object to be modulated by the modulator should be an analog signal, so the transmission device
  • the signal to be output needs to be converted into an analog signal by a digital-to-analog converter, and the converted analog signal is mixed with the first local oscillator signal.
  • FIG. 3 is a schematic flowchart of another phase noise correction method provided by an embodiment of the present application.
  • the receiving device described in FIG. 3 may correspond to the receiving device 120 shown in FIG. As shown in FIG. 3, the method includes but is not limited to the following steps:
  • S310 The receiving device receives the signal to be corrected sent by the sending device.
  • the receiving device receives the signal to be corrected, since the frequency of the signal to be corrected is relatively high, it is necessary to perform frequency reduction processing on it.
  • the receiving device sends the signal to be corrected to the demodulator, and mixes the first local oscillator signal output by the local oscillator with the signal to be corrected to reduce its frequency.
  • S320 The receiving device synthesizes the first synthesized signal and the second synthesized signal to obtain a jitter noise cancellation signal.
  • the receiving device synthesizes the first synthesized signal and the second synthesized signal, it is necessary to ensure that the frequency and delay of the first synthesized signal and the second synthesized signal are the same.
  • the first synthesized signal and the second synthesized signal can be passed through a complex number
  • the multiplier performs a complex conjugate operation on it to eliminate jitter noise to obtain a jitter noise cancellation signal.
  • the jitter in the second synthesized signal that is, the signal obtained after analog-to-digital conversion of the clock signal
  • Noise signal to remove the jitter noise signal in the first synthesized signal ie, the signal containing phase noise).
  • the first synthesized signal here refers to the signal obtained by synthesizing the signal obtained by the output signal of the frequency divider through the analog-to-digital converter and the first reference source signal
  • the second synthesized signal refers to the analog-digital conversion of the reference clock output signal The signal obtained after the synthesizer and the first delayed signal are synthesized.
  • the first reference source signal is the signal output by the reference source generator
  • the first delay signal is the signal output by the delayer.
  • the purpose of introducing the reference source generator and the delayer is to ensure that the first synthesized signal and the second The synthesized signal can meet the requirements of frequency and time delay, can perform complex conjugate operation, eliminate jitter noise, and obtain a jitter noise cancellation signal. All the first and second references in the embodiments of the present application are only for distinguishing, and do not constitute a specific limitation.
  • the receiving device before the receiving device synthesizes the first synthesized signal and the second synthesized signal, the receiving device performs frequency multiplication processing on the signal obtained after the reference clock output signal passes through the analog-to-digital converter to obtain the first
  • the clock signal causes the reference source generator to output a second reference source signal according to the first clock signal, and the second reference source signal has the same frequency as the first clock signal.
  • the reference clock output signal is an analog signal, so it needs to be digitally sampled by an analog-to-digital converter and converted into a digital signal. It can be understood that if the correction of the phase noise signal is completed by an analog device, the requirements for the analog device are high, the cost is too high, and the implementation is complicated and the accuracy is not high.
  • the analog signal is converted into a digital signal by an analog-to-digital converter.
  • the digital device completes the correction of the phase noise, which can avoid the non-ideal effect of analog correction, improve the accuracy and achieve simple, low difficulty.
  • the frequency of the reference clock output signal is relatively low compared to the frequency of the local oscillation signal, etc. Even after it is converted to a digital signal by an analog-to-digital converter, its frequency is still low. In order to increase its frequency, you can After being converted into a digital signal, it is frequency-doubled to increase its frequency.
  • a frequency multiplier to increase its signal frequency, and it can be processed by double frequency, quadruple frequency or other multiples.
  • the specific multiple can be set according to actual needs.
  • the method and specific frequency multiplier are not specifically limited.
  • the analog-to-digital converter will introduce jitter noise in the process of converting the analog signal to a digital signal to simplify the calculation.
  • the reference source generator performs frequency multiplication processing on the reference clock signal After the first clock signal is obtained, a second reference source signal consistent with the frequency of the first clock signal is output, and the second reference source signal is used to adjust the frequency of the frequency divider output signal so that it matches the first clock signal The frequency of the signal is the same, so that subsequent synchronization configuration and adjustment can be performed.
  • the receiving device synthesizes the signal obtained by the second reference source signal and the frequency divider output signal after passing through the analog-to-digital converter to obtain the first Three combined signals, the third combined signal has the same frequency as the first clock signal.
  • the receiving device needs to filter the signal output by the frequency divider to extract Phase noise signal.
  • the signal output by the frequency divider contains a phase noise signal.
  • the phase noise signal needs to be extracted to obtain a phase noise correction signal, so the output signal of the frequency divider can be filtered by a band pass filter to extract Phase noise signal.
  • the receiving device may filter the output signal of the frequency divider before passing through the analog-to-digital converter to extract the signal containing phase noise, or may filter and extract the signal of the frequency divider after passing through the analog-to-digital converter.
  • the phase noise signal is filtered before passing through the analog-to-digital converter, an analog bandwidth filter needs to be deployed for filtering and extraction. If it is filtered after passing through the analog-to-digital converter, a digital bandwidth filter needs to be deployed for filtering and extraction.
  • the deployment position of the pass filter and the bandwidth selection ie, the filter range) can be set according to actual needs, which is not limited in this application.
  • the frequency divider divides the local oscillator signal, it will attenuate the energy of the local oscillator signal and the phase noise signal it contains.
  • the number of frequency divisions is closely related to the strength of the signal. Every additional frequency division, The corresponding signal energy will be reduced by 6 decibels (dB).
  • dB decibels
  • the frequency of the local oscillator signal and the phase noise it contains is 10 GHz, and the corresponding signal energy is -115 dB, which is divided (divided by two)
  • the frequency of the frequency-divided signal output by the frequency divider is 5 GHz, and the corresponding signal energy is -121 dB.
  • phase noise signal of this application is to filter the output signal of the frequency divider by setting a band-pass filter, which can effectively reduce the frequency division multiple of the frequency divider, and ensure that the analog-to-digital converter can correctly digitalize the output signal of the frequency divider Sampling to ensure that the digital signal output contains the phase noise signal that needs to be extracted to improve the accuracy of phase noise recovery.
  • the receiving device uses the second reference source signal to adjust the frequency of the signal obtained after the frequency divider output signal passes through the analog-to-digital converter. Since the frequency of the second reference source signal is consistent with the first clock signal, the frequency adjustment , the signal containing phase noise (ie, the third synthesized signal) has the same frequency as the first clock signal.
  • the receiving device performs correlation calculation on the first clock signal and the third synthesized signal to obtain delay information, and configures the delay information into the reference source generator, so that the reference source generator outputs the first delay information according to the delay information.
  • a reference source signal, or the delay information is configured in the delayer, so that the delayer outputs the first delay signal according to the delay information.
  • the receiving device sends the first clock signal and the third synthesized signal to the correlator together for correlation calculation.
  • both the first clock signal and the third synthesized signal are converted into digital signals by the analog-to-digital converter, their time delay Not synchronized, it may be that the third composite signal is leading, the first clock signal is lagging, or it may be that the first clock signal is leading, and the third composite signal is lagging.
  • the correlator can obtain the delay information of the clock synchronization between them after the correlation calculation.
  • the receiving device will configure the delay information calculated by the correlator to In the reference source generator, the reference source generator outputs the first reference source signal to adjust the delay of the third synthesized signal (that is, synthesize the third synthesized signal and the first reference source signal to obtain the first synthesized signal), so that Synchronize with the time delay of the first clock signal, at this time, the frequency and delay of the first reference source signal and the first clock signal are also the same, then the frequency and delay of the first composite signal and the first clock signal are also synchronized .
  • the delay configuration of the delayer can be set to 0, then the frequency and time delay of the second synthesized signal and the first clock signal are also the same, thereby realizing the frequency and time of the first synthesized signal and the second synthesized signal
  • the first synthesized signal and the second synthesized signal can be subjected to complex conjugate operations to eliminate jitter noise and obtain a jitter noise cancellation signal.
  • the receiving device will configure the delay information calculated by the correlator to the delay device, so that the delay device outputs the first delay signal according to the configured delay information.
  • the delay signal adjusts the time delay of the first clock signal (that is, synthesizes the first clock signal and the first delay signal to obtain a second synthesized signal) to synchronize the delay with the third synthesized signal.
  • the first delayed signal The frequency and delay of the third composite signal are also the same, and the frequency and delay of the second composite signal and the third composite signal are also synchronized.
  • the delay configuration of the reference source generator can be set to 0, and the frequency and delay of the first synthesized signal and the third synthesized signal are also the same, thereby realizing the frequencies of the first synthesized signal and the second synthesized signal Synchronized with the time delay, and further, the first synthesized signal and the second synthesized signal can be subjected to complex conjugate operation to eliminate jitter noise, thereby obtaining a jitter noise cancellation signal.
  • the receiving device performs filtering and tracking on the jitter noise cancellation signal to obtain a phase noise correction signal.
  • the receiving device synthesizes the first synthesized signal and the second synthesized signal to obtain a jitter noise cancellation signal, although the jitter noise is eliminated, the extracted phase noise signal is not pure, and some other noises still exist
  • the signal needs to be further processed to extract a relatively pure phase noise signal.
  • the receiving device passes the jitter noise cancellation signal through an adaptive filter (such as a Kalman filter) to filter out the interference noise signal therein to obtain a phase noise correction signal.
  • an adaptive filter such as a Kalman filter
  • the receiving device before the jitter noise cancellation signal is filtered and tracked, the receiving device performs a first rate conversion on the jitter noise cancellation signal through a rate converter, and after filtering and tracking the jitter noise cancellation signal, The jitter noise cancellation signal undergoes a second rate conversion by a rate converter.
  • the sampling rate corresponding to the jitter noise cancellation signal is relatively high. If it is filtered and tracked directly through the adaptive filter, the calculation amount is relatively large. Therefore, before performing the filter tracking, the rate converter is used to eliminate the jitter noise cancellation signal. Re-sampling to reduce its sampling rate can reduce the amount of calculation. After filtering and tracking (that is, after filtering out other interference noise signals through an adaptive filter), in order to match the transmission rate of the baseband signal, it needs to be re-sampled again by a rate converter to increase its sampling rate.
  • S340 The receiving device uses the phase noise correction signal to perform phase noise correction on the signal to be corrected.
  • the receiving device before the receiving device uses the phase noise correction signal to perform phase noise correction on the signal to be corrected, the receiving device mixes the signal to be corrected with the first local oscillator signal to generate a first output signal, which The vibration signal is a signal output by a local oscillator, and converts the first output signal to a digital signal through an analog-to-digital converter.
  • the receiving device needs to mix the signal to be corrected with the first local oscillator signal, and then uses the phase noise correction signal and the first output signal to perform complex conjugate operation to eliminate the phase noise in the corrected first output signal Since the phase noise correction signal is a digital signal and the first output signal is an analog signal, the phase noise correction can be performed only after the first output signal is converted into a digital signal by an analog-to-digital converter.
  • the first local oscillator signal is a signal output by the local oscillator after receiving the first input signal
  • the first input signal is a reference sent by the local oscillator phase-locked loop after receiving the reference clock The signal output after the clock signal.
  • the reference clock provides a reference clock signal for the local oscillator PLL.
  • the local oscillator PLL After receiving the reference clock signal, the local oscillator PLL outputs a first-level local oscillation signal from a voltage controlled oscillator (VCO).
  • VCO voltage controlled oscillator
  • LO local oscillator
  • the local oscillator receives the first-stage local oscillation signal (that is, the first After an input signal)
  • frequency multiply the first-level local oscillation signal to increase the frequency of the signal.
  • the number of frequency multiplications can be set according to actual needs, which is not limited in this application.
  • the local oscillator outputs the first local oscillator signal after frequency multiplication processing to increase the signal frequency.
  • FIG. 4 is a schematic structural diagram of a transmission device according to an embodiment of the present application.
  • the transmission device 400 includes at least: a synthesis unit 410, a filter tracking unit 420, a superposition unit 430, and a mixing output unit 440; wherein:
  • the synthesizing unit 410 is configured to synthesize the first synthesized signal and the second synthesized signal to obtain a jitter noise cancellation signal, where the frequency and delay of the first synthesized signal and the second synthesized signal are the same;
  • the filter tracking unit 420 is configured to filter and track the jitter noise cancellation signal to obtain a phase noise correction signal
  • the superimposing unit 430 is configured to superimpose the baseband signal and the phase noise correction signal to generate a signal to be output;
  • the mixing output unit 440 is configured to mix the signal to be output with the first local oscillator signal, generate an output signal, and send the output signal to a receiving device;
  • the sending device 400 further includes an oscillation signal generating unit 450 for generating a first local oscillator signal; a reference signal generating unit 460 for generating a first reference source signal; and a delay signal generating unit 470 for generating a first Delay signal; clock signal generation unit 480, used to generate a reference clock signal; frequency division unit 490, used to divide the first local oscillator signal to obtain a frequency-divided signal; analog-to-digital conversion unit 4110, used to divide the frequency-divided signal and Perform analog-to-digital conversion on the reference clock signal to obtain a frequency-divided digital signal and a reference clock digital signal; the synthesizing unit 410 is further configured to convert the frequency-divided digital signal output from the analog-to-digital conversion unit 4110 and the first The reference source signal is synthesized to obtain a first synthesized signal; the synthesizing unit 410 is further configured to synthesize the reference clock digital signal output from the analog-to-digital conversion unit 4110 and
  • the transmission device performs analog-to-digital conversion on the frequency-divided signal output by the frequency-dividing unit 490 and the reference clock signal output from the clock signal generating unit 480 by using the analog-to-digital conversion unit 4110, and the synthesis unit 410 performs synthesis
  • the jitter noise cancellation signal and the signal are used to correct the first local oscillator signal output by the oscillation signal generating unit 450, which can effectively remove the interference of the jitter noise on the correction signal and improve the phase noise correction performance.
  • the sending device 400 further includes a frequency multiplication unit 4120, configured to perform frequency multiplication processing on the reference clock digital signal output by the analog-to-digital conversion unit 4110 to output a first clock signal; the reference signal The generating unit 460 is further configured to generate a second reference source signal, and the second reference source signal has the same frequency as the first clock signal.
  • the synthesis unit 410 is further configured to synthesize the second reference source signal output by the reference signal generation unit 460 and the frequency-divided digital signal output by the analog-to-digital conversion unit 4110 to obtain a third synthesized signal ,
  • the third synthesized signal has the same frequency as the first clock signal;
  • the sending device 400 further includes a correlation calculation unit 4130, configured to perform correlation calculation on the first clock signal and the third synthesized signal output by the frequency multiplication unit 4120 to obtain delay information, and configure the delay information to the reference A signal generating unit 460, so that the reference signal generating unit 460 outputs a first reference source signal, and the frequency and delay of the first reference source signal and the first clock signal are the same;
  • a correlation calculation unit 4130 configured to perform correlation calculation on the first clock signal and the third synthesized signal output by the frequency multiplication unit 4120 to obtain delay information, and configure the delay information to the reference A signal generating unit 460, so that the reference signal generating unit 460 outputs a first reference source signal, and the frequency and delay of the first reference source signal and the first clock signal are the same;
  • the correlation calculation unit 4130 configures the delay information to the delay signal generation unit 470, so that the delay signal generation unit 470 outputs the first delay signal, the frequency and time of the first delay signal and the third synthesized signal The same.
  • the sending device 400 further includes a filtering unit 4140 for filtering the frequency-divided signal output by the frequency-dividing unit 490 to extract a signal containing phase noise.
  • the sending device 400 further includes a second local oscillator signal generating unit 4150 for receiving the reference clock signal output by the clock signal generating unit 480 and outputting the second local oscillator signal to the oscillation signal generation In unit 450, the frequency of the second local oscillator signal is lower than the frequency of the first local oscillator signal.
  • the sending device 400 further includes a rate changing unit 4160, which is used to perform a first rate transformation on the jitter noise cancellation signal output by the synthesis unit 410; the rate changing unit 4160 is also used to convert The signal output by the filter tracking unit 420 undergoes second rate conversion.
  • a rate changing unit 4160 which is used to perform a first rate transformation on the jitter noise cancellation signal output by the synthesis unit 410; the rate changing unit 4160 is also used to convert The signal output by the filter tracking unit 420 undergoes second rate conversion.
  • the sending device 400 further includes a digital-to-analog conversion unit 4170 for digital-to-analog conversion of the signal to be output from the superposition unit 430 to obtain a digital signal to be output, and the digital to be output The signal is sent to the mixing output unit 440.
  • a digital-to-analog conversion unit 4170 for digital-to-analog conversion of the signal to be output from the superposition unit 430 to obtain a digital signal to be output, and the digital to be output The signal is sent to the mixing output unit 440.
  • the synthesis unit 410 may be a complex multiplier, or a frequency adjuster, or a multiplexer and other devices corresponding to the above functions, and the filter tracking unit 420 may be adaptive A filter, such as a Kalman filter, the superposition unit 430 may be a multiplexer, the mixing output unit 440 may be a modulator, the oscillation signal generation unit 450 may be a local oscillator, and the reference signal generation unit 460 may be a reference source generator
  • the delay signal generation unit 470 may be a delay
  • the clock signal generation unit 480 may be a reference clock generator
  • the frequency division unit 490 may be a frequency divider
  • the analog-to-digital conversion unit 4110 may be an analog-to-digital converter
  • the frequency multiplication unit 4120 may Is a frequency multiplier
  • the correlation calculation unit 4130 can be a correlator
  • the filtering unit 4140 can be a band-pass filter
  • the second local oscillator signal generating unit 4150 can
  • each unit may also correspond to the corresponding description of the method embodiment shown in FIG. 2, and details are not described here.
  • FIG. 5 is a schematic structural diagram of another transmission device according to an embodiment of the present application.
  • the transmission device 500 includes at least: a local oscillator 510, a modulator 520, a transmitter 530, a frequency divider 540, and a reference clock generation. 550, analog-to-digital converter 560, reference source generator 570, delay 580, frequency delay adjuster 590 and complex multiplier 5110; where:
  • a local oscillator 510 used to generate a first local oscillator signal
  • the modulator 520 is configured to mix the signal to be output after the baseband signal and the phase noise correction signal are superimposed with the first local oscillator signal to generate an output signal;
  • the transmitter 530 may be a transceiver interface or a communication interface of the sending device 500, and is used to send the output signal to the receiving device;
  • a frequency divider 540 configured to divide the first local oscillator signal and output a frequency-divided signal
  • the reference clock generator 550 is used to provide a reference clock signal
  • An analog-to-digital converter 560 configured to convert the frequency-divided signal and the reference clock signal into digital signals
  • Reference source generator 570 used to provide a first reference source signal
  • the delay 580 is used to provide a first delayed signal
  • the frequency delay adjuster 590 is used to synthesize the frequency-divided digital signal output from the analog-to-digital converter 560 and the first reference source signal output from the reference source generator 570 to obtain a first synthesized signal, and is also used to convert the analog-to-digital converter
  • the reference clock digital signal output by 560 is synthesized with the first delayed signal output by the delay 580 to obtain a second synthesized signal;
  • the complex multiplier 5110 is used to synthesize the first synthesized signal and the second synthesized signal (for complex conjugate operation) to eliminate jitter noise to obtain a jitter noise cancellation signal, wherein the frequencies of the first synthesized signal and the second synthesized signal Same as the delay.
  • the sending device 500 further includes a frequency multiplier 5120, configured to perform frequency multiplication processing on the reference clock digital signal output by the analog-to-digital converter 560, and output a first clock signal;
  • the reference source generator 570 is also used to provide a second reference source signal, and the second reference source signal has the same frequency as the first clock signal.
  • the frequency delay adjuster 590 is also used to synthesize the second reference source signal output by the reference source generator 570 and the frequency-divided digital signal output by the analog-to-digital converter 560 (frequency adjustment) To obtain a third synthesized signal, which has the same frequency as the first clock signal;
  • the sending device 500 further includes a correlator 5130 for correlating the first clock signal and the third synthesized signal output by the frequency multiplier 5120 to obtain delay information, and configuring the delay information to the reference source 570, so that it outputs a first reference source signal, the first reference source signal and the first clock signal have the same frequency and delay;
  • the correlator 5130 configures the delay information into the delay 580 so that it outputs a first delayed signal, and the first delayed signal and the third synthesized signal have the same frequency and delay.
  • the sending device 500 further includes a band-pass filter 5140 for filtering the frequency-divided signal output by the frequency divider 540 to extract a signal containing phase noise.
  • a band-pass filter 5140 can be deployed between the frequency divider 540 and the analog-to-digital converter 560 for filtering.
  • the band-pass filter 5140 is an analog band-pass filter, or it can be the analog-to-digital converter 560.
  • a band-pass filter 5140 is deployed for filtering.
  • the band-pass filter 5140 is a digital band-pass filter, which can be selected and deployed according to actual needs. This application There are no restrictions on this.
  • the sending device 500 further includes a phase-locked loop 5150 for receiving the reference clock signal output by the reference clock generator 550 and outputting the second local oscillator signal to the local oscillator 510, where The frequency of the second local oscillator signal is lower than the frequency of the first local oscillator signal.
  • the sending device 500 further includes an adaptive filter 5160 and a sampler 5170.
  • the adaptive filter 5160 may be a Kalman filter, which is used to filter the jitter noise signal to obtain a phase noise correction Signal;
  • the sampler 5170 can be used to perform a first rate conversion on the jitter noise cancellation signal output by the complex multiplier 5110 before filtering, to reduce its sampling rate and facilitate calculation; it is also used to adapt The signal output by the filter 5160 undergoes a second rate conversion to increase its sampling rate to match the transmission rate.
  • the sending device 500 further includes a multiplexer 5180 and a digital-to-analog converter 5190.
  • the multiplexer 5180 is used to superimpose the baseband signal and the phase noise correction signal to output the signal to be output.
  • the converter 5190 is configured to perform digital-to-analog conversion on the signal to be output from the multiplexer 5180 to obtain a digital signal to be output, and send the digital signal to be output to the modulator 520.
  • the transmitting device performs analog-to-digital conversion on the frequency-divided signal output from the frequency divider 540 and the reference clock signal output from the reference clock generator 550 by using the analog-to-digital converter 560, and passes the complex number
  • the multiplier 5110 performs complex conjugate operation to obtain a jitter noise cancellation signal, and uses the signal to correct the first local oscillator signal output by the local oscillator 510, which can effectively remove the interference of the jitter noise on the correction signal and improve the phase noise correction performance.
  • each operation may also correspond to the corresponding description of the method embodiment shown in FIG. 2 and the corresponding description of the embodiment shown in FIG. 4, which will not be repeated here.
  • FIG. 6 is a schematic structural diagram of a receiving device according to an embodiment of the present application.
  • the receiving device 600 includes at least: a receiving unit 610, a synthesis unit 620, a filter tracking unit 630, and a correction unit 640; wherein:
  • the receiving unit 610 is configured to receive the signal to be corrected sent by the sending device
  • the synthesizing unit 620 is configured to synthesize the first synthesized signal and the second synthesized signal to obtain a jitter noise cancellation signal, wherein the frequency and delay of the first synthesized signal and the second synthesized signal are the same;
  • the filter tracking unit 630 is configured to filter and track the jitter noise cancellation signal to obtain a phase noise correction signal
  • the correction unit 640 is configured to correct the phase noise of the signal to be corrected
  • the receiving device further includes a reference signal generating unit 650 for generating a first reference source signal; a delay signal generating unit 660 for generating a first delayed signal; a clock signal generating unit 670 for generating a reference clock signal; Frequency dividing unit 680 is used to divide the input signal to obtain a frequency-divided signal; analog-to-digital conversion unit 690 is used to perform analog-to-digital conversion on the frequency-divided signal and the reference clock signal to obtain a frequency-divided digital signal and a reference clock digital signal.
  • the synthesizing unit 620 is also used to synthesize the frequency-divided digital signal output by the analog-to-digital conversion unit 690 and the first reference source signal output by the reference signal generating unit 650 to obtain a first synthesized signal; the synthesizing unit 620 also It is used to synthesize the reference clock digital signal output by the analog-to-digital conversion unit 690 and the first delay signal output by the delay signal generation unit 660 to obtain
  • the receiving device simultaneously performs analog-to-digital conversion on the frequency-divided signal output from the frequency-dividing unit 680 and the reference clock signal output from the clock signal generating unit 670 by using the analog-to-digital conversion unit 690, and the synthesis unit 620 synthesizes
  • the jitter noise cancellation signal, and using the signal to correct the signal to be corrected output by the receiving unit 610, can effectively remove the interference of the jitter noise on the correction signal and improve the phase noise correction performance.
  • the receiving device 600 further includes a frequency multiplication unit 6110, configured to perform frequency multiplication processing on the reference clock digital signal output by the analog-to-digital conversion unit 690 to output a first clock signal; the reference signal The generating unit 650 is further configured to generate a second reference source signal, and the second reference source signal has the same frequency as the first clock signal.
  • the synthesis unit 620 is further configured to synthesize the second reference source signal output by the reference signal generation unit 650 and the frequency-divided digital signal output by the analog-to-digital conversion unit 690 to obtain a third synthesized signal ,
  • the third synthesized signal has the same frequency as the first clock signal;
  • the receiving device 600 further includes a correlation calculation unit 6120, configured to perform correlation calculation on the first clock signal and the third synthesized signal output by the frequency multiplication unit 6110 to obtain delay information, and configure the delay information to the reference
  • the reference signal generating unit 650 outputs a first reference source signal, and the frequency and delay of the first reference source signal and the first clock signal are the same;
  • the correlation calculation unit 6120 configures the delay information to the delay signal generation unit 660, so that the delay signal generation unit 660 outputs the first delay signal, the frequency and time of the first delay signal and the third synthesized signal The same.
  • the receiving device 600 further includes a filtering unit 6130, configured to filter the frequency-divided signal output by the frequency-dividing unit 680 to extract a signal containing phase noise.
  • the receiving device 600 further includes an oscillating signal generating unit 6140 and a mixing output unit 6150.
  • the oscillating signal generating unit 6140 is used to generate a first local oscillator signal;
  • the mixing output unit 6150 uses Mixing the signal to be corrected with the first local oscillator signal to generate a first output signal;
  • the analog-to-digital conversion unit 690 is also used to perform analog-to-digital conversion on the first output signal output by the mixing output unit 6150 and convert it into a digital signal.
  • the receiving device 600 further includes a second local oscillator signal generating unit 6160 for receiving the reference clock signal output by the clock signal generating unit 670 and outputting the second local oscillator signal to the oscillation signal generation Unit 6140, the frequency of the second local oscillator signal is lower than the frequency of the first local oscillator signal.
  • the receiving device 600 further includes a rate changing unit 6170, which is used to perform a first rate conversion on the jitter noise cancellation signal output by the synthesis unit 620; the rate changing unit 6170 is also used to convert The signal output by the filter tracking unit 630 undergoes second rate conversion.
  • a rate changing unit 6170 which is used to perform a first rate conversion on the jitter noise cancellation signal output by the synthesis unit 620; the rate changing unit 6170 is also used to convert The signal output by the filter tracking unit 630 undergoes second rate conversion.
  • the receiving unit 610 may be a receiver or a receiving antenna
  • the combining unit 620 may be a complex multiplier, or a frequency adjuster, or a multiplexer, etc., corresponding to the above functions Device
  • the filter tracking unit 630 may be an adaptive filter, such as a Kalman filter
  • the correction unit 640 may be a signal corrector
  • the reference signal generation unit 650 may be a reference source generator
  • the delayed signal generation unit 660 may be a delay
  • the clock signal generation unit 670 may be a reference clock generator
  • the frequency division unit 680 may be a frequency divider
  • the analog-to-digital conversion unit 690 may be an analog-to-digital converter
  • the frequency multiplication unit 6110 may be a frequency multiplier
  • the correlation calculation unit 6120 may Is a correlator
  • the filtering unit 6130 may be a band-pass filter
  • the oscillating signal generating unit 6140 may be a local oscillator
  • each unit may also correspond to the corresponding description of the method embodiment shown in FIG. 3, and details are not described here.
  • FIG. 7 is a schematic structural diagram of another receiving device according to an embodiment of the present application.
  • the receiving device 700 includes at least: a local oscillator 710, a receiver 720, a modulator 730, a frequency divider 740, and a reference clock generation. 750, analog-to-digital converter 760, reference source generator 770, delay 780, frequency delay adjuster 790 and complex multiplier 7110; where:
  • a local oscillator 710 used to generate a first local oscillator signal
  • the receiver 720 may be a transceiver interface or a communication interface of the receiving device 700, and is used to receive the signal to be corrected sent by the sending device;
  • the demodulator 730 is configured to mix the signal to be corrected with the first local oscillator signal to generate a first output signal
  • Frequency divider 740 is used to divide the first local oscillator signal and output a frequency-divided signal
  • the reference clock generator 750 is used to provide a reference clock signal
  • An analog-to-digital converter 760 configured to convert the frequency-divided signal and the reference clock signal into digital signals
  • Reference source generator 770 which is used to provide a first reference source signal
  • the delay 780 is used to provide a first delayed signal
  • the frequency delay adjuster 790 is used to synthesize the frequency-divided digital signal output from the analog-to-digital converter 760 and the first reference source signal output from the reference source generator 770 to obtain a first synthesized signal, and is also used to convert the analog-to-digital converter
  • the reference clock digital signal output by 760 is synthesized with the first delayed signal output by the delay 780 to obtain a second synthesized signal;
  • the receiving device 700 further includes a frequency multiplier 7120, configured to perform frequency multiplication processing on the reference clock digital signal output by the analog-to-digital converter 760 to output a first clock signal;
  • the reference source generator 770 is also used to provide a second reference source signal, and the second reference source signal has the same frequency as the first clock signal.
  • the frequency delay adjuster 790 is also used to synthesize the second reference source signal output by the reference source generator 770 and the frequency-divided digital signal output by the analog-to-digital converter 760 (frequency adjustment) To obtain a third synthesized signal, which has the same frequency as the first clock signal;
  • the receiving device 700 further includes a correlator 7130 for correlating the first clock signal and the third synthesized signal output by the frequency multiplier 7120 to obtain delay information, and configuring the delay information to the reference source 770, so that it outputs a first reference source signal, the first reference source signal and the first clock signal have the same frequency and delay;
  • the correlator 7130 configures the delay information to the delayer 780 so that it outputs a first delayed signal whose frequency and delay are the same as the third synthesized signal.
  • the receiving device 700 further includes a band-pass filter 7140 for filtering the frequency-divided signal output by the frequency divider 740 to extract a signal containing phase noise.
  • a band-pass filter 7140 can be deployed between the frequency divider 740 and the analog-to-digital converter 760 for filtering.
  • the band-pass filter 7140 is an analog band-pass filter, or it can be the analog-to-digital converter 760.
  • a band-pass filter 7140 is deployed for filtering.
  • the band-pass filter 7140 is a digital band-pass filter, which can be selected and deployed according to actual needs. This application There are no restrictions on this.
  • the receiving device 700 further includes a phase-locked loop 7150 for receiving the reference clock signal output by the reference clock generator 750 and outputting the second local oscillator signal to the local oscillator 710, where The frequency of the second local oscillator signal is lower than the frequency of the first local oscillator signal.
  • the receiving device 700 further includes an adaptive filter 7160, a sampler 7170, and a signal corrector 7180.
  • the adaptive filter 7160 may be a Kalman filter, which is used to filter the jitter noise signal , To obtain a phase noise correction signal; the sampler 7170 can be used to perform a first rate conversion on the jitter noise cancellation signal output by the complex multiplier 7110 before filtering, to reduce the sampling rate and facilitate calculation; Used to perform a second rate conversion on the signal output from the adaptive filter 7160 to increase its sampling rate to match the transmission rate; a signal corrector 7180 is used to receive the phase noise correction signal and mode output from the sampler 7170 The mixed digital signal to be corrected output by the digital converter 760 is corrected by the phase noise correction signal.
  • the receiving device performs analog-to-digital conversion on the frequency-divided signal output from the frequency divider 740 and the reference clock signal output from the reference clock generator 750 by using the analog-to-digital converter 760, and passes the complex number
  • the multiplier 7110 performs complex conjugate operation to obtain the jitter noise cancellation signal, and uses this signal to correct the mixed signal to be corrected output by the demodulator 730, which can effectively remove the interference of the jitter noise on the correction signal and improve the phase noise correction. performance.
  • each operation may also correspond to the corresponding description of the method embodiment shown in FIG. 3 and the corresponding description of the embodiment shown in FIG. 6, which will not be repeated here.
  • the embodiments of the present application are not only applicable to the application scenarios of phase noise correction on microwave systems, but also applicable to the application scenarios of phase noise correction on radio frequency systems, and can also be applied to optical phase adjustment noise on laser systems.
  • the corrected application scenarios can also be applied to the transmission scenarios of radio frequency communication signals on microwave repeaters. It should be noted that the above application scenario is just an example, and the actual application is not limited to this.
  • the size of the sequence numbers of the above processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not be implemented by the embodiments of the present application.
  • the process constitutes no limitation.
  • the disclosed device and method may be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the modules and units is only a division of logical functions.
  • there may be other divisions for example, multiple units or components may be The combination can either be integrated into another system, or some features can be ignored, or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be accomplished through some interfaces, and the indirect coupling or communication connection of the device or unit may be in electrical, mechanical, or other forms.
  • the unit described as a separate component may be physically separated or not, and the component displayed as a unit may be a physical unit or not a physical unit, that is, it may be located in one place, or may be distributed to On multiple network elements. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments of the present application.
  • the functional units involved in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above integrated unit may be implemented in the form of hardware or a software functional unit, which is not limited in this application.
  • Embodiments of the present application also provide a computer-readable storage medium, in which instructions are stored in the computer-readable storage medium, which when executed on a computer or processor, causes the computer or processor to perform any of the foregoing embodiments One or more steps in the method. If each component module of the above device is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in the computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or It is said that part of the contribution to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer product is stored in a computer-readable storage medium.
  • the foregoing computer-readable storage medium may be an internal storage unit of the sending device or the receiving device described in the foregoing embodiments, such as a hard disk or a memory.
  • the computer-readable storage medium may also be an external storage device of the sending device or the receiving device, such as an equipped plug-in hard disk, a smart memory card (Smart) Media (SMC), a secure digital (SD) card, and a flash memory Card (Flash), etc.
  • the computer-readable storage medium may also include both the internal storage unit of the transmission device or the reception device and the external storage device.
  • the aforementioned computer-readable storage medium is used to store the aforementioned computer program and other programs and data required by the aforementioned sending device or receiving device.
  • the above-mentioned computer-readable storage medium can also be used to temporarily store data that has been or will be output.
  • the modules in the device of the embodiment of the present application may be combined, divided, and deleted according to actual needs.

Abstract

本申请实施例提供了一种相位噪声校正方法和相关设备。其中，该方法主要包括：发送设备利用模数转换器对分频器输出的信号进行采样，并通过滤波器以提取恢复高频相位噪声，同时利用模数转换器对参考时钟输出的信号进行采样以恢复数模转换器在进行采样时所引入的抖动噪声，并在恢复的高频相位噪声中去除抖动噪声，利用去除抖动噪声的相位噪声与基带信号进行叠加并与第一本振信号进行混频，生成输出信号。实施本申请实施例，可以减少分频器分频倍数，有效去除抖动噪声对校正信号的干扰，提升相位噪声恢复精度和校正性能。

Description

一种相位噪声校正方法和相关设备 技术领域
本申请涉及信号处理技术领域，尤其涉及一种相位噪声校正方法和相关设备。
背景技术
相位噪声是用来衡量频率标准源(高稳晶振、原子频标等)频稳质量的重要指标，同时也是通信系统的一种调制噪声。在无线通信系统中通常通过定制性能较高的本振来降低相位噪声的影响。但随着频率的提升，相位噪声的恶化越来越严重，使得在无线通信系统或微波通信系统上，所能获取的本振的相位噪声越差，从而对系统可能的调制方式越来越有限。
在第五代移动通信技术(5th-Generation，5G)的微波高频无线收发信机需求背景下，由于采用微波高频本振的原因，收发信机本振相位噪声成为了影响信号通信质量的关键因素。为了提高微波高频信号通信质量，需要采用一种高频相位噪声改善技术以提升微波高频收发信机的指标性能，改善通信质量。
现有技术通过采用本振分频后与参考源进行鉴相的方法提取本振相噪或采用本振分频后放大采样的方法来获取本振相噪完成发射与接收相噪的校正，但是，发明人发现，上述的相位噪声校正方法在提取本振相位噪声的过程中会引入新的噪声(抖动(jitter)噪声)，导致获取到的本振相位噪声并不准确，整体校正性能不够理想。
发明内容
本申请提供了一种相位噪声校正方法和相关设备，能够减少分频器分频倍数，提升相位噪声恢复精度，有效去除抖动噪声对校正信号的干扰，提升相位噪声校正性能。
第一方面，提供了一种相位噪声校正方法，所述方法包括：发送设备将第一合成信号与第二合成信号进行合成得到抖动噪声消除信号；发送设备将所述抖动噪声消除信号进行滤波跟踪得到相位噪声校正信号；发送设备将基带信号与所述相位噪声校正信号进行叠加，生成待输出信号；发送设备将所述待输出信号与第一本振信号混频，生成输出信号，并将所述输出信号发送至接收设备；其中，所述第一合成信号与所述第二合成信号的频率和时延相同，所述第一合成信号是分频器输出信号经过模数转换器后得到的信号与第一参考源信号进行合成得到的信号，所述第二合成信号是参考时钟输出信号经过模数转换器后得到的信号与第一延迟信号进行合成得到的信号，所述第一本振信号是本地振荡器输出的信号，所述第一参考源信号是参考源发生器输出的信号，所述第一延迟信号是延迟器输出的信号。
通过执行上述方法，发送设备通过对分频器输出的信号和参考时钟输出的信号同时进行模数转换，并通过合成(即消除抖动噪声)得到抖动噪声消除信号，进而得到相位噪声校正信号，并利用该校正信号对第一本振信号进行校正，可以有效去除抖动噪声对校正信号的干扰，提升相位噪声校正性能。
在第一方面的一种可能的实现方式中，在所述第一合成信号与所述第二合成信号进行合成之前，所述方法还包括：发送设备将所述参考时钟输出信号经过模数转换器后得到的信号进行倍频处理得到第一时钟信号；发送设备根据所述第一时钟信号，以使所述参考源发生器输出第二参考源信号，所述第二参考源信号与所述第一时钟信号的频率相同。
在第一方面的又一种可能的实现方式中，在所述参考源输出第二参考源信号之后，所述方法还包括：将所述第二参考源信号与所述分频器输出信号经过模数转换器后得到的信号进行合成得到第三合成信号，所述第三合成信号与所述第一时钟信号的频率相同；将所述第一时钟信号与第三合成信号进行相关计算得到延时信息，并将所述延时信息配置到所述参考源发生器中，以使所述参考源发生器根据所述时延信息输出所述第一参考源信号，所述第一参考源信号与所述第一时钟信号的频率和时延相同；或者是，将所述第一时钟信号与第三合成信号进行相关计算得到延时信息，并将所述延时信息配置到所述延迟器中，以使所述延迟器根据所述时延信息输出所述第一延迟信号，所述第一延迟信号与所述第三合成信号的频率和时延相同。
通过执行上述方法，发送设备可以通过第二参考源信号对分频器输出信号经过模数转换器后得到的信号进行频率调整，使其与第一时钟信号的频率相同，以使其可以与第一时钟信号进行相关计算，得到延时信息，通过将延时信息配置在参考源发生器或延迟器中，使最终得到的第一合成信号和第二合成信号的频率和时延相同，进而可以实现对抖动噪声的消除过程。
在第一方面的又一种可能的实现方式中，发送设备将所述第二参考源信号与所述分频器输出信号经过模数转换器后得到的信号进行合成得到第三合成信号之前，所述方法还包括：发送设备对所述分频器输出信号进行滤波，提取得到包含相位噪声的信号。
通过执行上述方法，发送设备通过将第一本振信号进行分频后对得到的信号进行滤波，可以保证能够有效提取包含相位噪声的信号。
在第一方面的又一种可能的实现方式中，所述第一本振信号是所述本地振荡器在接收到第一输入信号之后输出的信号，所述第一输入信号是本振锁相环在接收到所述参考时钟发送的参考时钟信号后输出的信号。
在第一方面的又一种可能的实现方式中，将所述抖动噪声消除信号进行滤波跟踪之前，所述方法还包括：对所述抖动噪声消除信号进行第一速率变换；将所述抖动噪声消除信号进行滤波跟踪之后，所述方法还包括：对所述抖动噪声消除信号进行第二速率变换。
通过执行上述方法，发送设备通过对抖动噪声消除信号进行速率变换，可以将速率降低，以便于在滤波跟踪等过程中可以减少计算量，提高效率，在最后再通过速率变换将速率升高，保证与发射速率相匹配。
在第一方面的又一种可能的实现方式中，发送设备将所述待输出信号通过数模转换器 转换为模拟信号，将得到的所述模拟信号与所述第一本振信号进行混频。
通过执行上述方法，发送设备可以将数字域信号转换为模拟域信号，保证待输出信号能够与第一本振信号进行正确的混频，完成发射过程。
第二方面，提供了一种相位噪声校正方法，所述方法包括：接收设备接收发送设备发送的待校正信号；接收设备将第一合成信号与第二合成信号进行合成得到抖动噪声消除信号；将所述抖动噪声消除信号进行滤波跟踪得到相位噪声校正信号；利用所述相位噪声校正信号对所述待校正信号进行相位噪声校正；其中，所述第一合成信号与所述第二合成信号的频率和时延相同，所述第一合成信号是分频器输出信号经过模数转换器后得到的信号与第一参考源信号进行合成得到的信号，所述第二合成信号是参考时钟输出信号经过模数转换器后得到的信号与第一延迟信号进行合成得到的信号，所述第一参考源信号是参考源发生器输出的信号，所述第一延迟信号是延迟器输出的信号。
通过执行上述方法，接收设备通过对分频器输出的信号和参考时钟输出的信号同时进行模数转换，并通过合成(即消除抖动噪声)得到抖动噪声消除信号，进而得到相位噪声校正信号，并利用该校正信号对接收到的待校正信号进行校正，可以有效去除抖动噪声对校正信号的干扰，提升相位噪声校正性能。
在第二方面的一种可能的实现方式中，在所述第一合成信号与所述第二合成信号进行合成之前，所述方法还包括：接收设备将所述参考时钟输出信号经过模数转换器后得到的信号进行倍频处理得到第一时钟信号；接收设备根据所述第一时钟信号，以使所述参考源发生器输出第二参考源信号，所述第二参考源信号与所述第一时钟信号的频率相同。
在第二方面的又一种可能的实现方式中，在所述参考源输出第二参考源信号之后，所述方法还包括：接收设备将所述第二参考源信号与所述分频器输出信号经过模数转换器后得到的信号进行合成得到第三合成信号，所述第三合成信号与所述第一时钟信号的频率相同；接收设备将所述第一时钟信号与第三合成信号进行相关计算得到延时信息，并将所述延时信息配置到所述参考源发生器中，以使所述参考源发生器根据所述时延信息输出所述第一参考源信号，所述第一参考源信号与所述第一时钟信号的频率和时延相同；或者是，接收设备将所述第一时钟信号与第三合成信号进行相关计算得到延时信息，并将所述延时信息配置到所述延迟器中，以使所述延迟器根据所述时延信息输出所述第一延迟信号，所述第一延迟信号与所述第三合成信号的频率和时延相同。
通过执行上述方法，接收设备可以通过第二参考源信号对分频器输出信号经过模数转换器后得到的信号进行频率调整，使其与第一时钟信号的频率相同，以使其可以与第一时钟信号进行相关计算，得到延时信息，通过将延时信息配置在参考源发生器或延迟器中，使最终得到的第一合成信号和第二合成信号的频率和时延相同，进而可以实现对抖动噪声的消除过程。
在第二方面的又一种可能的实现方式中，接收设备将所述第二参考源信号与所述分频 器输出信号经过模数转换器后得到的信号进行合成得到第三合成信号之前，所述方法还包括：接收设备对所述分频器输出信号进行滤波，提取得到包含相位噪声的信号。
通过执行上述方法，接收设备通过将第一本振信号进行分频后对得到的信号进行滤波，可以保证能够有效提取包含相位噪声的信号。
在第二方面的又一种可能的实现方式中，接收设备利用所述相位噪声校正信号对所述待校正信号进行相位噪声校正之前，所述方法还包括：接收设备将所述待校正信号与第一本振信号混频，生成第一输出信号，所述第一本振信号是本地振荡器输出的信号；接收设备将所述第一输出信号通过模数转换器转换为数字信号。
在第二方面的又一种可能的实现方式中，所述第一本振信号是所述本地振荡器在接收到第一输入信号之后输出的信号，所述第一输入信号是本振锁相环在接收到所述参考时钟发送的参考时钟信号后输出的信号。
在第二方面的又一种可能的实现方式中，接收设备将所述抖动噪声消除信号进行滤波跟踪之前，所述方法还包括：接收设备对所述抖动噪声消除信号进行第一速率变换；接收设备将所述抖动噪声消除信号进行滤波跟踪之后，所述方法还包括：接收设备对所述抖动噪声消除信号进行第二速率变换。
通过执行上述方法，接收设备通过对抖动噪声消除信号进行速率变换，可以将速率降低，以便于在滤波跟踪等过程中可以减少计算量，提高效率，在最后再通过速率变换将速率升高，保证与接收速率相匹配。
第三方面，提供了一种发送设备，所述发送设备包括：
合成单元，用于将第一合成信号与第二合成信号进行合成得到抖动噪声消除信号；
滤波跟踪单元，用于将所述抖动噪声消除信号进行滤波跟踪得到相位噪声校正信号；
叠加单元，用于将基带信号与所述相位噪声校正信号进行叠加，生成待输出信号；
混频输出单元，用于将所述待输出信号与第一本振信号混频，生成输出信号，并将所述输出信号发送至接收设备；
其中，所述第一合成信号与所述第二合成信号的频率和时延相同，所述第一合成信号是分频器输出信号经过模数转换器后得到的信号与第一参考源信号进行合成得到的信号，所述第二合成信号是参考时钟输出信号经过模数转换器后得到的信号与第一延迟信号进行合成得到的信号，所述第一本振信号是本地振荡器输出的信号，所述第一参考源信号是参考源发生器输出的信号，所述第一延迟信号是延迟器输出的信号。
第四方面，提供了一种发送设备，所述发送设备包括：收发模块、调制器、本地振荡器、模数转换器、分频器、参考源发生器、延迟器、合波模块和参考时钟模块，其中：
所述本地振荡器，用于产生第一本振信号；
所述调制器，用于将基带信号与相位噪声校正信号叠加后的待输出信号与所述第一本 振信号混频，生成输出信号；
所述收发模块，用于将所述输出信号发送至接收设备；
所述分频器，用于将所述第一本振信号进行分频，输出分频信号；
所述参考时钟模块，用于提供参考时钟信号；
所述模数转换器，用于将所述分频信号和所述参考时钟信号转换为数字信号；
所述参考源发生器，用于提供第一参考源信号；
所述延迟器，用于提供第一延迟信号；
合波模块，用于将所述参考时钟模块输出信号经过所述模数转换器后得到的信号与所述第一延迟信号进行合成得到第二合成信号，以及将所述第一参考源信号与所述分频器输出信号经过所述模数转换器后得到的信号进行合成得到第一合成信号，还用于将所述第一合成信号与所述第二合成信号进行合成得到抖动噪声消除信号；
其中，所述第一合成信号与所述第二合成信号的频率和时延相同。
在第四方面的一种可能的实现方式中，所述发送设备还包括倍频器，所述倍频器，用于将所述参考时钟模块输出信号经过所述模数转换器后得到的信号进行倍频处理，得到第一时钟信号；所述参考源发生器，还用于提供第二参考源信号，所述第二参考源信号与所述第一时钟信号的频率相同。
在第四方面的又一种可能的实现方式中，所述合波模块，还用于将所述第二参考源信号与所述分频信号经过所述模数转换器后得到的信号进行合成得到第三合成信号，所述第三合成信号与所述第一时钟信号的频率相同；所述发送设备还包括相关器，用于将所述第一时钟信号与所述第三合成信号进行相关计算，得到延时信息，并将所述延时信息配置到所述参考源发生器中，以使所述参考源发生器根据所述时延信息输出所述第一参考源信号，所述第一参考源信号与所述第一时钟信号的频率和时延相同；或者是，将所述延时信息配置到所述延迟器中，以使所述延迟器根据所述时延信息输出所述第一延迟信号，所述第一延迟信号与所述第三合成信号的频率和时延相同。
在第四方面的又一种可能的实现方式中，所述发送设备还包括滤波器，用于对所述分频信号进行滤波，提取得到包含相位噪声的信号。
在第四方面的又一种可能的实现方式中，所述发送设备还包括本振锁相环，用于接收所述参考时钟模块输出的参考时钟信号并输出第一输出信号，以使所述本地振荡器根据所述第一输出信号输出所述第一本振信号。
在第四方面的又一种可能的实现方式中，所述发送设备还包括速率变化模块，用于在所述抖动噪声消除信号经过滤波跟踪之前对所述抖动噪声消除信号进行第一速率变换，以及在所述抖动噪声消除信号经过滤波跟踪之后对所述抖动噪声消除信号进行第二速率变换。
在第四方面的又一种可能的实现方式中，所述发送设备还包括数模转换器，用于将所述待输出信号转换为模拟信号，并将所述模拟信号发送给所述调制器，以使所述调制器将所述模拟信号与所述第一本振信号进行混频。
第五方面，提供了一种接收设备，所述接收设备包括：
接收单元，用于接收发送设备发送的待校正信号；
合成单元，用于将第一合成信号与第二合成信号进行合成得到抖动噪声消除信号；
滤波跟踪单元，用于将所述抖动噪声消除信号进行滤波跟踪得到相位噪声校正信号；
校正单元，用于根据所述相位噪声校正信号对所述待校正信号进行相位噪声校正；
其中，所述第一合成信号与所述第二合成信号的频率和时延相同，所述第一合成信号是分频器输出信号经过模数转换器后得到的信号与第一参考源信号进行合成得到的信号，所述第二合成信号是参考时钟输出信号经过模数转换器后得到的信号与第一延迟信号进行合成得到的信号，所述第一参考源信号是参考源发生器输出的信号，所述第一延迟信号是延迟器输出的信号。
第六方面，提供了一种接收设备，所述接收设备包括：收发模块、解调器、本地振荡器、模数转换器、分频器、参考源发生器、延迟器、合波模块和参考时钟模块，其中：
所述本地振荡器，用于产生第一本振信号；
所述收发模块，用于接收发送设备发送的待校正信号；
所述解调器，用于将所述待校正信号与所述第一本振信号混频，生成第一输出信号；
所述分频器，用于将所述第一本振信号进行分频，输出分频信号；
所述参考时钟模块，用于提供参考时钟信号；
所述模数转换器，用于将所述分频信号和所述参考时钟信号转换为数字信号；
所述参考源发生器，用于提供第一参考源信号；
所述延迟器，用于提供第一延迟信号；
合波模块，用于将所述参考时钟模块输出信号经过所述模数转换器后得到的信号与所述第一延迟信号进行合成得到第二合成信号，以及将所述第一参考源信号与所述分频器输出信号经过所述模数转换器后得到的信号进行合成得到第一合成信号，还用于将所述第一合成信号与所述第二合成信号进行合成得到抖动噪声消除信号；
其中，所述第一合成信号与所述第二合成信号的频率和时延相同。
在第六方面的一种可能的实现方式中，所述接收设备还包括倍频器，所述倍频器，用于将所述参考时钟模块输出信号经过所述模数转换器后得到的信号进行倍频处理，得到第一时钟信号；所述参考源发生器，还用于提供第二参考源信号，所述第二参考源信号与所述第一时钟信号的频率相同。
在第六方面的又一种可能的实现方式中，所述合波模块，还用于将所述第二参考源信 号与所述分频信号经过所述模数转换器后得到的信号进行合成得到第三合成信号，所述第三合成信号与所述第一时钟信号的频率相同；所述发送设备还包括相关器，用于将所述第一时钟信号与所述第三合成信号进行相关计算，得到延时信息，并将所述延时信息配置到所述参考源发生器中，以使所述参考源发生器根据所述时延信息输出所述第一参考源信号，所述第一参考源信号与所述第一时钟信号的频率和时延相同；或者是，将所述延时信息配置到所述延迟器中，以使所述延迟器根据所述时延信息输出所述第一延迟信号，所述第一延迟信号与所述第三合成信号的频率和时延相同。
在第六方面的又一种可能的实现方式中，所述接收设备还包括滤波器，用于对所述分频信号进行滤波，提取得到包含相位噪声的信号。
在第六方面的又一种可能的实现方式中，所述接收设备还包括本振锁相环，所述本振锁相环，用于接收所述参考时钟模块输出的参考时钟信号并输出第二输出信号，以使所述本地振荡器根据所述第二输出信号输出所述第一本振信号；所述模数转换器，还用于将所述第一输出信号转换为数字信号。
在第六方面的又一种可能的实现方式中，所述接收设备还包括速率变化模块，用于在所述抖动噪声消除信号经过滤波跟踪之前对所述抖动噪声消除信号进行第一速率变换，以及在所述抖动噪声消除信号经过滤波跟踪之后对所述抖动噪声消除信号进行第二速率变换。
附图说明
图1为本申请实施例提供的一种场景架构示意图；
图2为本申请实施例提供的一种相位噪声校正方法的流程示意图；
图3为本申请实施例提供的另一种相位噪声校正方法的流程示意图；
图4为本申请实施例提供的一种发送设备的结构示意图；
图5为本申请实施例提供的另一种发送设备的结构示意图；
图6为本申请实施例提供的一种接收设备的结构示意图；
图7为本申请实施例提供的另一种接收设备的结构示意图。
具体实施方式
下面将结合附图对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例的技术方案可以应用于长期演进(long term evolution，LTE)系统架构，还可以应用于通用移动通信系统(universal mobile telecommunications system，UMTS)陆地无线接入网(UMTS terrestrial radio access network，UTRAN)架构，或者全球移动通信系统(global system for mobile communication GSM)，增强型数据速率GSM演进(enhanced data rate for GSM evolution，EDGE)系统的无线接入网(GSM EDGE radio access network，GERAN)架构。本申请实施例的技术方案还可以应用于其它通信系统，例如公共陆地移动网络(publish land mobile network，PLMN)系统，甚至未来的5G通信系统或5G之后的通信系统等，本申请实施例对此不作限定。
本申请实施例涉及一种发送设备。该发送设备可以是任意一种具有无线发射功能的设备或可设置于该设备的芯片，该设备包括但不限于：演进型节点B(evolved Node B，eNB)、无线网络控制器(radio network controller，RNC)、节点B(Node B，NB)、基站控制器(base station controller，BSC)、基站收发台(base transceiver station，BTS)、家庭基站(例如，home evolved NodeB，或home Node B，HNB)、基带单元(base band Unit，BBU)，无线保真(wireless fidelity，WIFI)系统中的接入点(access point，AP)、无线中继节点、无线回传节点、传输点(transmission point，TP)或者发送接收点(transmission and reception point，TRP)等，还可以为5G，如，NR，系统中的gNB，或，传输点(TRP或TP)，5G系统中的基站的一个或一组(包括多个天线面板)天线面板，或者，还可以为构成gNB或传输点的网络节点，如基带单元(BBU)，或，分布式单元(distributed unit，DU)等。
本申请实施例还涉及一种接收设备。该接收设备可以是任意一种具有无线接收功能的设备或可设置于该设备的芯片，该设备包括但不限于：演进型节点B(evolved Node B，eNB)、无线网络控制器(radio network controller，RNC)、节点B(Node B，NB)、基站控制器(base station controller，BSC)、基站收发台(base transceiver station，BTS)、家庭基站(例如，home evolved NodeB，或home Node B，HNB)、基带单元(base band Unit，BBU)，无线保真(wireless fidelity，WIFI)系统中的接入点(access point，AP)、无线中继节点、无线回传节点、传输点(transmission point，TP)或者发送接收点(transmission and reception point，TRP)等，还可以为5G，如，NR，系统中的gNB，或，传输点(TRP或TP)，5G系统中的基站的一个或一组(包括多个天线面板)天线面板，或者，还可以为构成gNB或传输点的网络节点，如基带单元(BBU)，或，分布式单元(distributed unit，DU)等。
该发送设备和/或接收设备还可以是新一代用户设备(new generation UE，gUE)。用户设备也可以称为终端设备(user equipment，UE)、接入终端、用户单元、用户站、移动站、移动台、远方站、远程终端、移动设备、用户终端、终端、无线通信设备、用户代理或用户装置。终端设备可以是无线局域网(wireless local area networks，WLAN)中的站点(station，STA)，可以是蜂窝电话、无绳电话、会话启动协议(session initiation protocol，SIP)电话、无线本地环路(wireless local loop，WLL)站、个人数字处理(personal digital assistant，PDA)设备、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备、车载设备、可穿戴设备以及下一代通信系统，例如，第五代通信 (fifth-generation，5G)网络中的终端设备或者未来演进的公共陆地移动网络(public land mobile network，PLMN)网络中的终端设备，新无线(new radio，NR)通信系统中的终端设备等。作为示例而非限定，在本申请实施例中，该终端设备还可以是可穿戴设备。可穿戴设备也可以称为穿戴式智能设备，是应用穿戴式技术对日常穿戴进行智能化设计、开发出可以穿戴的设备的总称，如眼镜、手套、手表、服饰及鞋等。可穿戴设备即直接穿在身上，或是整合到用户的衣服或配件的一种便携式设备。可穿戴设备不仅仅是一种硬件设备，更是通过软件支持以及数据交互、云端交互来实现强大的功能。广义穿戴式智能设备包括功能全、尺寸大、可不依赖智能手机实现完整或者部分的功能，例如：智能手表或智能眼镜等，以及只专注于某一类应用功能，需要和其它设备如智能手机配合使用，如各类进行体征监测的智能手环、智能首饰等。
本申请提供一种相位噪声校正方法，能够有效去除抖动噪声对校正信号的干扰，提升相位噪声校正性能。
参见图1，图1是本申请实施例提供的一种场景架构示意图。如图1所示，该架构包括发送设备110和接收设备120，发送设备110和接收设备120组成一个通信系统。在该通信系统中，发送设备110通过调制将待发送数据利用微波或射频通过高频无线网络向接收设备120发送无线信号，接收设备120通过高频无线网络接收发送设备110发送的无线信号，并通过对其进行解调等操作，获取其中携带的数据。
下面详细介绍本申请实施例的方法及相关设备。需要说明的是，本申请实施例的展示顺序仅代表实施例的先后顺序，并不代表实施例所提供的技术方案的优劣。
请参见图2，图2是本申请实施例提供的一种相位噪声校正方法的流程示意图，图2中所描述的发送设备可以对应于图1中所示的发送设备110。如图2所示，该方法包括但不限于以下步骤：
S210：发送设备将第一合成信号与第二合成信号进行合成得到抖动噪声消除信号。
具体地，发送设备将第一合成信号与第二合成信号进行合成之前，需要保证第一合成信号与第二合成信号的频率和时延都是相同的。
进一步地，在保证频率和时延都相同的情况下，由于第一合成信号中存在抖动噪声信号，第二合成信号中也存在抖动噪声信号，可以将第一合成信号与第二合成信号通过复数乘法器，对其执行复共轭运算，以消除抖动噪声，得到抖动噪声消除信号，在本申请中，是通过利用第二合成信号(即对时钟信号进行模数转换后得到信号)中的抖动噪声信号来消除第一合成信号(即包含相位噪声的信号)中的抖动噪声信号。
此外，这里的第一合成信号是指分频器输出信号经过模数转换器后得到的信号与第一参考源信号进行合成得到的信号，第二合成信号是指参考时钟输出信号经过模数转换器后得到的信号与第一延迟信号进行合成得到的信号。
值得说明的是，第一参考源信号是参考源发生器输出的信号，第一延迟信号是延迟器输出的信号，引入参考源发生器和延迟器的目的是为了保证第一合成信号与第二合成信号能够满足频率和时延的要求，能够进行复共轭运算，消除抖动噪声，得到抖动噪声消除信 号。本申请实施例所有涉及到的第一和第二仅仅是为了进行区分，并不构成具体的限定。
在一种可能的实现方式中，发送设备在将第一合成信号与第二合成信号进行合成之前，该发送设备将参考时钟输出信号经过模数转换器后得到的信号进行倍频处理得到第一时钟信号，根据该第一时钟信号，使参考源发生器输出第二参考源信号，该第二参考源信号与第一时钟信号的频率相同。
具体地，参考时钟输出信号是模拟信号，所以需要通过模数转换器对其进行数字采样，转换为数字信号。可以理解，若通过模拟器件来完成对相位噪声信号的校正，对模拟器件的要求较高，成本太高，而且实现复杂且精度不高，通过模数转换器将模拟信号转换为数字信号，通过数字器件完成对相位噪声的校正，可以避免模拟校正的非理想性影响，提高精度且实现简单，难度较低。
进一步地，参考时钟输出信号的频率相对于本地振荡信号等的频率来说是比较低的，即使经过模数转换器转换为数字信号后，其频率仍然较低，为了提高其频率，可以在其转换为数字信号之后，对其进行倍频处理以提高其频率。
具体地，可以将其通过倍频器以提高其信号频率，可以对其进行二倍频、四倍频或其它倍数的处理，其具体的倍数可以按照实际需要进行设置，本申请对其倍频方式和具体的倍频倍数不作具体限定。
值得说明的是，模数转换器在将模拟信号转换为数字信号以简化计算的过程中，会引入抖动噪声，为了消除抖动噪声带来的影响，参考源发生器在参考时钟信号进行倍频处理得到第一时钟信号后，会输出一个与该第一时钟信号的频率一致的第二参考源信号，该第二参考源信号用于对分频器输出信号进行频率调整，使其与第一时钟信号的频率一致，以便后续进行同步配置和调整。
在一种可能的实现方式中，发送设备在参考源发生器输出第二参考源信号之后，将该第二参考源信号与分频器输出信号经过模数转换器后得到的信号进行合成得到第三合成信号，该第三合成信号与第一时钟信号的频率相同。
可选地，在将第二参考源信号与分频器输出信号经过模数转换器后得到的信号进行合成得到第三合成信号之前，发送设备需要对分频器输出的信号进行滤波，提取包含相位噪声的信号。可以理解，分频器输出的信号里面包含相位噪声信号，本申请需要提取出相位噪声信号以得到相位噪声校正信号，所以可以通过带通滤波器对分频器输出信号进行滤波，以提取得到包含相位噪声的信号。、
特别的，发送设备可以在分频器输出信号通过模数转换器之前对其进行滤波提取包含相位噪声的信号，也可以是在分频器输出信号通过模数转换器之后对其进行滤波提取包含相位噪声的信号，若在通过模数转换器之前进行滤波，则需要部署模拟带宽滤波器进行滤波提取，若是在通过模数转换器之后进行滤波，则需要部署数字带宽滤波器进行滤波提取，带通滤波器的部署位置以及带宽选择(即滤波范围)可以按照实际需要进行设置，本申请对此不作限定。
值得说明的是，分频器在对本振信号进行分频时，会对本振信号及其包含的相位噪声 信号的能量造成衰减，分频次数与信号的能量密切相关，每多进行一次分频，其对应的信号能量会减少6分贝(dB)，例如，此时，本振信号及其包含的相位噪声的频率是10GHz，对应的信号强度为-115dB，对其进行分频(二分频)，则分频器输出的分频信号的频率为5GHz，对应的信号能量为-121dB。而模数转换器在进行信号转换的时候，由于自身的采样精度有限，若分频器输出的信号及其包含的相位噪声信号的能量过低，可能输出的数字信号中不会包含需要提取得到的相位噪声信号，本申请通过设置带通滤波器对分频器输出信号进行滤波，可以有效的较少分频器分频倍数，保证模数转换器能够对分频器输出信号进行正确的数字采样，保证其输出的数字信号中包含需要提取得到的相位噪声信号，提升相位噪声恢复精度。
具体地，发送设备利用第二参考源信号对分频器输出信号经过模数转换器后得到的信号进行频率调整，由于第二参考源信号与第一时钟信号的频率一致，故经过频率调整后，包含相位噪声的信号(即第三合成信号)与第一时钟信号的频率相同。
进一步地，发送设备将第一时钟信号与第三合成信号进行相关计算得到延时信息，并将该延时信息配置到参考源发生器中，以使参考源发生器根据该时延信息输出第一参考源信号，或者是，将该延时信息配置到延迟器中，以使延迟器根据该时延信息输出第一时延信号。
具体地，发送设备将第一时钟信号和第三合成信号一起送入相关器进行相关计算，虽然第一时钟信号和第三合成信号都通过模数转换器转换为了数字信号，但是他们的时延并不同步，可能是第三合成信号超前了，第一时钟信号滞后了，也可能是第一时钟信号超前了，第三合成信号滞后了。而相关器进行相关计算后可以得到它们之间时钟同步的延时信息，若是第三合成信号超前了，第一时钟信号滞后了，则发送设备则会将相关器计算得到的延时信息配置到参考源发生器中，以使参考源发生器输出第一参考源信号对第三合成信号进行时延调整(即将第三合成信号与第一参考源信号进行合成得到第一合成信号)，使其与第一时钟信号的时延同步，此时，第一参考源信号与第一时钟信号的频率和时延也是相同的，则第一合成信号与第一时钟信号的频率和时延也实现同步。此时，可以将延迟器的延时配置设置为0，则第二合成信号与第一时钟信号的频率和时延也是相同的，从而实现了第一合成信号与第二合成信号的频率和时延同步，进而，可以将第一合成信号与第二合成信号进行复共轭运算，消除抖动噪声，得到抖动噪声消除信号。
同样的，若是第一时钟信号超前了，第三合成信号滞后了，则发送设备会将相关器计算得到的延时信息配置到延迟器中，以使延迟器根据配置的延时信息输出第一延迟信号对第一时钟信号进行时延调整(即将第一时钟信号与第一延迟信号进行合成得到第二合成信号)，使其与第三合成信号的时延同步，此时，第一延迟信号与第三合成信号的频率和时延也是相同的，则第二合成信号与第三合成信号的频率和时延也实现同步。此时，可以将参考源发生器的延时配置设置为0，则第一合成信号与第三合成信号的频率和时延也是相同的，从而实现了第一合成信号与第二合成信号的频率和时延同步，进而，可以将第一合成信号与第二合成信号进行复共轭运算，消除抖动噪声，得到抖动噪声消除信号。
S220：发送设备将抖动噪声消除信号进行滤波跟踪得到相位噪声校正信号。
具体地，发送设备在将第一合成信号和第二合成信号进行合成得到抖动噪声消除信号后，虽然消除了抖动噪声，但是提取得到的相位噪声信号并不纯净，其中仍然存在着一些其它的噪声信号，需要对其做进一步的处理，以提取得到比较纯净的相位噪声信号。
发送设备将抖动噪声消除信号通过自适应滤波器(例如卡尔曼滤波器)，对其中的干扰噪声信号进行滤除，得到相位噪声校正信号。
在一种可能的实现方式中，发送设备在将抖动噪声消除信号进行滤波跟踪之前，将该抖动噪声消除信号通过速率变换器进行第一速率变换，在将抖动噪声消除信号进行滤波跟踪之后，将该抖动噪声消除信号通过速率变换器进行第二速率变换。
具体地，抖动噪声消除信号对应的采样速率比较高，若直接通过自适应滤波器对其进行滤波跟踪，计算量是比较巨大的，故在进行滤波跟踪之前，利用速率变换器对抖动噪声消除信号进行重新取样，降低其采样速率，可以减小计算量。在滤波跟踪之后(即通过自适应滤波器滤除其它干扰噪声信号之后)，为了与基带信号的发射速率相匹配，需要通过速率变换器对其再次进行重新取样，提高其采样速率。
S230：发送设备将基带信号与相位噪声校正信号进行叠加，生成待输出信号。
S240：发送设备将待输出信号与第一本振信号混频，生成输出信号，并将所述输出信号发送至接收设备。
具体地，本振器产生第一本振信号之后，该第一本振信号中存在相位噪声，待输出信号是需要发送的基带信号与相位噪声校正信号的叠加，发送设备在将待输出信号与第一本振信号混频的过程中，发送设备会利用相位噪声校正信号对第一本振信号进行相位噪声校正，例如，对相位噪声校正信号与第一本振信号进行复共轭运算，以消除校正第一本振信号中的相位噪声。
进一步地，发送设备通过将待输出信号与第一本振信号送入调制器中，利用已经经过相位噪声消除校正的本振信号对基带信号进行调制，由于第一本振信号频率较高，所以可以将基带信号调制到射频或者微波频点上，生成输出信号，并通过发射天线等将该输出信号发送至接收设备。
在一种可能的实现方式中，该第一本振信号是本地振荡器在接收到第一输入信号之后输出的信号，该第一输入信号是本振锁相环在接收到参考时钟发送的参考时钟信号后输出的信号。
具体地，参考时钟为本振锁相环提供参考时钟信号，本振锁相环在接收到参考时钟信号之后，由压控振荡器(voltage control oscillator，VCO)输出第一级本地振荡信号，此时该第一级本地振荡信号的频率较低，需要将其送入本地振荡器(local oscillator，LO)，本地振荡器在接收到本振锁相环发送的第一级本地振荡信号(即第一输入信号)之后，对该第一级本地振荡信号进行倍频处理，将该信号的频率升高，具体进行多少倍频处理， 可以按照实际需要进行设置，本申请对此不作限定。本地振荡器在进行倍频处理，升高信号频率之后，输出第一本振信号。
在一种可能的实现方式中，发送设备在将待输出信号送入调制器与第一本振信号混频之前，发送设备将该待输出信号通过数模转换器转换为模拟信号，将得到的该模拟信号与第一本振信号混频。
具体地，发送设备在将基带信号与相位噪声校正信号进行叠加之后，得到的是数字信号，而第一本振信号是模拟信号，此外，调制器进行调制的对象应该是模拟信号，所以发送设备需要将待输出信号通过数模转换器将数字信号转换为模拟信号，并将转换后得到的模拟信号与第一本振信号混频。
请参见图3，图3是本申请实施例提供的另一种相位噪声校正方法的流程示意图，图3中所描述的接收设备可以对应于图1中所示的接收设备120。如图3所示，该方法包括但不限于以下步骤：
S310：接收设备接收发送设备发送的待校正信号。
具体地，接收设备在接收到待校正信号之后，由于该待校正信号的频率较高，所以需要对其进行降频处理。
进一步地，接收设备将待校正信号送入解调器中，利用本地振荡器输出的第一本振信号与该待校正信号进行混频，将其频率降低。
S320：接收设备将第一合成信号与第二合成信号进行合成得到抖动噪声消除信号。
具体地，接收设备将第一合成信号与第二合成信号进行合成之前，需要保证第一合成信号与第二合成信号的频率和时延都是相同的。
进一步地，在保证频率和时延都相同的情况下，由于第一合成信号中存在抖动噪声信号，第二合成信号中也存在抖动噪声信号，可以将第一合成信号与第二合成信号通过复数乘法器，对其执行复共轭运算，以消除抖动噪声，得到抖动噪声消除信号，在本申请中，是通过利用第二合成信号(即对时钟信号进行模数转换后得到信号)中的抖动噪声信号来消除第一合成信号(即包含相位噪声的信号)中的抖动噪声信号。
此外，这里的第一合成信号是指分频器输出信号经过模数转换器后得到的信号与第一参考源信号进行合成得到的信号，第二合成信号是指参考时钟输出信号经过模数转换器后得到的信号与第一延迟信号进行合成得到的信号。
值得说明的是，第一参考源信号是参考源发生器输出的信号，第一延迟信号是延迟器输出的信号，引入参考源发生器和延迟器的目的是为了保证第一合成信号与第二合成信号能够满足频率和时延的要求，能够进行复共轭运算，消除抖动噪声，得到抖动噪声消除信号。本申请实施例所有涉及到的第一和第二仅仅是为了进行区分，并不构成具体的限定。
在一种可能的实现方式中，接收设备在将第一合成信号与第二合成信号进行合成之前，该接收设备将参考时钟输出信号经过模数转换器后得到的信号进行倍频处理得到第一时钟 信号，根据该第一时钟信号，使参考源发生器输出第二参考源信号，该第二参考源信号与第一时钟信号的频率相同。
具体地，参考时钟输出信号是模拟信号，所以需要通过模数转换器对其进行数字采样，转换为数字信号。可以理解，若通过模拟器件来完成对相位噪声信号的校正，对模拟器件的要求较高，成本太高，而且实现复杂且精度不高，通过模数转换器将模拟信号转换为数字信号，通过数字器件完成对相位噪声的校正，可以避免模拟校正的非理想性影响，提高精度且实现简单，难度较低。
进一步地，参考时钟输出信号的频率相对于本地振荡信号等的频率来说是比较低的，即使经过模数转换器转换为数字信号后，其频率仍然较低，为了提高其频率，可以在其转换为数字信号之后，对其进行倍频处理以提高其频率。
具体地，可以将其通过倍频器以提高其信号频率，可以对其进行二倍频、四倍频或其它倍数的处理，其具体的倍数可以按照实际需要进行设置，本申请对其倍频方式和具体的倍频倍数不作具体限定。
值得说明的是，模数转换器在将模拟信号转换为数字信号以简化计算的过程中，会引入抖动噪声，为了消除抖动噪声带来的影响，参考源发生器在参考时钟信号进行倍频处理得到第一时钟信号后，会输出一个与该第一时钟信号的频率一致的第二参考源信号，该第二参考源信号用于对分频器输出信号进行频率调整，使其与第一时钟信号的频率一致，以便后续进行同步配置和调整。
在一种可能的实现方式中，接收设备在参考源发生器输出第二参考源信号之后，将该第二参考源信号与分频器输出信号经过模数转换器后得到的信号进行合成得到第三合成信号，该第三合成信号与第一时钟信号的频率相同。
可选地，在将第二参考源信号与分频器输出信号经过模数转换器后得到的信号进行合成得到第三合成信号之前，接收设备需要对分频器输出的信号进行滤波，提取包含相位噪声的信号。可以理解，分频器输出的信号里面包含相位噪声信号，本申请需要提取出相位噪声信号以得到相位噪声校正信号，所以可以通过带通滤波器对分频器输出信号进行滤波，以提取得到包含相位噪声的信号。、
特别的，接收设备可以在分频器输出信号通过模数转换器之前对其进行滤波提取包含相位噪声的信号，也可以是在分频器输出信号通过模数转换器之后对其进行滤波提取包含相位噪声的信号，若在通过模数转换器之前进行滤波，则需要部署模拟带宽滤波器进行滤波提取，若是在通过模数转换器之后进行滤波，则需要部署数字带宽滤波器进行滤波提取，带通滤波器的部署位置以及带宽选择(即滤波范围)可以按照实际需要进行设置，本申请对此不作限定。
值得说明的是，分频器在对本振信号进行分频时，会对本振信号及其包含的相位噪声信号的能量造成衰减，分频次数与信号的强度密切相关，每多进行一次分频，其对应的信号能量会减少6分贝(dB)，例如，此时，本振信号及其包含的相位噪声的频率是10GHz，对应的信号能量为-115dB，对其进行分频(二分频)，则分频器输出的分频信号的频率为5GHz，对应的信号能量为-121dB。而模数转换器在进行信号转换的时候，由于自身的采样 精度有限，若分频器输出的信号及其包含的相位噪声信号的能量过低，可能输出的数字信号中不会包含需要提取得到的相位噪声信号，本申请通过设置带通滤波器对分频器输出信号进行滤波，可以有效的较少分频器分频倍数，保证模数转换器能够对分频器输出信号进行正确的数字采样，保证其输出的数字信号中包含需要提取得到的相位噪声信号，提升相位噪声恢复精度。
具体地，接收设备利用第二参考源信号对分频器输出信号经过模数转换器后得到的信号进行频率调整，由于第二参考源信号与第一时钟信号的频率一致，故经过频率调整后，包含相位噪声的信号(即第三合成信号)与第一时钟信号的频率相同。
进一步地，接收设备将第一时钟信号与第三合成信号进行相关计算得到延时信息，并将该延时信息配置到参考源发生器中，以使参考源发生器根据该时延信息输出第一参考源信号，或者是，将该延时信息配置到延迟器中，以使延迟器根据该时延信息输出第一时延信号。
具体地，接收设备将第一时钟信号和第三合成信号一起送入相关器进行相关计算，虽然第一时钟信号和第三合成信号都通过模数转换器转换为了数字信号，但是他们的时延并不同步，可能是第三合成信号超前了，第一时钟信号滞后了，也可能是第一时钟信号超前了，第三合成信号滞后了。而相关器进行相关计算后可以得到它们之间时钟同步的延时信息，若是第三合成信号超前了，第一时钟信号滞后了，则接收设备则会将相关器计算得到的延时信息配置到参考源发生器中，以使参考源发生器输出第一参考源信号对第三合成信号进行时延调整(即将第三合成信号与第一参考源信号进行合成得到第一合成信号)，使其与第一时钟信号的时延同步，此时，第一参考源信号与第一时钟信号的频率和时延也是相同的，则第一合成信号与第一时钟信号的频率和时延也实现同步。此时，可以将延迟器的延时配置设置为0，则第二合成信号与第一时钟信号的频率和时延也是相同的，从而实现了第一合成信号与第二合成信号的频率和时延同步，进而，可以将第一合成信号与第二合成信号进行复共轭运算，消除抖动噪声，得到抖动噪声消除信号。
同样的，若是第一时钟信号超前了，第三合成信号滞后了，则接收设备会将相关器计算得到的延时信息配置到延迟器中，以使延迟器根据配置的延时信息输出第一延迟信号对第一时钟信号进行时延调整(即将第一时钟信号与第一延迟信号进行合成得到第二合成信号)，使其与第三合成信号的时延同步，此时，第一延迟信号与第三合成信号的频率和时延也是相同的，则第二合成信号与第三合成信号的频率和时延也实现同步。此时，可以将参考源发生器的延时配置设置为0，则第一合成信号与第三合成信号的频率和时延也是相同的，从而实现了第一合成信号与第二合成信号的频率和时延同步，进而，可以将第一合成信号与第二合成信号进行复共轭运算，消除抖动噪声，得到抖动噪声消除信号。
S330：接收设备将该抖动噪声消除信号进行滤波跟踪得到相位噪声校正信号。
具体地，接收设备在将第一合成信号和第二合成信号进行合成得到抖动噪声消除信号后，虽然消除了抖动噪声，但是提取得到的相位噪声信号并不纯净，其中仍然存在着一些其它的噪声信号，需要对其做进一步的处理，以提取得到比较纯净的相位噪声信号。
接收设备将抖动噪声消除信号通过自适应滤波器(例如卡尔曼滤波器)，对其中的干扰噪声信号进行滤除，得到相位噪声校正信号。
在一种可能的实现方式中，接收设备在将抖动噪声消除信号进行滤波跟踪之前，将该抖动噪声消除信号通过速率变换器进行第一速率变换，在将抖动噪声消除信号进行滤波跟踪之后，将该抖动噪声消除信号通过速率变换器进行第二速率变换。
具体地，抖动噪声消除信号对应的采样速率比较高，若直接通过自适应滤波器对其进行滤波跟踪，计算量是比较巨大的，故在进行滤波跟踪之前，利用速率变换器对抖动噪声消除信号进行重新取样，降低其采样速率，可以减小计算量。在滤波跟踪之后(即通过自适应滤波器滤除其它干扰噪声信号之后)，为了与基带信号的发射速率相匹配，需要通过速率变换器对其再次进行重新取样，提高其采样速率。
S340：接收设备利用该相位噪声校正信号对所述待校正信号进行相位噪声校正。
在一种可能的实现方式中，接收设备利用相位噪声校正信号对待校正信号进行相位噪声校正之前，接收设备将待校正信号与第一本振信号混频，生成第一输出信号，该第一本振信号是本地振荡器输出的信号，并将该第一输出信号通过模数转换器转换为数字信号。
具体地，本振器产生第一本振信号之后，该第一本振信号中存在相位噪声，待校正信号是高频信号，所以需要接收设备将待校正信号与第一本振信号混频，接收设备会将待校正信号变换为中频信号或低频信号(即第一输出信号)，然后利用相位噪声校正信号与第一输出信号进行复共轭运算，以消除校正第一输出信号中的相位噪声，由于相位噪声校正信号是数字信号，而第一输出信号是模拟信号，所以需要通过模数转换器将第一输出信号转换为数字信号之后才可以进行相位噪声校正。
在一种可能的实现方式中，该第一本振信号是本地振荡器在接收到第一输入信号之后输出的信号，该第一输入信号是本振锁相环在接收到参考时钟发送的参考时钟信号后输出的信号。
具体地，参考时钟为本振锁相环提供参考时钟信号，本振锁相环在接收到参考时钟信号之后，由压控振荡器(voltage control oscillator，VCO)输出第一级本地振荡信号，此时该第一级本地振荡信号的频率较低，需要将其送入本地振荡器(local oscillator，LO)，本地振荡器在接收到本振锁相环发送的第一级本地振荡信号(即第一输入信号)之后，对该第一级本地振荡信号进行倍频处理，将该信号的频率升高，具体进行多少倍频处理，可以按照实际需要进行设置，本申请对此不作限定。本地振荡器在进行倍频处理，升高信号频率之后，输出第一本振信号。
上述详细阐述了本申请实施例的方法，为了便于更好地实施本申请实施例的上述方案，相应地，下面还提供用于配合实施上述方案的相关装置。
参见图4，图4为本申请实施例提供的一种发送设备的结构示意图，该发送设备400至少包括：合成单元410、滤波跟踪单元420、叠加单元430和混频输出单元440；其中：
合成单元410，用于将第一合成信号与第二合成信号进行合成得到抖动噪声消除信号，其中，该第一合成信号与第二合成信号的频率和时延相同；
滤波跟踪单元420，用于将所述抖动噪声消除信号进行滤波跟踪得到相位噪声校正信号；
叠加单元430，用于将基带信号与所述相位噪声校正信号进行叠加，生成待输出信号；
混频输出单元440，用于将所述待输出信号与第一本振信号混频，生成输出信号，并将所述输出信号发送至接收设备；
其中，所述发送设备400还包括振荡信号生成单元450，用于生成第一本振信号；参考信号生成单元460，用于生成第一参考源信号；延迟信号生成单元470，用于生成第一延迟信号；时钟信号生成单元480，用于生成参考时钟信号；分频单元490，用于将第一本振信号进行分频得到分频信号；模数转换单元4110，用于将分频信号和参考时钟信号进行模数转换，得到分频数字信号和参考时钟数字信号；所述合成单元410，还用于将模数转换单元4110输出的分频数字信号与参考信号生成单元460输出的第一参考源信号进行合成得到第一合成信号；所述合成单元410，还用于将模数转换单元4110输出的参考时钟数字信号与延迟信号生成单元460输出的第一延迟信号进行合成得到第二合成信号。
实施本申请实施例，发送设备通过利用模数转换单元4110对分频单元490输出的分频信号和时钟信号生成单元480输出的参考时钟信号同时进行模数转换，并通过合成单元410进行合成得到抖动噪声消除信号，并利用该信号对振荡信号生成单元450输出的第一本振信号进行校正，可以有效去除抖动噪声对校正信号的干扰，提升相位噪声校正性能。
在一种可能的实现方式中，所述发送设备400还包括倍频单元4120，用于将模数转换单元4110输出的参考时钟数字信号进行倍频处理，输出第一时钟信号；所述参考信号生成单元460，还用于生成第二参考源信号，该第二参考源信号与第一时钟信号的频率相同。
在一种可能的实现方式中，所述合成单元410，还用于将参考信号生成单元460输出的第二参考源信号与模数转换单元4110输出的分频数字信号进行合成得到第三合成信号，该第三合成信号与第一时钟信号的频率相同；
所述发送设备400还包括相关计算单元4130，用于将倍频单元4120输出的第一时钟信号与第三合成信号进行相关计算得到延时信息，并将所述延时信息配置到所述参考信号生成单元460，以使参考信号生成单元460输出第一参考源信号，第一参考源信号与第一时钟信号的频率和时延相同；
或者是，该相关计算单元4130将所述延时信息配置到所述延迟信号生成单元470，以使延迟信号生成单元470输出第一延迟信号，第一延迟信号与第三合成信号的频率和时延相同。
在一种可能的实现方式中，所述发送设备400还包括滤波单元4140，用于对分频单元490输出的分频信号进行滤波，提取得到包含相位噪声的信号。
在一种可能的实现方式中，所述发送设备400还包括第二本振信号生成单元4150，用于接收时钟信号生成单元480输出的参考时钟信号，并输出第二本振信号到振荡信号生成单元450，该第二本振信号的频率比第一本振信号的频率低。
在一种可能的实现方式中，所述发送设备400还包括速率变化单元4160，用于将合成单元410输出的抖动噪声消除信号进行第一速率变换；所述速率变化单元4160，还用于将滤波跟踪单元420输出的信号进行第二速率变换。
在一种可能的实现方式中，所述发送设备400还包括数模转换单元4170，用于将叠加单元430输出的待输出信号进行数模转换，得到待输出数字信号，并将该待输出数字信号发送给混频输出单元440。
值得说明的是，在本申请实施例中，合成单元410可以是复数乘法器，或者是频率调整器，或者是合波器等具有与上述功能相对应的器件，滤波跟踪单元420可以是自适应滤波器，例如卡尔曼滤波器，叠加单元430可以是合波器，混频输出单元440可以是调制器，振荡信号生成单元450可以是本地振荡器，参考信号生成单元460可以是参考源发生器，延迟信号生成单元470可以是延迟器，时钟信号生成单元480可以是参考时钟发生器，分频单元490可以是分频器，模数转换单元4110可以是模数转换器，倍频单元4120可以是倍频器，相关计算单元4130可以是相关器，滤波单元4140可以是带通滤波器，第二本振信号生成单元4150可以是锁相环，速率变化单元4160可以是采样器，数模转换单元4170可以是数模转换器。
可以理解，上述单元模块所对应的具体器件，可以根据实际需要进行选择，本申请对此不作限定。
需要说明的是，各个单元的实现还可以对应参照图2所示的方法实施例的相应描述，这里不再赘述。
参见图5，图5为本申请实施例提供的另一种发送设备的结构示意图，该发送设备500至少包括：本地振荡器510、调制器520、发射器530、分频器540、参考时钟发生器550、模数转换器560、参考源发生器570、延迟器580、频率时延调整器590和复数乘法器5110；其中：
本地振荡器510，用于生成第一本振信号；
调制器520，用于将基带信号与相位噪声校正信号叠加后的待输出信号与所述第一本振信号混频，生成输出信号；
发射器530，可以是发送设备500的收发接口或通信接口，用于将输出信号发送至接收设备；
分频器540，用于将所述第一本振信号进行分频，输出分频信号；
参考时钟发生器550，用于提供参考时钟信号；
模数转换器560，用于将所述分频信号和所述参考时钟信号转换为数字信号；
参考源发生器570，用于提供第一参考源信号；
延迟器580，用于提供第一延迟信号；
频率时延调整器590，用于将模数转换器560输出的分频数字信号与参考源发生器570输出的第一参考源信号进行合成得到第一合成信号，还用于将模数转换器560输出的参考时钟数字信号与延迟器580输出的第一延迟信号进行合成得到第二合成信号；
复数乘法器5110，用于将第一合成信号与第二合成信号进行合成(进行复共轭运算)，消除抖动噪声，得到抖动噪声消除信号，其中，第一合成信号与第二合成信号的频率和时延相同。
在一种可能的实现方式中，该发送设备500还包括倍频器5120，用于将模数转换器560输出的参考时钟数字信号进行倍频处理，输出第一时钟信号；
所述参考源发生器570，还用于提供第二参考源信号，该第二参考源信号与第一时钟信号的频率相同。
在一种可能的实现方式中，频率时延调整器590，还用于将参考源发生器570输出的第二参考源信号与模数转换器560输出的分频数字信号进行合成(频率调整)，得到第三合成信号，该第三合成信号与第一时钟信号的频率相同；
进一步地，该发送设备500还包括相关器5130，用于将倍频器5120输出的第一时钟信号与第三合成信号进行相关计算得到延时信息，并将该延时信息配置到参考源发生器570中，以使其输出第一参考源信号，该第一参考源信号与第一时钟信号的频率和时延相同；
或者是，相关器5130将该延时信息配置到延迟器580中，以使其输出第一延迟信号，该第一延迟信号与第三合成信号的频率和时延相同。
在一种可能的实现方式中，该发送设备500还包括带通滤波器5140，用于对分频器540输出的分频信号进行滤波，提取得到包含相位噪声的信号。
特别地，可以在分频器540和模数转换器560之间部署带通滤波器5140进行滤波，此时该带通滤波器5140为模拟带通滤波器，也可以是在模数转换器560对分频器540输出的分频信号进行模数转换后，部署带通滤波器5140进行滤波，此时该带通滤波器5140为数字带通滤波器，可以按照实际需要进行选择部署，本申请对此不作限定。
在一种可能的实现方式中，该发送设备500还包括锁相环5150，用于接收参考时钟发生器550输出的参考时钟信号，并输出第二本振信号到本地振荡器510，其中，第二本振信号的频率比第一本振信号的频率低。
在一种可能的实现方式中，该发送设备500还包括自适应滤波器5160和采样器5170，自适应滤波器5160可以是卡尔曼滤波器，用于对抖动噪声信号进行滤波，得到相位噪声校正信号；采样器5170，可以用于在复数乘法器5110输出的抖动噪声消除信号进行滤波之前，对该抖动噪声消除信号进行第一速率变换，降低其采样速率，便于计算；还用于将自 适应滤波器5160输出的信号进行第二速率变换，以提高其采样速率，使其与发射速率相匹配。
在一种可能的实现方式中，该发送设备500还包括合波器5180和数模转换器5190，合波器5180，用于将基带信号与相位噪声校正信号进行叠加输出待输出信号，数模转换器5190，用于将合波器5180输出的待输出信号进行数模转换，得到待输出数字信号，并将该待输出数字信号发送给调制器520。
综上所述，通过实施本申请实施例，发送设备通过利用模数转换器560对分频器540输出的分频信号和参考时钟发生器550输出的参考时钟信号进行模数转换，并通过复数乘法器5110进行复共轭运算得到抖动噪声消除信号，并利用该信号对本地振荡器510输出的第一本振信号进行校正，可以有效去除抖动噪声对校正信号的干扰，提升相位噪声校正性能。
需要说明的是，各个操作的具体实现还可以对应参照图2所示的方法实施例的相应描述以及图4所示的实施例的相应描述，此处不再赘述。
参见图6，图6为本申请实施例提供的一种接收设备的结构示意图，该接收设备600至少包括：接收单元610、合成单元620、滤波跟踪单元630和校正单元640；其中：
接收单元610，用于接收发送设备发送的待校正信号；
合成单元620，用于将第一合成信号与第二合成信号进行合成得到抖动噪声消除信号，其中，该第一合成信号与第二合成信号的频率和时延相同；
滤波跟踪单元630，用于将所述抖动噪声消除信号进行滤波跟踪得到相位噪声校正信号；
校正单元640，用于对所述待校正信号进行相位噪声校正；
其中，所述接收设备还包括参考信号生成单元650，用于生成第一参考源信号；延迟信号生成单元660，用于生成第一延迟信号；时钟信号生成单元670，用于生成参考时钟信号；分频单元680，用于将输入的信号进行分频得到分频信号；模数转换单元690，用于将分频信号和参考时钟信号进行模数转换，得到分频数字信号和参考时钟数字信号；所述合成单元620，还用于将模数转换单元690输出的分频数字信号与参考信号生成单元650输出的第一参考源信号进行合成得到第一合成信号；所述合成单元620，还用于将模数转换单元690输出的参考时钟数字信号与延迟信号生成单元660输出的第一延迟信号进行合成得到第二合成信号。
实施本申请实施例，接收设备通过利用模数转换单元690对分频单元680输出的分频信号和时钟信号生成单元670输出的参考时钟信号同时进行模数转换，并通过合成单元620进行合成得到抖动噪声消除信号，并利用该信号对接收单元610输出的待校正信号进行校正，可以有效去除抖动噪声对校正信号的干扰，提升相位噪声校正性能。
在一种可能的实现方式中，所述接收设备600还包括倍频单元6110，用于将模数转换 单元690输出的参考时钟数字信号进行倍频处理，输出第一时钟信号；所述参考信号生成单元650，还用于生成第二参考源信号，该第二参考源信号与第一时钟信号的频率相同。
在一种可能的实现方式中，所述合成单元620，还用于将参考信号生成单元650输出的第二参考源信号与模数转换单元690输出的分频数字信号进行合成得到第三合成信号，该第三合成信号与第一时钟信号的频率相同；
所述接收设备600还包括相关计算单元6120，用于将倍频单元6110输出的第一时钟信号与第三合成信号进行相关计算得到延时信息，并将所述延时信息配置到所述参考信号生成单元650中，以使参考信号生成单元650输出第一参考源信号，第一参考源信号与第一时钟信号的频率和时延相同；
或者是，该相关计算单元6120将所述延时信息配置到所述延迟信号生成单元660，以使延迟信号生成单元660输出第一延迟信号，第一延迟信号与第三合成信号的频率和时延相同。
在一种可能的实现方式中，所述接收设备600还包括滤波单元6130，用于对分频单元680输出的分频信号进行滤波，提取得到包含相位噪声的信号。
在一种可能的实现方式中，所述接收设备600还包括振荡信号生成单元6140和混频输出单元6150，振荡信号生成单元6140，用于生成第一本振信号；混频输出单元6150，用于将待校正信号与第一本振信号混频，生成第一输出信号；
所述模数转换单元690，还用于将混频输出单元6150输出的第一输出信号进行模数转换，将其转换为数字信号。
在一种可能的实现方式中，所述接收设备600还包括第二本振信号生成单元6160，用于接收时钟信号生成单元670输出的参考时钟信号，并输出第二本振信号到振荡信号生成单元6140，该第二本振信号的频率比第一本振信号的频率低。
在一种可能的实现方式中，所述接收设备600还包括速率变化单元6170，用于将合成单元620输出的抖动噪声消除信号进行第一速率变换；所述速率变化单元6170，还用于将滤波跟踪单元630输出的信号进行第二速率变换。
值得说明的是，在本申请实施例中，接收单元610可以是接收器或接收天线，合成单元620可以是复数乘法器，或者是频率调整器，或者是合波器等具有与上述功能相对应的器件，滤波跟踪单元630可以是自适应滤波器，例如卡尔曼滤波器，校正单元640可以是信号校正器，参考信号生成单元650可以是参考源发生器，延迟信号生成单元660可以是延迟器，时钟信号生成单元670可以是参考时钟发生器，分频单元680可以是分频器，模数转换单元690可以是模数转换器，倍频单元6110可以是倍频器，相关计算单元6120可以是相关器，滤波单元6130可以是带通滤波器，振荡信号生成单元6140可以是本地振荡 器，混频输出单元6150可以是调制器，第二本振信号生成单元6160可以是锁相环，速率变化单元6170可以是采样器。
可以理解，上述单元模块所对应的具体器件，可以根据实际需要进行选择，本申请对此不作限定。
需要说明的是，各个单元的实现还可以对应参照图3所示的方法实施例的相应描述，这里不再赘述。
参见图7，图7为本申请实施例提供的另一种接收设备的结构示意图，该接收设备700至少包括：本地振荡器710、接收器720、调制器730、分频器740、参考时钟发生器750、模数转换器760、参考源发生器770、延迟器780、频率时延调整器790和复数乘法器7110；其中：
本地振荡器710，用于生成第一本振信号；
接收器720，可以是接收设备700的收发接口或通信接口，用于接收发送设备发送的待校正信号；
解调器730，用于将待校正信号与第一本振信号混频，生成第一输出信号；
分频器740，用于将第一本振信号进行分频，输出分频信号；
参考时钟发生器750，用于提供参考时钟信号；
模数转换器760，用于将所述分频信号和所述参考时钟信号转换为数字信号；
参考源发生器770，用于提供第一参考源信号；
延迟器780，用于用于提供第一延迟信号；
频率时延调整器790，用于将模数转换器760输出的分频数字信号与参考源发生器770输出的第一参考源信号进行合成得到第一合成信号，还用于将模数转换器760输出的参考时钟数字信号与延迟器780输出的第一延迟信号进行合成得到第二合成信号；
复数乘法器7110，用于将第一合成信号与第二合成信号进行合成(进行复共轭运算)，消除抖动噪声，得到抖动噪声消除信号，其中，第一合成信号与第二合成信号的频率和时延相同。
在一种可能的实现方式中，该接收设备700还包括倍频器7120，用于将模数转换器760输出的参考时钟数字信号进行倍频处理，输出第一时钟信号；
所述参考源发生器770，还用于提供第二参考源信号，该第二参考源信号与第一时钟信号的频率相同。
在一种可能的实现方式中，频率时延调整器790，还用于将参考源发生器770输出的第二参考源信号与模数转换器760输出的分频数字信号进行合成(频率调整)，得到第三合成信号，该第三合成信号与第一时钟信号的频率相同；
进一步地，该接收设备700还包括相关器7130，用于将倍频器7120输出的第一时钟信号与第三合成信号进行相关计算得到延时信息，并将该延时信息配置到参考源发生器770中，以使其输出第一参考源信号，该第一参考源信号与第一时钟信号的频率和时延相同；
或者是，相关器7130将该延时信息配置到延迟器780中，以使其输出第一延迟信号，该第一延迟信号与第三合成信号的频率和时延相同。
在一种可能的实现方式中，该接收设备700还包括带通滤波器7140，用于对分频器740输出的分频信号进行滤波，提取得到包含相位噪声的信号。
特别地，可以在分频器740和模数转换器760之间部署带通滤波器7140进行滤波，此时该带通滤波器7140为模拟带通滤波器，也可以是在模数转换器760对分频器740输出的分频信号进行模数转换后，部署带通滤波器7140进行滤波，此时该带通滤波器7140为数字带通滤波器，可以按照实际需要进行选择部署，本申请对此不作限定。
在一种可能的实现方式中，该接收设备700还包括锁相环7150，用于接收参考时钟发生器750输出的参考时钟信号，并输出第二本振信号到本地振荡器710，其中，第二本振信号的频率比第一本振信号的频率低。
在一种可能的实现方式中，该接收设备700还包括自适应滤波器7160、采样器7170和信号校正器7180，自适应滤波器7160可以是卡尔曼滤波器，用于对抖动噪声信号进行滤波，得到相位噪声校正信号；采样器7170，可以用于在复数乘法器7110输出的抖动噪声消除信号进行滤波之前，对该抖动噪声消除信号进行第一速率变换，降低其采样速率，便于计算；还用于将自适应滤波器7160输出的信号进行第二速率变换，以提高其采样速率，使其与发射速率相匹配；信号校正器7180，用于接收采样器7170输出的相位噪声校正信号和模数转换器760输出的经过混频的待校正数字信号，并利用该相位噪声校正信号对该待校正数字信号进行校正。
综上所述，通过实施本申请实施例，接收设备通过利用模数转换器760对分频器740输出的分频信号和参考时钟发生器750输出的参考时钟信号进行模数转换，并通过复数乘法器7110进行复共轭运算得到抖动噪声消除信号，并利用该信号对解调器730输出的经过混频的待校正信号进行校正，可以有效去除抖动噪声对校正信号的干扰，提升相位噪声校正性能。
需要说明的是，各个操作的具体实现还可以对应参照图3所示的方法实施例的相应描述以及图6所示的实施例的相应描述，此处不再赘述。
应理解，本申请的实施例不仅仅针对微波系统上对相位噪声校正的应用场景，还可以应用于射频系统上对相位噪声校正的应用场景，还可以应用于光通信系统上对激光器相位调整噪声校正的应用场景，还可以应用于微波直放站上对射频通信信号的传输场景。需要说明的是，上述应用场景只是一种示例，实际应用中并不仅限于此。
还应理解，本申请中涉及的第一、第二、第三以及各种数字编号仅仅为描述方便进行的区分，并不用来限制本申请的范围。
应理解，本申请中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三 种情况。另外，本申请中字符“/”，一般表示前后关联对象是一种“或”的关系。
此外，在本申请的各个实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及方法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚的了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。
在本申请所提供的实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块和单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的互相之间的耦合或直接耦合或通信连接可以是通过一些接口完成，装置或单元的间接耦合或通信连接，可以是电性、机械或其它的形式。
所述作为分离部件说明的单元可以是物理上分开的，也可以不是物理上分开的，作为单元显示的部件可以是物理单元，也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本申请实施例方案的目的。
此外，在本申请各个实施例中所涉及的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现，本申请对此不作限定。
本申请实施例还提供了一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当其在计算机或处理器上运行时，使得计算机或处理器执行上述任一个实施例所述方法中的一个或多个步骤。上述装置的各组成模块如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在所述计算机可读取存储介质中，基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机产品存储在计算机可读存储介质中。
上述计算机可读存储介质可以是前述实施例所述的发送设备或接收设备的内部存储单元，例如硬盘或内存。上述计算机可读存储介质也可以是上述发送设备或接收设备的外部存储设备，例如配备的插接式硬盘，智能存储卡(Smart Media Card，SMC)，安全数字(Secure Digital，SD)卡，闪存卡(Flash Card)等。进一步地，上述计算机可读存储介质还可以既包括上述发送设备或接收设备的内部存储单元也包括外部存储设备。上述计算机可读存 储介质用于存储上述计算机程序以及上述发送设备或接收设备所需的其他程序和数据。上述计算机可读存储介质还可以用于暂时地存储已经输出或者将要输出的数据。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，可通过计算机程序来指令相关的硬件来完成，该计算机的程序可存储于计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可存储程序代码的介质。
本申请实施例方法中的步骤可以根据实际需要进行顺序调整、合并和删减。
本申请实施例装置中的模块可以根据实际需要进行合并、划分和删减。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (29)

  1. 一种相位噪声校正方法，其特征在于，包括：
    发送设备将第一合成信号与第二合成信号进行合成得到抖动噪声消除信号；
    将所述抖动噪声消除信号进行滤波跟踪得到相位噪声校正信号；
    将基带信号与所述相位噪声校正信号进行叠加，生成待输出信号；
    将所述待输出信号与第一本振信号混频，生成输出信号，并将所述输出信号发送至接收设备；
    其中，所述第一合成信号与所述第二合成信号的频率和时延相同，所述第一合成信号是分频器输出信号经过模数转换器后得到的信号与第一参考源信号进行合成得到的信号，所述第二合成信号是参考时钟输出信号经过模数转换器后得到的信号与第一延迟信号进行合成得到的信号，所述第一本振信号是本地振荡器输出的信号，所述第一参考源信号是参考源发生器输出的信号，所述第一延迟信号是延迟器输出的信号。
  2. 如权利要求1所述的方法，其特征在于，在所述第一合成信号与所述第二合成信号进行合成之前，所述方法还包括：
    将所述参考时钟输出信号经过模数转换器后得到的信号进行倍频处理得到第一时钟信号；
    根据所述第一时钟信号，以使所述参考源发生器输出第二参考源信号，所述第二参考源信号与所述第一时钟信号的频率相同。
  3. 如权利要求1或2所述的方法，其特征在于，在所述参考源发生器输出第二参考源信号之后，所述方法还包括：
    将所述第二参考源信号与所述分频器输出信号经过模数转换器后得到的信号进行合成得到第三合成信号，所述第三合成信号与所述第一时钟信号的频率相同；
    将所述第一时钟信号与第三合成信号进行相关计算得到延时信息，并将所述延时信息配置到所述参考源发生器中，以使所述参考源发生器根据所述时延信息输出所述第一参考源信号，所述第一参考源信号与所述第一时钟信号的频率和时延相同；或者是
    将所述第一时钟信号与第三合成信号进行相关计算得到延时信息，并将所述延时信息配置到所述延迟器中，以使所述延迟器根据所述时延信息输出所述第一延迟信号，所述第一延迟信号与所述第三合成信号的频率和时延相同。
  4. 如权利要求3所述的方法，其特征在于，将所述第二参考源信号与所述分频器输出信号经过模数转换器后得到的信号进行合成得到第三合成信号之前，所述方法还包括：
    对所述分频器输出信号进行滤波，提取得到包含相位噪声的信号。
  5. 如权利要求1至4任一项所述的方法，其特征在于，所述第一本振信号是所述本地振荡器在接收到第一输入信号之后输出的信号，所述第一输入信号是本振锁相环在接收到 所述参考时钟发送的参考时钟信号后输出的信号。
  6. 如权利要求1至5任一项所述的方法，其特征在于，将所述抖动噪声消除信号进行滤波跟踪之前，所述方法还包括：对所述抖动噪声消除信号进行第一速率变换；
    将所述抖动噪声消除信号进行滤波跟踪之后，所述方法还包括：对所述抖动噪声消除信号进行第二速率变换。
  7. 如权利要求1至6任一项所述的方法，其特征在于，所述将所述待输出信号与第一本振信号混频包括：
    所述发送设备将所述待输出信号通过数模转换器转换为模拟信号，将得到的所述模拟信号与所述第一本振信号进行混频。
  8. 一种相位噪声校正方法，其特征在于，包括：
    接收设备接收发送设备发送的待校正信号；
    接收设备将第一合成信号与第二合成信号进行合成得到抖动噪声消除信号；
    将所述抖动噪声消除信号进行滤波跟踪得到相位噪声校正信号；
    利用所述相位噪声校正信号对所述待校正信号进行相位噪声校正；
    其中，所述第一合成信号与所述第二合成信号的频率和时延相同，所述第一合成信号是分频器输出信号经过模数转换器后得到的信号与第一参考源信号进行合成得到的信号，所述第二合成信号是参考时钟输出信号经过模数转换器后得到的信号与第一延迟信号进行合成得到的信号，所述第一参考源信号是参考源发生器输出的信号，所述第一延迟信号是延迟器输出的信号。
  9. 如权利要求8所述的方法，其特征在于，在所述第一合成信号与所述第二合成信号进行合成之前，所述方法还包括：
    将所述参考时钟输出信号经过模数转换器后得到的信号进行倍频处理得到第一时钟信号；
    根据所述第一时钟信号，以使所述参考源发生器输出第二参考源信号，所述第二参考源信号与所述第一时钟信号的频率相同。
  10. 如权利要求8或9所述的方法，其特征在于，在所述参考源输出第二参考源信号之后，所述方法还包括：
    将所述第二参考源信号与所述分频器输出信号经过模数转换器后得到的信号进行合成得到第三合成信号，所述第三合成信号与所述第一时钟信号的频率相同；
    将所述第一时钟信号与第三合成信号进行相关计算得到延时信息，并将所述延时信息配置到所述参考源发生器中，以使所述参考源发生器根据所述时延信息输出所述第一参考源信号，所述第一参考源信号与所述第一时钟信号的频率和时延相同；或者是
    将所述第一时钟信号与第三合成信号进行相关计算得到延时信息，并将所述延时信息 配置到所述延迟器中，以使所述延迟器根据所述时延信息输出所述第一延迟信号，所述第一延迟信号与所述第三合成信号的频率和时延相同。
  11. 如权利要求10所述的方法，其特征在于，将所述第二参考源信号与所述分频器输出信号经过模数转换器后得到的信号进行合成得到第三合成信号之前，所述方法还包括：
    对所述分频器输出信号进行滤波，提取包含相位噪声的信号。
  12. 如权利要求8至11任一项所述的方法，其特征在于，利用所述相位噪声校正信号对所述待校正信号进行相位噪声校正之前，所述方法还包括：
    将所述待校正信号与第一本振信号混频，生成第一输出信号，所述第一本振信号是本地振荡器输出的信号；
    将所述第一输出信号通过模数转换器转换为数字信号。
  13. 如权利要求8至12任一项所述的方法，其特征在于，所述第一本振信号是所述本地振荡器在接收到第一输入信号之后输出的信号，所述第一输入信号是本振锁相环在接收到所述参考时钟发送的参考时钟信号后输出的信号。
  14. 如权利要求8至13任一项所述的方法，其特征在于，将所述抖动噪声消除信号进行滤波跟踪之前，所述方法还包括：对所述抖动噪声消除信号进行第一速率变换；
    将所述抖动噪声消除信号进行滤波跟踪之后，所述方法还包括：对所述抖动噪声消除信号进行第二速率变换。
  15. 一种发送设备，其特征在于，包括：
    合成单元，用于将第一合成信号与第二合成信号进行合成得到抖动噪声消除信号；
    滤波跟踪单元，用于将所述抖动噪声消除信号进行滤波跟踪得到相位噪声校正信号；
    叠加单元，用于将基带信号与所述相位噪声校正信号进行叠加，生成待输出信号；
    混频输出单元，用于将所述待输出信号与第一本振信号混频，生成输出信号，并将所述输出信号发送至接收设备；
    其中，所述第一合成信号与所述第二合成信号的频率和时延相同，所述第一合成信号是分频器输出信号经过模数转换器后得到的信号与第一参考源信号进行合成得到的信号，所述第二合成信号是参考时钟输出信号经过模数转换器后得到的信号与第一延迟信号进行合成得到的信号，所述第一本振信号是本地振荡器输出的信号，所述第一参考源信号是参考源发生器输出的信号，所述第一延迟信号是延迟器输出的信号。
  16. 一种发送设备，其特征在于，包括：收发模块、调制器、本地振荡器、模数转换器、分频器、参考源发生器、延迟器、合波模块和参考时钟模块，其中：
    所述本地振荡器，用于产生第一本振信号；
    所述调制器，用于将基带信号与相位噪声校正信号叠加后的待输出信号与所述第一本 振信号混频，生成输出信号；
    所述收发模块，用于将所述输出信号发送至接收设备；
    所述分频器，用于将所述第一本振信号进行分频，输出分频信号；
    所述参考时钟模块，用于提供参考时钟信号；
    所述模数转换器，用于将所述分频信号和所述参考时钟信号转换为数字信号；
    所述参考源发生器，用于提供第一参考源信号；
    所述延迟器，用于提供第一延迟信号；
    合波模块，用于将所述参考时钟模块输出信号经过所述模数转换器后得到的信号与所述第一延迟信号进行合成得到第二合成信号，以及将所述第一参考源信号与所述分频器输出信号经过所述模数转换器后得到的信号进行合成得到第一合成信号，还用于将所述第一合成信号与所述第二合成信号进行合成得到抖动噪声消除信号；
    其中，所述第一合成信号与所述第二合成信号的频率和时延相同。
  17. 如权利要求16所述的发送设备，其特征在于，所述发送设备还包括倍频器，
    所述倍频器，用于将所述参考时钟模块输出信号经过所述模数转换器后得到的信号进行倍频处理，得到第一时钟信号；
    所述参考源发生器，还用于提供第二参考源信号，所述第二参考源信号与所述第一时钟信号的频率相同。
  18. 如权利要求16或17所述的发送设备，其特征在于，
    所述合波模块，还用于将所述第二参考源信号与所述分频信号经过所述模数转换器后得到的信号进行合成得到第三合成信号，所述第三合成信号与所述第一时钟信号的频率相同；
    所述发送设备还包括相关器，用于将所述第一时钟信号与所述第三合成信号进行相关计算，得到延时信息，并将所述延时信息配置到所述参考源发生器中，以使所述参考源发生器根据所述时延信息输出所述第一参考源信号，所述第一参考源信号与所述第一时钟信号的频率和时延相同；或者是
    将所述延时信息配置到所述延迟器中，以使所述延迟器根据所述时延信息输出所述第一延迟信号，所述第一延迟信号与所述第三合成信号的频率和时延相同。
  19. 如权利要求18所述的发送设备，其特征在于，所述发送设备还包括滤波器，用于对所述分频信号进行滤波，提取得到包含相位噪声的信号。
  20. 如权利要求16至19任一项所述的发送设备，其特征在于，所述发送设备还包括本振锁相环，用于接收所述参考时钟模块输出的参考时钟信号并输出第一输出信号，以使所述本地振荡器根据所述第一输出信号输出所述第一本振信号。
  21. 如权利要求16至20任一项所述的发送设备，其特征在于，所述发送设备还包括 速率变化模块，用于在所述抖动噪声消除信号经过滤波跟踪之前对所述抖动噪声消除信号进行第一速率变换，以及在所述抖动噪声消除信号经过滤波跟踪之后对所述抖动噪声消除信号进行第二速率变换。
  22. 如权利要求16至21任一项所述的发送设备，其特征在于，所述发送设备还包括数模转换器，用于将所述待输出信号转换为模拟信号，并将所述模拟信号发送给所述调制器，以使所述调制器将所述模拟信号与所述第一本振信号进行混频。
  23. 一种接收设备，其特征在于，包括：
    接收单元，用于接收发送设备发送的待校正信号；
    合成单元，用于将第一合成信号与第二合成信号进行合成得到抖动噪声消除信号；
    滤波跟踪单元，用于将所述抖动噪声消除信号进行滤波跟踪得到相位噪声校正信号；
    校正单元，用于根据所述相位噪声校正信号对所述待校正信号进行相位噪声校正；
    其中，所述第一合成信号与所述第二合成信号的频率和时延相同，所述第一合成信号是分频器输出信号经过模数转换器后得到的信号与第一参考源信号进行合成得到的信号，所述第二合成信号是参考时钟输出信号经过模数转换器后得到的信号与第一延迟信号进行合成得到的信号，所述第一参考源信号是参考源发生器输出的信号，所述第一延迟信号是延迟器输出的信号。
  24. 一种接收设备，其特征在于，包括：收发模块、解调器、本地振荡器、模数转换器、分频器、参考源发生器、延迟器、合波模块和参考时钟模块，其中：
    所述本地振荡器，用于产生第一本振信号；
    所述收发模块，用于接收发送设备发送的待校正信号；
    所述解调器，用于将所述待校正信号与所述第一本振信号混频，生成第一输出信号；
    所述分频器，用于将所述第一本振信号进行分频，输出分频信号；
    所述参考时钟模块，用于提供参考时钟信号；
    所述模数转换器，用于将所述分频信号和所述参考时钟信号转换为数字信号；
    所述参考源发生器，用于提供第一参考源信号；
    所述延迟器，用于提供第一延迟信号；
    合波模块，用于将所述参考时钟模块输出信号经过所述模数转换器后得到的信号与所述第一延迟信号进行合成得到第二合成信号，以及将所述第一参考源信号与所述分频器输出信号经过所述模数转换器后得到的信号进行合成得到第一合成信号，还用于将所述第一合成信号与所述第二合成信号进行合成得到抖动噪声消除信号；
    其中，所述第一合成信号与所述第二合成信号的频率和时延相同。
  25. 如权利要求24所述的接收设备，其特征在于，所述接收设备还包括倍频器，
    所述倍频器，用于将所述参考时钟模块输出信号经过所述模数转换器后得到的信号进行倍频处理，得到第一时钟信号；
    所述参考源发生器，还用于提供第二参考源信号，所述第二参考源信号与所述第一时钟信号的频率相同。
  26. 如权利要求24或25所述的接收设备，其特征在于，
    所述合波模块，还用于将所述第二参考源信号与所述分频信号经过所述模数转换器后得到的信号进行合成得到第三合成信号，所述第三合成信号与所述第一时钟信号的频率相同；
    所述发送设备还包括相关器，用于将所述第一时钟信号与所述第三合成信号进行相关计算，得到延时信息，并将所述延时信息配置到所述参考源发生器中，以使所述参考源发生器根据所述时延信息输出所述第一参考源信号，所述第一参考源信号与所述第一时钟信号的频率和时延相同；或者是
    将所述延时信息配置到所述延迟器中，以使所述延迟器根据所述时延信息输出所述第一延迟信号，所述第一延迟信号与所述第三合成信号的频率和时延相同。
  27. 如权利要求26所述的接收设备，其特征在于，所述接收设备还包括滤波器，用于对所述分频信号进行滤波，提取得到包含相位噪声的信号。
  28. 如权利要求24至27任一项所述的接收设备，其特征在于，所述接收设备还包括本振锁相环，
    所述本振锁相环，用于接收所述参考时钟模块输出的参考时钟信号并输出第二输出信号，以使所述本地振荡器根据所述第二输出信号输出所述第一本振信号；
    所述模数转换器，还用于将所述第一输出信号转换为数字信号。
  29. 如权利要求24至28任一项所述的接收设备，其特征在于，所述接收设备还包括速率变化模块，用于在所述抖动噪声消除信号经过滤波跟踪之前对所述抖动噪声消除信号进行第一速率变换，以及在所述抖动噪声消除信号经过滤波跟踪之后对所述抖动噪声消除信号进行第二速率变换。
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