WO2020101164A1 - Transistor à couches minces à oxyde d'étain dopé et son procédé de fabrication - Google Patents

Transistor à couches minces à oxyde d'étain dopé et son procédé de fabrication Download PDF

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WO2020101164A1
WO2020101164A1 PCT/KR2019/011723 KR2019011723W WO2020101164A1 WO 2020101164 A1 WO2020101164 A1 WO 2020101164A1 KR 2019011723 W KR2019011723 W KR 2019011723W WO 2020101164 A1 WO2020101164 A1 WO 2020101164A1
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thin film
film transistor
channel layer
tin oxide
tin
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PCT/KR2019/011723
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Korean (ko)
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전형탁
박현우
정순신
문정민
최수석
유성필
정지환
장기석
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엘지디스플레이 주식회사
한양대학교 산학협력단
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Publication of WO2020101164A1 publication Critical patent/WO2020101164A1/fr

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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to a thin film transistor including a doped tin oxide as a channel layer and improved switching characteristics and charge mobility, and a method for manufacturing the same.
  • the thin film transistor is a device that is essentially included in the field in the display industry.
  • a thin film transistor performs a key function of switching each pixel in a display device such as an LCD or OLED.
  • amorphous silicon was mainly used as the active layer, but the amorphous silicon had a problem that it was difficult to apply to ultra-high-speed driving due to low electron mobility.
  • low-temperature polysilicon has a problem that the process is complicated and it is difficult to secure the uniformity of the semiconductor layer. Accordingly, an oxide semiconductor having a low leakage current compared to a silicon semiconductor and having an advantage of being transparent and facilitating a large-area process has recently attracted attention in the display industry.
  • the oxide semiconductor has various advantages such as high mobility, transparency, and applicability to a flexible substrate, as well as low deposition temperature, efforts to utilize the oxide semiconductor in thin film transistors have recently increased.
  • tin oxide is an oxide that has been studied for a long time and has attracted attention as an electronic material having physical, chemical, electrical and optical advantages.
  • tin dioxide is highly transparent due to its high band gap compared to other semiconductor materials, and has received great attention as a transparent conductive film due to its low electrical resistivity.
  • tin oxide is mainly produced through a spray pyrolysis process, and the process has disadvantages in that it is difficult to apply because the dosing device itself is difficult to apply to a large area and is not easily doped in oxide semiconductors.
  • the chemical vapor deposition method widely used in the current display industry has the advantage of being capable of uniformly depositing and performing a fine patterning process as a subsequent process.
  • the chemical vapor deposition method does not apply a flexible substrate such as plastic as a substrate because it requires a high process temperature to obtain high quality tin oxide, and further, there is a problem that doping is difficult.
  • the present invention is to solve the above-described problems, and an object of the present invention is to provide an oxide thin film transistor including a doped tin oxide channel layer to improve electrical characteristics of a switching element.
  • Another object of the present invention is to provide an oxide thin film transistor having a reduced charge concentration compared to pure tin oxide and an improved on / off current ratio ratio by doping the tin oxide channel layer.
  • another object of the present invention is to provide an oxide thin film transistor suitable for a large area process and having improved electrical properties after a doping process and a heat treatment process.
  • the present invention according to an embodiment of the present invention for achieving the above object, the base substrate; A gate electrode positioned on the base substrate; A gate insulating layer on the gate electrode; A channel layer positioned on the gate insulating layer; Located on the gate insulating layer, the source electrode and the drain electrode spaced apart from each other with the channel layer interposed therebetween.
  • the channel layer includes tin doped with aluminum, and has a charge concentration of 10 16 to 10 18.
  • a thin film transistor characterized by being / cm 3 is provided.
  • the thin film transistor has a charge effect (field effect mobility) of 0.1 ⁇ 4 cm 2 / Vs; characterized in that the thin film transistor may be provided.
  • the thin film transistor has a charge effect (field effect mobility) of 0.1 ⁇ 4 cm 2 / Vs; characterized in that the thin film transistor may be provided.
  • the thin film transistor has an on / off current ratio of (1 to 10) * 10 6 ; a thin film transistor may be provided.
  • the full width half maximum after air annealing of the channel layer is 1.6 than the full width of the XRD half after atmospheric annealing of undoped tin oxide (SnO 2 ) based on the (200) plane peak.
  • a thin film transistor characterized by being 2 times to 2.13 times larger may be provided.
  • the present invention according to another embodiment of the present invention for achieving the above object, the process of forming a gate electrode on a substrate; Forming a gate insulating layer on the gate electrode; Forming a channel layer on the gate insulating layer; Forming a source electrode and a drain electrode spaced apart from each other with the channel layer interposed therebetween;
  • the annealing process including, the process of forming the channel layer includes a tin oxide (SnO x ) cycle / argon (Ar) purging / aluminum oxide (Al 2 O 3 ) cycle / argon purging step, the aluminum oxide ( The Al 2 O 3 ) cycle is performed in the middle of a tin oxide (SnO x ) cycle that is performed multiple times; a method for manufacturing a thin film transistor is provided.
  • the tin oxide (SnO x ) cycle uses atomic layer deposition (ALD), and each step supplies tin chemicals to adsorb tin chemicals onto the substrate / argon purging step / oxygen source.
  • a method of manufacturing a thin film transistor comprising: a step of argon / argon purging by adsorbing an oxygen species on a substrate on which the tin species is adsorbed.
  • the tin species includes a tetravalent tin precursor, and the oxygen source is ozone or oxygen; a method for manufacturing a thin film transistor may be provided.
  • the annealing process is performed in an air (300) to 500 °C temperature range;
  • a method of manufacturing a thin film transistor characterized in that may be provided.
  • the charge concentration of the channel layer is 10 16 ⁇ 10 18 / cm 3;
  • a method of manufacturing a thin film transistor may be provided.
  • a charge effect (field effect mobility) of the thin film transistor is 0.1 to 4 cm 2 / Vs, and an on / off current ratio is 1 to 10 * 10 6 ; Methods can be provided.
  • the full width half maximum of the channel layer is 1.6 to 2.13 times larger than the full width of the XRD half of the undoped tin oxide (SnO 2 ) based on the (200) plane peak;
  • a method of manufacturing a thin film transistor characterized in that may be provided.
  • tin dioxide doped with aluminum is applied to the channel layer of the thin film transistor, it is possible to obtain an effect of delaying crystallization of the tin oxide channel layer during the annealing process.
  • delayed crystallization of the tin dioxide layer by the aluminum doping can obtain an effect of reducing the charge concentration and charge mobility of the doped tin dioxide layer to a level suitable for use as a switching device.
  • the delayed crystallization resulting from aluminum doping has an effect of improving the on / off current ratio of the thin film transistor according to the present invention.
  • the method of manufacturing a thin film transistor including an aluminum-doped tin dioxide channel layer according to the present invention enables stable doping of aluminum with a low process temperature.
  • the manufacturing method of the thin film transistor of the present invention can obtain an advantageous effect that can be used for a large area and a flexible substrate.
  • FIG. 1 is a cross-sectional view of a typical bottom gate co-planar thin film transistor.
  • FIG. 2 is a cross-sectional view of a thin film transistor having a bottom gate co-planar structure including a doped channel layer according to an exemplary embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a manufacturing process of a thin film transistor having a bottom gate co-planar structure of the present invention.
  • FIG. 4 is a schematic diagram of a manufacturing process for forming a doped channel layer according to an embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of a thin film transistor having a bottom gate co-planar structure including a doped channel layer according to a comparative example of the present invention.
  • FIG. 6 is a cross-sectional view of a bottom gate co-planar structure thin film transistor including a doped channel layer according to another comparative example of the present invention.
  • FIG. 7 is a graph showing the current-voltage characteristics of a thin-film transistor having a bottom gate co-planar structure immediately after deposition according to an embodiment and a comparative example of the present invention.
  • FIG. 8 shows the current of an as-annealed bottom gate co-planar structured thin film transistor at 300 ° C. after deposition according to embodiments and comparative examples of the present invention. It is a graph showing the voltage characteristics.
  • FIG. 9 shows the current of an as-annealed bottom gate co-planar structured thin film transistor at 400 ° C. after deposition according to embodiments and comparative examples of the present invention. It is a graph showing the voltage characteristics.
  • FIG. 13 is an XRD result of air annealed at 400 ° C. after deposition of an aluminum-doped tin oxide channel layer according to examples and comparative examples of the present invention.
  • any configuration provided or disposed in the "top (or bottom)" of the substrate or the “top (or bottom)” of the substrate means that any configuration is provided or disposed in contact with the top (or bottom) of the substrate. Not only does it mean, but is not limited to not including other configurations between the substrate and any configuration provided or disposed on (or under) the substrate.
  • the present invention provides a tin oxide thin film transistor including a tin oxide doped with aluminum as a channel layer and a method for manufacturing the same.
  • the present invention provides a tin oxide thin film transistor having improved electrical properties by delaying crystallization of a tin oxide channel layer even after heat treatment by changing the position of an aluminum doping layer in a tin oxide channel layer as an embodiment.
  • a manufacturing method for forming an aluminum doped layer in the channel layer is provided to manufacture a tin oxide thin film transistor with improved electrical properties.
  • tin oxide is included as a channel layer.
  • the thin film transistor has a structure as shown in FIG. 1, that is, a gate electrode 20, a gate insulating film 30, a channel layer 50, and a source / drain electrode 40 are sequentially stacked on a substrate 10. It may be composed of a bottom gate thin film transistor having a planar structure.
  • the substrate 10 a general one in this field may be used, and for example, it may be selected from glass, metal foil, plastic, or silicon. On the other hand, considering the applicability to the flexible substrate, plastic is more preferable among the substrate materials.
  • the gate electrode 20 may include a transparent oxide such as ITO, IZO, ZnO: Al (Ga), a metal having various low resistances such as Ti, Ag, Au, Al, Cr, Al / Cr / Al, Ni, or the like. Conductive polymers can be used, but are not necessarily limited to this.
  • the gate electrode 20 may be patterned after being deposited on the substrate 10 through a process such as sputtering, atomic layer deposition (ALD), chemical vapor deposition (CVD), to a typical thickness in this field.
  • the gate insulating film 30 formed on the substrate 10 and the gate electrode 20 includes any one or more of transparent oxide or nitride, for example, SiNx, AlON, TiO2, AlOx, TaOx, HfOx, SiON, SiOx It can be, preferably, aluminum oxide (Al 2 O 3 ) And the like can be used. In addition, thin films using polymers can also be applied. In addition, the gate insulating film 30 may be formed through processes such as atomic layer deposition (ALD), PECVD, and other sputtering methods with a typical thickness in this field. Although not shown, pads for electrode connection are formed after formation. It may be.
  • ALD atomic layer deposition
  • PECVD PECVD
  • pads for electrode connection are formed after formation. It may be.
  • the source / drain electrode 40 and the channel layer 50 formed on the channel region may include tin-containing oxide.
  • the tin-containing oxide may be present as a type of SnO 2 .
  • crystalline tin dioxide (SnO 2 ) has a very high charge concentration of about 10 20 ⁇ 10 22 / cm 3. Crystalline tin dioxide has an electrical conductivity that is too high for use as a channel layer, and is rather suitable for a conductive material such as an electrode. Therefore, in order for tin dioxide to be used as the channel layer, the electrical conductivity must first be adjusted to be suitable for use as the channel layer.
  • the thin film transistor of the present invention includes tin dioxide whose electrical conductivity and / or crystallinity is controlled. More specifically, the channel layer in the thin film transistor of the present invention is characterized by improving the electrical properties of the thin film transistor by controlling the doping position of the aluminum together with aluminum doping.
  • transparent oxides such as ITO, IZO, ZnO: Al (Ga), Al, Cr, Au, Ag, Metal or conductive polymers such as Ti can be used, but are not limited thereto.
  • the source and drain electrodes 40 may form a two-layer structure of the metal and oxide.
  • the source / drain electrodes can be deposited through a process such as sputtering, ALD, CVD, etc., to a typical thickness in this field.
  • a protective layer may be formed.
  • polymer materials such as polyimide polymer may be patterned after being formed through methods such as spin coating, dip coating, and casting.
  • insulating materials such as SiO 2 and Al 2 O 3 may be patterned after being formed through chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • FIG. 2 is a cross-sectional view of a thin film transistor having a bottom gate co-planar structure including a doped channel layer according to an exemplary embodiment of the present invention.
  • the manufacturing method and stacked structure of the base substrate, the gate electrode, the gate insulating layer, and the source electrode and the drain electrode can be applied in the same manner as the corresponding configuration of the thin film transistor of FIG. 1, and detailed description thereof will be omitted. .
  • description will be made focusing on the main technical features of the present invention.
  • the thin film transistor of FIG. 2 has a feature that additionally includes an aluminum doped layer 60 in the middle of the channel layer 50 when compared with the thin film transistor of FIG. 1.
  • the aluminum doped layer 60 of the embodiment of the present invention performs a function of improving the electrical properties as a switching element of the thin film transistor of the embodiment of the present invention.
  • the aluminum doping layer 60 of the embodiment of the present invention can improve the on / off current ratio, which is a main characteristic of the switching device, by doping the tin dioxide channel layer 50 with aluminum. .
  • the tin dioxide channel layer 50 has a high charge mobility corresponding to a conductive material, and thus is difficult to use as a channel layer of a thin film transistor.
  • the aluminum doped layer 60 of this embodiment may reduce the field effect mobility to be used as a channel layer by doping the tin dioxide channel layer 50 having high electrical conductivity with aluminum.
  • the aluminum doping layer 60 of the embodiment of the present invention is preferably located in the middle (1/2) in the thickness direction of the tin dioxide channel layer 50.
  • the thin film transistor typically includes an annealing step as a subsequent process after the deposition step. This is because in the deposition step of the thin film transistor, the substrate is heated to a predetermined temperature or higher for good deposition film quality, and further, a diffusion process is included in a subsequent process. If the aluminum doping layer 60 of the embodiment of the present invention is located in the middle in the thickness direction within the tin dioxide channel layer 50, aluminum diffuses into the tin dioxide channel layer 50 during the annealing process, thereby allowing the tin dioxide channel layer The crystallization of (50) can be delayed. As a result, the tin dioxide channel layer 50 cannot be crystallized or the complete crystallization is delayed, thereby reducing electrical conductivity and increasing the on / off current ratio.
  • annealing of the aluminum doped layer 60 of the embodiment of the present invention is preferably performed in a temperature range of 300 to 500 ° C. If the annealing temperature is lower than 300 ° C, a problem arises that the tin oxide 50 in an amorphous state as-dep cannot be crystallized and cannot form a channel. On the other hand, if the annealing temperature is higher than 500 ° C., the tin oxide layer 50 may cause aluminum and gallium (Ga) to enter the shallow level in the semiconductor energy band gap, thereby exhibiting p-type characteristics, resulting in deterioration of transistor characteristics. .
  • Ga aluminum and gallium
  • FIG. 3 is a schematic diagram of a manufacturing process of a bottom gate co-planar structure of a thin film transistor of FIG. 2, which is an embodiment of the present invention, and FIG. 4 is doped according to an embodiment of the present invention. It is a schematic diagram of the manufacturing process of forming a channel layer.
  • a 100 ⁇ 100 mm 3 alkali-free glass substrate was sequentially ultrasonically cleaned with acetone, iso-propyl alcohol and deionized water.
  • the gate electrode was deposited and patterned to a thickness of 150 nm by sputtering with DC-RF magnetron sputtering with ITO on the cleaned glass substrate.
  • a gate insulating layer having a thickness of 170 nm was formed by ALD method at 150 ° C using alumina.
  • FIG. 3 after coating the PR layer, patterning it into a shape of a channel layer, and then aluminum-doped (60) tin dioxide channel layer 50 according to an embodiment of the present invention as shown in FIG. 2 ) was formed.
  • FIG. 4 The method of forming the tin dioxide channel layer 50 and the aluminum doped layer 60 according to an embodiment of the present invention of FIG. 2 is shown in detail in FIG. 4.
  • the tin dioxide channel layer 50 and the aluminum doped layer 60 of one embodiment of the present invention were deposited by atomic layer deposition (ALD). More specifically, the atomic layer deposition method in the embodiment of the present invention includes a tin oxide (SnO x ) cycle / argon (Ar) purge / aluminum oxide (Al 2 O 3 ) cycle / argon purge step.
  • ALD atomic layer deposition
  • the tin oxide (SnO x ) cycle was repeated tens to hundreds of times depending on the thickness of the desired tin dioxide channel layer 50.
  • the aluminum oxide (Al 2 O 3 ) cycle was performed once.
  • the aluminum oxide (Al 2 O 3 ) cycle may be performed 1 to several times depending on the thickness of the desired aluminum doping layer.
  • the order in which the aluminum oxide (Al 2 O 3 ) cycle is applied is determined according to the position in the tin dioxide channel layer 50 of the aluminum doped layer 60. For example, when the aluminum doping layer 60 is located in the middle of the tin dioxide channel layer 50, as shown in one embodiment of the present invention shown in FIG. 2, the cycle of aluminum oxide (Al 2 O 3 ) is the entire tin oxide (SnO x ) It is located in the middle of the number of cycles.
  • the aluminum oxide (Al 2 O 3 ) cycle is the entire tin oxide (SnO x ) It is located in the vicinity of 1/4 or 3/4 of the number of cycles, respectively.
  • the tin oxide (SnO x ) cycle uses atomic layer deposition (ALD), and each step again supplies tin chemicals to adsorb tin chemicals on the substrate / argon purging step / oxygen source to supply tin chemicals
  • ALD atomic layer deposition
  • the step of adsorbing oxygen species on the adsorbed substrate causes an oxidation reaction / argon purging step.
  • the tin species is preferably a tetravalent tin precursor.
  • the tin precursor may include tetrakis (dimethylamino) tin (TDMASn), and the oxygen species may include ozone, oxygen, etc., but is not limited thereto.
  • Al 2 O 3 aluminum oxide
  • a tin dioxide channel layer 50 including the aluminum doping layer 60 is formed.
  • the thin film transistor according to an embodiment of the present invention formed by the above process was subjected to annealing treatment in a subsequent process ( Figures 7 to 10) and XRD analysis ( Figures 11 to 14).
  • a thin film transistor device was manufactured in the same manner as in Example 1, except that the aluminum doped layer 60 was positioned at 3/4 in the thickness direction of the tin dioxide channel layer 50.
  • the thin film transistor device of Comparative Example 1 under the same conditions as in Example 1 except that the aluminum oxide (Al 2 O 3 ) cycle of FIG. 4 is located in the vicinity of 3/4 of the total number of tin oxide (SnO x ) cycles was produced.
  • the thin film transistor according to Comparative Example 1 of the present invention was subjected to annealing treatment in a subsequent process (Figs. 7 to 10) and XRD analysis (Figs. 11 to 14).
  • a thin film transistor device was manufactured in the same manner as in Example 1, except that the aluminum doped layer 60 was positioned at 1/4 in the thickness direction of the tin dioxide channel layer 50.
  • the thin film transistor device of Comparative Example 1 under the same conditions as in Example 1, except that the aluminum oxide (Al 2 O 3 ) cycle of FIG. 4 is located near 1/4 of the total number of tin oxide (SnO x ) cycles was produced.
  • the thin film transistor according to Comparative Example 2 of the present invention was subjected to annealing treatment in a subsequent process (Figs. 7 to 10) and XRD analysis (Figs. 11 to 14).
  • the IV characteristic results of the device including the SnO 2 : Al (aluminum doped tin oxide) channel layer in the immediately after deposition (As-dep) state are firstly 1/4 (Comparative Example 1) and 3/4 (Comparative Example 2). It can be seen that the doping of the position has similar on / off current characteristics. On the contrary, it can be seen that in the doping of 1/2 (example), the on / off current characteristics are poor.
  • the electrical properties of the thin film transistor of the above embodiment are estimated to have reduced the on / off current ratio and the field effect mobility as a result of the fact that the channel cannot be formed due to the interference of the aluminum doping layer and the charge is not easily moved. do.
  • the thin film transistor of the embodiment of the present invention annealed at 300 to 500 ° C, it was measured that the on / off current ratio increased to a degree sufficient to be used as a switching element.
  • the improvement of the characteristics in the thin film transistor of the embodiment of the present invention is that the aluminum doped layer at the 1/2 position interferes with crystallization in the SnO 2 : Al SnO 2 : Al (aluminum doped tin oxide) channel and is suitable for use as a switching element. It is presumed to be due to the formation of a channel in the charge concentration region of 16 ⁇ 10 18 / cm 3 level.
  • the thin film transistor of the SnO 2 Al (aluminum doped tin oxide) channel layer including the aluminum doped layer at the 1/2 position annealed at 200 ° C is immediately after deposition (As-dep) of FIG. 7. It was measured that the on / off current characteristics were inferior to those of the thin film transistor of the SnO 2 : Al (aluminum doped tin oxide) channel layer including the aluminum doped layer at 1/2 position of.
  • the thin film transistor of the SnO 2 Al (aluminum doped tin oxide) channel layer including the aluminum doped layer at 1/2 position annealed at 550 ° C is 300 to 500 ° C in FIGS. 8 to 10. It was measured that the on / off current characteristics were inferior to those of the thin film transistor of the SnO 2 : Al (aluminum doped tin oxide) channel layer including the annealed aluminum doped layers at 1/4 and 3/4 positions. It is presumed that the annealing at 550 ° C. is a tin oxide layer 50 of aluminum, because aluminum and gallium (Ga) enter a shallow level at a semiconductor energy band gap and exhibit p-type characteristics, thereby degrading transistor characteristics.
  • Ga gallium
  • 11 to 14 are SnO 2 : Al (aluminum doped tin oxide) channel layers according to embodiments (1/2 position doping layer) and comparative examples (1/4 or 3/4 position doping layer) of the present invention, respectively. It is the result of XRD after air deposition and as-annealed at 300 ⁇ 500 ° C.
  • both the undoped tin oxide layer (SnO 2 ) as well as the SnO 2 : Al (aluminum doped tin oxide) channel layer of the embodiments and comparative examples of the present invention immediately after deposition (as-dep). It has been shown to have an amorphous structure.
  • the subsequent annealing process significantly changes the crystal structure of the undoped tin oxide layer (SnO 2 ) as well as the SnO 2 : Al (aluminum doped tin oxide) channel layer of the inventive examples and comparative examples.
  • both the SnO 2 : Al (aluminum doped tin oxide) channel layer and the undoped tin oxide (SnO 2 ) layer of the examples and comparative examples of the present invention show crystallinity by a subsequent annealing process at 300 to 500 ° C. It can be seen through Figures 12 to 14.
  • the crystal structures of undoped tin oxide (SnO 2 ) and SnO 2 : Al (aluminum doped tin oxide) were all measured to have rutile crystal structures.
  • the full width half maximum (FWHM) of the XRD of the rutile structure is compared with the comparative examples of the present invention or undoped tin oxide (SnO 2 ). It can be seen from FIGS. 12 to 14 that it has a broader tendency.
  • Table 5 below is a comparative example of the present invention, the channel layer thickness 1/4 and 3/4 doped at the positions and subsequently annealed SnO 2 : Al (aluminum doped tin oxide) thin film and the embodiment of the present invention channel layer thickness 1 / It is a summary of the results of the full width measurement of the XRD of the XRD relative to the (200) plane of the SnO 2 : Al (aluminum doped tin oxide) thin film doped at 2 positions and subsequently annealed.
  • SnO 2 The Al (aluminum doped tin oxide) thin film doped with the comparative example, which are a channel layer thickness of one-quarter and three-quarters
  • SnO 2 Al (aluminum Doping tin oxide)
  • the SnO 2 Al (aluminum doped tin oxide) thin film doped at a position of 1/2 of the channel layer thickness, which is an embodiment of the present invention, has an XRD half width of 160% to 200% in the entire annealing temperature range compared to undoped tin oxide (SnO 2 ). It can be seen from the measurement results in the above table that it is greater than 213%.
  • the XRD half width full width result means that the crystallinity of the annealed thin film after doping at the position of 1/2 of the thickness of the channel layer in the embodiment of the present invention is inferior to that of comparative examples and the undoped tin oxide (SnO 2 ) layer.
  • Embodiment of the invention is the crystalline deterioration due to the doped aluminum annealing diffuses into the SnO 2 is judged to be due to interference hayeotgi crystallization of SnO 2.
  • the low crystallinity of the embodiment of the present invention is considered to be one of the reasons why the on / off current ratio of the device having the channel layer of the embodiment of the present invention annealed in the IV analysis could be secured.
  • the SnO 2 : Al (aluminum doped tin oxide) thin film doped at positions 1/4 and 3/4 of the thickness of the channel layer has a smaller XRD half width than the embodiment of the present invention.
  • the SnO 2 : Al (aluminum doped tin oxide) thin film of Comparative Examples of the present invention has high crystallinity.
  • a thin film having a charge concentration of such a degree is not suitable for use as a thin film transistor device because it is similar to the charge concentration of ITO, which is widely used as a transparent conductive film.
  • gate insulating film 40 source / drain electrode
  • channel layer 60 aluminum doping layer

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Abstract

La présente invention concerne un transistor à couches minces comprenant une couche de canal de SnO2:Al (oxyde d'étain dopé à l'aluminium) dopée avec une couche de dopage d'aluminium à une position spécifique d'une couche de dioxyde d'étain, et son procédé de fabrication, de façon à pouvoir obtenir des caractéristiques de mobilité de charge et de rapport de courant conducteur/bloqué appropriées pour une utilisation en tant que couche de canal.
PCT/KR2019/011723 2018-11-16 2019-09-10 Transistor à couches minces à oxyde d'étain dopé et son procédé de fabrication WO2020101164A1 (fr)

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KR20100115220A (ko) * 2009-04-17 2010-10-27 삼성전자주식회사 인버터와 그 제조방법 및 인버터를 포함하는 논리회로
JP2018022879A (ja) * 2016-07-20 2018-02-08 株式会社リコー 電界効果型トランジスタ、及びその製造方法、並びに表示素子、画像表示装置、及びシステム

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JP2018022879A (ja) * 2016-07-20 2018-02-08 株式会社リコー 電界効果型トランジスタ、及びその製造方法、並びに表示素子、画像表示装置、及びシステム

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