WO2020097870A1

WO2020097870A1 - Current distribution circuit and storage device

Info

Publication number: WO2020097870A1
Application number: PCT/CN2018/115701
Authority: WO
Inventors: 王锐
Original assignee: 北京比特大陆科技有限公司
Priority date: 2018-11-15
Filing date: 2018-11-15
Publication date: 2020-05-22
Also published as: CN112805656A; CN112805656B

Abstract

A current distribution circuit and a storage device. The current distribution circuit comprises: a current distribution array (10), a control circuit (20) and a first protection circuit (30), wherein the current distribution array (10) comprises transistor array blocks distributed in an array, and generates multiple paths of externally supplied currents based on a reference current signal; the control circuit (20) is used for controlling a working state of the current distribution array (10); and the first protection circuit (30) is used for protecting a signal between the control circuit (20) and the current distribution array (10). By means of this method, a large-scale current distribution circuit can be realized, the current output of the large-scale current distribution circuit can be controlled, and a circuit signal can be guaranteed to be stable, so that an available current is provided for an ultra-large-scale power module.

Description

Current distribution circuit and storage device

Technical field

The present disclosure relates to the power supply technology of integrated circuits, in particular to a current distribution circuit and storage equipment,

Background technique

DDR (Double Data Rate) is a double-rate synchronous dynamic random access memory. The current distribution circuit is one of the important parts of DDR memory, which provides a fixed proportion of stable current for each sub-module. The design of the current distribution circuit determines the overall performance and stability of the DDR, so it is particularly important. The current distribution circuit in the existing DDR adopts a standard current mirror structure. For the input reference current, the circuit function realizes the desired multiple of amplification, and then outputs the desired currents.

Summary of the invention

The embodiments of the present disclosure provide a current distribution circuit and a storage device to solve the problems caused by the stability of the current distribution circuit and the expansion of the circuit scale in the prior art.

In a first aspect, an embodiment of the present disclosure provides a current distribution circuit, including: a current distribution array, a control circuit, and a first protection circuit; wherein,

The current distribution array includes transistor array blocks distributed in the array, and generates multiple externally supplied currents based on the reference current signal;

The control circuit is used to control the working state of the current distribution array;

The first protection circuit is used to protect the signal between the control circuit and the current distribution array.

Further, the current distribution circuit further includes: a second protection circuit; wherein,

The second protection circuit is used to protect the power supply voltage of the current distribution circuit.

Further, the second protection circuit includes a capacitive protection circuit.

Further, the current distribution circuit further includes: a third protection circuit; wherein,

The third protection circuit is used to protect the signal node between the current distribution circuit and the external module.

The third protection circuit includes a resistance type protection circuit and a capacitance type protection circuit.

Further, the current distribution circuit further includes: a fourth protection circuit;

Further, the fourth protection circuit is used to prevent the instantaneous voltage at the critical node on the current distribution circuit from being higher than the high voltage threshold or lower than the low voltage threshold.

The fourth protection circuit is a diode-type protection circuit, which prevents the instantaneous voltage at a critical node on the current distribution circuit from being higher than a high voltage threshold or lower than a low voltage threshold through a diode breakdown method.

Further, the current distribution array includes M rows of transistor array blocks, and M is a natural number greater than or equal to 3; wherein the M rows of transistor array blocks include a first region, a second region, and a third region on the circuit layout. The first region includes a first row of transistor array blocks, the first row of transistor array blocks is a reference array block, the second region includes a second row to M-1 row of transistor array blocks, and the second row to The M-1th row transistor array block is used for copying the reference current signal generated by the reference array block to output at least one first externally supplied current, and the third area includes the Mth row transistor array block for copying The reference current signal generated by the reference array block outputs at least one second externally supplied current.

Further, the first external supply current is a horizontal current in the circuit layout, the second external supply current is a vertical current in the circuit layout, and the current value of the first external supply current is greater than the first The current value of the external current supply.

Further, the first external current and the second external current are provided to different external modules respectively.

Further, each of the transistor array blocks includes a plurality of transistors distributed in an array, and the plurality of transistors are arranged to form a rectangular shape.

Further, among the M rows of transistor array blocks, transistor array blocks of different rows are independent of each other in circuit layout.

Further, each of the transistor array blocks in the M-row array distributed transistor array block includes an output current transistor and / or an auxiliary transistor.

Further, the current values of the first externally supplied current and the second externally supplied current are related to the output current transistor and / or the auxiliary transistor.

In a second aspect, an embodiment of the present disclosure provides a storage device, including the current distribution circuit according to any optional implementation manner of the first aspect.

The embodiments of the present disclosure use a transistor array block distributed in an array to implement a current distribution circuit, and provide multiple external supply currents based on the reference current signal. At the same time, the current distribution array is controlled by the control circuit and can automatically adjust whether the current distribution array works In order to provide a stable multi-channel external current supply to the current distribution array, a first protection circuit is also provided to protect the signal between the control circuit and the current distribution array to be stable. In this way, the embodiments of the present disclosure can realize a large-scale current distribution circuit, and make the current output of the large-scale current distribution circuit controllable, and can ensure the stability of the circuit signal, providing a usable current for a very large-scale power module.

BRIEF DESCRIPTION

In order to more clearly explain the embodiments of the present disclosure or the technical solutions in the prior art, the following will briefly introduce the drawings used in the description of the embodiments or the prior art. Obviously, the drawings in the following description These are some embodiments of the present disclosure. For those of ordinary skill in the art, without paying creative labor, other drawings may be obtained based on these drawings.

1 is a schematic structural diagram of a current distribution circuit 100 according to an embodiment of the present disclosure;

2 is a schematic structural diagram of a current distribution circuit 100 according to another embodiment of the present disclosure;

3 is a schematic diagram of a preferred circuit layout of a current distribution circuit 100 according to an embodiment of the present disclosure;

4 is a schematic diagram of a signal flow direction of a first partial transistor array block according to an embodiment of the present disclosure;

5 is a schematic diagram of a signal flow direction of a second partial transistor array block according to an embodiment of the present disclosure;

6 is a schematic structural diagram of a storage device 200 according to an embodiment of the present disclosure.

detailed description

To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are a part of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.

Those skilled in the art know that the embodiments of the present disclosure may be implemented as a system, device, device, method, or computer program product. Therefore, the present disclosure may be specifically implemented in the form of complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

When the current distribution circuit in the related art provides a large-scale current source current path, due to the surrounding modules of the current distribution circuit, the stability of the multi-channel current source is higher, and the stability of the traditional current mirror encounters the environment. The self-adjustment during the disturbance is not enough to meet the system requirements. This is a problem to be solved urgently in the design of the current distribution circuit in the DDR circuit. Therefore, the present disclosure proposes a current distribution circuit suitable for distributing stable current to surrounding modules when providing a large-scale current source current path. FIG. 1 is a schematic structural diagram of a current distribution circuit 100 according to an embodiment of the present disclosure. As shown in FIG. 1, the current distribution circuit 100 of the embodiment of the present disclosure includes: a current distribution array 10, a control circuit 20, and a first protection circuit 30; wherein,

The current distribution array 10 includes array-distributed transistor array blocks, and the current distribution array 10 can generate multiple externally supplied currents based on the reference current signal;

The control circuit 20 is used to control the working state of the current distribution array 10;

The first protection circuit 30 is used to protect the signal between the control circuit and the current distribution array.

In one embodiment, the current distribution array 10 includes M rows of transistor array blocks, and M is a natural number greater than or equal to 3. In the circuit layout, the M rows of transistor array blocks are distributed in an array; wherein, the first row of transistor array blocks 101 It can be a reference array block, and the second to Mth row transistor array blocks 102, ..., 10M can be used to duplicate the reference current signal generated by the reference array block to generate multiple external supply currents.

In this embodiment, the current distribution circuit includes a current distribution array 10, and the current distribution array 10 may include M rows of

transistor array blocks

101, 102, ..., 10M. In the circuit layout, M rows of transistor array blocks are distributed in an array. In addition, each row of transistor arrays may include N transistor array blocks, where N is a natural number; each transistor array block may include multiple transistors, and the multiple transistors may also be distributed in an array on the circuit layout.

In this embodiment, each transistor array block in the current distribution array 10 is laid out in an array of multiple rows and columns on the circuit layout, so that the structure of the current distribution array 10 is clear, the current ratio is clear, and if the circuit needs to make the current ratio When adjusting, adjusting the number of transistors, and adjusting the type of transistors, it is very convenient to change the layout of the circuit; at the same time, this layout layout of the circuit can save the wiring space and increase the layout space of each current channel on the circuit layout; and with the process level The gradual improvement of the gradual increase and the gradual decrease of the chip area, the current distribution array 10 in this embodiment can effectively avoid the limitation of layout area and increase the complexity of layout, while also avoiding the parasitic or The effect of coupling improves the performance of the circuit layout.

Since the current distribution array 10 in this embodiment can generate multiple channels of externally supplied current, a very large-scale current distribution circuit that provides one or more large currents and multiple small currents can be realized. Therefore, in order to adapt to a very large-scale current distribution circuit, this embodiment further provides a control circuit 20 for controlling the working state of the current distribution array 10.

In the circuit layout, the control circuit 20 may be disposed on one side of the current distribution array 10, and the control circuit 20 may be a current switch regulation circuit for controlling whether the current replication transistor in the current distribution array 10 works or not.

The control circuit 20 can control the working state of each transistor array block in the current distribution array, which is similar to a current switch, and is used to control the operation of each transistor array block. As shown in FIG. 2, the control circuit 20 can generate multiple control signals that, like the reference current signal, laterally penetrate each transistor array block in the current distribution array.

Since the current distribution array 10 in this embodiment can generate multi-channel externally supplied current, and the current distribution array 10 is controlled by the switch of the control circuit 10, it is provided to protect the signal between the control circuit 10 and the current distribution array 10 First protection circuit 30.

In some optional implementations, the control circuit 20 and the first protection circuit 30 may be located on the same side of the current distribution array 10, and form a neat and clear layout space with the current distribution array 10 on the entire circuit layout; for example, control The circuit 20 is located on the left side of the current distribution array 10, and the first protection circuit 30 is located between the control circuit 20 and the current distribution array 10.

In some optional implementations, the first protection circuit 30 may be a resistance-type protection circuit. The resistance-type protection circuit is composed of a resistor. The current-limiting function protects the closed-loop loop composed of the control circuit 20 and the current distribution array 10 . When external signals are injected into the loop, there are some risks, such as static electricity, hand touch, etc., which will break down the transistors that directly contact the external signals, thereby forming circuit damage. The resistance type protection circuit can limit the instantaneous large current in this case.

In some optional implementations, the first protection circuit 30 may include two resistance-type protection circuits, which are used to protect key nodes (eg, input and output terminals) of the circuit of the current distribution array 10 and key nodes of the control circuit 20 (Eg input and output).

In an embodiment, the output terminal of the control circuit 20 is connected to the input current base transistor of the current distribution array 10, that is, the transistor in the first row of the transistor array block. The output end of the input current base transistor returns to the input end of the control circuit through the resistance-type protection circuit, forming a closed loop. When the environment changes, causing the input signal of the current distribution array 10 to drift, the closed-loop adjustment function of the operational amplifier in the control circuit works, so that the input signal and the output signal are automatically adjusted to the normal working state.

The embodiments of the present disclosure use a transistor array block distributed in an array to implement a current distribution circuit, and provide multiple external supply currents based on the reference current signal. At the same time, the current distribution array is controlled by the control circuit and can automatically adjust whether the current distribution array works In order to provide a stable multi-channel external current supply to the current distribution array, a first protection circuit is also provided to protect the signal between the control circuit and the current distribution array to be stable. In this way, the embodiments of the present disclosure can realize a large-scale current distribution circuit, and make the current output of the large-scale current distribution circuit controllable, and can ensure the stability of the circuit signal, providing current support for a very large-scale power module.

In some optional implementations, as shown in FIG. 2, the current distribution circuit 100 further includes a second protection circuit 40 for protecting the power supply voltage of the current distribution circuit 100.

The second protection circuit 40 may include a capacitive protection circuit, and the capacitive protection circuit is composed of a capacitor. When the external voltage of the power supply voltage supplies power to the current distribution circuit, the capacitive protection circuit is added between the external voltage source and the current distribution circuit. Through the voltage stabilizing characteristic of the capacitor, the current distribution circuit is guaranteed to have a stable voltage, and the capacitive protection circuit has one end Connected to the power supply, the capacitive protection circuit can be set in the center of the entire current distribution circuit in the circuit layout. The second protection circuit 40 also includes a power supply voltage protection circuit. By inserting a capacitor into the power supply network, the power supply voltage protection circuit absorbs or releases charge when the power supply voltage rises or falls to a degree that affects the circuit function, and partially offsets the voltage fluctuations. The influence of internal circuits. The power supply voltage protection circuit includes two ends connected to the power supply and the ground respectively.

In this optional implementation manner, the second protection circuit 40 may be located in the upper area of the control circuit 20 on the circuit layout. Since the area of the current distribution array 10 on the circuit layout is larger than that of the control circuit 20, when the control circuit 20 is located on one side of the current distribution array 10 and is aligned with the middle of the current distribution array, a second protection circuit 40 can also be provided in the area above it , So that the layout of the entire circuit layout is clear and tidy.

In some optional implementations, as shown in FIG. 2, the current distribution circuit 100 further includes a third protection circuit 50, and the third protection circuit 50 is used to protect the signal between the current distribution circuit 100 and an external module node.

In this optional implementation, the third protection circuit 50 may be a hybrid protection circuit composed of a resistance type protection circuit and a capacitance type protection circuit, which is used to protect the signal node, such as current, between the current distribution circuit 100 and an external module The distribution circuit 100 outputs a signal to the output terminal of the external module, and an input terminal that receives the signal from the external module.

In an alternative implementation, the third protection circuit 50 may be located under the control circuit 20 on the circuit layout.

In some optional implementations, as shown in FIG. 2, the current distribution circuit 100 further includes a fourth protection circuit 60, and the fourth protection circuit is a diode-type protection circuit, which prevents the current distribution through a diode breakdown method The instantaneous voltage at critical nodes on the circuit is too large or too small. The high-voltage threshold and the low-voltage threshold can also be determined according to requirements, and the matched diode-type protection circuit can be determined according to the high-voltage threshold and the low-voltage threshold.

In this optional implementation, the key nodes on the current distribution circuit may include, but are not limited to, the current distribution array 10, the signal input terminal and the signal output terminal on the control circuit 20, and also include the signal between the current distribution circuit and the external module Node; the fourth protection circuit 60 is composed of a diode, which prevents the instantaneous voltage at the critical node on the current distribution circuit from being too large or too small by diode breakdown. The instantaneous voltage at the protected critical node is too large or too small, through the diode Breakdown to offset and compensate the voltage at the protected critical node.

In an alternative implementation, the fourth protection circuit 50 may be located below the first protection circuit 30 on the circuit layout.

Since the current distribution array 10 includes thousands of transistors, it occupies a large area on the circuit layout, and the control circuit 20, the first protection circuit 30, the second protection circuit 40, the third protection circuit 50, and the fourth protection circuit All of the 60 can be located on one side of the current distribution array 10, and form a neat layout, as far as possible to make the entire circuit layout rational use of the entire circuit board, to avoid wasting circuit board area.

FIG. 3 shows a schematic diagram of a circuit layout of an implementation manner of the current distribution circuit 100 in the embodiment of the present disclosure. As shown in FIG. 3, the first protection circuit 30 includes two resistance-type protection circuits, located between the control circuit 20 and the current distribution array 10, and is used to include the signal problem between the control circuit 20 and the current distribution array 10; The protection circuit 40 includes three power supply voltage stabilizing circuits for stabilizing the power supply voltage of the entire circuit; the second protection circuit 40 also includes a capacitive protection circuit located between the control circuit 20 and the current distribution array 10 (since it is a current The distribution circuit is closer to the center), used to protect the stability of the power supply voltage; the third protection circuit 50 includes a hybrid protection circuit, located in the area below the control circuit 20, for protecting the input end of the control circuit to be stable; It includes a diode-type protection circuit, which is located between the third protection circuit 50 and the current distribution array 10, and is used to maintain the voltage stability of key nodes on the entire circuit. Because there are multiple current paths in the large-scale current distribution circuit. How to optimize the current path, reduce parasitic and coupling, how to achieve optimal matching between the tubes, and an effective and area-saving layout are new problems encountered in the layout design of large-scale current distribution circuits. When the number of transistors in a traditional current mirror increases hundreds of times, these problems will be very serious. Need to redesign the layout structure to solve these problems.

Therefore, the embodiment of the present disclosure proposes a solution of the above current distribution circuit 100, in which the current distribution array can not only provide one or more large currents and nearly one hundred small currents, but also make the whole distributed through the array. The layout structure of the circuit is clear, which can avoid the layout area limitation and increase the layout complexity.

The layout layout design of the current distribution array proposed by the present disclosure is described below through specific implementations.

In some optional implementations, as shown in FIG. 1, the current distribution array includes M rows of transistor array blocks, M is a natural number greater than or equal to 3; wherein the M rows of transistor array blocks include A region, a second region, and a third region, the first region includes a first row transistor array block 101, the first row transistor array block is a reference array block, and the second region includes a second row to the Mth -1 row transistor array block 102, ... 10 (M-1), the second row to the M-1 row transistor array block is used to copy the reference current signal generated by the reference array block and output at least one way For the first external current supply, the third area includes the Mth row transistor array block 10M, which is used to replicate the reference current signal generated by the reference array block and output at least one second external current supply.

In this optional implementation, the first row transistor array block 101 is a reference array block, which is used to provide a reference current signal for the second row to the Mth row of transistor array blocks 102, ..., 10M, and the second row to the Mth Each row in the row transistor array block 102, ..., 10M is copied to generate an external supply current based on the reference current signal generated by the reference current block, and the magnitude of the external supply current generated by each row of the transistor array block is the same as that in the row transistor array block The number of transistors, the type of transistors, the setting of transistors, etc. are related, and the external supply current is proportional to the reference current. The magnitude of the external supply current generated by each row of transistor arrays can be the same or different, and the direction of the external supply current generated by each row of transistor array blocks is along the row direction of the row of transistor arrays, that is, each external supply current penetrates laterally Corresponding row of transistor array blocks.

In some optional implementations, the current distribution array 10 can be divided into three regions in units of rows, which are: a first region including the first row transistor array block 101, and a second row to the M-1 row transistor The second area of the array block includes the third area of the Mth row of transistor array blocks.

The first row of transistor array blocks 101 is used to generate a reference current signal. The first partial transistor array block may include one or more rows of transistor array blocks, and each row of transistor array blocks provides a horizontal first external current supply path. The external current supply runs horizontally through the row of transistor array blocks, and when wiring for each row of transistor array blocks, only one line needs to be used laterally as the line for external current supply; and in the layout design of the related art, each horizontal row The transistor is composed of transistors working in multiple current paths. Each transistor in the current path needs to have a line, and a row of transistors needs to use multiple lines. Therefore, the embodiments of the present disclosure Compared with the related art, the use of wire channels is greatly saved, the distance between channels is increased, and the problems of parasitic and coupling between channels are avoided.

The second area may include one or more rows of transistor array blocks, each row of transistor array blocks may generate one horizontal external supply current, and the multiple external supply currents generated by multiple rows of transistor array blocks in the second area eventually converge into at least one path The large current, that is, the first external supply current, is provided to an external module for use by a very large-scale power module.

The third area may include one or more rows of transistor array blocks, and each column in the third area may provide a longitudinal small current, that is, a second external current, similar to the lateral first external current, the vertical The two externally supplied currents vertically penetrate the column of transistor array blocks, and only one vertical line is required for each second externally supplied current. In some embodiments, since the transistor array block in the third area is located at the edge of the current distribution array, the second external current generated in the vertical direction can penetrate the column of transistor array blocks and extend to the outside of the current distribution array An external supply current forms a cross, which can make the whole circuit structure clear and effectively avoid the influence of many parasitic and coupling.

In some embodiments, the second region includes transistor array blocks 102, 103, ..., 10M-1 from the second to the M-1th row, and the third region includes transistor array block 10M of the Mth row. In this embodiment, the third area includes only the row of transistor array blocks on the outermost side, so that multiple second external supply currents can be provided longitudinally. Through the design of wiring and transistors, the current value of the first externally supplied current is much larger than the current value of the second externally supplied current. At this time, the current distribution array 10 can provide one or more externally supplied large currents and multiple externally supplied small currents. Used by each module of the electronic device.

In an alternative implementation, the first external supply current is a horizontal current on the circuit layout, the second external supply current is a vertical current on the circuit layout, and the first external supply current The current value is greater than the current value of the second external supply current.

In some optional implementation manners, the first external current and the second external current are provided to different external modules respectively.

Since the current value of the first externally supplied current is much greater than the current value of the first externally supplied current, the first externally supplied current and the second externally supplied current can be provided to the actual power consumption of each external module on the electronic device Different external modules are used.

FIG. 4 shows a schematic diagram of the signal flow direction of the transistor array block in the second area. As shown in FIG. 4, the transistors in the transistor array block of the second region are responsible for providing multiple first external supply currents with larger current values. In this exemplary embodiment, each first external supply current uses two lines Daolai serves as the first external current supply channel. The transistors in the transistor array block of the second area also receive the control signal from the control circuit 10 and the reference current signal of the reference array block, and the power / ground network supplies power to the transistors in the transistor array block of the second area.

FIG. 5 shows a schematic diagram of signal flow of the transistor array block in the third area. As shown in FIG. 5, the transistors in the transistor array block of the third region are responsible for providing multiple second external supply currents with smaller current values, and each channel of the second external supply current uses a line to flow as the second external power supply. Road. The transistors in the transistor array block of the third region also receive the control signal from the control circuit 10 and the reference current signal of the reference array block, and the power / ground network supplies power to the transistors in the second partial transistor array block.

In some optional embodiments, the current distribution array 10 includes multiple rows of transistor array blocks, each row of transistor array blocks includes multiple transistor array blocks, and each transistor array block includes multiple transistors distributed in an array, and each The transistor array block has a rectangular shape in the wiring space. In one embodiment, the transistor array block has an approximately square shape.

The setting of the number of transistors in the current distribution array 10 is set based on the actual demand for the current provided by the current distribution circuit. How much current needs to be provided determines how many transistors need to be used, and the number of transistors in each current path can be After constructing the circuit architecture, it is determined through simulation experiments.

In some optional implementation manners, among the M rows of transistor array blocks, transistor array blocks of different rows are independent of each other in circuit layout.

In this optional implementation, the transistors on each externally supplied current output branch, such as the transistors on each row of transistor array blocks in the second part of the transistor array block, are independent of the transistors on other externally supplied current output branches. The transistors on the output branches of different external supply circuits are not staggered. Therefore, the distribution of the current supply circuit corresponding to each external current channel is also independent, and there is no staggered distribution.

The number of externally supplied current paths of the current distribution array designed in the embodiments of the present disclosure may be large, and the distribution on the corresponding layout is independent of each other, and does not interfere with each other, which can easily identify each externally supplied current channel and each channel in the layout The ratio of current supplied outside the road is also easy to distinguish and calculate.

In some optional implementation manners, each transistor array block in the M-row array distributed transistor array block includes an output current transistor and / or an auxiliary transistor.

In this optional implementation, each transistor array block in each row of transistor array blocks can be provided with an output current transistor and / or an auxiliary transistor, so that the output current transistor and / or auxiliary transistor can replicate the reference current signal and generate a reference current The signal is proportional to the external supply current. The output current transistors and auxiliary transistors on the external power supply circulation paths also occupy an array, and are not staggered. In this way, when modifying the current value, output current transistor, and auxiliary transistor of a certain external current path, it is much more convenient than the prior art layout. In the prior art, several paths are mixed and distributed in an array, or the output current transistor and the auxiliary transistor are cross-distributed, and it is troublesome to modify some transistors separately.

In some optional implementation manners, the current values of the first externally supplied current and the second externally supplied current are related to the output current transistor and / or the auxiliary transistor.

The magnitude of the external supply current is related to the output current transistor and the auxiliary transistor, and the magnitude of the external supply current of different external supply current paths can be adjusted by adjusting the number, type, and implementation of the output current transistor and / or the auxiliary transistor.

The embodiments of the present disclosure are based on a function expansion of the basic current mirror to realize the replication and multiplication of the current signal, and realize the current gain by copying the current of the input branch to the output branch. The output stage of the current distribution circuit provided by the embodiment of the present disclosure can provide nearly one hundred current paths to the outside, and the number of transistors required by the entire functional module is several thousand, so it can be called a large-scale current distribution circuit. The input end of the current distribution circuit provides a basic current source, which acts on the gates of all output transistors, respectively, thereby controlling the current output by the drain end of the output transistor. Among them, the current distribution circuit also contains some other transistors to ensure that the input transistor and the output transistor work in the specified working area. Thousands of output tubes of the current distribution circuit can be divided into transistor array blocks one by one according to the output current to be provided. The first row of transistor arrays in the current distribution array of the embodiments of the present disclosure serves as a basic current source provided at an input terminal, and the transistors in other rows of transistor array blocks serve as output transistors.

6 is a schematic structural diagram of a storage device according to an embodiment of the present disclosure. As shown in FIG. 6, the storage device 200 of the embodiment of the present disclosure includes the current distribution circuit 100 of any of the foregoing embodiments.

Alternatively, the storage device in the present disclosure may use the current distribution circuit 100 to provide different currents to the various modules on the storage device, for example, the storage device may be a DDR storage device.

Those skilled in the art should understand that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Moreover, the present disclosure may take the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

The present disclosure is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each flow and / or block in the flowchart and / or block diagram and a combination of the flow and / or block in the flowchart and / or block diagram may be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, special-purpose computer, embedded processing machine, or other programmable data processing device to produce a machine that enables the generation of instructions executed by the processor of the computer or other programmable data processing device An apparatus for realizing the functions specified in one block or multiple blocks of one flow or multiple flows of a flowchart and / or one block or multiple blocks of a block diagram.

These computer program instructions may also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, the instructions The device implements the functions specified in one block or multiple blocks of the flowchart one flow or multiple flows and / or block diagrams.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operating steps are performed on the computer or other programmable device to produce computer-implemented processing, which is executed on the computer or other programmable device The instructions provide steps for implementing the functions specified in one block or multiple blocks of the flowchart one flow or multiple flows and / or block diagrams.

This disclosure uses specific examples to explain the principles and implementations of this disclosure. The descriptions of the above examples are only used to help understand the methods and core ideas of this disclosure; meanwhile, for those of ordinary skill in the art, based on this The disclosed ideas are subject to change in specific implementation and application scope. In summary, the content of this specification should not be construed as limiting the disclosure.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, but not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features thereof may be equivalently replaced; and these modifications or replacements do not deviate from the essence of the corresponding technical solutions of the technical solutions of the embodiments of the present disclosure range.

Claims

A current distribution circuit is characterized by comprising: a current distribution array and a first protection circuit of a control circuit; wherein,

The current distribution array includes transistor array blocks distributed in the array, and generates multiple externally supplied currents based on the reference current signal;

The control circuit is used to control the working state of the current distribution array;

The first protection circuit is used to protect the signal between the control circuit and the current distribution array.
The current distribution circuit according to claim 1, further comprising: a second protection circuit; wherein,

The second protection circuit is used to protect the power supply voltage of the current distribution circuit.
The current distribution circuit according to claim 2, wherein the second protection circuit includes a capacitive protection circuit.
The current distribution circuit according to claim 1 or 2, further comprising: a third protection circuit; wherein,

The third protection circuit is used to protect the signal node between the current distribution circuit and the external module.
The current distribution circuit according to claim 4, wherein the third protection circuit includes a resistance type protection circuit and a capacitance type protection circuit.
The current distribution circuit according to claim 1 or 2, further comprising: a fourth protection circuit;

The fourth protection circuit is used to prevent the instantaneous voltage at a critical node on the current distribution circuit from being higher than a high voltage threshold or lower than a low voltage threshold.
The current distribution circuit according to claim 6, wherein the fourth protection circuit is a diode-type protection circuit, and the instantaneous voltage at a critical node on the current distribution circuit is prevented from being higher than a high voltage threshold through a diode breakdown method Or below the low pressure threshold.
The current distribution circuit according to claim 1 or 2, wherein the current distribution array includes M rows of transistor array blocks, M is a natural number greater than or equal to 3; wherein the M rows of transistor array blocks are on the circuit layout It includes a first region, a second region, and a third region. The first region includes a first row of transistor array blocks, the first row of transistor array blocks is a reference array block, and the second region includes second to third rows M-1 row transistor array block, the second row to the M-1th row transistor array block is used to copy the reference current signal generated by the reference array block and output at least one first external supply current, the first The three regions include the Mth row transistor array block, which is used to copy the reference current signal generated by the reference array block and output at least one second external supply current.
The current distribution circuit according to claim 8, wherein the first externally supplied current is a horizontal current on a circuit layout, and the second externally supplied current is a vertical current on a circuit layout, and the The current value of the first externally supplied current is greater than the current value of the second externally supplied current.
The current distribution circuit according to claim 9, wherein the first external current and the second external current are provided to different external modules respectively.
The current distribution circuit according to any one of claims 1-2, 9-10, wherein each of the transistor array blocks includes a plurality of transistors distributed in an array, and the plurality of transistors are arranged to form a rectangular shape.
The current distribution circuit according to claim 8, wherein in the M rows of transistor array blocks, transistor array blocks of different rows are independent of each other in circuit layout.
The current distribution circuit according to claim 8, wherein each transistor array block in the M-row array distributed transistor array block includes an output current transistor and / or an auxiliary transistor.
The current distribution circuit according to claim 8, wherein the current values of the first externally supplied current and the second externally supplied current are related to the output current transistor and / or the auxiliary transistor.
A storage device, characterized by comprising the current distribution circuit according to any one of claims 1-14.