CN112805656A

CN112805656A - Current distribution circuit and storage device

Info

Publication number: CN112805656A
Application number: CN201880098328.8A
Authority: CN
Inventors: 王锐
Original assignee: Bitmain Technologies Inc
Current assignee: Bitmain Technologies Inc
Priority date: 2018-11-15
Filing date: 2018-11-15
Publication date: 2021-05-14
Anticipated expiration: 2038-11-15
Also published as: CN112805656B; WO2020097870A1

Abstract

A current distribution circuit and a memory device are provided. The current distribution circuit includes: a current distribution array (10), a control circuit (20) and a first protection circuit (30); wherein the current distribution array (10) comprises transistor array blocks distributed in an array, and generates a plurality of external supply currents based on a reference current signal; the control circuit (20) is used for controlling the working state of the current distribution array (10); the first protection circuit (30) is used for protecting signals between the control circuit (20) and the current distribution array (10), so that a large-scale current distribution circuit can be realized, the current output of the large-scale current distribution circuit is controllable, the circuit signals can be ensured to be stable, and available current is provided for an ultra-large-scale power utilization module.

Description

Current distribution circuit and storage device

Technical Field

The present disclosure relates to integrated circuit power supply technology, and more particularly, to a current distribution circuit and a memory device,

Background

DDR (double Data Rate) is double Data Rate synchronous dynamic random Access memory. The current distribution circuit is one of the important parts of the DDR memory and provides stable currents with fixed proportion for each submodule. The design of the current distribution circuit is particularly important because it determines the overall performance and stability of the DDR. The current distribution circuit in the existing DDR adopts a standard current mirror structure. The circuit function amplifies the input reference current by a desired multiple, and then outputs the desired currents.

Disclosure of Invention

The embodiment of the disclosure provides a current distribution circuit and a storage device, so as to solve the problems caused by the stability of the current distribution circuit and the enlargement of the circuit scale in the prior art.

In a first aspect, an embodiment of the present disclosure provides a current distribution circuit, including: the protection circuit comprises a current distribution array, a control circuit and a first protection circuit; wherein the content of the first and second substances,

the current distribution array comprises transistor array blocks distributed in an array manner, and generates a plurality of paths of external supply currents based on a reference current signal;

the control circuit is used for controlling the working state of the current distribution array;

the first protection circuit is used for protecting signals between the control circuit and the current distribution array.

Further, the current distribution circuit further includes: a second protection circuit; wherein the content of the first and second substances,

the second protection circuit is used for protecting the power supply voltage of the current distribution circuit.

Further, the second protection circuit includes a capacitance type protection circuit.

Further, the current distribution circuit further includes: a third protection circuit; wherein the content of the first and second substances,

the third protection circuit is used for protecting a signal node between the current distribution circuit and an external module.

The third protection circuit comprises a resistance type protection circuit and a capacitance type protection circuit.

Further, the current distribution circuit further includes: a fourth protection circuit;

further, the fourth protection circuit is configured to prevent the instantaneous voltage at the key node on the current distribution circuit from being above the high voltage threshold or below the low voltage threshold.

The fourth protection circuit is a diode type protection circuit, and instantaneous voltage at a key node on the current distribution circuit is prevented from being higher than a high-voltage threshold or lower than a low-voltage threshold in a diode breakdown mode.

Further, the current distribution array comprises M rows of transistor array blocks, wherein M is a natural number greater than or equal to 3; the M-row transistor array block comprises a first area, a second area and a third area on the circuit layout, the first area comprises a first row of transistor array blocks, the first row of transistor array blocks are reference array blocks, the second area comprises a second row to an M-1-th row of transistor array blocks, the second row to the M-1-th row of transistor array blocks are used for copying the reference current signals generated by the reference array blocks and outputting at least one path of first external supply current, and the third area comprises an M-row transistor array block and is used for copying the reference current signals generated by the reference array blocks and outputting at least one path of second external supply current.

Further, the first external current is a transverse current on the circuit layout, the second external current is a longitudinal current on the circuit layout, and the current value of the first external current is greater than that of the second external current.

Further, the first external supply current and the second external supply current are respectively provided for different external modules.

Further, each transistor array block includes a plurality of transistors distributed in an array, and the plurality of transistors are arranged to form a rectangular shape.

Furthermore, in the M rows of transistor array blocks, the transistor array blocks in different rows are independent from each other in circuit layout.

Further, each transistor array block in the transistor array blocks distributed in the M rows comprises an output current transistor and/or an auxiliary transistor.

Further, the magnitude of the current value of the first external supply current and the second external supply current is related to the output current transistor and/or the auxiliary transistor.

In a second aspect, an embodiment of the present disclosure provides a memory device, including the current distribution circuit according to any one of the optional implementations of the first aspect.

The embodiment of the disclosure realizes the current distribution circuit by using the transistor array blocks distributed in an array, provides multiple paths of external supply currents based on the reference current signal, and the current distribution array is controlled by the control circuit to automatically adjust whether the current distribution array works or not. According to the embodiment of the disclosure, a large-scale current distribution circuit can be realized in such a way, the current output of the large-scale current distribution circuit is controllable, the circuit signal stability can be ensured, and the available current is provided for the ultra-large-scale power utilization module.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present disclosure, and it is also possible for those skilled in the art to obtain other drawings based on the drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of a current distribution circuit 100 according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a current distribution circuit 100 according to another embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a preferred circuit layout of the current distribution circuit 100 according to an embodiment of the present disclosure;

fig. 4 is a signal flow schematic diagram of a first partial transistor array block of an embodiment of the present disclosure;

fig. 5 is a signal flow schematic diagram of a second partial transistor array block according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a storage device 200 according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below in detail and completely with reference to the accompanying drawings in the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

As will be appreciated by one skilled in the art, embodiments of the present disclosure may be embodied as a system, apparatus, device, method, or computer program product. Accordingly, the present disclosure may be embodied in the form of: entirely hardware, entirely software (including firmware, resident software, micro-code, etc.), or a combination of hardware and software.

When the current distribution circuit in the related art provides a large-scale current source current path, the requirement on the stability of multiple current sources is high due to surrounding modules of the current distribution circuit, and the self-adaptation condition of the traditional current mirror when environmental disturbance occurs is insufficient to meet the system requirement, which is a problem to be solved urgently by the design of the current distribution circuit in the DDR circuit. Accordingly, the present disclosure provides a current distribution circuit adapted to distribute a stable current to surrounding modules while providing a large-scale current source current path. Fig. 1 is a schematic structural diagram of a current distribution circuit 100 according to an embodiment of the present disclosure. As shown in fig. 1, a current distribution circuit 100 of an embodiment of the present disclosure includes: a current distribution array 10, a control circuit 20, and a first protection circuit 30; wherein the content of the first and second substances,

the current distribution array 10 includes transistor array blocks distributed in an array, and the current distribution array 10 is capable of generating multiple external supply currents based on a reference current signal;

the control circuit 20 is used for controlling the working state of the current distribution array 10;

a first protection circuit 30 is used to protect the signals between the control circuit and the current distribution array.

In one embodiment, the current distribution array 10 includes M rows of transistor array blocks, where M is a natural number greater than or equal to 3, and the M rows of transistor array blocks are distributed in an array on the circuit layout; the first row transistor array block 101 may be a reference array block, and the second row to mth row transistor array blocks 102, … …, and 10M may be configured to copy a reference current signal generated by the reference array block to generate multiple external supply currents.

In this embodiment, the current distribution circuit includes a current distribution array 10, the current distribution array 10 may include M rows of

transistor array blocks

101, 102, … …, and 10M, and in the circuit layout, the M rows of transistor array blocks are distributed in an array, and each row of transistor array may include N transistor array blocks, where N is a natural number; each transistor array block may include a plurality of transistors, and the plurality of transistors may also be distributed in an array on the circuit layout.

In this embodiment, each transistor array block in the current distribution array 10 is laid out in a circuit layout in an array form of multiple rows and multiple columns, so that the structure of the current distribution array 10 is clear, the current proportion is clear, and meanwhile, if the circuit needs to make current proportion adjustment, transistor quantity adjustment and transistor type adjustment, the circuit layout is very convenient to change; meanwhile, the layout mode of the circuit layout can save the line space and increase the layout space of each current channel on the circuit layout; with the improvement trend of gradually increasing the process level and gradually decreasing the chip area, the current distribution array 10 in this embodiment can effectively avoid the increase of the layout complexity due to the limitation of the layout area, and simultaneously avoid the parasitic or coupling influence caused by too compact wiring, thereby improving the performance of the circuit layout.

Since the current distribution array 10 in this embodiment can generate multi-path external supply current, an ultra-large scale current distribution circuit that provides one or more paths of large current and multiple paths of small current can be implemented. Therefore, in order to accommodate the ultra-large scale current distribution circuit, the present embodiment is further provided with a control circuit 20 for controlling the operation state of the current distribution array 10.

In the circuit layout, the control circuit 20 may be disposed at one side of the current distribution array 10, and the control circuit 20 may be a current switch regulating circuit for controlling whether the current replica transistor in the current distribution array 10 operates or not.

The control circuit 20 may control the operation state of each transistor array block in the current distribution array, which is similar to a current switch, for controlling the operation or non-operation of each transistor array block. As shown in fig. 2, control circuit 20 may generate multiple control signals that traverse each transistor array block in the current distribution array as the reference current signal.

Since the current distribution array 10 in this embodiment is capable of generating a multi-channel external supply current, and the current distribution array 10 is controlled by the switches of the control circuit 10, the first protection circuit 30 is provided for protecting signals between the control circuit 10 and the current distribution array 10.

In some alternative implementations, the control circuit 20 and the first protection circuit 30 may be located on the same side of the current distribution array 10, and form a neat and clear layout space with the current distribution array 10 on the whole circuit layout; for example, the control circuit 20 is located on the left side of the current distribution array 10, and the first protection circuit 30 is located between the control circuit 20 and the current distribution array 10.

In some alternative implementations, the first protection circuit 30 may be a resistor-type protection circuit, and the resistor-type protection circuit is composed of resistors, and protects a closed loop formed by the control circuit 20 and the current distribution array 10 by current limiting. When an external signal is injected into the loop, there is a risk that a transistor directly contacting the external signal is broken down, thereby causing circuit damage, such as static electricity, hand touch, and the like. And the resistance type protection circuit can play a role in limiting the instantaneous large current in the situation.

In some alternative implementations, the first protection circuit 30 may include two resistor-type protection circuits for protecting critical circuit nodes (e.g., input and output terminals) of the current distribution array 10 and critical circuit nodes (e.g., input and output terminals) of the control circuit 20, respectively.

In one embodiment, the output terminal of the control circuit 20 is connected to the input current base transistor of the current distribution array 10, i.e., the transistor in the first row of transistor array block. The output end of the input current basic transistor returns to the input end of the control circuit through the resistance type protection circuit to form a closed loop. When the environment changes and the input signal of the current distribution array 10 drifts, the closed loop adjusting function of the operational amplifier in the control circuit plays a role, so that the input signal and the output signal are automatically adjusted to the normal working state.

The embodiment of the disclosure realizes the current distribution circuit by using the transistor array blocks distributed in an array, provides multiple paths of external supply currents based on the reference current signal, and the current distribution array is controlled by the control circuit to automatically adjust whether the current distribution array works or not. According to the embodiment of the disclosure, a large-scale current distribution circuit can be realized in such a way, the current output of the large-scale current distribution circuit is controllable, the circuit signal stability can be ensured, and the current support is provided for the ultra-large-scale power utilization module.

In some alternative implementations, as shown in fig. 2, the current distribution circuit 100 further includes a second protection circuit 40 for protecting the supply voltage of the current distribution circuit 100.

The second protection circuit 40 may include a capacitive type protection circuit, which is composed of a capacitor. When the external voltage of the power supply voltage supplies power to the current distribution circuit, the capacitive type protection circuit is added between the external voltage source and the current distribution circuit, the current distribution circuit is guaranteed to have stable voltage through the voltage stabilization characteristic of the capacitor, one end of the capacitive type protection circuit is connected out and used for being connected with the power supply, and the capacitive type protection circuit can be arranged at the position, close to the center, of the whole current distribution circuit in the circuit layout. The second protection circuit 40 further includes a power supply voltage protection circuit that adsorbs or releases electric charges when the power supply voltage rises or falls to such an extent that the circuit function is affected by inserting a capacitor into the power supply network, to partially cancel the effect of voltage fluctuation on the internal circuit. The power supply voltage protection circuit comprises two ends which are connected with a power supply and a ground respectively.

In this alternative implementation, the second protection circuit 40 may be located in an upper region of the control circuit 20 on the circuit layout. Because the area of the current distribution array 10 on the circuit layout is larger than that of the control circuit 20, when the control circuit 20 is located at one side of the current distribution array 10 and aligned with the middle of the current distribution array, the second protection circuit 40 can be further arranged in the area above the control circuit 20, so that the whole circuit layout is clear and tidy.

In some optional implementations, as shown in fig. 2, the current distribution circuit 100 further includes a third protection circuit 50, and the third protection circuit 50 is used for protecting a signal node between the current distribution circuit 100 and an external module.

In this alternative implementation, the third protection circuit 50 may be a hybrid protection circuit composed of a resistive protection circuit and a capacitive protection circuit, and is used for protecting signal nodes between the current distribution circuit 100 and the external module, such as an output terminal of the current distribution circuit 100 outputting signals to the external module, an input terminal receiving signals from the external module, and the like.

In an alternative implementation, the third protection circuit 50 may be located below the control circuit 20 on the circuit layout.

In some optional implementations, as shown in fig. 2, the current distribution circuit 100 further includes a fourth protection circuit 60, which is a diode-type protection circuit, and prevents the transient voltage at the key node on the current distribution circuit from being too large or too small through a diode breakdown manner. And a high-voltage threshold and a low-voltage threshold can be determined according to requirements, and a matched diode type protection circuit can be determined according to the high-voltage threshold and the low-voltage threshold.

In this alternative implementation, the key nodes on the current distribution circuit may include, but are not limited to, the current distribution array 10, the signal input terminal and the signal output terminal on the control circuit 20, and further include a signal node between the current distribution circuit and an external module; the fourth protection circuit 60 is formed by a diode, and avoids the transient voltage at the key node on the current distribution circuit from being too large or too small in a diode breakdown mode, and when the transient voltage of the protected key node is too large or too small, the voltage at the protected key node is offset and compensated through diode breakdown.

In an alternative implementation, the fourth protection circuit 50 may be located below the first protection circuit 30 on the circuit layout.

The current distribution array 10 includes thousands of transistors, so the occupied area on the circuit layout is large, and the control circuit 20, the first protection circuit 30, the second protection circuit 40, the third protection circuit 50 and the fourth protection circuit 60 can all be located at one side of the current distribution array 10, and form a neat layout, so that the whole circuit board is reasonably utilized in the whole circuit layout mode as much as possible, and the area of the circuit board is prevented from being wasted.

Fig. 3 shows a circuit layout schematic diagram of an implementation of the current distribution circuit 100 in the embodiment of the present disclosure. As shown in fig. 3, the first protection circuit 30 includes two resistance type protection circuits, which are located between the control circuit 20 and the current distribution array 10, for including a signal problem between the control circuit 20 and the current distribution array 10; the second protection circuit 40 includes three power supply voltage stabilizing circuits for stabilizing the power supply voltage of the whole circuit; the second protection circuit 40 further includes a capacitive protection circuit, located between the control circuit 20 and the current distribution array 10 (since this is the more central location of the current distribution circuit), for protecting the supply voltage from settling; the third protection circuit 50 includes a hybrid protection circuit, which is located in the area below the control circuit 20 and is used for protecting the input end of the control circuit from being stable; the fourth protection circuit 60 includes a diode type protection circuit, and is located between the third protection circuit 50 and the current distribution array 10, for keeping the voltage of the key node stable throughout the circuit. Because of the multiple current paths in the large-scale current distribution circuit. How to optimize the current path, reduce the parasitic coupling, how to realize the optimal matching between the tubes, and effectively and save the layout of the area is a new problem encountered in the layout design of the large-scale current distribution circuit. These problems are exacerbated when the number of transistors in a conventional current mirror is increased by a factor of several hundred. The layout structure needs to be redesigned to solve the problems.

Therefore, the embodiment of the present disclosure provides a solution for the current distribution circuit 100, in which not only one or multiple paths of large currents and nearly one hundred paths of small currents can be provided through the current distribution array, but also the layout structure of the whole circuit is clear through the array distribution mode, and the increase of layout complexity due to the limitation of layout area can be avoided.

The layout design of the current distribution array proposed by the present disclosure is described below by way of specific embodiments.

In some alternative implementations, as shown in fig. 1, the current distribution array includes M rows of transistor array blocks, M being a natural number greater than or equal to 3; the M-row transistor array block comprises a first area, a second area and a third area on the circuit layout, the first area comprises a first row of transistor array blocks 101, the first row of transistor array blocks are reference array blocks, the second area comprises second row to M-1-th row of transistor array blocks 102 and … … 10(M-1), the second row to M-1-th row of transistor array blocks are used for copying the reference current signals generated by the reference array blocks and outputting at least one path of first external supply current, and the third area comprises an M-th row of transistor array blocks 10M and is used for copying the reference current signals generated by the reference array blocks and outputting at least one path of second external supply current.

In this optional implementation manner, the first row of transistor array blocks 101 is a reference array block and is configured to provide a reference current signal for the second to mth row of transistor array blocks 102, … …, 10M, each row of the second to mth row of transistor array blocks 102, … …, 10M is copied based on the reference current signal generated by the reference current block to generate an external supply current, the size of the external supply current generated by each row of transistor array blocks is related to the number of transistors, the types of transistors, the arrangement of transistors, and the like arranged in the row of transistor array blocks, and the external supply current and the reference current are in a proportional relationship. The external current generated by each row of transistor array may be the same or different in magnitude, and the direction of the external current generated by each row of transistor array block is along the row direction of the row of transistor array, that is, each external current transversely penetrates through the corresponding row of transistor array block.

In some alternative implementations, the current distribution array 10 may be divided into three regions in units of rows, respectively: a first region including a first row of transistor array blocks 101, a second region including a second row through an M-1 th row of transistor array blocks, and a third region including an M-th row of transistor array blocks.

The first row of transistor array blocks 101 are configured to generate a reference current signal, the first part of the transistor array blocks may include one or more rows of transistor array blocks, each row of transistor array block provides a first external current supply path in a transverse direction, each external current supply path transversely penetrates through the row of transistor array block, and when each row of transistor array block is wired, only one line channel needs to be transversely used as a line channel for external current supply; in the layout design of the related art, each horizontal transistor is composed of transistor tubes working in a plurality of current paths, one wire needs to be reserved for the transistor in each current path, and a plurality of wires need to be used for one row of transistors, so that compared with the related art, the embodiment of the disclosure greatly saves the use of the wires, increases the distance between channels, and avoids the problems of parasitic coupling between the channels.

The second region may include one or more rows of transistor array blocks, each row of transistor array block may generate a horizontal external supply current, and the multiple external supply currents generated by the multiple rows of transistor array blocks in the second region are finally converged into at least one path of large current, i.e., the first external supply current, and then are provided to an external module for use, which may be used by a super-large scale power module.

The third region may include one or more rows of transistor array blocks, and each column in the third region may provide a path of longitudinal small current, that is, a second external supply current, similar to the transverse first external supply current, the longitudinal second external supply current longitudinally penetrates through the column of transistor array blocks, and each path of second external supply current only uses one longitudinal line. In some embodiments, because the transistor array block in the third region is located at the edge of the current distribution array, the second external supply current generated longitudinally may penetrate through the column of transistor array blocks and extend to the outside of the current distribution array, and does not intersect with the first external supply current in the transverse direction, so that the whole circuit structure is clear, and many parasitic and coupling influences are effectively avoided.

In some embodiments, the second area includes a second row to an M-1 row of transistor array blocks 102, 103, … …, 10M-1, and the third area includes an M-th row of transistor array block 10M. In this embodiment, the third region includes only one row of transistor array blocks on the extreme side, so that multiple second external supply currents can be supplied longitudinally. Through the design of the wiring and the transistor, the current value of the first external supply current is much larger than that of the second external supply current, and at this time, the current distribution array 10 can provide one or more external supply large currents and multiple external supply small currents for each module of the electronic device.

In an optional implementation manner, the first external supply current is a transverse current on the circuit layout, the second external supply current is a longitudinal current on the circuit layout, and a current value of the first external supply current is greater than a current value of the second external supply current.

In some alternative implementations, the first external supply current and the second external supply current are provided separately for use by different external modules.

Because the current value of the first external supply current is far greater than that of the first external supply current, the first external supply current and the second external supply current can be provided for different external modules according to the actual power utilization condition of each external module on the electronic equipment.

Fig. 4 shows a signal flow diagram of the transistor array block in the second region. As shown in fig. 4, the transistors in the transistor array block in the second area are responsible for providing multiple paths of first external supply currents with larger current values, and in this exemplary embodiment, two lines are used for each path of first external supply current to serve as first external supply current channels. The transistors in the transistor array block of the second area also receive control signals from the control circuit 10 and reference current signals from the reference array block, and the power/ground network supplies power to the transistors in the transistor array block of the second area.

Fig. 5 shows a signal flow diagram of the transistor array block of the third region. As shown in fig. 5, the transistors in the transistor array block in the third area are responsible for providing multiple paths of second external power supply currents with smaller current values, and each path of second external power supply current uses one wire path as a second external power supply channel. The transistors in the transistor array block of the third area also receive control signals from the control circuit 10 and reference current signals from the reference array block, and the power/ground network supplies power to the transistors in the second partial transistor array block.

In some alternative embodiments, the current distribution array 10 includes a plurality of rows of transistor array blocks, each row of transistor array blocks including a plurality of transistor array blocks, each transistor array block including a plurality of transistors distributed in an array, and each transistor array block having a rectangular shape in a wiring space. In one embodiment, the transistor array block is approximately square in shape.

The number of transistors in the current distribution array 10 is set based on the actual demand for the current distribution circuit to supply current to the outside, how much current needs to be supplied, and how many transistors need to be used are determined, and the number of transistors in each current path can be determined through simulation experiments after the circuit architecture is constructed.

In some optional implementations, in the M rows of transistor array blocks, the transistor array blocks of different rows are independent from each other in circuit layout.

In this alternative implementation, the transistors in each external current supply output branch, for example, the transistors in each row of the transistor array block in the second partial transistor array block, are independent of the transistors in the other external current supply output branches. The transistors on the output branches of different external supply circuits are not distributed in a staggered mode. Therefore, the distribution of each external current supply channel in the layout corresponding to the current distribution circuit is also independent and not staggered.

The number of the external current supply channels of the current distribution array designed by the embodiment of the disclosure can be very large, the distribution on the corresponding layout is mutually independent and does not interfere with each other, and the external current supply channels of each path and the proportion of the external current supply of each path can be easily identified and calculated in the layout.

In some optional implementations, each of the transistor array blocks of the M rows of transistor array distribution includes an output current transistor and/or an auxiliary transistor.

In this alternative implementation, each transistor array block in each row of transistor array blocks may be provided with an output current transistor and/or an auxiliary transistor, such that the output current transistor and/or the auxiliary transistor can replicate the reference current signal and generate an external supply current proportional to the reference current signal. The output current transistors and the auxiliary transistors on the external current supply paths respectively occupy an array instead of being arranged in a staggered manner. Therefore, compared with the prior art, the layout is more convenient when the current value of a certain external supply current path, the output current transistor and the auxiliary transistor are modified. The prior art is troublesome when modifying some transistors individually because several paths are mixed and distributed in an array or output current transistors and auxiliary transistors are distributed in a cross way.

In some optional implementations, the magnitude of the current values of the first and second external supply currents is related to the output current transistor and/or the auxiliary transistor.

The magnitude of the external supply current is related to the output current transistor and the auxiliary transistor, and the magnitude of the external supply current of different external supply current paths can be adjusted by adjusting the number, the types, the implementation and the like of the output current transistor and/or the auxiliary transistor.

The embodiment of the disclosure realizes the duplication and multiplication of current signals based on one function expansion of a basic current mirror, and realizes the current gain by copying the current of an input branch to an output branch. The output stage of the current distribution circuit provided by the embodiment of the disclosure can provide hundreds of external current paths, and the number of transistors required by the whole functional module is thousands, so that the current distribution circuit can be called as a large-scale current distribution circuit. The input end of the current distribution circuit provides a basic current source which acts on the grids of all the output transistors respectively so as to control the current output by the drain ends of the output transistors. The current distribution circuit also comprises other transistors for ensuring that the input transistor and the output transistor work in a designated working area. Thousands of output tubes of the current distribution circuit may be divided into one transistor array block during layout according to the difference of output currents to be supplied. The first row transistor array in the current distribution array of the disclosed embodiments serves as the base current source provided at the input, while the transistors in the other row transistor array blocks serve as the output transistors.

Fig. 6 is a schematic structural diagram of a storage device according to an embodiment of the present disclosure. As shown in fig. 6, a memory device 200 of an embodiment of the present disclosure includes the current distribution circuit 100 of any of the foregoing embodiments.

Alternatively, the memory device in the present disclosure may use the current distribution circuit 100 to provide different currents to the respective modules on the memory device, for example, the memory device may be a DDR memory device.

As will be appreciated by one skilled in the art, embodiments of the present disclosure may be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.

The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The principle and the implementation mode of the present disclosure are explained by applying specific embodiments in the present disclosure, and the above description of the embodiments is only used to help understanding the method and the core idea of the present disclosure; meanwhile, for a person skilled in the art, based on the idea of the present disclosure, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present disclosure should not be construed as a limitation to the present disclosure.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present disclosure, and not for limiting the same; while the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present disclosure.

Claims

A current distribution circuit, comprising: the current distribution array and the first protection circuit of the control circuit; wherein the content of the first and second substances,

the current distribution array comprises transistor array blocks distributed in an array manner, and generates a plurality of paths of external supply currents based on a reference current signal;

the control circuit is used for controlling the working state of the current distribution array;

the first protection circuit is used for protecting signals between the control circuit and the current distribution array.
The current distribution circuit of claim 1, further comprising: a second protection circuit; wherein the content of the first and second substances,

the second protection circuit is used for protecting the power supply voltage of the current distribution circuit.
The current distribution circuit of claim 2, wherein the second protection circuit comprises a capacitive protection circuit.
The current distribution circuit according to claim 1 or 2, further comprising: a third protection circuit; wherein the content of the first and second substances,

the third protection circuit is used for protecting a signal node between the current distribution circuit and an external module.
The current distribution circuit of claim 4, wherein the third protection circuit comprises a resistive protection circuit, a capacitive protection circuit.
The current distribution circuit according to claim 1 or 2, further comprising: a fourth protection circuit;

the fourth protection circuit is used for preventing the instantaneous voltage at the key node on the current distribution circuit from being higher than a high-voltage threshold value or lower than a low-voltage threshold value.
The current sharing circuit of claim 6 wherein the fourth protection circuit is a diode type protection circuit that prevents the instantaneous voltage at the key node on the current sharing circuit from going above the high voltage threshold or below the low voltage threshold by way of diode breakdown.
The current distribution circuit according to claim 1 or 2, wherein the current distribution array includes M rows of transistor array blocks, M being a natural number equal to or greater than 3; the M-row transistor array block comprises a first area, a second area and a third area on the circuit layout, the first area comprises a first row of transistor array blocks, the first row of transistor array blocks are reference array blocks, the second area comprises a second row to an M-1-th row of transistor array blocks, the second row to the M-1-th row of transistor array blocks are used for copying the reference current signals generated by the reference array blocks and outputting at least one path of first external supply current, and the third area comprises an M-row transistor array block and is used for copying the reference current signals generated by the reference array blocks and outputting at least one path of second external supply current.
The current distribution circuit according to claim 8, wherein the first external supply current is a lateral current on a circuit layout, the second external supply current is a longitudinal current on the circuit layout, and a current value of the first external supply current is larger than a current value of the second external supply current.
The current distribution circuit of claim 9, wherein the first external supply current and the second external supply current are each provided for use by a different external module.
The current distribution circuit according to any one of claims 1-2 and 9-10, wherein each of the transistor array blocks includes a plurality of transistors distributed in an array, and the plurality of transistors are arranged to form a rectangular shape.
The current distribution circuit of claim 8, wherein transistor array blocks of different rows of the M rows of transistor array blocks are independent of each other in circuit layout.
The current distribution circuit of claim 8, wherein each of the M rows of transistor array distributed transistor array blocks includes an output current transistor and/or an auxiliary transistor.
The current distribution circuit of claim 8, wherein the first external supply current and the second external supply current have current values of magnitudes related to the output current transistor and/or the auxiliary transistor.
A memory device comprising a current distribution circuit according to any of claims 1-14.