WO2020087671A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2020087671A1
WO2020087671A1 PCT/CN2018/120509 CN2018120509W WO2020087671A1 WO 2020087671 A1 WO2020087671 A1 WO 2020087671A1 CN 2018120509 W CN2018120509 W CN 2018120509W WO 2020087671 A1 WO2020087671 A1 WO 2020087671A1
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WO
WIPO (PCT)
Prior art keywords
signal line
metal layer
source driver
chip
segment
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/120509
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English (en)
French (fr)
Inventor
何怀亮
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HKC Co Ltd
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HKC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd filed Critical HKC Co Ltd
Priority to US17/258,452 priority Critical patent/US11537013B2/en
Publication of WO2020087671A1 publication Critical patent/WO2020087671A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133305—Flexible substrates, e.g. plastics, organic film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • This application relates to the field of display technology, in particular to display panels and display devices.
  • liquid crystal display which include a liquid crystal panel and a backlight module.
  • the working principle of the liquid crystal panel is to place liquid crystal molecules in two parallel glass substrates, and apply a driving voltage on the two glass substrates to control the rotation direction of the liquid crystal molecules, so as to refract the light of the backlight module to generate a picture.
  • a thin film transistor liquid crystal display includes a liquid crystal panel and a backlight module.
  • the liquid crystal panel includes a color filter substrate (Color Filter Substrate, CF Substrate, also known as a color filter substrate), a thin film transistor array substrate (Thin Film Tran-sistor Substrate, TFT Substrate ) And a mask, there are transparent electrodes on the opposite inner side of the substrate.
  • a layer of liquid crystal molecules (Liquid Crystal, LC) is sandwiched between the two substrates. The display will cause poor bonding of the flexible circuit board, affecting the use of the display and people's viewing experience.
  • the purpose of the present application is to provide a display panel and a display device, so as to solve the problem that the flexible circuit board of the display is poorly attached, affects the use effect of the display, and people's viewing experience.
  • the signal line is symmetrically connected to two sets of the pins on the first side and the second side of the same source driver chip.
  • signal lines are dispersedly connected to the pins of at least two source driver chips.
  • the non-display area includes a metal layer, the metal layer includes a first metal layer and a second metal layer, the first metal layer includes a data line, and the first metal layer includes a first through hole And the second through hole, the signal line includes a second segment signal line, a third segment signal line, and a fourth segment signal line, the second segment signal line is disposed on the first metal layer, and the third segment signal The line is provided on the second metal layer, the fourth signal line is provided on the first metal layer, the second signal line is connected to the third signal line through the first via, and the third signal The line is connected to the fourth signal line through a second through hole, the first through hole and the second through hole are provided on the first metal layer, and are located on the first side of the corresponding position of the data line and On the second side, the other end of the fourth signal line is connected to the gate chip.
  • the non-display area includes a metal layer, the metal layer includes a first metal layer and an insulating layer, the insulating layer is disposed on the surface of the first metal layer, and the first metal layer includes a data line, The data line is provided on the surface of the first metal layer, the insulating layer covers the data line, the signal line is laid from above the insulating layer, and then connected to the gate chip.
  • the non-display area includes a metal layer, the metal layer includes a first metal layer and a second metal layer, the first metal layer includes a first through hole, and the first metal layer is provided with data Line, the signal line includes a second segment signal line and a third segment signal line, one end of the second segment signal line is connected to a pin, the third segment signal line is provided on the second metal layer, the first The other end of the second segment signal line is connected to one end of the third segment signal line through the first through hole, and the other end of the third segment signal line is connected to the gate chip.
  • the signal line is connected to the source driver chips at both ends of the first side.
  • the display panel includes a circuit board, there are two circuit boards, each of the circuit boards is connected with two of the flexible circuit boards, the non-display area includes a metal layer, and the metal layer includes A first metal layer and a second metal layer, the other end of the source driver chip is connected to the circuit board through the flexible circuit board, and the signal line includes a first segment signal line, a second segment signal line, a third Segment signal line and fourth segment signal line, the first segment signal line is set on the flexible circuit board, both ends are respectively connected to the circuit board and the source driver chip, and the second segment signal Two ends of the wire are respectively connected to the pins and the first metal layer, the third section signal line is provided on the second metal layer, and one end of the third section signal line is connected to the second section Signal lines are connected, the fourth section of signal line is provided on the first metal layer, one end of the fourth section of signal line is connected to the other end of the third section of signal line, and the other end of the fourth section of signal line Connected with the gate chip.
  • the present application also discloses a display panel including a substrate, a flexible circuit board, a source driver chip and a gate chip.
  • the substrate includes a display area and a non-display area, and a signal line is provided in the non-display area;
  • the flexible circuit board is connected to the substrate ;
  • the source driver chip is set on the flexible circuit board and connected to the substrate through the flexible circuit board;
  • the source driver chip includes two sets of pins, and the two sets of the pins are respectively located at the first of the same source driver chip Side and second side;
  • the gate chip is provided at the edge of the substrate, located at the first side and the second side of the source driver chip, and is connected to the substrate; the gate chip is connected to the signal line respectively On the pins of different groups;
  • the signal line is symmetrically connected to two sets of the pins on the first side and the second side of the same source driver chip;
  • the non-display area includes a metal layer, the metal layer includes a first metal layer and a second metal layer, the first metal layer includes a data line, and the first metal layer includes a first through hole and a second through hole ,
  • the signal line includes a second segment signal line, a third segment signal line, and a fourth segment signal line, the second segment signal line is disposed on the first metal layer, and the third segment signal line is disposed on the second
  • the fourth signal line is provided on the first metal layer, the second signal line is connected to the third signal line through the first via, and the third signal line is connected through the second
  • the hole is connected to the fourth section of the signal line, the first through hole and the second through hole are provided on the first metal layer, and are located on the first side and the second side of the corresponding position of the data line.
  • the other end of the fourth signal line is connected to the gate chip.
  • the display panel includes a first side, the source driver chip is connected to the first side, and the signal line is connected to the source driver chips at both ends of the first side.
  • the present application also discloses a display device including the above-mentioned display panel.
  • the pins of the source driver chip are set on the first side and the second side.
  • the signal lines are respectively connected to different groups of pins, making full use of the surplus pins of the source driver chip and the pins of the source driver chip The number can be further reduced.
  • the spacing between the pins can be appropriately increased, or the pins can be further widened, thereby increasing the bonding area and improving the bonding yield.
  • FIG. 2 is a schematic diagram of a display panel structure according to another embodiment of the present application.
  • FIG. 3 is a schematic diagram of a display panel structure according to one embodiment of the present application.
  • FIG. 5 is a schematic diagram of a signal line routing path according to one embodiment of the present application.
  • FIG. 7 is a schematic diagram of a structure of a display device according to one embodiment of the present application.
  • connection should be understood in a broad sense, for example, it can be fixed connection or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • installation should be understood in a broad sense, for example, it can be fixed connection or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • the required voltage and signal of the gate part of the display panel are transmitted to the gate through the traces of the source flexible circuit board (source) COF (bypass pin) and array wiring (WOA, wire on array) ) Circuits, gates (Gate) required signals and voltages usually use more than 20 traces, usually from the edge of the source flexible circuit board (source COF) on the edge of the panel to the panel, and then through the array
  • the wiring (WOA, wire on array) is given to the gate.
  • an embodiment of the present application discloses a display panel 100 including a substrate 200, a flexible circuit board 400, a source driving chip 500, and a gate chip 600.
  • the substrate 200 includes a display area 210 and a non-display Zone 300, the non-display zone 300 is arranged around the edge of the display zone 210; the non-display zone 300 is provided with signal lines 310; the flexible circuit board 400 is arranged on the first side 100a of the substrate 200; the source driver chip 500 is arranged on the flexible circuit board 400
  • the source driver chip 500 includes two sets of pins 510, which are located on the first side 500a and the second side 500b of the same source driver chip 500; the gate chip 600 is disposed on the second side of the substrate 200 100b and the third side 100c, the second side 100b and the third side 100c are respectively located on the first side and the second side of the first side 100a, and the gate chip 600 is respectively connected to different groups of pins 510 through the signal line 310 on.
  • the pin 510 of the source driver chip 500 is provided on the first side and the second side.
  • the signal line 310 is respectively connected to the pin 510 of a different group, and the surplus tube of the source driver chip 500 is fully utilized
  • the number of pins of the source driver chip 500 can be further reduced.
  • the spacing between the pins can be appropriately increased, or the pins can be further widened to increase the number of pins
  • the combined area increases the bonding yield.
  • one end of the signal line 300 is connected to one gate chip 600, and the other end of the signal line 310 is symmetrically connected to the first side and second side pins 510 of the same source driver chip 500 .
  • the pins 510 on the first side and the second side of a source driver chip 500 are symmetrically connected, and all pins 510 are used reasonably without increasing the number of source driver chips 500 required. This reduces the number of pins 510 required for the source driver chip 500.
  • the signal line 310 is dispersed to one source driver chip 500, which is reduced by at most half. If it is dispersed to two, it is theoretically a quarter, and so on, so that one source driver chip 500 is required. The number of set pins 510 is reduced even more.
  • the non-display area 300 includes a first metal layer 331 and a second metal layer 332, the first metal layer 331 includes a data line 333, and the first metal layer 331 includes a first through hole 334 and a second through hole 335
  • the signal line 310 includes a second signal line 312, a third signal line 313, and a fourth signal line 314.
  • the second signal line 312 is disposed on the first metal layer 331, and the third signal line 313 is disposed on the first On the second metal layer 332, the fourth signal line 314 is disposed on the first metal layer 331, the second signal line 312 is connected to the third signal line 313 through the first via 334, and the third signal line 313 passes through the
  • the second through hole 335 is connected to the fourth signal line 314.
  • the first through hole 334 and the second through hole 335 are disposed on the first metal layer 331, and are located on the first side and the second side of the position corresponding to the data line 333.
  • the other end of the four-segment signal line 314 is connected to the gate chip 600.
  • the non-display area 300 includes a first metal layer 331 and an insulating layer 320.
  • the insulating layer 320 is disposed on the surface of the first metal layer 331.
  • the first metal layer 331 includes the data line 333.
  • the insulating layer 320 covers the data line 333, and the signal line 310 is laid from above the insulating layer 320 and then connected to the gate chip 600.
  • an insulating layer 320 is covered above the data line 333, and then the signal line 310 is laid over the insulating layer 320, so that the data line 333 and the signal line 310 can be divided without the need to improve other existing structures Separated to prevent interference between the signal line 310 and the data line 333.
  • the non-display area 300 includes a first metal layer 331 and a second metal layer 332, the first metal layer 331 includes a first through hole 334, the first metal layer 331 is provided with a data line 333, and a signal line 310
  • the second segment signal line 312 and the third segment signal line 313 are connected.
  • One end of the second segment signal line 312 is connected to the pin 510, the third segment signal line 313 is disposed on the second metal layer 332, and the second segment signal line 312 is One end is connected to one end of the third-stage signal line 313 through the first through hole 334, and the other end of the third-stage signal line 313 is connected to the gate chip 600.
  • the signal line 310 is laid by the source driver chip 500, and then the signal line 310 is redirected to the second metal layer 332 through the first through hole 334 on the first metal layer 331, and then routed to On the gate chip 600, the data line 333 and the signal line 310 are directly disposed on the first metal layer 331 and the second metal layer 332, respectively, so that the data line 333 and the signal line 310 do not cross, preventing mutual interference.
  • the signal line 310 is connected to the source driving chip 500 at both ends of the first side 100a.
  • the signal line 310 is laid using the source driver chip 500 on the outside, which shortens the length of the signal line 310 to be laid and reduces the difficulty of laying.
  • the display panel 100 includes a circuit board 700, and there are two circuit boards 700, two flexible circuit boards 400 are connected to each circuit board 700, the non-display area 300 includes a metal layer 330, and the metal layer 330 includes a first The metal layer 331 and the second metal layer 332, the other end of the source driver chip 500 is connected to the circuit board 700 through the flexible circuit board 400, and the signal line 310 includes a first segment signal line 311, a second segment signal line 312, and a third segment signal Line 313 and the fourth segment signal line 314, the first segment signal line 311 is provided on the flexible circuit board 400, the two ends are respectively connected to the circuit board 700 and the source driver chip 500, and the second segment signal line 312 is both ends Connected to the pin 510 and the first metal layer 331 respectively, the third section signal line 313 is disposed on the second metal layer 332, one end of the third section signal line 313 is connected to the second section signal line 312, and the fourth section signal line 314 is disposed on the first metal layer 331, one end
  • the circuit board 700 is a control circuit board.
  • the signal line 310 is laid through the existing structure in the display panel 100, and no additional structure is needed, which saves material cost and space.
  • a display panel 100 including a substrate 200, a flexible circuit board 400, a source driving chip 500, and a gate chip 600.
  • the substrate 200 includes a display The area 210 and the non-display area 300, the non-display area 300 is arranged around the edge of the display area 210; the non-display area 300 is provided with a signal line 310; the flexible circuit board 400 is provided on the edge of the substrate 200 and connected to the substrate 200; the source driver chip 500 It is disposed on the flexible circuit board 400 and connected to the substrate 200 through the flexible circuit board 400; the source driving chip 500 includes two sets of pins 510, and the two sets of pins 510 are respectively located on the first side 500a and the first side of the same source driving chip 500.
  • the gate chip 600 is disposed on the edge of the substrate 200, and is located at the first side and the second side of the source driver chip 500, and is connected to the substrate 200; the gate chip 600 is respectively connected to different through the signal line 310 Group pin 510;
  • One end of the signal line 300 is connected to one gate chip 600, and the other end of the signal line 310 is symmetrically connected to the first side and second side pins 510 of the same source driver chip 500;
  • the non-display area 300 includes a first metal layer 331 and a second metal layer 332.
  • the first metal layer 331 includes a data line 333
  • the first metal layer 331 includes a first via 334 and a second via 335
  • the signal line 310 includes a The second-stage signal line 312, the third-stage signal line 313, and the fourth-stage signal line 314, the second-stage signal line 312 is disposed on the first metal layer 331, and the third-stage signal line 313 is disposed on the second metal layer 332,
  • the fourth signal line 314 is disposed on the first metal layer 331, the second signal line 312 is connected to the third signal line 313 through the first through hole 334, and the third signal line 313 is connected to the third signal line through the second through hole 335
  • Four sections of signal lines 314 are connected.
  • the first through holes 334 and the second through holes 335 are disposed on the first metal layer 332 and are located on the first and second sides of the corresponding positions of the data lines 333. One
  • the display panel 100 includes a first side 100a, a source driver chip 500 is connected to the first side 100a, and a signal line 310 is connected to the source driver chips 500 at both ends of the first side 100a.
  • the pin 510 of the source driver chip 500 is provided on the first side and the second side.
  • the signal line 310 is respectively connected to the pin 510 of a different group, and the surplus tube of the source driver chip 500 is fully utilized
  • the number of pins of the source driver chip 500 can be further reduced.
  • the spacing between the pins can be appropriately increased, or the pins can be further widened to increase the number of pins
  • the combined area increases the bonding yield.
  • a display device 800 As another embodiment of the present application, as shown in FIGS. 2 to 7, a display device 800 is disclosed.
  • the display device 800 includes the above-mentioned display panel 100.
  • the panel of this application can be a TN panel (full name Twisted Nematic, namely twisted nematic panel), IPS panel (In-Plane Switching, plane switching), VA panel (Multi-domain Vertica Aignment, multi-quadrant vertical alignment technology), Of course, other types of panels can also be used.
  • TN panel full name Twisted Nematic, namely twisted nematic panel
  • IPS panel In-Plane Switching, plane switching
  • VA panel Multi-domain Vertica Aignment, multi-quadrant vertical alignment technology

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)

Abstract

一种显示面板（100）和显示装置（800）。显示面板（100）包括基板（200）、源极驱动芯片（500）和栅极芯片（600），源极驱动芯片（500）包括两组管脚（510），两组管脚（510）分别位于同一源极驱动芯片（500）的第一侧和第二侧；栅极芯片（600）连接于不同组的管脚（510）上。

Description

显示面板和显示装置
本申请要求于2018年10月31日提交中国专利局，申请号为CN201821778183.X，发明名称为“一种显示面板和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及显示面板和显示装置.
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着科技的发展和进步，液晶显示器由于具备机身薄、省电和辐射低等热点而成为显示器的主流产品，得到了广泛应用。市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶面板及背光模组(backlight module)。液晶面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，并在两片玻璃基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
其中，薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)由于具有低的功耗、优异的画面品质以及较高的生产良率等性能，目前已经逐渐占据了显示领域的主导地位。同样，薄膜晶体管液晶显示器包含液晶面板和背光模组，液晶面板包括彩膜基板(Color Filter Substrate，CF Substrate，也称彩色滤光片基板)、薄膜晶体管阵列基板(Thin Film Tran-sistor Substrate，TFTSubstrate)和光罩(Mask)，上述基板的相对内侧存在透明电极。两片基板之间夹一层液晶分子(Liquid Crystal，LC)。显示器会导致柔性电路板贴合不良发生，影响显示器的使用效果和人们的观看体验。
技术解决方案
本申请的目的在于提供一种显示面板和显示装置，以解决显示器的柔性电路板贴合不良影响显示器的使用效果和人们的观看体验。
为实现上述目的，本申请提供了一种显示面板，包括基板、柔性电路板、源极驱动芯片和栅极芯片，基板包括显示区和非显示区，非显示区内设有信号线；柔性电路板与基板的第一边连接；源极驱动芯片设置在柔性电路板上；源极驱动芯片包括两组管脚，两组管脚分别位于同一源极驱动芯片的第一侧和第二侧；栅极芯片分别设置在所述基板的第二边和第三边，所述第二边和第三边分别位于所述第一边的第一侧和第二侧；所述栅极芯片通过所述信 号线分别连接于不同组的所述管脚上。
可选的，所述信号线对称连接于同一颗所述源极驱动芯片第一侧和第二侧的两组所述管脚上。
可选的，所述源极驱动芯片至少有两颗，信号线分散连接到至少两颗所述源极驱动芯片的所述管脚上。
可选的，所述非显示区包括包括金属层，所述金属层包括第一金属层和第二金属层，所述第一金属层包括数据线，所述第一金属层包括第一通孔和第二通孔，所述信号线包括第二段信号线、第三段信号线和第四段信号线，所述第二段信号线设置在第一金属层上，所述第三段信号线设置在第二金属层上，所述第四段信号线设置在第一金属层上，所述第二段信号线通过第一通孔与第三段信号线连接，所述第三段信号线通过第二通孔与第四段信号线连接，所述第一通孔和所述第二通孔设置在所述第一金属层上，位于所述数据线所对应位置的第一侧和第二侧，所述第四段信号线另一端连接到所述栅极芯片。
可选的，所述非显示区包括金属层，所述金属层包括第一金属层和绝缘层，所述绝缘层设置在所述第一金属层表面，所述第一金属层包括数据线，所述数据线设置在第一金属层的表面上，所述绝缘层覆盖在所述数据线的上面，所述信号线从所述绝缘层的上方铺设，然后连接到所述栅极芯片上。
可选的，所述非显示区包括金属层，所述金属层包括第一金属层和第二金属层，所述第一金属层包括第一通孔，所述第一金属层上设有数据线，所述信号线包括第二段信号线和第三段信号线，所述第二段信号线一端与管脚连接，所述第三段信号线设置在第二金属层上，所述第二段信号线另一端与所述第三段信号线一端通过所述第一通孔连接，所述第三段信号线另一端与栅极芯片连接。
可选的，所述信号线连接到所述第一边两端的所述源极驱动芯片上。
可选的，所述显示面板包括电路板，所述电路板有两个，每个所述电路板上连接两个所述柔性电路板，所述非显示区包括金属层，所述金属层包括第一金属层和第二金属层，所述源极驱动芯片另一端通过所述柔性电路板与所述电路板连接，所述信号线包括第一段信号线、第二段信号线、第三段信号线和第四段信号线，所诉第一段信号线设置在所述柔性电路板上，两端分别连接于所述电路板和所述源极驱动芯片上，所述第二段信号线两端分别连接于所述管脚和所述第一金属层上，所述第三段信号线设置在所述第二金属层上，所述第三段信号线一端与所述第二段信号线连接，所述第四段信号线设置在所述第一金属层上，所述第四段信号线一端与所述第三段信号线另一端连接，所述第四段信号线另一端与所述栅极芯片连接。
本申请还公开了一种显示面板，包括基板、柔性电路板、源极驱动芯片和栅极芯片，基 板包括显示区和非显示区，非显示区内设有信号线；柔性电路板与基板连接；源极驱动芯片设置在柔性电路板上，通过柔性电路板与基板连接；所述源极驱动芯片包括两组管脚，两组所述管脚分别位于同一所述源极驱动芯片的第一侧和第二侧；栅极芯片设置在所述基板边缘，位于源极驱动芯片第一侧和第二侧的位置，与所述基板连接；所述栅极芯片通过所述信号线分别连接于不同组的所述管脚上；
所述信号线对称连接于同一颗所述源极驱动芯片第一侧和第二侧的两组所述管脚上；
所述非显示区包括金属层，所述金属层包括第一金属层和第二金属层，所述第一金属层包括数据线，所述第一金属层包括第一通孔和第二通孔，所述信号线包括第二段信号线、第三段信号线和第四段信号线，所述第二段信号线设置在第一金属层上，所述第三段信号线设置在第二金属层上，所述第四段信号线设置在第一金属层上，所述第二段信号线通过第一通孔与第三段信号线连接，所述第三段信号线通过第二通孔与第四段信号线连接，所述第一通孔和所述第二通孔设置在所述第一金属层上，位于所述数据线所对应位置的第一侧和第二侧，所述第四段信号线另一端连接到所述栅极芯片。
所述显示面板包括第一边，所述源极驱动芯片连接在所述第一边上，所述信号线连接到所述第一边两端的所述源极驱动芯片上。
本申请还公开了一种显示装置，所述显示装置包括上述的显示面板。
源极驱动芯片的管脚设置在第一侧和第二侧，本申请将信号线分别连接在不同组的管脚上，充分利用源极驱动芯片富余的管脚，源极驱动芯片的引脚数量能进一步缩减，在柔性电路板尺寸不变的情况下，引脚之间的间距可以适当增大，或者将引脚进一步做宽，从而增加贴合面积提高贴合良率。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请的其中一个实施例的一种显示面板结构的示意图；
图2是本申请的另一个实施例的一种显示面板结构的示意图；
图3是本申请的其中一个实施例的一种显示面板结构的示意图；
图4是本申请的其中一个实施例的一种数据线与信号线铺设的截面结构的示意图；
图5是本申请的其中一个实施例的一种信号线走线路径的示意图；
图6是本申请的另一个实施例的一种信号线走线路径的示意图；
图7是本申请的其中一个实施例的一种显示装置结构的示意图。
具体实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
显示面板栅极(gate)部分所需电压和信号都是通过源级柔性电路板(source COF)的管脚(bypass pin)和阵列布线(WOA，wire on array)走线传输到栅极(gate)电路，栅极(Gate)所需信号和电压通常会用到20根以上走线，一般都是从面板边上那颗源级柔性电路板(source COF)的边沿传输到面板，再通过阵列布线(WOA，wire on array)给到栅极(gate)。
下面结合附图和实施例对本申请作进一步说明。
如图2至图6所示，本申请实施例公布了一种显示面板100，包括基板200、柔性电路板400、源极驱动芯片500和栅极芯片600，基板200包括显示区210和非显示区300，非 显示区300环绕显示区210边缘设置；非显示区300内设有信号线310；柔性电路板400设置在基板200的第一边100a；源极驱动芯片500设置在柔性电路板400上；源极驱动芯片500包括两组管脚510，两组管脚510分别位于同一源极驱动芯片500的第一侧500a和第二侧500b；栅极芯片600设置在基板200的第二边100b和第三边100c，第二边100b和第三边100c分别位于所述第一边100a的第一侧和第二侧，栅极芯片600通过信号线310分别连接于不同组的管脚510上。
本方案中，源极驱动芯片500的管脚510设置在第一侧和第二侧，本申请将信号线310分别连接在不同组的管脚510上，充分利用源极驱动芯片500富余的管脚510，源极驱动芯片500的引脚数量能进一步缩减，在柔性电路板400尺寸不变的情况下，引脚之间的间距可以适当增大，或者将引脚进一步做宽，从而增加贴合面积提高贴合良率。
在一个实施例中，信号线300的一端连接于一颗栅极芯片600上，信号线310的另一端对称连接于同一颗源极驱动芯片500的第一侧和第二侧的管脚510上。
本方案中，对称连接在一颗源极驱动芯片500的第一侧和第二侧的管脚510上，合理利用上所有管脚510，不需要再增加所需要的源极驱动芯片500数量，使得源极驱动芯片500所需设置的管脚510数减少。
在一个实施例中，源极驱动芯片500至少有两颗，信号线310分散连接到至少两颗源极驱动芯片500的管脚510上。
本方案中，信号线310分散到一颗源极驱动芯片500，最多缩减一半，如果分散到二颗，理论上就是四分之一，以此类推，使得一颗源极驱动芯片500上所需设置的管脚510数减少更多。
在一个实施例中，非显示区300包括第一金属层331和第二金属层332，第一金属层331包括数据线333，第一金属层331包括第一通孔334和第二通孔335，信号线310包括第二段信号线312、第三段信号线313和第四段信号线314，第二段信号线312设置在第一金属层331上，第三段信号线313设置在第二金属层332上，第四段信号线314设置在第一金属层331上，第二段信号线312通过第一通孔334与第三段信号线313连接，第三段信号线313通过第二通孔335与第四段信号线314连接，第一通孔334和第二通孔335设置在第一金属层331上，位于数据线333所对应位置的第一侧和第二侧，第四段信号线314另一端连接到栅极芯片600。
本方案中，信号线310快连接到数据线333位置的时候，通过绕到第二金属层332再绕回第一金属层331，不需要再增加其他结构，避免了与数据线333相交，防止信号线310与数据线333产生干扰。
在一个实施例中，非显示区300包括第一金属层331和绝缘层320，绝缘层320设置在 第一金属层331表面，第一金属层331包括数据线333，数据线333设置在第一金属层331的表面上，绝缘层320覆盖在数据线333的上面，信号线310从绝缘层320的上方铺设，然后连接到栅极芯片600上。
本方案中，在数据线333上方覆盖一层绝缘层320，然后信号线310在绝缘层320的上方铺设，这样不需要再对其他已有结构进行改进就可以将数据线333与信号线310分隔开，防止信号线310与数据线333产生干扰。
在一个实施例中，非显示区300包括第一金属层331和第二金属层332，第一金属层331包括第一通孔334，第一金属层331上设有数据线333，信号线310包括第二段信号线312和第三段信号线313，第二段信号线312一端与管脚510连接，第三段信号线313设置在第二金属层332上，第二段信号线312另一端与第三段信号线313一端通过第一通孔334连接，第三段信号线313另一端与栅极芯片600连接。
本方案中，通过源极驱动芯片500来铺设信号线310，然后通过第一金属层331上的第一通孔334将信号线310再引导到第二金属层332走线，然后再走线到栅极芯片600上，直接将数据线333和信号线310分别设置在第一金属层331和第二金属层332上，使得数据线333和信号线310不会发生交叉，防止互相产生干扰。
在一个实施例中，信号线310连接到第一边100a两端的源极驱动芯片500上。
本方案中，利用外侧的源极驱动芯片500来铺设信号线310，缩短了所需铺设的信号线310的长度，降低铺设难度。
在一个实施例中，显示面板100包括电路板700，电路板700有两个，每个电路板700上连接两个柔性电路板400，非显示区300包括金属层330，金属层330包括第一金属层331和第二金属层332，源极驱动芯片500另一端通过柔性电路板400与电路板700连接，信号线310包括第一段信号线311、第二段信号线312、第三段信号线313和第四段信号线314，所诉第一段信号线311设置在柔性电路板400上，两端分别连接于电路板700和源极驱动芯片500上，第二段信号线312两端分别连接于管脚510和第一金属层331上，第三段信号线313设置在第二金属层332上，第三段信号线313一端与第二段信号线312连接，第四段信号线314设置在第一金属层331上，第四段信号线314一端与第三段信号线313另一端连接，第四段信号线314另一端与栅极芯片600连接。
其中，电路板700为控制电路板。
本方案中，通过显示面板100中的内部已有结构来铺设信号线310，无需再额外增加其他结构，节省材料成本和空间。
作为本申请的另一实施例，如图2至图6所示，公开了一种显示面板100，包括基板200、柔性电路板400、源极驱动芯片500和栅极芯片600，基板200包括显示区210和非显示区 300，非显示区300环绕显示区210边缘设置；非显示区300内设有信号线310；柔性电路板400设置在基板200边缘，与基板200连接；源极驱动芯片500设置在柔性电路板400上，通过柔性电路板400与基板200连接；源极驱动芯片500包括两组管脚510，两组管脚510分别位于同一源极驱动芯片500的第一侧500a和第二侧500b；栅极芯片600设置在基板200边缘，位于源极驱动芯片500所在边的第一侧和第二侧的位置，与基板200连接；栅极芯片600通过信号线310分别连接于不同组的管脚510上；
信号线300的一端连接于一颗栅极芯片600上，信号线310的另一端对称连接于同一颗源极驱动芯片500的第一侧和第二侧的管脚510上；
非显示区300包括第一金属层331和第二金属层332，第一金属层331包括数据线333，第一金属层331包括第一通孔334和第二通孔335，信号线310包括第二段信号线312、第三段信号线313和第四段信号线314，第二段信号线312设置在第一金属层331上，第三段信号线313设置在第二金属层332上，第四段信号线314设置在第一金属层331上，第二段信号线312通过第一通孔334与第三段信号线313连接，第三段信号线313通过第二通孔335与第四段信号线314连接，第一通孔334和第二通孔335设置在第一金属层332上，位于数据线333所对应位置的第一侧和第二侧，第四段信号线314另一端连接到栅极芯片600；
显示面板100包括第一边100a，源极驱动芯片500连接在第一边100a上，信号线310连接到第一边100a两端的源极驱动芯片500上。
本方案中，源极驱动芯片500的管脚510设置在第一侧和第二侧，本申请将信号线310分别连接在不同组的管脚510上，充分利用源极驱动芯片500富余的管脚510，源极驱动芯片500的引脚数量能进一步缩减，在柔性电路板400尺寸不变的情况下，引脚之间的间距可以适当增大，或者将引脚进一步做宽，从而增加贴合面积提高贴合良率。对称连接在一颗源极驱动芯片500的第一侧和第二侧的管脚510上，合理利用上所有管脚510，不需要再增加所需要的源极驱动芯片500数量，使得源极驱动芯片500所需设置的管脚510数减少。信号线310快连接到数据线333位置的时候，通过绕到第二金属层332再绕回第一金属层331，不需要再增加其他结构，避免了与数据线333相交，防止信号线310与数据线333产生干扰。利用外侧的源极驱动芯片500来铺设信号线310，缩短了所需铺设的信号线310的长度，降低铺设难度。
作为本申请的另一实施例，如图2至图7所示，公开了一种显示装置800，显示装置800包括上述的显示面板100。
本申请的面板可以是TN面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS面板(In-Plane Switching，平面转换)、VA面板(Multi-domain Vertica Aignment，多象限垂直配向技术)，当然，也可以是其他类型的面板，适用即可。
以上内容是结合具体的实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (17)

  1. 一种显示面板，包括：
    基板；
    显示区，设置在所述基板上；
    非显示区；所述非显示区环绕所述显示区边缘设置；所述非显示区内设有信号线；
    柔性电路板，设置在在所述基板的第一边；
    源极驱动芯片，设置在柔性电路板上，所述源极驱动芯片包括两组管脚，两组所述管脚分别位于同一所述源极驱动芯片的第一侧和第二侧；
    以及栅极芯片，分别设置在所述基板的第二边和第三边，所述第二边和第三边分别位于所述第一边的第一侧和第二侧；所述栅极芯片通过所述信号线分别连接于不同组的所述管脚上。
  2. 如权利要求1所述的一种显示面板，其中，所述信号线的一端连接于所述栅极芯片上，所述信号线的另一端对称连接于同一颗所述源极驱动芯片第一侧和第二侧的两组所述管脚上。
  3. 如权利要求1所述的一种显示面板，其中，所述源极驱动芯片至少有两颗，信号线分别连接到至少两颗所述源极驱动芯片的所述管脚上。
  4. 如权利要求1所述的一种显示面板，其中，所述非显示区包括金属层，所述金属层包括第一金属层和第二金属层，所述第一金属层包括数据线、第一通孔和第二通孔，所述信号线包括第二段信号线、第三段信号线和第四段信号线，所述第二段信号线设置在第一金属层上，所述第三段信号线设置在第二金属层上，所述第四段信号线设置在第一金属层上，所述第二段信号线通过第一通孔与第三段信号线连接，所述第三段信号线通过第二通孔与第四段信号线连接，所述第一通孔和所述第二通孔设置在所述第一金属层上的所述数据线所对应位置的第一侧和第二侧，所述第四段信号线另一端连接到所述栅极芯片。
  5. 如权利要求1所述的一种显示面板，其中，所述非显示区包括金属层，所述金属层包括第一金属层和绝缘层，所述绝缘层设置在所述第一金属层表面，所述第一金属层包括数据线，所述数据线设置在第一金属层的表面上，所述绝缘层覆盖在所述数据线的上面，所述信号线从所述绝缘层的上方铺设，然后连接到所述栅极芯片上。
  6. 如权利要求1所述的一种显示面板，其中，所述非显示区包括金属层，所述金属层包括第一金属层和第二金属层，所述第一金属层包括第一通孔，所述第一金属层上设有数据线，所述信号线包括第二段信号线和第三段信号线，所述第二段信号线一端与管脚连接，所述第三段信号线设置在第二金属层上，所述第二段信号线另一端与所述第三段信号线一端通 过所述第一通孔连接，所述第三段信号线另一端与栅极芯片连接。
  7. 如权利要求2所述的一种显示面板，其中，所述信号线连接到所述第一边两端的所述源极驱动芯片上。
  8. 如权利要求1所述的一种显示面板，其中，所述显示面板包括电路板，所述电路板有两个，每个所述电路板上连接两个所述柔性电路板，所述非显示区包括金属层，所述金属层包括第一金属层和第二金属层，所述源极驱动芯片另一端通过所述柔性电路板与所述电路板连接，所述信号线包括第一段信号线、第二段信号线、第三段信号线和第四段信号线，所诉第一段信号线设置在所述柔性电路板上，两端分别连接于所述电路板和所述源极驱动芯片上，所述第二段信号线两端分别连接于所述管脚和所述第一金属层上，所述第三段信号线设置在所述第二金属层上，所述第三段信号线一端与所述第二段信号线连接，所述第四段信号线设置在所述第一金属层上，所述第四段信号线一端与所述第三段信号线另一端连接，所述第四段信号线另一端与所述栅极芯片连接。
  9. 一种显示面板，包括：
    基板，包括显示区和非显示区，所述非显示区环绕所述显示区边缘设置；所述非显示区内设有信号线；
    柔性电路板，设置在基板边缘，与基板连接；
    源极驱动芯片，设置在柔性电路板上，通过柔性电路板与基板连接，所述源极驱动芯片包括两组管脚，两组所述管脚分别位于同一所述源极驱动芯片的第一侧和第二侧；
    以及栅极芯片，设置在所述基板边缘，位于源极驱动芯片第一侧和第二侧的位置，与所述基板连接；所述栅极芯片通过所述信号线分别连接于不同组的所述管脚上；
    所述信号线对称连接于同一颗所述源极驱动芯片第一侧和第二侧的两组所述管脚上；
    所述非显示区包括金属层，所述金属层包括第一金属层和第二金属层，所述第一金属层包括数据线，所述第一金属层包括第一通孔和第二通孔，所述信号线包括第二段信号线、第三段信号线和第四段信号线，所述第二段信号线设置在第一金属层上，所述第三段信号线设置在第二金属层上，所述第四段信号线设置在第一金属层上，所述第二段信号线通过第一通孔与第三段信号线连接，所述第三段信号线通过第二通孔与第四段信号线连接，所述第一通孔和所述第二通孔设置在第一金属层上，位于数据线所对应位置的第一侧和第二侧，所述第四段信号线另一端连接到所述栅极芯片；
    所述显示面板包括第一边，所述源极驱动芯片连接在所述第一边上，所述信号线连接到所述第一边两端的所述源极驱动芯片上。
  10. 一种显示装置，包括：
    基板；
    显示区，设置在所述基板上；
    非显示区；所述非显示区环绕所述显示区边缘设置；所述非显示区内设有信号线；
    柔性电路板，设置在在所述基板的第一边；
    源极驱动芯片，设置在柔性电路板上，所述源极驱动芯片包括两组管脚，两组所述管脚分别位于同一所述源极驱动芯片的第一侧和第二侧；
    以及栅极芯片，分别设置在所述基板的第二边和第三边，所述第二边和第三边分别位于所述第一边的第一侧和第二侧；所述栅极芯片通过所述信号线分别连接于不同组的所述管脚上。
  11. 如权利要求10所述的一种显示装置，其中，所述信号线的一端连接于所述栅极芯片上，所述信号线的另一端对称连接于同一颗所述源极驱动芯片第一侧和第二侧的两组所述管脚上。
  12. 如权利要求10所述的一种显示装置，其中，所述源极驱动芯片至少有两颗，信号线分别连接到至少两颗所述源极驱动芯片的所述管脚上。
  13. 如权利要求10所述的一种显示装置，其中，所述非显示区包括金属层，所述金属从包括第一金属层和第二金属层，所述第一金属层包括数据线、第一通孔和第二通孔，所述信号线包括第二段信号线、第三段信号线和第四段信号线，所述第二段信号线设置在第一金属层上，所述第三段信号线设置在第二金属层上，所述第四段信号线设置在第一金属层上，所述第二段信号线通过第一通孔与第三段信号线连接，所述第三段信号线通过第二通孔与第四段信号线连接，所述第一通孔和所述第二通孔设置在所述第一金属层上的所述数据线所对应位置的第一侧和第二侧，所述第四段信号线另一端连接到所述栅极芯片。
  14. 如权利要求10所述的一种显示装置，其中，所述非显示区包括金属层，所述金属层包括第一金属层和绝缘层，所述绝缘层设置在所述第一金属层表面，所述第一金属层包括数据线，所述数据线设置在第一金属层的表面上，所述绝缘层覆盖在所述数据线的上面，所述信号线从所述绝缘层的上方铺设，然后连接到所述栅极芯片上。
  15. 如权利要求10所述的一种显示装置，其中，所述非显示区包括金属层，所述金属层包括第一金属层和第二金属层，所述第一金属层包括第一通孔，所述第一金属层上设有数据线，所述信号线包括第二段信号线和第三段信号线，所述第二段信号线一端与管脚连接，所述第三段信号线设置在第二金属层上，所述第二段信号线另一端与所述第三段信号线一端通过所述第一通孔连接，所述第三段信号线另一端与栅极芯片连接。
  16. 如权利要求11所述的一种显示装置，其中，所述信号线连接到所述第一边两端的所述源极驱动芯片上。
  17. 如权利要求10所述的一种显示装置，其中，所述显示面板包括电路板，所述电路 板有两个，每个所述电路板上连接两个所述柔性电路板，所述非显示区包括金属层，所述金属层包括第一金属层和第二金属层，所述源极驱动芯片另一端通过所述柔性电路板与所述电路板连接，所述信号线包括第一段信号线、第二段信号线、第三段信号线和第四段信号线，所诉第一段信号线设置在所述柔性电路板上，两端分别连接于所述电路板和所述源极驱动芯片上，所述第二段信号线两端分别连接于所述管脚和所述第一金属层上，所述第三段信号线设置在所述第二金属层上，所述第三段信号线一端与所述第二段信号线连接，所述第四段信号线设置在所述第一金属层上，所述第四段信号线一端与所述第三段信号线另一端连接，所述第四段信号线另一端与所述栅极芯片连接。
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