WO2020087618A1 - 驱动电路及显示驱动装置 - Google Patents

驱动电路及显示驱动装置 Download PDF

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Publication number
WO2020087618A1
WO2020087618A1 PCT/CN2018/118052 CN2018118052W WO2020087618A1 WO 2020087618 A1 WO2020087618 A1 WO 2020087618A1 CN 2018118052 W CN2018118052 W CN 2018118052W WO 2020087618 A1 WO2020087618 A1 WO 2020087618A1
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WIPO (PCT)
Prior art keywords
controlled
controlled switch
switch
display
terminal
Prior art date
Application number
PCT/CN2018/118052
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English (en)
French (fr)
Inventor
黄笑宇
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惠科股份有限公司
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Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to US17/041,082 priority Critical patent/US11081074B2/en
Publication of WO2020087618A1 publication Critical patent/WO2020087618A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present application relates to a driving circuit and a display driving device.
  • the liquid crystal display panel is a display device composed of a certain number of color or black and white pixels and placed in front of a light source or a reflective surface.
  • TFT-LCD Thin Film Transistor Liquid Crystal
  • LCD Thin Film Transistor Liquid Crystal
  • the system motherboard connects R / G / B compressed signals, control signals, and power to the connector on the PCB through wires, and the data passes through the TCON (Timing Controller) on the PCB ) After IC processing, it is connected to the display area through the PCB board through S-COF (Source-Chip on Film) and G-COF (Gate-Chip on Film).
  • S-COF Source-Chip on Film
  • G-COF Gate-Chip on Film
  • the signals that enable the TFT-LCD to implement the display function include the line start signal output by TCON, the gate-on signal output by G-COF to the gate of the transistor, and the display signal output by S-COF to the source of the transistor .
  • a sub-pixel is generally divided into two mutually independent parts, each part includes a pixel electrode, and the sub-pixel display is realized through the two parts. Due to the material characteristics of the liquid crystal, setting the same voltage on the liquid crystal for a long time will cause the liquid crystal to polarize, resulting in abnormal display. Therefore, the TFT-LCD needs a reference voltage during display, and then defines the voltage value higher than the reference voltage as positive polarity and the voltage value lower than the reference voltage as negative polarity. During the display process, the voltage set on the liquid crystal is switched from positive polarity to negative polarity every frame to avoid polarization of the liquid crystal.
  • the charging time is insufficient, the voltage on the pixel electrode is directly switched from the positive polarity to the negative polarity, and the larger voltage across will cause insufficient charging, that is, the voltage on the pixel electrode cannot be switched to the target voltage within a limited charging time.
  • a driving circuit and a display driving device are provided.
  • a driving circuit includes a signal processing circuit and a controlled switch circuit; each controlled switch circuit corresponds to each sub-pixel in one-to-one correspondence;
  • the signal processing circuit is set to access the line start signal of the timing controller, and outputs a control signal according to a line start signal;
  • the controlled switch circuit includes a display switch circuit and a reference switch circuit
  • the input terminal of the display switch circuit is set to access the display signal output from the source thin film driver chip, the controlled terminal of the display switch circuit is connected to the control signal, and the first output terminal of the display switch circuit is set to connect to the transistor corresponding to the first part of the sub-pixel Source, the second output of the display switch circuit is set to connect to the source of the transistor corresponding to the second part of the sub-pixel;
  • the input terminal of the reference switch circuit is set to connect to the reference voltage
  • the controlled terminal of the reference switch circuit is connected to the control signal
  • the first output terminal of the reference switch circuit is set to connect to the reference voltage terminal of the first part of the corresponding subpixel
  • the second output terminal is set to connect to the reference voltage terminal of the second part of the corresponding sub-pixel;
  • a control signal can make the display switch circuit turn on its input end and first output end, make the reference switch circuit turn on its input end and second output end; or, make the display switch circuit turn on its input end and second output end So that the reference switch circuit conducts its input end and the first output end.
  • the signal processing circuit includes a D flip-flop, a first controlled switch, and a second controlled switch;
  • the input terminal of the first controlled switch is set to access a logic high voltage; the input terminal of the second controlled switch is set to ground;
  • the output terminal of the first controlled switch is set to be connected to the output terminal of the second controlled switch, and is set to ground, and is also set to output the control signal;
  • the control end of the D flip-flop is set to access the line start signal, the pulse input end of the D flip-flop is connected to the output end of the first controlled switch, and the output end of the D flip-flop is connected to the controlled end of the first controlled switch and the first The controlled end of the controlled switch;
  • the input end and output end of the first controlled switch are turned on, and the input end and output end of the second controlled switch are turned off; or, the first controlled switch The input end and output end of the are off, and the input end and output end of the second controlled switch are on.
  • the D flip-flop includes a rising edge D flip-flop.
  • the first controlled switch includes a first P-channel field effect transistor, and the second controlled switch includes a first N-channel field effect transistor;
  • the controlled end of the first controlled switch is the gate of the first P-channel field effect transistor
  • the controlled terminal of the second controlled switch is the gate of the first N-channel field effect transistor.
  • the signal processing circuit further includes a protection resistor
  • the output of the first controlled switch is set to ground through a protective resistor.
  • the display switch circuit includes a third controlled switch and a fourth controlled switch
  • the input terminal of the third controlled switch and the input terminal of the fourth controlled switch are the input terminals of the display switch circuit, the output terminal of the third controlled switch is the first output terminal of the display switch circuit, and the output of the fourth controlled switch The terminal is the second output terminal of the display switch circuit;
  • the controlled end When the controlled end receives the same control signal, the input end and output end of the third controlled switch are on, and the input end and output end of the fourth controlled switch are off; or, the input end of the third controlled switch and The output is turned off, and the input and output of the fourth controlled switch are turned on.
  • the third controlled switch includes a second N-channel field effect transistor, and the fourth controlled switch includes a second P-channel field effect transistor;
  • the controlled end of the third controlled switch is the gate of the second N-channel field effect transistor
  • the controlled end of the fourth controlled switch is the gate of the second P-channel field effect transistor.
  • the reference switch circuit includes a fifth controlled switch and a sixth controlled switch
  • the input terminal of the fifth controlled switch and the input terminal of the sixth controlled switch are the input terminal of the reference switch circuit, the output terminal of the fifth controlled switch is the first output terminal of the reference switch circuit, and the output of the sixth controlled switch End is the second output end of the reference switch circuit;
  • the controlled end When the controlled end receives the same control signal, the input end and output end of the fifth controlled switch are on, and the input end and output end of the sixth controlled switch are off; or, the input end of the fifth controlled switch and The output terminal is turned off, and the input terminal and output terminal of the sixth controlled switch are turned on.
  • the fifth controlled switch includes a second P-channel field effect transistor, and the sixth controlled switch includes a second N-channel field effect transistor;
  • the controlled end of the fifth controlled switch is the gate of the second P-channel field effect transistor
  • the controlled terminal of the sixth controlled switch is the gate of the second N-channel field effect transistor.
  • a display driving device includes a timing controller, a source thin film driving chip, a gate thin film driving chip, and a driving circuit; the timing controller is respectively connected to the source thin film driving chip and the gate thin film driving chip;
  • the driving circuit includes a signal processing circuit and a controlled switch circuit; each controlled switch circuit corresponds to each sub-pixel in one-to-one correspondence;
  • the signal processing circuit is connected to the line start signal of the timing controller, and outputs a control signal according to a line start signal;
  • the controlled switch circuit includes a display switch circuit and a reference switch circuit
  • the input terminal of the display switch circuit is connected to the display signal output by the source thin film driver chip, the controlled terminal of the display switch circuit is connected to the control signal, and the first output terminal of the display switch circuit is set as a source connected to the transistor corresponding to the first part of the sub-pixel Electrode, the second output terminal of the display switch circuit is set to connect to the source of the transistor corresponding to the second part of the sub-pixel;
  • the input terminal of the reference switch circuit is set to connect to the reference voltage
  • the controlled terminal of the reference switch circuit is connected to the control signal
  • the first output terminal of the reference switch circuit is set to connect to the reference voltage terminal of the first part of the corresponding sub-pixel.
  • the second output terminal is set to connect to the reference voltage terminal of the second part of the corresponding sub-pixel;
  • the gate thin film driving chip is arranged to connect the gates of the transistors in each part of each sub-pixel;
  • a control signal can make the display switch circuit turn on its input end and first output end, make the reference switch circuit turn on its input end and second output end; or, make the display switch circuit turn on its input end and second output end So that the reference switch circuit conducts its input end and the first output end.
  • the signal processing circuit includes a D flip-flop, a first controlled switch, and a second controlled switch;
  • the input terminal of the first controlled switch is set to access a logic high voltage; the input terminal of the second controlled switch is set to ground;
  • the output terminal of the first controlled switch is set to be connected to the output terminal of the second controlled switch, and is set to ground, and is also set to output the control signal;
  • the control end of the D flip-flop is set to access the line start signal, the pulse input end of the D flip-flop is connected to the output end of the first controlled switch, and the output end of the D flip-flop is connected to the controlled end of the first controlled switch and the first The controlled end of the controlled switch;
  • the input end and output end of the first controlled switch are turned on, and the input end and output end of the second controlled switch are turned off; or, the first controlled switch The input end and output end of the are off, and the input end and output end of the second controlled switch are on.
  • the D flip-flop includes a rising edge D flip-flop.
  • the first controlled switch includes a first P-channel field effect transistor, and the second controlled switch includes a first N-channel field effect transistor;
  • the controlled end of the first controlled switch is the gate of the first P-channel field effect transistor
  • the controlled terminal of the second controlled switch is the gate of the first N-channel field effect transistor.
  • the signal processing circuit further includes a protection resistor
  • the output of the first controlled switch is set to ground through a protective resistor.
  • the display switch circuit includes a third controlled switch and a fourth controlled switch
  • the input terminal of the third controlled switch and the input terminal of the fourth controlled switch are the input terminals of the display switch circuit, the output terminal of the third controlled switch is the first output terminal of the display switch circuit, and the output of the fourth controlled switch The terminal is the second output terminal of the display switch circuit;
  • the controlled end When the controlled end receives the same control signal, the input end and output end of the third controlled switch are on, and the input end and output end of the fourth controlled switch are off; or, the input end of the third controlled switch and The output is turned off, and the input and output of the fourth controlled switch are turned on.
  • the third controlled switch includes a second N-channel field effect transistor, and the fourth controlled switch includes a second P-channel field effect transistor;
  • the controlled end of the third controlled switch is the gate of the second N-channel field effect transistor
  • the controlled end of the fourth controlled switch is the gate of the second P-channel field effect transistor.
  • the reference switch circuit includes a fifth controlled switch and a sixth controlled switch
  • the input terminal of the fifth controlled switch and the input terminal of the sixth controlled switch are the input terminal of the reference switch circuit, the output terminal of the fifth controlled switch is the first output terminal of the reference switch circuit, and the output of the sixth controlled switch End is the second output end of the reference switch circuit;
  • the controlled end When the controlled end receives the same control signal, the input end and output end of the fifth controlled switch are on, and the input end and output end of the sixth controlled switch are off; or, the input end of the fifth controlled switch and The output terminal is turned off, and the input terminal and output terminal of the sixth controlled switch are turned on.
  • the fifth controlled switch includes a second P-channel field effect transistor, and the sixth controlled switch includes a second N-channel field effect transistor;
  • the controlled end of the fifth controlled switch is the gate of the second P-channel field effect transistor
  • the controlled terminal of the sixth controlled switch is the gate of the second N-channel field effect transistor.
  • a display device including a display driving device, a backlight board and a display array
  • the display driving device includes a timing controller, a source thin film driving chip, a gate thin film driving chip and a driving circuit; the timing controller is respectively connected to the source thin film driving chip and the gate thin film driving chip;
  • the driving circuit includes a signal processing circuit and a controlled switch circuit; each controlled switch circuit corresponds to each sub-pixel in one-to-one correspondence;
  • the signal processing circuit is connected to the line start signal of the timing controller, and outputs a control signal according to a line start signal;
  • the controlled switch circuit includes a display switch circuit and a reference switch circuit
  • the input terminal of the display switch circuit is connected to the display signal output by the source thin film driver chip, the controlled terminal of the display switch circuit is connected to the control signal, and the first output terminal of the display switch circuit is set as a source connected to the transistor corresponding to the first part of the sub-pixel Electrode, the second output terminal of the display switch circuit is set to connect to the source of the transistor corresponding to the second part of the sub-pixel;
  • the input terminal of the reference switch circuit is set to connect to the reference voltage
  • the controlled terminal of the reference switch circuit is connected to the control signal
  • the first output terminal of the reference switch circuit is set to connect to the reference voltage terminal of the first part of the corresponding sub-pixel.
  • the second output terminal is set to connect to the reference voltage terminal of the second part of the corresponding sub-pixel;
  • the gate thin film driving chip is arranged to connect the gates of the transistors in each part of each sub-pixel;
  • a control signal can make the display switch circuit turn on its input end and first output end, make the reference switch circuit turn on its input end and second output end; or, make the display switch circuit turn on its input end and second output end To make the reference switch circuit turn on its input end and the first output end;
  • the display array is respectively connected to the source thin film driving chip and the gate thin film driving chip;
  • the backlight panel is configured to provide a light source to the display array.
  • the display array includes a liquid crystal display array.
  • FIG. 1 is a circuit structural diagram of a driving circuit according to one or more embodiments
  • FIG. 2 is a circuit structural diagram of another driving circuit according to one or more embodiments.
  • FIG. 3 is a driving circuit diagram according to one or more embodiments
  • FIG. 4 is a structural diagram of still another driving circuit according to one or more embodiments.
  • FIG. 5 is another driving circuit diagram according to one or more embodiments.
  • FIG. 6 is a structural diagram of still another driving circuit according to one or more embodiments.
  • FIG. 7 is yet another driving circuit diagram according to one or more embodiments.
  • FIG. 8 is a circuit structural diagram of a display driving device according to one or more embodiments.
  • An embodiment of the present invention provides a driving circuit.
  • a driving circuit of an embodiment includes a signal processing circuit 100 and a controlled switch circuit 101; in one of the examples, each The controlled switch circuit 101 corresponds to each sub-pixel one by one;
  • the signal processing circuit 100 is set to access the line start signal STV of the timing controller, and output a control signal according to a line start signal STV;
  • the line start signal STV is a pulse-shaped signal, that is, the line start signal STV is a pulse signal one by one.
  • the signal processing circuit 100 When receiving a line start signal STV, the signal processing circuit 100 outputs a control signal according to the received line start signal STV. When receiving the next line start signal, the signal processing circuit 100 outputs another control signal according to the received new line start signal STV to replace the original control signal.
  • FIG. 2 is a structural diagram of another driving circuit according to one or more embodiments.
  • the signal processing circuit includes a D flip-flop D1, a first controlled switch 200, and a first Two controlled switches 201;
  • the input terminal of the first controlled switch 200 is set to access a logic high voltage VDD; the input terminal of the second controlled switch 201 is set to ground GND;
  • the output terminal of the first controlled switch 200 is set to be connected to the output terminal of the second controlled switch 201, and is set to the ground GND, and is also set to output the control signal;
  • the control terminal C of the D flip-flop D1 is set to access the line start signal STV, the pulse input terminal D of the D flip-flop D1 is connected to the output terminal of the first controlled switch 200, and the output terminal Q of the D flip-flop D1 is connected to the first receiver The controlled end of the control switch 200 and the controlled end of the second controlled switch 201;
  • the D flip-flop D1 when the D flip-flop D1 receives a line start signal STV, it assigns the received logic potential value of the pulse input terminal D to the output terminal Q.
  • the D flip-flop D1 includes a rising edge D flip-flop.
  • a rising edge D flip-flop is used, that is, when a line start signal STV is received, trigger assignment is performed according to the rising edge of the line start signal STV, so as to be more suitable for the characteristics of the line start signal STV.
  • the input terminal and the output terminal of the first controlled switch 200 are turned on, and the input terminal and the output terminal of the second controlled switch 201 Turn off; or, the input end and output end of the first controlled switch 200 are turned off, and the input end and output end of the second controlled switch 201 are turned on.
  • the logic level output from the output of the D flip-flop D1 is unique.
  • the first controlled switch 200 and the second controlled switch 201 are selectively turned on, that is, only the input end and the output end of the first controlled switch 200 are turned on, or the second controlled switch 201 The input and output terminals are on, and the other is off.
  • the control signal is a logic high voltage VDD; if the input terminal and output terminal of the second controlled switch 201 are turned on, The control signal is the ground potential, that is, the logic low voltage.
  • the logic low voltage of the control signal In the initial state, because the output of the first controlled switch 200 is grounded, the logic low voltage of the control signal. That is, the D input terminal of the D flip-flop D1 is a logic low-level voltage.
  • the D input value of the pulse input terminal of the D flip-flop D1 is assigned to the output terminal Q.
  • the output terminal Q outputs a logic low voltage, and the first controlled switch 200 is turned on.
  • the two controlled switches 101 are closed.
  • the control signal is a logic high voltage.
  • the output D of the D flip-flop D1 is a logic high voltage.
  • the D input value of the pulse input terminal of the D flip-flop D1 is assigned to the output terminal Q.
  • the output terminal Q outputs a logic high voltage
  • the second controlled switch 201 is turned on
  • the first controlled switch 100 is turned off .
  • the control signal is a logic low voltage.
  • the output D of the D flip-flop D1 is a logic low voltage.
  • the first controlled switch 200 and the second controlled switch 201 include three-terminal switching elements such as electronic switches or field effect transistors.
  • FIG. 3 is a driving circuit diagram according to one or more embodiments.
  • the first controlled switch 200 includes a first P-channel field effect transistor M1 and a second controlled switch 201 Including the first N-channel field effect transistor M2;
  • the controlled end of the first controlled switch 200 is the gate of the first P-channel field effect transistor M1;
  • the controlled terminal of the second controlled switch 201 is the gate of the first N-channel field effect transistor M2.
  • the gate of the first P-channel field effect transistor M1 is turned on when it receives a logic low voltage, and vice versa; the gate of the first N-channel field effect transistor M2 is on Turns on when a logic high voltage is received, otherwise turns off. Based on this, the first controlled switch 200 and the second controlled switch 201 are selectively turned on.
  • the controlled switch circuit 101 includes a display switch circuit 1010 and a reference switch circuit 1011;
  • the input terminal of the display switch circuit 1010 is set to access the display signal output by the source thin film driver chip, the controlled terminal of the display switch circuit 1010 is connected to the control signal, and the first output terminal of the display switch circuit 1010 is set to connect the corresponding sub-pixel
  • the source of a part of the transistor, the second output terminal of the display switch circuit 1010 is set to connect to the source of the transistor of the second part of the corresponding sub-pixel;
  • the display switch circuit 1010 is configured to turn on its input terminal and the first output terminal, or turn on its input terminal and the second output terminal according to the received control signal. In one of the embodiments, the display switch circuit 1010 is turned on at any time, and the input terminal is only turned on with one output terminal in one of the embodiments, that is, the other is turned on.
  • the display signal output by the source thin film driver chip is transmitted to the source of the transistor corresponding to the first part of the sub-pixel, and when the gate of the transistor of the first part receives the gate-on signal, The pixel electrode corresponding to the first part of the sub-pixel is powered on for display.
  • the display signal output by the source thin film driver chip is transmitted to the source of the transistor of the second part of the corresponding subpixel, and the gate of the transistor of the second part receives the gate-on signal At this time, the pixel electrode corresponding to the second part of the sub-pixel is powered on for display.
  • the signal processing circuit 100 further includes a protection resistor R1;
  • the output terminal of the first controlled switch 200 is set to be grounded through the protection resistor R1.
  • the protection resistor R1 prevents the output terminal of the first controlled switch 200 from being short-circuited to the ground terminal.
  • FIG. 4 is a structural diagram of yet another driving circuit according to one or more embodiments.
  • the display switch circuit 1010 includes a third controlled switch 300 and a fourth controlled switch 301;
  • the controlled terminal of the third controlled switch 300 and the controlled terminal of the fourth controlled switch 301 access control signals;
  • the input terminal of the third controlled switch 300 and the input terminal of the fourth controlled switch 301 are the input terminals of the display switch circuit 1010, and the output terminal of the third controlled switch 300 is the first output terminal of the display switch circuit 1010, the fourth The output terminal of the controlled switch 301 is the second output terminal of the display switch circuit 1010;
  • the input end and output end of the third controlled switch 300 are turned on, and the input end and output end of the fourth controlled switch 301 are turned off; or, The input terminal and the output terminal of the third controlled switch 300 are turned off, and the input terminal and the output terminal of the fourth controlled switch 301 are turned on.
  • the third controlled switch 300 and the fourth controlled switch 301 when receiving any control signal, are turned on, that is, only the input terminal and output of the third controlled switch 300 are available at any time.
  • the terminal is turned on, or the input terminal and the output terminal of the fourth controlled switch 301 are turned on. Based on this, the display switch circuit 1010 is selectively turned on.
  • FIG. 5 is another driving circuit diagram according to one or more embodiments.
  • the third controlled switch 300 includes a second N-channel field effect transistor M3 and a fourth controlled
  • the switch 301 includes a second P-channel field effect transistor M4;
  • the controlled terminal of the third controlled switch 300 is the gate of the second N-channel field effect transistor M3;
  • the controlled terminal of the fourth controlled switch 301 is the gate of the second P-channel field effect transistor M4.
  • the gate of the second P-channel field effect transistor M4 is turned on when it receives a logic low voltage, and vice versa; the gate of the second N-channel field effect transistor M3 is on Turns on when a logic high voltage is received, otherwise turns off. Based on this, the third controlled switch 300 and the fourth controlled switch 301 are selectively turned on.
  • the input terminal of the reference switch circuit 1011 is set to access the reference voltage VCOM, the controlled terminal of the reference switch circuit 1011 is connected to the control signal, and the first output terminal of the reference switch circuit 1011 is set to the reference voltage terminal connected to the first part of the corresponding sub-pixel.
  • the second output terminal of the reference switch circuit 1011 is set to connect to the reference voltage terminal of the second part of the corresponding sub-pixel;
  • the reference switch circuit 1011 is configured to turn on its input terminal and the first output terminal, or turn on its input terminal and the second output terminal according to the received control signal. In one of the embodiments, the reference switch circuit 1011 at any time, the input terminal is connected to only one output terminal in one of the embodiments, that is, one of the two terminals is turned on.
  • the reference voltage terminal corresponding to the first part of the sub-pixel receives the reference voltage VCOM
  • the pixel electrode of the first part of the sub-pixel is charged to the reference voltage VCOM.
  • the reference voltage terminal corresponding to the second part of the sub-pixel receives the reference voltage VCOM
  • the pixel electrode of the second part of the sub-pixel is charged to the reference voltage VCOM.
  • FIG. 6 is a structural diagram of still another driving circuit according to one or more embodiments.
  • the reference switch circuit 1011 includes a fifth controlled switch 400 and a sixth controlled switch 401;
  • the controlled end of the fifth controlled switch 400 and the controlled end of the sixth controlled switch 401 access control signals;
  • the input terminal of the fifth controlled switch 400 and the input terminal of the sixth controlled switch 401 are the input terminals of the reference switch circuit, the output terminal of the fifth controlled switch 400 is the first output terminal of the reference switch circuit 1011, and the sixth The output terminal of the control switch 401 is the second output terminal of the reference switch circuit 1011;
  • the input end and output end of the fifth controlled switch 400 are turned on, and the input end and output end of the sixth controlled switch 401 are turned off; or, The input terminal and the output terminal of the fifth controlled switch 400 are turned off, and the input terminal and the output terminal of the sixth controlled switch 401 are turned on.
  • FIG. 7 is another driving circuit diagram according to one or more embodiments.
  • the fifth controlled switch 400 includes a third P-channel field effect transistor M5, and the sixth controlled
  • the switch 401 includes a third N-channel field effect transistor M6;
  • the controlled end of the fifth controlled switch 400 is the gate of the third P-channel field effect transistor M5;
  • the controlled terminal of the sixth controlled switch 401 is the gate of the third N-channel field effect transistor M6.
  • the gate of the third P-channel field effect transistor M5 is turned on when it receives a logic low voltage, and vice versa; the gate of the third N-channel field effect transistor M6 is on Turns on when a logic high voltage is received, otherwise turns off. Based on this, the fifth controlled switch 400 and the sixth controlled switch 401 are selectively turned on.
  • a control signal can make the display switch circuit 1010 turn on its input end and the first output end, make the reference switch circuit 1011 turn on its input end and the second output end; or, make the display switch circuit 1010 Turning on the input terminal and the second output terminal, so that the reference switch circuit 1011 turns on the input terminal and the first output terminal.
  • the embodiment of the invention also provides a display driving device.
  • a display driving device of an embodiment includes a timing controller 500, a source thin film driving chip 501, and a gate thin film driving chip 502 and the driving circuit 503; in one of the embodiments, the timing controller 500 is connected to the source thin film driving chip 501 and the gate thin film driving chip 502, respectively;
  • the driving circuit 503 includes a signal processing circuit 100 and a controlled switch circuit 101; in one embodiment, each controlled switch circuit 101 corresponds to each sub-pixel in one-to-one correspondence;
  • the signal processing circuit 100 is connected to the line start signal STV of the timing controller 500, and outputs a control signal according to a line start signal;
  • the controlled switch circuit 101 includes a display switch circuit 1010 and a reference switch circuit 1011;
  • the input terminal of the display switch circuit 1010 is connected to the display signal output by the source thin film driver chip 501, the controlled terminal of the display switch circuit 1010 is connected to the control signal, and the first output terminal of the display switch circuit 1010 is set to connect to the first part of the corresponding sub-pixel
  • the source of the transistor, the second output of the display switch circuit 1010 is set to connect to the source of the transistor corresponding to the second part of the sub-pixel;
  • the input terminal of the reference switch circuit 1011 is set to access the reference voltage VCOM, the controlled terminal of the reference switch circuit 1011 is connected to the control signal, and the first output terminal of the reference switch circuit 1011 is set to the reference voltage terminal connected to the first part of the corresponding sub-pixel.
  • the second output terminal of the reference switch circuit 1011 is set to connect to the reference voltage terminal of the second part of the corresponding sub-pixel;
  • the gate thin film driving chip 502 is arranged to connect the gates of the transistors in each part of each sub-pixel;
  • a control signal can make the display switch circuit 1010 turn on its input end and the first output end, make the reference switch circuit 1011 turn on its input end and the second output end; or, make the display switch circuit 1010 Turning on the input terminal and the second output terminal, so that the reference switch circuit 1011 turns on the input terminal and the first output terminal.
  • the signal processing circuit 100 outputs a control signal according to a line start signal STV.
  • a line start signal STV When any control signal is applied, only the display signal output to the corresponding source of a part of the transistor source in one of the embodiments is connected to the corresponding sub-pixel, so that this part completes the display of the sub-pixel.
  • the reference voltage VCOM is connected to the reference voltage terminal of the other part of the corresponding sub-pixel, so that the pixel electrode of the other part is charged to the reference voltage VCOM.
  • the pixel electrode When the next control signal of any control signal acts, the pixel electrode is precharged to the reference voltage VCOM to quickly complete the charging, and at the same time, the pixel electrode that is a part of the sub-pixel that performs display when any control signal acts is charged to the reference voltage VCOM. Based on this, before each control signal inversion, a part of the sub-pixel is in operation, and the other part is first precharged to the reference voltage VCOM, thereby improving the charging efficiency of the pixel electrode and ensuring that the voltage on the pixel electrode can be switched to the target voltage.
  • a display device including a display driving device, a backlight board and a display array
  • the display driving device includes a timing controller, a source thin film driving chip, a gate thin film driving chip and a driving circuit; the timing controller is respectively connected to the source thin film driving chip and the gate thin film driving chip;
  • the driving circuit includes a signal processing circuit and a controlled switch circuit; each controlled switch circuit corresponds to each sub-pixel in one-to-one correspondence;
  • the signal processing circuit is connected to the line start signal of the timing controller, and outputs a control signal according to a line start signal;
  • the controlled switch circuit includes a display switch circuit and a reference switch circuit
  • the input terminal of the display switch circuit is connected to the display signal output by the source thin film driver chip, the controlled terminal of the display switch circuit is connected to the control signal, and the first output terminal of the display switch circuit is set as a source connected to the transistor corresponding to the first part of the sub-pixel Electrode, the second output terminal of the display switch circuit is set to connect to the source of the transistor corresponding to the second part of the sub-pixel;
  • the input terminal of the reference switch circuit is set to connect to the reference voltage
  • the controlled terminal of the reference switch circuit is connected to the control signal
  • the first output terminal of the reference switch circuit is set to connect to the reference voltage terminal of the first part of the corresponding sub-pixel.
  • the second output terminal is set to connect to the reference voltage terminal of the second part of the corresponding sub-pixel;
  • the gate thin film driving chip is arranged to connect the gates of the transistors in each part of each sub-pixel;
  • a control signal can make the display switch circuit turn on its input end and first output end, make the reference switch circuit turn on its input end and second output end; or, make the display switch circuit turn on its input end and second output end To make the reference switch circuit turn on its input end and the first output end;
  • the display array is respectively connected to the source thin film driving chip and the gate thin film driving chip;
  • the backlight panel is configured to provide a light source to the display array.
  • the display array includes a liquid crystal display array.

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Abstract

一种驱动电路及显示驱动装置包括：在信号处理模块在任一控制信号作用时，只导通显示信号输出至对应子像素的其中一部分的晶体管源极的通路，使这部分完成子像素的显示。同时将基准电压接入对应子像素的另一部分的基准电压端，使另一部分的像素电极充电至基准电压。基于此，在每次控制信号翻转前，子像素的一部分处于工作，另一部分先预充至基准电压，以此提高像素电极的充电效率，保证像素电极上的电压可切换至目标电压。

Description

驱动电路及显示驱动装置
本申请要求于2018年10月29日提交中国专利局，申请号为2018112699246，申请名称为“驱动电路及显示驱动装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及一种驱动电路及显示驱动装置。
背景技术
液晶显示面板是由一定数量的彩色或黑白像素组成，放置于光源或反射面前方的显示设备。在其中一个实施例中，TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示面板)是当前液晶显示面板的主要品种之一，已经成为了现代IT、视讯产品中重要的显示平台。以TFT-LCD的显示驱动为例，系统主板将R/G/B压缩信号、控制信号及电源通过线材与PCB板上的connector相连接，数据经过PCB板上的TCON(Timing Controller，时序控制器)IC处理后，经PCB板，通过S-COF(Source-Chip on Film，源级薄膜驱动芯片)和G-COF(Gate-Chip on Film，栅极薄膜驱动芯片)与显示区连接，通过显示阵列上的Data line(数据线)和Scan line(扫描线)对电压进行传输，从而使TFT-LCD实现显示功能。在其中一个实施例中，使TFT-LCD实现显示功能的信号包括TCON输出的行起始信号、G-COF输出至晶体管栅极的栅极开启信号和S-COF输出至晶体管源极的显示信号。
同时，在液晶显示面板中，一个子像素一般分为两个相互独立的部分，各部分均包括一个像素电极，通过两个部分实现子像素的显示。由于液晶的材料特性，以相同的电压长时间作设置为液晶上，会导致液晶极化，造成显示异常。因此，TFT-LCD在显示过程中需要基准电压，然后将高于基准电压的电压值定义为正极性，低于基准电压的电压值定义为负极性。显示过程中，作设置为液晶上的电压每一帧会从正极性与负极性之间切换，以避免液晶极化。因为充电时间不足，直接将像素电极上的电压从正极性切换为负极性，跨压较大，会造成充电不足，即在有限的充电时间内无法将像素电极上的电压切换至目标电压。
发明内容
根据本申请公开的各种实施例，提供一种驱动电路及显示驱动装置。
一种驱动电路，包括信号处理电路和受控开关电路；各受控开关电路与各子像素一一对应；
信号处理电路设置为接入时序控制器的行起始信号，并根据一个行起始信号输出一个控制信号；
受控开关电路包括显示开关电路和基准开关电路；
显示开关电路的输入端设置为接入源极薄膜驱动芯片输出的显示信号，显示开关电路的受控端接入控制信号，显示开关电路的第一输出端设置为连接对应子像素第一部分的晶体管的源极，显示开关电路的第二输出端设置为连接对应子像素第二部分的晶体管的源极；
基准开关电路的输入端设置为接入基准电压，基准开关电路的受控端接入控制信号，基准开关电路的第一输出端设置为连接对应子像素第一部分的基准电压端，基准开关电路的第二输出端设置为连接对应子像素第二部分的基准电压端；
一个控制信号可使显示开关电路导通其输入端与第一输出端，使基准开关电路导通其输入端与第二输出端；或，使显示开关电路导通其输入端与第二输出端，使基准开关电路导通其输入端与第一输出端。
在其中一个实施例中，信号处理电路包括D触发器、第一受控开关和第二受控开关；
第一受控开关的输入端设置为接入逻辑高电平电压；第二受控开关的输入端设置为接地；
第一受控开关的输出端设置为连接第二受控开关的输出端，并设置为接地，还设置为输出控制信号；
D触发器的控制端设置为接入行起始信号，D触发器的脉冲输入端连接第一受控开关的输出端，D触发器的输出端连接第一受控开关的受控端和第二受控开关的受控端；
D触发器的输出端在输出同一逻辑电平电压时，第一受控开关的输入端与输出端导通，第二受控开关的输入端与输出端关断；或，第一受控开关的输入端与输出端关断，第 二受控开关的输入端与输出端导通。
在其中一个实施例中，D触发器包括上升沿D触发器。
在其中一个实施例中，第一受控开关包括第一P沟道场效应管，第二受控开关包括第一N沟道场效应管；
第一受控开关的受控端为第一P沟道场效应管的栅极；
第二受控开关的受控端为第一N沟道场效应管的栅极。
在其中一个实施例中，信号处理电路还包括保护电阻；
第一受控开关的输出端设置为通过保护电阻接地。
在其中一个实施例中，显示开关电路包括第三受控开关和第四受控开关；
第三受控开关的受控端和第四受控开关的受控端接入控制信号；
第三受控开关的输入端和第四受控开关的输入端为显示开关电路的输入端，第三受控开关的输出端为显示开关电路的第一输出端，第四受控开关的输出端为显示开关电路的第二输出端；
在受控端接收到同一控制信号时，第三受控开关的输入端与输出端导通，第四受控开关的输入端与输出端关断；或，第三受控开关的输入端与输出端关断，第四受控开关的输入端与输出端导通。
在其中一个实施例中，第三受控开关包括第二N沟道场效应管，第四受控开关包括第二P沟道场效应管；
第三受控开关的受控端为第二N沟道场效应管的栅极；
第四受控开关的受控端为第二P沟道场效应管的栅极。
在其中一个实施例中，基准开关电路包括第五受控开关和第六受控开关；
第五受控开关的受控端和第六受控开关的受控端接入控制信号；
第五受控开关的输入端和第六受控开关的输入端为基准开关电路的输入端，第五受控开关的输出端为基准开关电路的第一输出端，第六受控开关的输出端为基准开关电路的第二输出端；
在受控端接收到同一控制信号时，第五受控开关的输入端与输出端导通，第六受控开关的输入端与输出端关断；或，第五受控开关的输入端与输出端关断，第六受控开关的输 入端与输出端导通。
在其中一个实施例中，第五受控开关包括第二P沟道场效应管，第六受控开关包括第二N沟道场效应管；
第五受控开关的受控端为第二P沟道场效应管的栅极；
第六受控开关的受控端为第二N沟道场效应管的栅极。
一种显示驱动装置，包括时序控制器、源极薄膜驱动芯片、栅极薄膜驱动芯片和驱动电路；时序控制器分别连接源极薄膜驱动芯片和栅极薄膜驱动芯片；
驱动电路包括信号处理电路和受控开关电路；各受控开关电路与各子像素一一对应；
信号处理电路接入时序控制器的行起始信号，并根据一个行起始信号输出一个控制信号；
受控开关电路包括显示开关电路和基准开关电路；
显示开关电路的输入端接入源极薄膜驱动芯片输出的显示信号，显示开关电路的受控端接入控制信号，显示开关电路的第一输出端设置为连接对应子像素第一部分的晶体管的源极，显示开关电路的第二输出端设置为连接对应子像素第二部分的晶体管的源极；
基准开关电路的输入端设置为接入基准电压，基准开关电路的受控端接入控制信号，基准开关电路的第一输出端设置为连接对应子像素第一部分的基准电压端，基准开关电路的第二输出端设置为连接对应子像素第二部分的基准电压端；
栅极薄膜驱动芯片设置为连接各子像素中各部分的晶体管的栅极；
一个控制信号可使显示开关电路导通其输入端与第一输出端，使基准开关电路导通其输入端与第二输出端；或，使显示开关电路导通其输入端与第二输出端，使基准开关电路导通其输入端与第一输出端。
在其中一个实施例中，信号处理电路包括D触发器、第一受控开关和第二受控开关；
第一受控开关的输入端设置为接入逻辑高电平电压；第二受控开关的输入端设置为接地；
第一受控开关的输出端设置为连接第二受控开关的输出端，并设置为接地，还设置为输出控制信号；
D触发器的控制端设置为接入行起始信号，D触发器的脉冲输入端连接第一受控开关 的输出端，D触发器的输出端连接第一受控开关的受控端和第二受控开关的受控端；
D触发器的输出端在输出同一逻辑电平电压时，第一受控开关的输入端与输出端导通，第二受控开关的输入端与输出端关断；或，第一受控开关的输入端与输出端关断，第二受控开关的输入端与输出端导通。
在其中一个实施例中，D触发器包括上升沿D触发器。
在其中一个实施例中，第一受控开关包括第一P沟道场效应管，第二受控开关包括第一N沟道场效应管；
第一受控开关的受控端为第一P沟道场效应管的栅极；
第二受控开关的受控端为第一N沟道场效应管的栅极。
在其中一个实施例中，信号处理电路还包括保护电阻；
第一受控开关的输出端设置为通过保护电阻接地。
在其中一个实施例中，显示开关电路包括第三受控开关和第四受控开关；
第三受控开关的受控端和第四受控开关的受控端接入控制信号；
第三受控开关的输入端和第四受控开关的输入端为显示开关电路的输入端，第三受控开关的输出端为显示开关电路的第一输出端，第四受控开关的输出端为显示开关电路的第二输出端；
在受控端接收到同一控制信号时，第三受控开关的输入端与输出端导通，第四受控开关的输入端与输出端关断；或，第三受控开关的输入端与输出端关断，第四受控开关的输入端与输出端导通。
在其中一个实施例中，第三受控开关包括第二N沟道场效应管，第四受控开关包括第二P沟道场效应管；
第三受控开关的受控端为第二N沟道场效应管的栅极；
第四受控开关的受控端为第二P沟道场效应管的栅极。
在其中一个实施例中，基准开关电路包括第五受控开关和第六受控开关；
第五受控开关的受控端和第六受控开关的受控端接入控制信号；
第五受控开关的输入端和第六受控开关的输入端为基准开关电路的输入端，第五受控开关的输出端为基准开关电路的第一输出端，第六受控开关的输出端为基准开关电路的第 二输出端；
在受控端接收到同一控制信号时，第五受控开关的输入端与输出端导通，第六受控开关的输入端与输出端关断；或，第五受控开关的输入端与输出端关断，第六受控开关的输入端与输出端导通。
在其中一个实施例中，第五受控开关包括第二P沟道场效应管，第六受控开关包括第二N沟道场效应管；
第五受控开关的受控端为第二P沟道场效应管的栅极；
第六受控开关的受控端为第二N沟道场效应管的栅极。
一种显示装置，包括显示驱动装置、背光板和显示阵列；
显示驱动装置包括时序控制器、源极薄膜驱动芯片、栅极薄膜驱动芯片和驱动电路；时序控制器分别连接源极薄膜驱动芯片和栅极薄膜驱动芯片；
驱动电路包括信号处理电路和受控开关电路；各受控开关电路与各子像素一一对应；
信号处理电路接入时序控制器的行起始信号，并根据一个行起始信号输出一个控制信号；
受控开关电路包括显示开关电路和基准开关电路；
显示开关电路的输入端接入源极薄膜驱动芯片输出的显示信号，显示开关电路的受控端接入控制信号，显示开关电路的第一输出端设置为连接对应子像素第一部分的晶体管的源极，显示开关电路的第二输出端设置为连接对应子像素第二部分的晶体管的源极；
基准开关电路的输入端设置为接入基准电压，基准开关电路的受控端接入控制信号，基准开关电路的第一输出端设置为连接对应子像素第一部分的基准电压端，基准开关电路的第二输出端设置为连接对应子像素第二部分的基准电压端；
栅极薄膜驱动芯片设置为连接各子像素中各部分的晶体管的栅极；
一个控制信号可使显示开关电路导通其输入端与第一输出端，使基准开关电路导通其输入端与第二输出端；或，使显示开关电路导通其输入端与第二输出端，使基准开关电路导通其输入端与第一输出端；
显示阵列分别连接源极薄膜驱动芯片和栅极薄膜驱动芯片；
背光板设置为给显示阵列提供光源。
在其中一个实施例中，显示阵列包括液晶显示阵列。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为根据一个或多个实施例中的驱动电路电路结构图；
图2为根据一个或多个实施例中的另一驱动电路电路结构图；
图3为根据一个或多个实施例中的驱动电路图；
图4为根据一个或多个实施例中的又一驱动电路电路结构图；
图5为根据一个或多个实施例中的另一驱动电路图；
图6为根据一个或多个实施例中的再一驱动电路电路结构图；
图7为根据一个或多个实施例中的又一驱动电路图；
图8为根据一个或多个实施例中的显示驱动装置电路结构图。
具体实施方式
为了使本申请的技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处描述的具体实施例仅仅用以解释本申请，并不设置为限定本申请。
本发明实施例提供一种驱动电路。
图1为根据一个或多个实施例中的驱动电路电路结构图，如图1所示，一实施方式的驱动电路包括信号处理电路100和受控开关电路101；在其中一个实施例中，各受控开关电路101与各子像素一一对应；
信号处理电路100设置为接入时序控制器的行起始信号STV，并根据一个行起始信号STV输出一个控制信号；
在其中一个实施例中，行起始信号STV为脉冲形式的信号，即行起始信号STV为一个接一个的脉冲信号。信号处理电路100在接收到一个行起始信号STV时，即根据接收到的行起始信号STV输出一个控制信号。信号处理电路100在接收到下一个行起始信号时，则根据接收到的新的行起始信号STV输出另一个控制信号以替换原控制信号。
在其中一个实施例中，图2为根据一个或多个实施例中的另一驱动电路电路结构图，如图2所示，信号处理电路包括D触发器D1、第一受控开关200和第二受控开关201；
第一受控开关200的输入端设置为接入逻辑高电平电压VDD；第二受控开关201的输入端设置为接地GND；
第一受控开关200的输出端设置为连接第二受控开关201的输出端，并设置为接地GND，还设置为输出控制信号；
D触发器D1的控制端C设置为接入行起始信号STV，D触发器D1的脉冲输入端D连接第一受控开关200的输出端，D触发器D1的输出端Q连接第一受控开关200的受控端和第二受控开关201的受控端；
在其中一个实施例中，D触发器D1在接收到一个行起始信号STV时，即将脉冲输入端D的接收到的逻辑电位值赋值给输出端Q。
在其中一个实施例中，D触发器D1包括上升沿D触发器。
在其中一个实施例中,采用上升沿D触发器，即在接收到行起始信号STV时，根据行起始信号STV的上升沿进行触发赋值，以更适应行起始信号STV的特点。
在其中一个实施例中，D触发器D1的输出端在输出同一逻辑电平电压时，第一受控开关200的输入端与输出端导通，第二受控开关201的输入端与输出端关断；或，第一受控开关200的输入端与输出端关断，第二受控开关201的输入端与输出端导通。
在其中一个实施例中，在任一时刻，D触发器D1的输出端输出的逻辑电平唯一。在唯一的逻辑电平中，第一受控开关200和第二受控开关201择一开启，即只有第一受控开关200的输入端与输出端导通，或第二受控开关201的输入端与输出端导通，另一关断。在其中一个实施例中，若第一受控开关200的输入端与输出端导通，则控制信号为逻辑高电平电压VDD；若第二受控开关201的输入端与输出端导通，则控制信号为地电位，即逻辑低电平电压。
以下以D触发器D1包括上升沿D触发器，对信号处理电路100的处理过程进行解释：
初始状态时，因为第一受控开关200的输出端接地，所以控制信号的逻辑低电平电压。即D触发器D1的脉冲输入端D端为逻辑低电平电压。
当第一个行起始信号STV到来时，D触发器D1的脉冲输入端D值赋值给输出端Q，此时输出端Q输出为逻辑低电平电压，第一受控开关200开启，第二受控开关101关闭。此时控制信号为逻辑高电平电压。此时D触发器D1的输出端D为逻辑高电平电压。
当下一个STV到来时，D触发器D1的脉冲输入端D值赋值给输出端Q，此时输出端Q输出为逻辑高电平电压，第二受控开关201开启，第一受控开关100关闭。此时控制信号为逻辑低电平电压。此时D触发器D1的输出端D为逻辑低电平电压。
如此循坏反复。
在其中一个实施例中，第一受控开关200和第二受控开关201包括电子开关或场效应管等三端开关元件。
在其中一个实施例中，图3为根据一个或多个实施例中的驱动电路图，如图3所示，第一受控开关200包括第一P沟道场效应管M1，第二受控开关201包括第一N沟道场效应管M2；
第一受控开关200的受控端为第一P沟道场效应管M1的栅极；
第二受控开关201的受控端为第一N沟道场效应管M2的栅极。
在其中一个实施例中，如图3所示，第一P沟道场效应管M1的栅极在接收到逻辑低电平电压时开启，反之关闭；第一N沟道场效应管M2的栅极在接收到逻辑高电平电压时开启，反之关闭。基于此，实现第一受控开关200和第二受控开关201的择一开启。
受控开关电路101包括显示开关电路1010和基准开关电路1011；
显示开关电路1010的输入端设置为接入源极薄膜驱动芯片输出的显示信号，显示开关电路1010的受控端接入控制信号，显示开关电路1010的第一输出端设置为连接对应子像素第一部分的晶体管的源极，显示开关电路1010的第二输出端设置为连接对应子像素第二部分的晶体管的源极；
在其中一个实施例中，显示开关电路1010设置为根据接收到的控制信号，导通其输入端与第一输出端，或导通其输入端与第二输出端。在其中一个实施例中，显示开关电路 1010在任一时刻，输入端只与在其中一个实施例中一个输出端导通，即择一导通。在输入端与第一输出端导通时，源极薄膜驱动芯片输出的显示信号传输至对应子像素第一部分的晶体管的源极，在第一部分的晶体管的栅极接收到栅极开启信号时，对应子像素第一部分的像素电极上电进行显示。在输入端与第二输出端导通时，源极薄膜驱动芯片输出的显示信号传输至对应子像素第二部分的晶体管的源极，在第二部分的晶体管的栅极接收到栅极开启信号时，对应子像素第二部分的像素电极上电进行显示。
在其中一个实施例中，如图3所示，信号处理电路100还包括保护电阻R1；
所述第一受控开关200的输出端设置为通过所述保护电阻R1接地。
通过保护电阻R1，防止第一受控开关200的输出端与接地端短路。
在其中一个实施例中，图4为根据一个或多个实施例中的又一驱动电路电路结构图，如图4所示，显示开关电路1010包括第三受控开关300和第四受控开关301；
第三受控开关300的受控端和第四受控开关301的受控端接入控制信号；
第三受控开关300的输入端和第四受控开关301的输入端为显示开关电路1010的输入端，第三受控开关300的输出端为显示开关电路1010的第一输出端，第四受控开关301的输出端为显示开关电路1010的第二输出端；
在其中一个实施例中，在受控端接收到同一控制信号时，第三受控开关300的输入端与输出端导通，第四受控开关301的输入端与输出端关断；或，第三受控开关300的输入端与输出端关断，第四受控开关301的输入端与输出端导通。
在其中一个实施例中，在接收到任一控制信号时，第三受控开关300和第四受控开关301择一导通，即任一时刻只有第三受控开关300的输入端与输出端导通，或第四受控开关301的输入端与输出端导通。基于此，实现显示开关电路1010的择一导通。
在其中一个实施例中，图5为根据一个或多个实施例中的另一驱动电路图，如图5所示，第三受控开关300包括第二N沟道场效应管M3，第四受控开关301包括第二P沟道场效应管M4；
第三受控开关300的受控端为第二N沟道场效应管M3的栅极；
第四受控开关301的受控端为第二P沟道场效应管M4的栅极。
在其中一个实施例中，如图5所示，第二P沟道场效应管M4的栅极在接收到逻辑低 电平电压时开启，反之关闭；第二N沟道场效应管M3的栅极在接收到逻辑高电平电压时开启，反之关闭。基于此，实现第三受控开关300和第四受控开关301的择一开启。
基准开关电路1011的输入端设置为接入基准电压VCOM，基准开关电路1011的受控端接入控制信号，基准开关电路1011的第一输出端设置为连接对应子像素第一部分的基准电压端，基准开关电路1011的第二输出端设置为连接对应子像素第二部分的基准电压端；
在其中一个实施例中，基准开关电路1011设置为根据接收到的控制信号，导通其输入端与第一输出端，或导通其输入端与第二输出端。在其中一个实施例中，基准开关电路1011在任一时刻，输入端只与在其中一个实施例中一个输出端导通，即择一导通。在输入端与第一输出端导通时，对应子像素第一部分的基准电压端接收到基准电压VCOM，子像素第一部分的像素电极充电至基准电压VCOM。在输入端与第二输出端导通时，对应子像素第二部分的基准电压端接收到基准电压VCOM，子像素第二部分的像素电极充电至基准电压VCOM。
在其中一个实施例中，图6为根据一个或多个实施例中的再一驱动电路电路结构图，如图6所示，基准开关电路1011包括第五受控开关400和第六受控开关401；
第五受控开关400的受控端和第六受控开关401的受控端接入控制信号；
第五受控开关400的输入端和第六受控开关401的输入端为基准开关电路的输入端，第五受控开关400的输出端为基准开关电路1011的第一输出端，第六受控开关401的输出端为基准开关电路1011的第二输出端；
在其中一个实施例中，在受控端接收到同一控制信号时，第五受控开关400的输入端与输出端导通，第六受控开关401的输入端与输出端关断；或，第五受控开关400的输入端与输出端关断，第六受控开关401的输入端与输出端导通。
在其中一个实施例中，图7为根据一个或多个实施例中的又一驱动电路图，如图7所示，第五受控开关400包括第三P沟道场效应管M5，第六受控开关401包括第三N沟道场效应管M6；
第五受控开关400的受控端为第三P沟道场效应管M5的栅极；
第六受控开关401的受控端为第三N沟道场效应管M6的栅极。
在其中一个实施例中，如图7所示，第三P沟道场效应管M5的栅极在接收到逻辑低电平电压时开启，反之关闭；第三N沟道场效应管M6的栅极在接收到逻辑高电平电压时开启，反之关闭。基于此，实现第五受控开关400和第六受控开关401的择一开启。
在其中一个实施例中，一个控制信号可使显示开关电路1010导通其输入端与第一输出端，使基准开关电路1011导通其输入端与第二输出端；或，使显示开关电路1010导通其输入端与第二输出端，使基准开关电路1011导通其输入端与第一输出端。
本发明实施例还提供一种显示驱动装置。
图8为根据一个或多个实施例中的显示驱动装置电路结构图，如图8所示，一实施方式的显示驱动装置包括时序控制器500、源极薄膜驱动芯片501、栅极薄膜驱动芯片502和驱动电路503；在其中一个实施例中，时序控制器500分别连接源极薄膜驱动芯片501和栅极薄膜驱动芯片502；
驱动电路503包括信号处理电路100和受控开关电路101；在其中一个实施例中，各受控开关电路101与各子像素一一对应；
信号处理电路100接入时序控制器500的行起始信号STV，并根据一个行起始信号输出一个控制信号；
受控开关电路101包括显示开关电路1010和基准开关电路1011；
显示开关电路1010的输入端接入源极薄膜驱动芯片501输出的显示信号，显示开关电路1010的受控端接入控制信号，显示开关电路1010的第一输出端设置为连接对应子像素第一部分的晶体管的源极，显示开关电路1010的第二输出端设置为连接对应子像素第二部分的晶体管的源极；
基准开关电路1011的输入端设置为接入基准电压VCOM，基准开关电路1011的受控端接入控制信号，基准开关电路1011的第一输出端设置为连接对应子像素第一部分的基准电压端，基准开关电路1011的第二输出端设置为连接对应子像素第二部分的基准电压端；
栅极薄膜驱动芯片502设置为连接各子像素中各部分的晶体管的栅极；
在其中一个实施例中，一个控制信号可使显示开关电路1010导通其输入端与第一输出端，使基准开关电路1011导通其输入端与第二输出端；或，使显示开关电路1010导通 其输入端与第二输出端，使基准开关电路1011导通其输入端与第一输出端。
上述的驱动电路及显示驱动装置，信号处理电路100根据一个行起始信号STV输出一个控制信号。在任一控制信号作用时，只导通显示信号输出至对应子像素的在其中一个实施例中一部分的晶体管源极的通路，使这部分完成子像素的显示。同时将基准电压VCOM接入对应子像素的另一部分的基准电压端，使另一部分的像素电极充电至基准电压VCOM。在任一控制信号的下一个控制信号作用时，像素电极预充至基准电压VCOM可迅速完成充电，而同时为在任一控制信号作用时进行显示的子像素的一部分的像素电极充电至基准电压VCOM。基于此，在每次控制信号翻转前，子像素的一部分处于工作，另一部分先预充至基准电压VCOM，以此提高像素电极的充电效率，保证像素电极上的电压可切换至目标电压。
本发明实施例还提供一种显示装置：
一种显示装置，包括显示驱动装置、背光板和显示阵列；
显示驱动装置包括时序控制器、源极薄膜驱动芯片、栅极薄膜驱动芯片和驱动电路；时序控制器分别连接源极薄膜驱动芯片和栅极薄膜驱动芯片；
驱动电路包括信号处理电路和受控开关电路；各受控开关电路与各子像素一一对应；
信号处理电路接入时序控制器的行起始信号，并根据一个行起始信号输出一个控制信号；
受控开关电路包括显示开关电路和基准开关电路；
显示开关电路的输入端接入源极薄膜驱动芯片输出的显示信号，显示开关电路的受控端接入控制信号，显示开关电路的第一输出端设置为连接对应子像素第一部分的晶体管的源极，显示开关电路的第二输出端设置为连接对应子像素第二部分的晶体管的源极；
基准开关电路的输入端设置为接入基准电压，基准开关电路的受控端接入控制信号，基准开关电路的第一输出端设置为连接对应子像素第一部分的基准电压端，基准开关电路的第二输出端设置为连接对应子像素第二部分的基准电压端；
栅极薄膜驱动芯片设置为连接各子像素中各部分的晶体管的栅极；
一个控制信号可使显示开关电路导通其输入端与第一输出端，使基准开关电路导通其输入端与第二输出端；或，使显示开关电路导通其输入端与第二输出端，使基准开关电路 导通其输入端与第一输出端；
显示阵列分别连接源极薄膜驱动芯片和栅极薄膜驱动芯片；
背光板设置为给显示阵列提供光源。
在其中一个实施例中，显示阵列包括液晶显示阵列。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种驱动电路，包括信号处理电路和受控开关电路；各受控开关电路与各子像素一一对应；
    所述信号处理电路设置为接入时序控制器的行起始信号，并根据所述一个行起始信号输出一个控制信号；
    所述受控开关电路包括显示开关电路和基准开关电路；
    所述显示开关电路的输入端设置为接入源极薄膜驱动芯片输出的显示信号，所述显示开关电路的受控端接入所述控制信号，所述显示开关电路的第一输出端设置为连接对应子像素第一部分的晶体管的源极，所述显示开关电路的第二输出端设置为连接对应子像素第二部分的晶体管的源极；
    所述基准开关电路的输入端设置为接入基准电压，所述基准开关电路的受控端接入所述控制信号，所述基准开关电路的第一输出端设置为连接对应子像素第一部分的基准电压端，所述基准开关电路的第二输出端设置为连接对应子像素第二部分的基准电压端；
    一个所述控制信号可使所述显示开关电路导通其输入端与第一输出端，使所述基准开关电路导通其输入端与第二输出端；或，使所述显示开关电路导通其输入端与第二输出端，使所述基准开关电路导通其输入端与第一输出端。
  2. 根据权利要求1所述的驱动电路，其特征在于，所述信号处理电路包括D触发器、第一受控开关和第二受控开关；
    所述第一受控开关的输入端设置为接入逻辑高电平电压；所述第二受控开关的输入端设置为接地；
    所述第一受控开关的输出端设置为连接所述第二受控开关的输出端，并设置为接地，还设置为输出所述控制信号；
    所述D触发器的控制端设置为接入所述行起始信号，所述D触发器的脉冲输入端连接所述第一受控开关的输出端，所述D触发器的输出端连接所述第一受控开关的受控端和所述第二受控开关的受控端；
    所述D触发器的输出端在输出同一逻辑电平电压时，所述第一受控开关的输入端与输出端导通，所述第二受控开关的输入端与输出端关断；或，所述第一受控开关的输入端与 输出端关断，所述第二受控开关的输入端与输出端导通。
  3. 根据权利要求2所述的驱动电路，其特征在于，所述D触发器包括上升沿D触发器。
  4. 根据权利要求2所述的驱动电路，其特征在于，所述第一受控开关包括第一P沟道场效应管，所述第二受控开关包括第一N沟道场效应管；
    所述第一受控开关的受控端为所述第一P沟道场效应管的栅极；
    所述第二受控开关的受控端为所述第一N沟道场效应管的栅极。
  5. 根据权利要求2所述的驱动电路，其特征在于，所述信号处理电路还包括保护电阻；
    所述第一受控开关的输出端设置为通过所述保护电阻接地。
  6. 根据权利要求1所述的驱动电路，其特征在于，所述显示开关电路包括第三受控开关和第四受控开关；
    所述第三受控开关的受控端和所述第四受控开关的受控端接入所述控制信号；
    所述第三受控开关的输入端和所述第四受控开关的输入端为所述显示开关电路的输入端，所述第三受控开关的输出端为所述显示开关电路的第一输出端，所述第四受控开关的输出端为所述显示开关电路的第二输出端；
    在受控端接收到同一所述控制信号时，所述第三受控开关的输入端与输出端导通，所述第四受控开关的输入端与输出端关断；或，所述第三受控开关的输入端与输出端关断，所述第四受控开关的输入端与输出端导通。
  7. 根据权利要求6所述的驱动电路，其特征在于，所述第三受控开关包括第二N沟道场效应管，所述第四受控开关包括第二P沟道场效应管；
    所述第三受控开关的受控端为所述第二N沟道场效应管的栅极；
    所述第四受控开关的受控端为所述第二P沟道场效应管的栅极。
  8. 根据权利要求1所述的驱动电路，其特征在于，所述基准开关电路包括第五受控开关和第六受控开关；
    所述第五受控开关的受控端和所述第六受控开关的受控端接入所述控制信号；
    所述第五受控开关的输入端和所述第六受控开关的输入端为所述基准开关电路的输 入端，所述第五受控开关的输出端为所述基准开关电路的第一输出端，所述第六受控开关的输出端为所述基准开关电路的第二输出端；
    在受控端接收到同一所述控制信号时，所述第五受控开关的输入端与输出端导通，所述第六受控开关的输入端与输出端关断；或，所述第五受控开关的输入端与输出端关断，所述第六受控开关的输入端与输出端导通。
  9. 根据权利要求8所述的驱动电路，其特征在于，所述第五受控开关包括第二P沟道场效应管，所述第六受控开关包括第二N沟道场效应管；
    所述第五受控开关的受控端为所述第二P沟道场效应管的栅极；
    所述第六受控开关的受控端为所述第二N沟道场效应管的栅极。
  10. 一种显示驱动装置，包括时序控制器、源极薄膜驱动芯片、栅极薄膜驱动芯片和驱动电路；所述时序控制器分别连接所述源极薄膜驱动芯片和所述栅极薄膜驱动芯片；
    所述驱动电路包括信号处理电路和受控开关电路；各受控开关电路与各子像素一一对应；
    所述信号处理电路接入所述时序控制器的行起始信号，并根据所述一个行起始信号输出一个控制信号；
    所述受控开关电路包括显示开关电路和基准开关电路；
    所述显示开关电路的输入端接入所述源极薄膜驱动芯片输出的显示信号，所述显示开关电路的受控端接入所述控制信号，所述显示开关电路的第一输出端设置为连接对应子像素第一部分的晶体管的源极，所述显示开关电路的第二输出端设置为连接对应子像素第二部分的晶体管的源极；
    所述基准开关电路的输入端设置为接入基准电压，所述基准开关电路的受控端接入所述控制信号，所述基准开关电路的第一输出端设置为连接对应子像素第一部分的基准电压端，所述基准开关电路的第二输出端设置为连接对应子像素第二部分的基准电压端；
    所述栅极薄膜驱动芯片设置为连接各子像素中各部分的晶体管的栅极；
    一个所述控制信号可使所述显示开关电路导通其输入端与第一输出端，使所述基准开关电路导通其输入端与第二输出端；或，使所述显示开关电路导通其输入端与第二输出端，使所述基准开关电路导通其输入端与第一输出端。
  11. 根据权利要求10所述的显示驱动装置，其特征在于，所述信号处理电路包括D触发器、第一受控开关和第二受控开关；
    所述第一受控开关的输入端设置为接入逻辑高电平电压；所述第二受控开关的输入端设置为接地；
    所述第一受控开关的输出端设置为连接所述第二受控开关的输出端，并设置为接地，还设置为输出所述控制信号；
    所述D触发器的控制端设置为接入所述行起始信号，所述D触发器的脉冲输入端连接所述第一受控开关的输出端，所述D触发器的输出端连接所述第一受控开关的受控端和所述第二受控开关的受控端；
    所述D触发器的输出端在输出同一逻辑电平电压时，所述第一受控开关的输入端与输出端导通，所述第二受控开关的输入端与输出端关断；或，所述第一受控开关的输入端与输出端关断，所述第二受控开关的输入端与输出端导通。
  12. 根据权利要求11所述的显示驱动装置，其特征在于，所述D触发器包括上升沿D触发器。
  13. 根据权利要求11所述的显示驱动装置，其特征在于，所述第一受控开关包括第一P沟道场效应管，所述第二受控开关包括第一N沟道场效应管；
    所述第一受控开关的受控端为所述第一P沟道场效应管的栅极；
    所述第二受控开关的受控端为所述第一N沟道场效应管的栅极。
  14. 根据权利要求11所述的显示驱动装置，其特征在于，所述信号处理电路还包括保护电阻；
    所述第一受控开关的输出端设置为通过所述保护电阻接地。
  15. 根据权利要求10所述的显示驱动装置，其特征在于，所述显示开关电路包括第三受控开关和第四受控开关；
    所述第三受控开关的受控端和所述第四受控开关的受控端接入所述控制信号；
    所述第三受控开关的输入端和所述第四受控开关的输入端为所述显示开关电路的输入端，所述第三受控开关的输出端为所述显示开关电路的第一输出端，所述第四受控开关的输出端为所述显示开关电路的第二输出端；
    在受控端接收到同一所述控制信号时，所述第三受控开关的输入端与输出端导通，所述第四受控开关的输入端与输出端关断；或，所述第三受控开关的输入端与输出端关断，所述第四受控开关的输入端与输出端导通。
  16. 根据权利要求15所述的显示驱动装置，其特征在于，所述第三受控开关包括第二N沟道场效应管，所述第四受控开关包括第二P沟道场效应管；
    所述第三受控开关的受控端为所述第二N沟道场效应管的栅极；
    所述第四受控开关的受控端为所述第二P沟道场效应管的栅极。
  17. 根据权利要求10所述的显示驱动装置，其特征在于，所述基准开关电路包括第五受控开关和第六受控开关；
    所述第五受控开关的受控端和所述第六受控开关的受控端接入所述控制信号；
    所述第五受控开关的输入端和所述第六受控开关的输入端为所述基准开关电路的输入端，所述第五受控开关的输出端为所述基准开关电路的第一输出端，所述第六受控开关的输出端为所述基准开关电路的第二输出端；
    在受控端接收到同一所述控制信号时，所述第五受控开关的输入端与输出端导通，所述第六受控开关的输入端与输出端关断；或，所述第五受控开关的输入端与输出端关断，所述第六受控开关的输入端与输出端导通。
  18. 根据权利要求17所述的显示驱动装置，其特征在于，所述第五受控开关包括第二P沟道场效应管，所述第六受控开关包括第二N沟道场效应管；
    所述第五受控开关的受控端为所述第二P沟道场效应管的栅极；
    所述第六受控开关的受控端为所述第二N沟道场效应管的栅极。
  19. 一种显示装置，包括显示驱动装置、背光板和显示阵列；
    所述显示驱动装置包括时序控制器、源极薄膜驱动芯片、栅极薄膜驱动芯片和驱动电路；所述时序控制器分别连接所述源极薄膜驱动芯片和所述栅极薄膜驱动芯片；
    所述驱动电路包括信号处理电路和受控开关电路；各受控开关电路与各子像素一一对应；
    所述信号处理电路接入所述时序控制器的行起始信号，并根据所述一个行起始信号输出一个控制信号；
    所述受控开关电路包括显示开关电路和基准开关电路；
    所述显示开关电路的输入端接入所述源极薄膜驱动芯片输出的显示信号，所述显示开关电路的受控端接入所述控制信号，所述显示开关电路的第一输出端设置为连接对应子像素第一部分的晶体管的源极，所述显示开关电路的第二输出端设置为连接对应子像素第二部分的晶体管的源极；
    所述基准开关电路的输入端设置为接入基准电压，所述基准开关电路的受控端接入所述控制信号，所述基准开关电路的第一输出端设置为连接对应子像素第一部分的基准电压端，所述基准开关电路的第二输出端设置为连接对应子像素第二部分的基准电压端；
    所述栅极薄膜驱动芯片设置为连接各子像素中各部分的晶体管的栅极；
    一个所述控制信号可使所述显示开关电路导通其输入端与第一输出端，使所述基准开关电路导通其输入端与第二输出端；或，使所述显示开关电路导通其输入端与第二输出端，使所述基准开关电路导通其输入端与第一输出端；
    所述显示阵列分别连接所述源极薄膜驱动芯片和所述栅极薄膜驱动芯片；
    所述背光板设置为给所述显示阵列提供光源。
  20. 根据权利要求19所述的显示装置，其特征在于，所述显示阵列包括液晶显示阵列。
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