WO2020075852A1 - Substrate for semiconductor growth, semiconductor element, semiconductor light-emitting element, and method for producing semiconductor light-emitting element - Google Patents

Substrate for semiconductor growth, semiconductor element, semiconductor light-emitting element, and method for producing semiconductor light-emitting element Download PDF

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WO2020075852A1
WO2020075852A1 PCT/JP2019/040305 JP2019040305W WO2020075852A1 WO 2020075852 A1 WO2020075852 A1 WO 2020075852A1 JP 2019040305 W JP2019040305 W JP 2019040305W WO 2020075852 A1 WO2020075852 A1 WO 2020075852A1
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layer
semiconductor
plane
aln buffer
buffer layer
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Japanese (ja)
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大樹 神野
杉森　正吾
大長　久芳
上山　智
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株式会社小糸製作所
学校法人 名城大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/38—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

Definitions

  • the present disclosure relates to a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element and a semiconductor element manufacturing method, and more particularly to a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element and a semiconductor element manufacturing method for growing an a-plane GaN crystal layer.
  • GaN gallium nitride
  • LEDs Light Emitting Diodes
  • the thickness of the light emitting layer is increased to reduce the carrier density inside the light emitting layer so that the electrons and holes can be efficiently emitted and recombined even if the current density is increased.
  • the light emitting layer is formed of a GaN-based material having a non-polar or semi-polar plane orientation as the main surface, thereby eliminating the influence of the piezoelectric field in the stacking direction and increasing the film thickness.
  • a technique that enables light emission with an electric current has also been proposed.
  • the a-plane and the m-plane are non-polar planes, and a typical example of the semi-polar plane is the r-plane.
  • Patent Document 1 discloses a technique for growing an a-plane GaN layer on the r-plane of a sapphire substrate using a metal organic chemical vapor deposition method (MOCVD method: Metal Organic Chemical Vapor Deposition).
  • MOCVD method Metal Organic Chemical Vapor Deposition
  • An a-plane GaN layer formed on an r-plane sapphire substrate is used as a base layer, and an n-type layer, a light-emitting layer, and a p-type layer are sequentially grown to increase the film thickness with the main surface of the light-emitting layer as the a-plane.
  • the droop characteristic of the LED can be improved.
  • the in-plane anisotropy is large, the crystallinity is good, and the surface is good. It was difficult to obtain a high quality a-plane GaN layer having excellent flatness.
  • the present disclosure has been made in view of the above conventional problems.
  • the present disclosure discloses a semiconductor growth substrate capable of growing a high-quality a-plane GaN layer having good crystallinity and excellent surface flatness, and a semiconductor device, a semiconductor light emitting device, and a semiconductor device manufacturing method using the same. The purpose is to provide.
  • a semiconductor growth substrate of the present disclosure includes a sapphire substrate having an r-plane as a main surface and an AlN buffer layer formed on the main surface, and the AlN buffer layer has a stacking direction. And has uniaxial orientation in the in-plane direction.
  • the AlN buffer layer has a uniaxial orientation in the stacking direction and the in-plane direction, abnormal growth is suppressed, crystallinity is good, and surface flatness is high. It becomes possible to grow an a-plane GaN layer.
  • the peak angle of X-ray diffraction in the stacking direction of the AlN buffer layer is shifted to the lower angle side in the range of 0.2 to 0.8 degrees compared to the bulk AlN single crystal. .
  • the peak angle of X-ray diffraction in the in-plane direction of the AlN buffer layer is shifted to a higher angle side in the range of 0.2 to 0.8 degrees than that of the bulk AlN single crystal.
  • the impurity concentration of carbon contained in the AlN buffer layer is less than 2.5 ⁇ 10 19 atoms / cm 3 .
  • the impurity concentration of oxygen contained in the AlN buffer layer is less than 7.0 ⁇ 10 20 atoms / cm 3 .
  • a semiconductor device of the present disclosure is characterized by using the semiconductor growth substrate according to any one of the above and providing a functional layer on the semiconductor growth substrate.
  • a semiconductor light emitting device of the present disclosure is characterized by using the semiconductor growth substrate according to any one of the above and having an active layer on the semiconductor growth substrate.
  • a semiconductor element manufacturing method includes a sputtering step of forming an AlN buffer layer on a sapphire substrate having an r-plane as a main surface by a sputtering method, and annealing the AlN buffer layer. Then, an annealing process for uniaxially uniaxially crystallizing in the stacking direction and the in-plane direction, and a semiconductor layer growing process for growing an a-plane GaN layer on the AlN buffer layer are provided.
  • the AlN buffer layer has a uniaxial orientation in the stacking direction and the in-plane direction, abnormal growth is suppressed, crystallinity is good, and high-quality a It is possible to grow a planar GaN layer.
  • a semiconductor growth substrate capable of growing a high quality a-plane GaN layer having good crystallinity and excellent surface flatness, and a semiconductor element, a semiconductor light emitting element, and a semiconductor element using the same.
  • a manufacturing method can be provided.
  • FIG. 6 is a table showing the impurity concentration in the AlN buffer layer 2 and the crystallinity of the a-plane GaN layer 3 depending on the difference in sputtering conditions. It is a graph which shows the XRC (X-ray Rocking Curve) measurement result of AlN buffer layer 2, and shows the half value width in a surface. It is a graph which shows the XRC measurement result of AlN buffer layer 2, and shows the half value width in m surface. 6 is a graph showing the X-ray diffraction measurement results of the AlN buffer layer 2, (A-1) of FIG. 4 showing the 2 ⁇ / ⁇ measurement results, (B-1) of FIG.
  • FIG. 4 shows the 2 ⁇ / ⁇ measurement results
  • 4A-2 shows the relationship between the film thickness and the peak diffraction intensity on the a-plane
  • FIG. 4B-2 shows the relationship between the film thickness and the peak diffraction intensity on the m-plane
  • 6 is a graph showing a diffraction spectrum of an a-plane GaN layer 3 measured by XRC
  • FIG. 5 (A) shows a result in the c-axis direction in the a-plane
  • FIG. 5 (B) shows an m-axis in the a-plane
  • FIG. 5C shows the result in the ⁇ 10-11 ⁇ plane.
  • It is a schematic cross section which shows LED10 which is a semiconductor device of 2nd Embodiment.
  • FIG. 1 is a schematic cross-sectional view showing a semiconductor growth substrate according to the first embodiment of the present disclosure.
  • the semiconductor growth substrate of this embodiment includes a sapphire substrate 1 having a hexagonal r-plane as a main surface, an AlN buffer layer 2 formed on the sapphire substrate 1, and an AlN buffer layer 2. It is provided with an a-plane GaN layer 3 having an a-plane as a main surface formed thereon.
  • the sapphire substrate 1 is a just substrate having an inclination angle of 0 ° here, it may be an off substrate in which the r-plane is inclined several degrees in a predetermined plane direction.
  • the AlN buffer layer 2 is a layer for alleviating the difference in lattice constant between the sapphire substrate 1 and the a-plane GaN layer 3.
  • the range is preferably 5 to 300 nm, more preferably 5 to 90 nm, and further preferably 5 to 30 nm. preferable.
  • the concentration of impurities contained in the AlN buffer layer 2 is preferably less than 2.5 ⁇ 10 19 atoms / cm 3 for carbon and less than 7.0 ⁇ 10 20 atoms / cm 3 for oxygen. It is preferable. If the concentration of impurities contained in the AlN buffer layer 2 is above these ranges, it tends to be difficult to epitaxially grow the single crystal a-plane GaN layer 3.
  • the a-plane GaN layer 3 is a base layer grown on the AlN buffer layer 2 so that the main surface is the a-plane, and is a layer for epitaxially growing a nitride semiconductor layer thereon.
  • a method for forming the a-plane GaN layer 3 a known method such as MOCVD or HVPE (Hydride Vapor Phase Epitaxy) can be used, but the MOCVD method is preferably used.
  • the film thickness of the a-plane GaN layer 3 is not particularly limited, but it is preferably formed to 1 ⁇ m or more.
  • the AlN buffer layer 2 is formed by the sputtering method on the sapphire substrate 1 having the r-plane as the main surface.
  • a sputtering method for forming the AlN buffer layer 2 a reactive sputtering method using Al as a target material and N 2 and Ar gas may be adopted, but it is more preferable to use Ar gas as the target material and AlN.
  • the target material AlN may be a single crystal substrate or a powder fired body, and its state or form is not limited.
  • the AlN buffer layer 2 is formed by the reactive sputtering method using N 2 and Ar gas with Al as the target material, in addition to the physical deposition process of the AlN film, the reaction between the Al target material and the N 2 gas The process needs to be considered. Therefore, in the reactive sputtering method, it becomes difficult to appropriately set and control the film forming conditions for obtaining the desired AlN buffer layer 2. In particular, as the area of the semiconductor substrate increases, it becomes more difficult because the in-plane distribution of the substrate surface must be taken into consideration.
  • the substrate temperature is preferably in the range of 200 ° C. or higher and lower than 500 ° C.
  • the impurity concentration of oxygen and carbon contained in the AlN buffer layer 2 becomes high after film formation, and it tends to be difficult to epitaxially grow the a-plane GaN layer 3 on the AlN buffer layer 2. is there.
  • the sputtering step is performed at 200 to 500 ° C., which is lower than about 1500 ° C. at which high-quality AlN crystals are obtained, the AlN buffer layer 2 immediately after film formation has an amorphous-like crystal. It seems to be sex.
  • the AlN buffer layer 2 formed in the sputtering process is annealed to promote recrystallization of the AlN buffer layer 2 so as to have uniaxial orientation in the stacking direction and the in-plane direction.
  • a heat treatment apparatus using a high frequency induction heating method can be used.
  • an annealing condition it is preferable to continue a state in which the substrate temperature is maintained at 1300 ° C. or higher and lower than 1700 ° C. for 0.5 to 3.0 hours in an inert gas (eg nitrogen or Ar) atmosphere.
  • the substrate temperature is more preferably 1300 ° C. or higher and 1600 ° C. or lower.
  • An annealing temperature (substrate temperature) of 1700 ° C. or higher is not preferable because the sapphire substrate 1 may be thermally decomposed and deteriorated. If the annealing temperature is lower than 1300 ° C., the recrystallization of the AlN buffer layer 2 is insufficient, and the uniaxial orientation of the AlN buffer layer 2 in the stacking direction and the in-plane direction may be insufficient.
  • the MOCVD method Next, after cleaning the surface of the AlN buffer layer 2, hydrogen and nitrogen are used as a carrier gas, ammonia (NH 3 ) is used as a group V raw material, and TMG (Trimethyl Gallium) is used as a group III raw material by the MOCVD method.
  • the a-plane GaN layer 3 is grown.
  • the growth sequence is composed of two stages, the growth temperature is kept constant after the temperature is raised, and the reactor pressure, the V / III ratio and the growth time are changed. For example, in the first step immediately after raising the temperature, the V / III ratio is set to about 4000 to 5000 and the pressure is set to 900 to 1000 hPa and maintained for about 10 to 20 minutes.
  • the V / III ratio is set to about 100 to 200, the pressure is set to 100 to 150 hPa, and maintained for 90 to 120 minutes.
  • the a-plane GaN layer 3 is grown, it is cooled to room temperature and taken out, whereby the semiconductor growth substrate of the present embodiment shown in FIG. 1 can be obtained.
  • the AlN buffer layer 2 is formed under the conditions of RF output of 450 W, 10 rpm, Ar flow rate of 5.0 sccm, N 2 flow rate of 5.0 sccm, substrate temperature of 300 ° C., and ultimate vacuum of 1.53 ⁇ 10 ⁇ 5 Pa. did.
  • the substrate was set in the carbon susceptor of the heat treatment apparatus, depressurized, and then N 2 was filled to 380 torr, and the temperature was raised to 1600 ° C. at a heating rate of 20 ° C./min and annealed for 1 hour.
  • the temperature was raised to 1010 ° C., and then the growth temperature was kept constant at 1010 ° C., the V / III ratio was 4400, the pressure was 933 hPa, and the growth time was 10 minutes in the first step, and the second step was the second step.
  • the a-plane GaN layer 3 was grown at a V / III ratio of 100, a pressure of 100 hPa, and a growth time of 90 minutes to obtain a semiconductor growth substrate.
  • the AlN buffer layers 2 having the film thicknesses of 30 nm, 90 nm, and 180 nm were taken as Examples 1 to 3, respectively.
  • Example 3 A semiconductor growth substrate was obtained under the same conditions as in Example 1 except that the semiconductor element growth step was performed without performing the annealing step after the sputtering step.
  • the AlN buffer layers 2 having thicknesses of 30 nm, 90 nm, and 180 nm were set as Comparative Examples 1 to 3, respectively.
  • Comparative example 4 A semiconductor growth substrate of Comparative Example 4 was obtained under the same conditions as in Comparative Example 1 except that the substrate temperature in the sputtering step was 600 ° C. and the ultimate vacuum was 4.47 ⁇ 10 ⁇ 4 Pa.
  • FIG. 2 is a table showing the impurity concentration in the AlN buffer layer 2 and the crystallinity of the a-plane GaN layer 3 depending on the difference in sputtering conditions.
  • the impurity concentration in the AlN buffer layer 2 was measured by SIMS (Secondary Ion Mass Spectrometry), and the crystallinity of the a-plane GaN layer 3 was evaluated by SEM (Scanning Electron Microscope) image and X-ray diffraction.
  • the results of Example 1 are shown on the left side of the figure, and the results of Comparative Example 4 are shown on the right side of the figure.
  • the concentration of impurities contained in the AlN buffer layer 2 was 6.58 ⁇ 10 20 atoms / cm 3 in Example 1 and 2.19 ⁇ 10 19 atoms / cm 3 in carbon concentration. Met.
  • the oxygen concentration was 2.66 ⁇ 10 21 atoms / cm 3 and the carbon concentration was 9.72 ⁇ 10 19 atoms / cm 3 .
  • the single crystal a-plane GaN layer 3 could be grown on the AlN buffer layer 2, but in Comparative Example 4, the single crystal a-plane GaN layer 3 could be grown. I know I haven't. Therefore, it is understood that when the sputtering condition is 500 ° C. or higher, the ultimate vacuum degree is low and the impurity concentration is high, so that it is difficult to grow the single crystal a-plane GaN layer.
  • 3A and 3B are graphs showing XRC (X-ray Rocking Curve) measurement results of the AlN buffer layer 2.
  • FIG. 3A shows the full width at half maximum on the a-plane
  • FIG. 3B shows the full width at half maximum on the m-plane.
  • annealed sp-AlN indicates Examples 1 to 3
  • sp-AlN indicates Comparative Examples 1 to 3
  • ep-AlN indicates Comparative Examples 5 to 7.
  • the FWHMs on the a-plane and the m-plane are the largest in Comparative Examples 1 to 3, and the smallest in Examples 1 to 3. Therefore, it can be seen that the crystallinity of the AlN buffer layer 2 is the best in Examples 1 to 3 which have undergone the annealing process after being formed by the sputtering method.
  • FIG. 4 is a graph showing the X-ray diffraction measurement result of the AlN buffer layer 2.
  • 4A-1 shows the 2 ⁇ / ⁇ measurement result
  • FIG. 4B-1 shows the 2 ⁇ / ⁇ measurement result
  • FIG. 4A-2 shows the film thickness and the a-plane. The relationship between the peak diffraction intensities is shown
  • FIG. 4B-2 shows the relationship between the film thickness and the peak diffraction intensities on the m-plane.
  • (A-1) of FIG. 4 diffraction peaks can be confirmed around 53 ° and around 59 ° in all measurement results.
  • the peak near 53 ° corresponds to the r-plane of the sapphire substrate 1
  • the peak near 59 ° corresponds to the a-plane of the AlN buffer layer 2.
  • the peak angle was shifted to the lower angle side in the range of 0.2 to 0.8 degrees than the theoretical peak angle of the bulk AlN single crystal.
  • the peak angle to the low angle side in the 2 ⁇ / ⁇ measurement shows the spread of the lattice plane spacing in the stacking direction of the AlN buffer layer 2, and it is considered that tensile stress acts in the stacking direction in Examples 1 to 3. .
  • the peak intensities of Examples 1 to 3 are significantly higher than those of Comparative Examples 1 to 3, and the peak intensities of Examples 1 and 2 are higher than those of Comparative Examples 5 and 6. . Therefore, it can be seen that in Examples 1 and 2, the AlN buffer layer 2 is favorably a-axis oriented in the stacking direction.
  • the peak intensities of Examples 1 and 2 are significantly larger than those of Comparative Examples 1 and 2, and the peak intensity of Example 1 is larger than that of Comparative Example 5. Therefore, in Examples 1 and 2, it can be seen that the AlN buffer layer 2 is favorably oriented in the in-plane m-axis.
  • the uniaxial orientation in the in-plane direction and the stacking direction of the AlN buffer layer 2 is highest in Examples 1 and 2, and the uniaxial orientation in the in-plane direction is better as the film thickness is smaller. Can be said. Further, in Examples 1 to 3, the angle was shifted to the lower angle side in the range of 0.2 to 0.8 degrees in the stacking direction from the theoretical peak angle in the bulk AlN single crystal, and 0.2 in the in-plane direction. The angle shifts to the high angle side in the range of up to 0.8 degrees, and the in-plane compressive stress is applied to the AlN buffer layer 2.
  • FIG. 5 is a graph showing a diffraction spectrum of the a-plane GaN layer 3 measured by XRC.
  • 5A shows the result in the c-axis direction in the a-plane
  • FIG. 5B shows the result in the m-axis direction in the a-plane
  • FIG. 5C shows ⁇ 10- 11 ⁇ shows the results in the plane.
  • 5A to 5C show the measurement results of Example 1, Comparative Example 1, and Comparative Example 5 in which the thickness of the AlN buffer layer 2 was 30 nm.
  • the full width at half maximum (unit: arcsec) in the measurement result shown in FIG. 5A was 505 in Example 1, 609 in Comparative Example 1, and 562 in Comparative Example 5.
  • Example 1 was 729
  • Comparative Example 1 was 758
  • Comparative Example 5 was 995.
  • FIG. 5C the result was 1071 in Example 1, 1472 in Comparative Example 1, and 1404 in Comparative Example 5.
  • Example 1 As shown in (A) to (C) of FIG. 5, the crystallinity of Example 1 is better than that of Comparative Examples 1 and 5.
  • the crystallinity and surface flatness of the a-plane GaN layer 3 can be improved.
  • the AlN buffer layer has the uniaxial orientation in the stacking direction and the in-plane direction, so that abnormal growth is suppressed and crystallinity is good and surface flatness is improved. It becomes possible to grow an excellent and high quality a-plane GaN layer.
  • FIG. 6 is a schematic cross-sectional view showing the LED 10 which is the semiconductor device of the second embodiment.
  • the LED 10 includes a sapphire substrate 11 having an r-plane as a main surface, an AlN buffer layer 12, an a-plane GaN layer 13, an n-type semiconductor layer 14, a light emitting layer (active layer) 15, and a p-type semiconductor layer 16. , N-side electrode 17 and p-side electrode 18.
  • a sapphire substrate 11 whose main surface is the r-plane is prepared, and an AlN buffer layer 12 is formed on the sapphire substrate 11 by a sputtering process.
  • the AlN buffer layer 12 is annealed to be a single crystal, and has uniaxial orientation in the stacking direction and the in-plane direction.
  • the a-plane GaN layer 13 is epitaxially grown on the AlN buffer layer 12 in the semiconductor layer growth step, and then the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 are sequentially grown by the MOCVD method to form a semiconductor substrate.
  • an LED 10 is obtained by forming an electrode material on the exposed surfaces of the n-type semiconductor layer 14 and the p-type semiconductor layer 16 by vapor deposition or the like, and dicing it into individual chips.
  • the n-type semiconductor layer 14 and the p-type semiconductor layer 16 have been described as single layers, respectively, a plurality of layers having different materials and compositions may be included.
  • the n-type semiconductor layer 14 and the p-type semiconductor layer 16 may include a clad layer, a contact layer, a current diffusion layer, an electron block layer, a waveguide layer, and the like.
  • the light emitting layer 15 has been described as a single layer, it may be formed of a plurality of layers such as a multi quantum well structure (MQW: Multi Quantum Well).
  • MQW Multi Quantum Well
  • the n-type semiconductor layer 14 is a layer whose main surface is the a-plane epitaxially grown on the a-plane GaN layer 13.
  • the n-type semiconductor layer 14 is a semiconductor layer doped with an n-type impurity, and is a layer into which electrons are injected from the n-side electrode 17 and supplies the electrons to the light emitting layer 15.
  • Examples of the material forming the n-type semiconductor layer 14 include GaN, AlGaN, InGaN, and AlInGaN as the III-V compound semiconductor layer, and Si as the n-type impurity.
  • the light emitting layer 15 is a semiconductor layer whose main surface is an a-plane epitaxially grown on the n-type semiconductor layer 14.
  • the LED 10 emits light when the electrons and the holes are radiatively recombined in the light emitting layer 15.
  • the light emitting layer 15 is made of a material having a smaller band gap than the n-type semiconductor layer 14 and the p-type semiconductor layer 16. Examples of such a material include InGaN and AlInGaN.
  • the light emitting layer 15 may be non-doped intentionally containing no impurities, n-type containing n-type impurities or p-type containing p-type impurities.
  • the light-emitting layer 15 is a semiconductor layer having the a-plane as the main surface, even if the light-emitting layer 15 is made thicker, spatial separation of electrons and holes due to the piezoelectric field is less likely to occur, and even if the current density is increased, positive electrons and holes are efficiently generated.
  • the holes can be radiatively recombined.
  • the p-type semiconductor layer 16 is a semiconductor layer whose main surface is the a-plane epitaxially grown on the light emitting layer 15. Holes are injected from the p-side electrode 18 into the p-type semiconductor layer 16. Then, the p-type semiconductor layer 16 supplies the injected holes to the light emitting layer 15.
  • Examples of the material forming the p-type semiconductor layer 16 include GaN, AlGaN, InGaN, and AlInGaN for the III-V group compound semiconductor layer, and Zn, Mg, and the like for the p-type impurity.
  • the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 are formed on the AlN buffer layer 12 having a uniaxial orientation in the stacking direction and the in-plane direction with the a-plane GaN layer 13 as a base layer. It is epitaxially grown. Therefore, as described in the first embodiment, the a-plane GaN layer 13 has good crystallinity and surface flatness, and the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 grown on the a-plane GaN layer 13 are also good. Good crystallinity and surface flatness.
  • the characteristics of the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 are improved, and the external quantum efficiency of the LED 10 is expected to be improved.
  • the present embodiment is an example in which the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 are provided as the functional layers.
  • the functional layer is a layer for exhibiting predetermined electrical and chemical functions in the semiconductor element.
  • the semiconductor element may not include the light emitting layer 15.
  • the LED 10 which is the semiconductor device of the present invention can achieve high brightness because it has little droop due to the piezoelectric field and has small anisotropy in the a-plane and good crystal quality. By using it for a lamp such as a lamp, it is possible to reduce the number of chips and increase the output.
  • the semiconductor device is not limited to the LED, and may be other applications such as a semiconductor laser and a high electron mobility transistor (HEMT: High Electron Mobility Transistor).
  • the functional layer is a layer for exhibiting a predetermined electrical and chemical function in the semiconductor element.

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Abstract

Provided is a substrate for semiconductor growth, comprising a sapphire substrate (1) having an r-plane as a principle surface, and an AlN buffer layer (2) formed on the principle surface, wherein the AlN buffer layer (2) has uniaxial alignment in the laminating direction and in the in-plane direction.

Description

半導体成長用基板、半導体素子、半導体発光素子および半導体素子製造方法Substrate for semiconductor growth, semiconductor device, semiconductor light emitting device, and method for manufacturing semiconductor device
　本開示は、半導体成長用基板、半導体素子、半導体発光素子および半導体素子製造方法に関し、特にａ面ＧａＮ結晶層を成長させる半導体成長用基板、半導体素子、半導体発光素子および半導体素子製造方法に関する。 The present disclosure relates to a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element and a semiconductor element manufacturing method, and more particularly to a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element and a semiconductor element manufacturing method for growing an a-plane GaN crystal layer.
　照明用途に用いられる紫色から青色を発光するＬＥＤ（Ｌｉｇｈｔ　Ｅｍｉｔｔｉｎｇ　Ｄｉｏｄｅ）としては、窒化ガリウム（ＧａＮ）系材料の化合物半導体が一般的に用いられている。近年になって、発光ダイオード（ＬＥＤ）を用いた照明装置等が普及するにつれ、ＬＥＤチップの高輝度化が望まれるようになってきた。ＬＥＤを高輝度化するためには、電流密度を高くしても効率的に電子と正孔が発光再結合できるように、発光層の膜厚を厚くして発光層内部でのキャリア密度を下げる必要がある。 Compound semiconductors of gallium nitride (GaN) -based materials are generally used as LEDs (Light Emitting Diodes) that emit purple to blue light used for lighting purposes. In recent years, with the spread of lighting devices and the like using light emitting diodes (LEDs), there has been a demand for higher brightness of LED chips. In order to increase the brightness of the LED, the thickness of the light emitting layer is increased to reduce the carrier density inside the light emitting layer so that the electrons and holes can be efficiently emitted and recombined even if the current density is increased. There is a need.
　しかし、一般的に用いられているｃ面を主面とするＧａＮ系半導体材料では、ｃ軸方向にピエゾ電界が生じるため、厚膜化した発光層内に電位差が生じ電子と正孔が空間的に分離してしまい、発光再結合の効率が著しく低下してしまうドループ特性が問題となっている。 However, in a commonly used GaN-based semiconductor material having a c-plane as a main surface, a piezo electric field is generated in the c-axis direction, so that a potential difference occurs in the thickened light emitting layer and electrons and holes are spatially separated. However, there is a problem with the droop characteristic in that the efficiency of the radiative recombination is remarkably lowered.
　この問題を解決するため、非極性や半極性の面方位を主面としたＧａＮ系材料で発光層を形成することで、積層方向へのピエゾ電界の影響を無くして厚膜化を図り、大電流での発光を可能にする技術も提案されている。ＧａＮ系半導体層では、ａ面やｍ面が非極性面であり、半極性面の代表例としてｒ面がある。 In order to solve this problem, the light emitting layer is formed of a GaN-based material having a non-polar or semi-polar plane orientation as the main surface, thereby eliminating the influence of the piezoelectric field in the stacking direction and increasing the film thickness. A technique that enables light emission with an electric current has also been proposed. In the GaN-based semiconductor layer, the a-plane and the m-plane are non-polar planes, and a typical example of the semi-polar plane is the r-plane.
　特許文献１には、サファイア基板のｒ面上に有機金属気相成長法（ＭＯＣＶＤ法：Ｍｅｔａｌ　Ｏｒｇａｎｉｃ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）を用いてａ面ＧａＮ層を成長させる技術が開示されている。ｒ面サファイア基板上に形成されたａ面ＧａＮ層を下地層として用い、ｎ型層と発光層とｐ型層とを順次成長させることで、発光層の主面をａ面として厚膜化とＬＥＤのドループ特性の改善を図ることができる。 Patent Document 1 discloses a technique for growing an a-plane GaN layer on the r-plane of a sapphire substrate using a metal organic chemical vapor deposition method (MOCVD method: Metal Organic Chemical Vapor Deposition). An a-plane GaN layer formed on an r-plane sapphire substrate is used as a base layer, and an n-type layer, a light-emitting layer, and a p-type layer are sequentially grown to increase the film thickness with the main surface of the light-emitting layer as the a-plane. The droop characteristic of the LED can be improved.
日本国特開２００８－２１４１３２号公報Japanese Patent Laid-Open No. 2008-214132
　しかし、ｒ面サファイア基板上に形成されるａ面ＧａＮでは、成長面内に＋ｃ軸方向、－ｃ軸方向、ｍ軸方向が存在して面内異方性が大きく、結晶性が良好で表面平坦性に優れた高品質なａ面ＧａＮ層を得ることが困難であった。 However, in the a-plane GaN formed on the r-plane sapphire substrate, the + c-axis direction, the −c-axis direction, and the m-axis direction are present in the growth plane, the in-plane anisotropy is large, the crystallinity is good, and the surface is good. It was difficult to obtain a high quality a-plane GaN layer having excellent flatness.
　本開示は、上記従来の問題点に鑑みなされたものである。本開示は、結晶性が良好で表面平坦性に優れた高品質なａ面ＧａＮ層を成長させることが可能な半導体成長用基板、並びにそれを用いた半導体素子、半導体発光素子および半導体素子製造方法を提供することを目的とする。 The present disclosure has been made in view of the above conventional problems. The present disclosure discloses a semiconductor growth substrate capable of growing a high-quality a-plane GaN layer having good crystallinity and excellent surface flatness, and a semiconductor device, a semiconductor light emitting device, and a semiconductor device manufacturing method using the same. The purpose is to provide.
　上記課題を解決するために、本開示の半導体成長用基板は、ｒ面を主面とするサファイア基板と、前記主面上に形成されたＡｌＮバッファ層を備え、前記ＡｌＮバッファ層は、積層方向および面内方向に一軸配向性を有することを特徴とする。 In order to solve the above problems, a semiconductor growth substrate of the present disclosure includes a sapphire substrate having an r-plane as a main surface and an AlN buffer layer formed on the main surface, and the AlN buffer layer has a stacking direction. And has uniaxial orientation in the in-plane direction.
　このような本開示の半導体成長用基板では、ＡｌＮバッファ層が積層方向および面内方向に一軸配向性を有することで、異常成長を抑制し結晶性が良好で表面平坦性に優れた高品質なａ面ＧａＮ層を成長させることが可能となる。 In such a semiconductor growth substrate of the present disclosure, since the AlN buffer layer has a uniaxial orientation in the stacking direction and the in-plane direction, abnormal growth is suppressed, crystallinity is good, and surface flatness is high. It becomes possible to grow an a-plane GaN layer.
　また本開示の一態様では、前記ＡｌＮバッファ層は、積層方向におけるＸ線回折のピーク角度が、バルクＡｌＮ単結晶よりも０．２～０．８度の範囲で低角側にシフトしている。 In one aspect of the present disclosure, the peak angle of X-ray diffraction in the stacking direction of the AlN buffer layer is shifted to the lower angle side in the range of 0.2 to 0.8 degrees compared to the bulk AlN single crystal. .
　また本開示の一態様では、前記ＡｌＮバッファ層は、面内方向におけるＸ線回折のピーク角度が、バルクＡｌＮ単結晶よりも０．２～０．８度の範囲で高角側にシフトしている。 Further, in one aspect of the present disclosure, the peak angle of X-ray diffraction in the in-plane direction of the AlN buffer layer is shifted to a higher angle side in the range of 0.2 to 0.8 degrees than that of the bulk AlN single crystal. .
　また本開示の一態様では、前記ＡｌＮバッファ層に含まれる炭素の不純物濃度が、２．５×１０19ａｔｏｍｓ／ｃｍ3未満である。 In one aspect of the present disclosure, the impurity concentration of carbon contained in the AlN buffer layer is less than 2.5 × 10 19 atoms / cm 3 .
　また本開示の一態様では、前記ＡｌＮバッファ層に含まれる酸素の不純物濃度が、７．０×１０20ａｔｏｍｓ／ｃｍ3未満である。 In one aspect of the present disclosure, the impurity concentration of oxygen contained in the AlN buffer layer is less than 7.0 × 10 20 atoms / cm 3 .
　また上記課題を解決するために本開示の半導体素子は、上記何れか一つに記載の半導体成長用基板を用い、前記半導体成長用基板上に機能層を備えることを特徴とする。 In order to solve the above problems, a semiconductor device of the present disclosure is characterized by using the semiconductor growth substrate according to any one of the above and providing a functional layer on the semiconductor growth substrate.
　また上記課題を解決するために本開示の半導体発光素子は、上記何れか一つに記載の半導体成長用基板を用い、前記半導体成長用基板上に活性層を備えることを特徴とする。 In order to solve the above problems, a semiconductor light emitting device of the present disclosure is characterized by using the semiconductor growth substrate according to any one of the above and having an active layer on the semiconductor growth substrate.
　また上記課題を解決するために本開示の半導体素子製造方法は、ｒ面を主面とするサファイア基板上にスパッタ法を用いてＡｌＮバッファ層を形成するスパッタ工程と、前記ＡｌＮバッファ層をアニールして、積層方向および面内方向に一軸配向性を有する単結晶化するアニール工程と、前記ＡｌＮバッファ層上にａ面ＧａＮ層を成長させる半導体層成長工程とを備えることを特徴とする。 Further, in order to solve the above problems, a semiconductor element manufacturing method according to the present disclosure includes a sputtering step of forming an AlN buffer layer on a sapphire substrate having an r-plane as a main surface by a sputtering method, and annealing the AlN buffer layer. Then, an annealing process for uniaxially uniaxially crystallizing in the stacking direction and the in-plane direction, and a semiconductor layer growing process for growing an a-plane GaN layer on the AlN buffer layer are provided.
　このような本開示の半導体素子製造方法では、ＡｌＮバッファ層が積層方向および面内方向に一軸配向性を有するため、異常成長を抑制し結晶性が良好で表面平坦性に優れた高品質なａ面ＧａＮ層を成長させることが可能となる。 In such a semiconductor device manufacturing method of the present disclosure, since the AlN buffer layer has a uniaxial orientation in the stacking direction and the in-plane direction, abnormal growth is suppressed, crystallinity is good, and high-quality a It is possible to grow a planar GaN layer.
　本開示によれば、結晶性が良好で表面平坦性に優れた高品質なａ面ＧａＮ層を成長させることが可能な半導体成長用基板、並びにそれを用いた半導体素子、半導体発光素子および半導体素子製造方法を提供することができる。 According to the present disclosure, a semiconductor growth substrate capable of growing a high quality a-plane GaN layer having good crystallinity and excellent surface flatness, and a semiconductor element, a semiconductor light emitting element, and a semiconductor element using the same. A manufacturing method can be provided.
第１実施形態における半導体成長用基板を示す模式断面図である。It is a schematic cross section which shows the semiconductor growth substrate in 1st Embodiment. スパッタ条件の違いによるＡｌＮバッファ層２中の不純物濃度と、ａ面ＧａＮ層３の結晶性を示す表である。6 is a table showing the impurity concentration in the AlN buffer layer 2 and the crystallinity of the a-plane GaN layer 3 depending on the difference in sputtering conditions. ＡｌＮバッファ層２のＸＲＣ（Ｘ－ｒａｙ　Ｒｏｃｋｉｎｇ　Ｃｕｒｖｅ）測定結果を示すグラフであり、ａ面での半値幅を示すものである。It is a graph which shows the XRC (X-ray Rocking Curve) measurement result of AlN buffer layer 2, and shows the half value width in a surface. ＡｌＮバッファ層２のＸＲＣ測定結果を示すグラフであり、ｍ面での半値幅を示すものである。It is a graph which shows the XRC measurement result of AlN buffer layer 2, and shows the half value width in m surface. ＡｌＮバッファ層２のＸ線回折測定結果を示すグラフであり、図４の（Ａ－１）は２θ／θ測定結果を示し、図４の（Ｂ－１）は２θχ／φ測定結果を示し、図４の（Ａ－２）は膜厚とａ面でのピーク回折強度の関係を示し、図４の（Ｂ－２）は膜厚とｍ面でのピーク回折強度の関係を示している。6 is a graph showing the X-ray diffraction measurement results of the AlN buffer layer 2, (A-1) of FIG. 4 showing the 2θ / θ measurement results, (B-1) of FIG. 4 showing the 2θχ / φ measurement results, 4A-2 shows the relationship between the film thickness and the peak diffraction intensity on the a-plane, and FIG. 4B-2 shows the relationship between the film thickness and the peak diffraction intensity on the m-plane. ａ面ＧａＮ層３のＸＲＣ測定の回折スペクトルを示すグラフであり、図５の（Ａ）はａ面内のｃ軸方向での結果を示し、図５の（Ｂ）はａ面内のｍ軸方向での結果を示し、図５の（Ｃ）は｛１０－１１｝面内での結果を示している。6 is a graph showing a diffraction spectrum of an a-plane GaN layer 3 measured by XRC, FIG. 5 (A) shows a result in the c-axis direction in the a-plane, and FIG. 5 (B) shows an m-axis in the a-plane. FIG. 5C shows the result in the {10-11} plane. 第２実施形態の半導体装置であるＬＥＤ１０を示す模式断面図である。It is a schematic cross section which shows LED10 which is a semiconductor device of 2nd Embodiment.
　（第１実施形態）
　以下、本開示の実施の形態について、図面を参照して詳細に説明する。各図面に示される同一または同等の構成要素、部材、処理には、同一の符号を付すものとし、適宜重複した説明は省略する。図１は、本開示の第１実施形態における半導体成長用基板を示す模式断面図である。 (1st Embodiment)
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The same or equivalent constituent elements, members, and processes shown in each drawing will be denoted by the same reference numerals, and duplicated description will be omitted as appropriate. FIG. 1 is a schematic cross-sectional view showing a semiconductor growth substrate according to the first embodiment of the present disclosure.
　図１に示すように、本実施形態の半導体成長用基板は、六方晶のｒ面を主面とするサファイア基板１と、サファイア基板１上に形成されたＡｌＮバッファ層２と、ＡｌＮバッファ層２上に形成されたａ面を主面とするａ面ＧａＮ層３を備えている。ここではサファイア基板１として傾斜角度が０度のジャスト基板を示したが、ｒ面を所定の面方位に数度傾斜させたオフ基板としてもよい。 As shown in FIG. 1, the semiconductor growth substrate of this embodiment includes a sapphire substrate 1 having a hexagonal r-plane as a main surface, an AlN buffer layer 2 formed on the sapphire substrate 1, and an AlN buffer layer 2. It is provided with an a-plane GaN layer 3 having an a-plane as a main surface formed thereon. Although the sapphire substrate 1 is a just substrate having an inclination angle of 0 ° here, it may be an off substrate in which the r-plane is inclined several degrees in a predetermined plane direction.
　ＡｌＮバッファ層２はサファイア基板１とａ面ＧａＮ層３との格子定数の相違を緩和するための層である。ＡｌＮバッファ層２の厚みとしては、厚くしすぎるとａ面ＧａＮ層３の結晶品質が低下するため、５～３００ｎｍの範囲が好ましく、５～９０ｎｍの範囲がより好ましく、５～３０ｎｍの範囲がさらに好ましい。また、ＡｌＮバッファ層２中に含まれる不純物濃度は、炭素が２．５×１０19ａｔｏｍｓ／ｃｍ3未満であることが好ましく、また、酸素が７．０×１０20ａｔｏｍｓ／ｃｍ3未満であることが好ましい。ＡｌＮバッファ層２中に含まれる不純物濃度がこれらの範囲以上であると、単結晶のａ面ＧａＮ層３をエピタキシャル成長させにくくなる傾向にある。 The AlN buffer layer 2 is a layer for alleviating the difference in lattice constant between the sapphire substrate 1 and the a-plane GaN layer 3. As the thickness of the AlN buffer layer 2 is too thick, the crystal quality of the a-plane GaN layer 3 deteriorates, so that the range is preferably 5 to 300 nm, more preferably 5 to 90 nm, and further preferably 5 to 30 nm. preferable. The concentration of impurities contained in the AlN buffer layer 2 is preferably less than 2.5 × 10 19 atoms / cm 3 for carbon and less than 7.0 × 10 20 atoms / cm 3 for oxygen. It is preferable. If the concentration of impurities contained in the AlN buffer layer 2 is above these ranges, it tends to be difficult to epitaxially grow the single crystal a-plane GaN layer 3.
　ａ面ＧａＮ層３は、ＡｌＮバッファ層２上において、主面がａ面となるように成長した下地層であり、その上に窒化物半導体層をエピタキシャル成長させるための層である。ａ面ＧａＮ層３の形成方法としては、ＭＯＣＶＤ法やＨＶＰＥ法（ハイドライド気相成長法：Ｈｙｄｒｉｄｅ　Ｖａｐｏｒ　Ｐｈａｓｅ　Ｅｐｉｔａｘｙ）などの公知の方法を用いることができるが、ＭＯＣＶＤ法を用いることが好ましい。ａ面ＧａＮ層３の膜厚は特に限定されないが、１μｍ以上形成することが好ましい。 The a-plane GaN layer 3 is a base layer grown on the AlN buffer layer 2 so that the main surface is the a-plane, and is a layer for epitaxially growing a nitride semiconductor layer thereon. As a method for forming the a-plane GaN layer 3, a known method such as MOCVD or HVPE (Hydride Vapor Phase Epitaxy) can be used, but the MOCVD method is preferably used. The film thickness of the a-plane GaN layer 3 is not particularly limited, but it is preferably formed to 1 μm or more.
　次に、図１に示した半導体成長用基板の製造方法について説明する。 Next, a method of manufacturing the semiconductor growth substrate shown in FIG. 1 will be described.
　（スパッタ工程）
　はじめに、ｒ面を主面とするサファイア基板１上に、スパッタ法を用いてＡｌＮバッファ層２を形成する。ＡｌＮバッファ層２を形成するスパッタ法としては、Ａｌをターゲット材としてＮ2およびＡｒガスを用いる反応性スパッタ法を採用してもよいが、ＡｌＮをターゲット材としてＡｒガスを用いることがより好ましい。ターゲット材となるＡｌＮとしては、単結晶基板であっても粉末焼体であってもよく、その状態や形態は限定されない。 (Sputtering process)
First, the AlN buffer layer 2 is formed by the sputtering method on the sapphire substrate 1 having the r-plane as the main surface. As a sputtering method for forming the AlN buffer layer 2, a reactive sputtering method using Al as a target material and N 2 and Ar gas may be adopted, but it is more preferable to use Ar gas as the target material and AlN. The target material AlN may be a single crystal substrate or a powder fired body, and its state or form is not limited.
　反応性スパッタ法によりＡｌをターゲット材としてＮ2およびＡｒガスを用いてＡｌＮバッファ層２を形成する場合には、ＡｌＮ膜の物理的な堆積プロセスに加えて、Ａｌターゲット材とＮ2ガスの反応プロセスを考慮する必要がある。そのため反応性スパッタ法では、所望のＡｌＮバッファ層２を得るための成膜条件を適切に設定して制御する難易度が高くなる。特に、半導体基板の大面積化が進むと、基板表面の面内分布も考慮する必要があるためさらに難易度が高くなる。 When the AlN buffer layer 2 is formed by the reactive sputtering method using N 2 and Ar gas with Al as the target material, in addition to the physical deposition process of the AlN film, the reaction between the Al target material and the N 2 gas The process needs to be considered. Therefore, in the reactive sputtering method, it becomes difficult to appropriately set and control the film forming conditions for obtaining the desired AlN buffer layer 2. In particular, as the area of the semiconductor substrate increases, it becomes more difficult because the in-plane distribution of the substrate surface must be taken into consideration.
　一方、ＡｌＮをターゲット材としてＡｒガスを用いるスパッタ法によりＡｌＮバッファ層２を形成する場合には、Ａｌターゲット材とＮ2の反応プロセスを考慮する必要が無く、Ａｒガス流量やチャンバー内の真空度等のパラメータを最適化するだけでよい。したがって、反応性スパッタ法でＡｌＮバッファ層２を形成するよりも、ＡｌＮをターゲット材としてＡｒガスを用いるスパッタ法を用いるほうが、ＡｌＮバッファ層２を形成する際の成膜条件の設定や制御が容易であり、大面積化にも対応が容易となる。 On the other hand, when forming the AlN buffer layer 2 by the sputtering method using AlN as a target material and Ar gas, it is not necessary to consider the reaction process of the Al target material and N 2 , and the flow rate of Ar gas and the degree of vacuum in the chamber are not required. It is only necessary to optimize the parameters such as. Therefore, it is easier to set and control film forming conditions when forming the AlN buffer layer 2 by using the sputtering method using Ar gas with AlN as the target material than forming the AlN buffer layer 2 by the reactive sputtering method. Therefore, it becomes easy to deal with a large area.
　ＡｌＮバッファ層２を形成する反応性スパッタの条件としては、基板温度は２００℃以上５００℃未満の範囲が好ましい。基板温度を５００℃以上にすると、成膜後にＡｌＮバッファ層２に含まれる酸素や炭素の不純物濃度が高くなり、ＡｌＮバッファ層２上にａ面ＧａＮ層３をエピタキシャル成長させることが困難になる傾向にある。本実施形態の半導体素子成長方法では、高品質なＡｌＮ結晶が得られる１５００℃程度よりも低温の２００～５００℃でスパッタ工程を実施するため、成膜直後のＡｌＮバッファ層２はアモルファスライクな結晶性であると思われる。 As the conditions for the reactive sputtering for forming the AlN buffer layer 2, the substrate temperature is preferably in the range of 200 ° C. or higher and lower than 500 ° C. When the substrate temperature is set to 500 ° C. or higher, the impurity concentration of oxygen and carbon contained in the AlN buffer layer 2 becomes high after film formation, and it tends to be difficult to epitaxially grow the a-plane GaN layer 3 on the AlN buffer layer 2. is there. In the semiconductor device growth method of the present embodiment, since the sputtering step is performed at 200 to 500 ° C., which is lower than about 1500 ° C. at which high-quality AlN crystals are obtained, the AlN buffer layer 2 immediately after film formation has an amorphous-like crystal. It seems to be sex.
　（アニール工程）
　次に、スパッタ工程で成膜したＡｌＮバッファ層２のアニール処理を実施し、ＡｌＮバッファ層２の再結晶化を促進して、積層方向および面内方向に一軸配向性を持たせる。アニール処理としては、例えば高周波誘導加熱方式による熱処理装置を用いることができる。アニール条件としては、不活性ガス（例えば窒素やＡｒ）雰囲気中において基板温度を１３００℃以上１７００℃未満に保った状態を０．５～３．０時間継続することが好ましい。基板温度は、より好ましくは１３００℃以上１６００℃以下である。アニール温度（基板温度）が１７００℃以上であると、サファイア基板１が熱分解して劣化する恐れがあるため好ましくない。また、アニール温度が１３００℃未満であると、ＡｌＮバッファ層２の再結晶化が不十分であり、ＡｌＮバッファ層２の積層方向および面内方向における一軸配向性が不十分となる恐れがある。 (Annealing process)
Next, the AlN buffer layer 2 formed in the sputtering process is annealed to promote recrystallization of the AlN buffer layer 2 so as to have uniaxial orientation in the stacking direction and the in-plane direction. As the annealing treatment, for example, a heat treatment apparatus using a high frequency induction heating method can be used. As an annealing condition, it is preferable to continue a state in which the substrate temperature is maintained at 1300 ° C. or higher and lower than 1700 ° C. for 0.5 to 3.0 hours in an inert gas (eg nitrogen or Ar) atmosphere. The substrate temperature is more preferably 1300 ° C. or higher and 1600 ° C. or lower. An annealing temperature (substrate temperature) of 1700 ° C. or higher is not preferable because the sapphire substrate 1 may be thermally decomposed and deteriorated. If the annealing temperature is lower than 1300 ° C., the recrystallization of the AlN buffer layer 2 is insufficient, and the uniaxial orientation of the AlN buffer layer 2 in the stacking direction and the in-plane direction may be insufficient.
　（半導体層成長工程）
　次に、ＡｌＮバッファ層２の表面を洗浄した後に、キャリアガスとして水素、窒素を用い、Ｖ族原料としてアンモニア（ＮＨ3）を用い、ＩＩＩ族原料としてＴＭＧ（ＴｒｉｍｅｔｈｙｌＧａｌｌｉｕｍ）を用いて、ＭＯＣＶＤ法でａ面ＧａＮ層３を成長させる。このとき、成長シーケンスは２段階で構成し、昇温した後に成長温度を一定とし、リアクタ圧力とＶ／ＩＩＩ比および成長時間を変更している。例えば、昇温直後の第１ステップではＶ／ＩＩＩ比を４０００～５０００程度とし、圧力を９００～１０００ｈＰａとして１０～２０分程度維持する。第２ステップでは例えばＶ／ＩＩＩ比を１００～２００程度とし、圧力を１００～１５０ｈＰａとして９０～１２０分維持する。ａ面ＧａＮ層３が成長した後に室温まで冷却して取り出すことで、図１に示した本実施形態の半導体成長用基板を得ることができる。 (Semiconductor layer growth process)
Next, after cleaning the surface of the AlN buffer layer 2, hydrogen and nitrogen are used as a carrier gas, ammonia (NH 3 ) is used as a group V raw material, and TMG (Trimethyl Gallium) is used as a group III raw material by the MOCVD method. The a-plane GaN layer 3 is grown. At this time, the growth sequence is composed of two stages, the growth temperature is kept constant after the temperature is raised, and the reactor pressure, the V / III ratio and the growth time are changed. For example, in the first step immediately after raising the temperature, the V / III ratio is set to about 4000 to 5000 and the pressure is set to 900 to 1000 hPa and maintained for about 10 to 20 minutes. In the second step, for example, the V / III ratio is set to about 100 to 200, the pressure is set to 100 to 150 hPa, and maintained for 90 to 120 minutes. After the a-plane GaN layer 3 is grown, it is cooled to room temperature and taken out, whereby the semiconductor growth substrate of the present embodiment shown in FIG. 1 can be obtained.
　（実施例１～３）
　スパッタ工程で、ＲＦ出力４５０Ｗ、１０ｒｐｍ、Ａｒ流量５．０ｓｃｃｍ、Ｎ2流量５．０ｓｃｃｍ、基板温度を３００℃、到達真空度１．５３×１０-5Ｐａの条件で、ＡｌＮバッファ層２を形成した。その後にアニール工程で、熱処理装置のカーボンサセプタ内に基板をセットし、減圧した後にＮ2封入して３８０ｔｏｒｒにし、昇温レート２０℃／ｍｉｎで１６００℃まで昇温して一時間アニールした。次に半導体素子成長工程で、温度を１０１０℃まで昇温した後に成長温度を１０１０℃で一定とし、第１段階ではＶ／ＩＩＩ比４４００、圧力９３３ｈＰａ、成長時間を１０分とし、第２段階ではＶ／ＩＩＩ比１００、圧力１００ｈＰａ、成長時間を９０分でａ面ＧａＮ層３を成長させて半導体成長用基板を得た。ＡｌＮバッファ層２の膜厚が３０ｎｍ、９０ｎｍ、１８０ｎｍのものをそれぞれ実施例１～３とした。 (Examples 1 to 3)
In the sputtering process, the AlN buffer layer 2 is formed under the conditions of RF output of 450 W, 10 rpm, Ar flow rate of 5.0 sccm, N 2 flow rate of 5.0 sccm, substrate temperature of 300 ° C., and ultimate vacuum of 1.53 × 10 −5 Pa. did. After that, in the annealing step, the substrate was set in the carbon susceptor of the heat treatment apparatus, depressurized, and then N 2 was filled to 380 torr, and the temperature was raised to 1600 ° C. at a heating rate of 20 ° C./min and annealed for 1 hour. Next, in the semiconductor element growth step, the temperature was raised to 1010 ° C., and then the growth temperature was kept constant at 1010 ° C., the V / III ratio was 4400, the pressure was 933 hPa, and the growth time was 10 minutes in the first step, and the second step was the second step. The a-plane GaN layer 3 was grown at a V / III ratio of 100, a pressure of 100 hPa, and a growth time of 90 minutes to obtain a semiconductor growth substrate. The AlN buffer layers 2 having the film thicknesses of 30 nm, 90 nm, and 180 nm were taken as Examples 1 to 3, respectively.
　（比較例１～３）
　スパッタ工程の後にアニール工程を実施せず、半導体素子成長工程を実施した他は実施例１と同様の条件で半導体成長用基板を得た。ＡｌＮバッファ層２の膜厚が３０ｎｍ、９０ｎｍ、１８０ｎｍのものをそれぞれ比較例１～３とした。 (Comparative Examples 1 to 3)
A semiconductor growth substrate was obtained under the same conditions as in Example 1 except that the semiconductor element growth step was performed without performing the annealing step after the sputtering step. The AlN buffer layers 2 having thicknesses of 30 nm, 90 nm, and 180 nm were set as Comparative Examples 1 to 3, respectively.
　（比較例４）
　スパッタ工程での基板温度を６００℃とし、到達真空度が４．４７×１０-4Ｐａである他は比較例１と同様の条件で比較例４の半導体成長用基板を得た。 (Comparative example 4)
A semiconductor growth substrate of Comparative Example 4 was obtained under the same conditions as in Comparative Example 1 except that the substrate temperature in the sputtering step was 600 ° C. and the ultimate vacuum was 4.47 × 10 −4 Pa.
　（比較例５～７）
　スパッタ工程を用いず、ｒ面を主面とするサファイア基板１上に、ＭＯＣＶＤ法を用いてＡｌＮバッファ層２をエピタキシャル成長させた他は、比較例１～３と同様にして半導体成長用基板を得た。成長条件は、成長温度１３４０℃、Ｖ／ＩＩＩ比６３００、であった。ＡｌＮバッファ層２の膜厚が３０ｎｍ、９０ｎｍ、１８０ｎｍのものをそれぞれ比較例５～７とした。 (Comparative Examples 5 to 7)
Substrates for semiconductor growth were obtained in the same manner as in Comparative Examples 1 to 3 except that the AlN buffer layer 2 was epitaxially grown on the sapphire substrate 1 having the r-plane as the main surface by the MOCVD method without using the sputtering process. It was The growth conditions were a growth temperature of 1340 ° C. and a V / III ratio of 6300. The AlN buffer layers 2 having thicknesses of 30 nm, 90 nm, and 180 nm were set as Comparative Examples 5 to 7, respectively.
　（スパッタ条件）
　図２は、スパッタ条件の違いによるＡｌＮバッファ層２中の不純物濃度と、ａ面ＧａＮ層３の結晶性を示す表である。ＡｌＮバッファ層２中の不純物濃度はＳＩＭＳ（Ｓｅｃｏｎｄａｒｙ　Ｉｏｎ　Ｍａｓｓ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）により測定し、ａ面ＧａＮ層３の結晶性はＳＥＭ（Ｓｃａｎｎｉｎｇ　Ｅｌｅｃｔｒｏｎ　Ｍｉｃｒｏｓｃｏｐｅ）像とＸ線回折により評価した。図中左側に実施例１の結果を示し、図中右側に比較例４の結果を示している。 (Sputtering conditions)
FIG. 2 is a table showing the impurity concentration in the AlN buffer layer 2 and the crystallinity of the a-plane GaN layer 3 depending on the difference in sputtering conditions. The impurity concentration in the AlN buffer layer 2 was measured by SIMS (Secondary Ion Mass Spectrometry), and the crystallinity of the a-plane GaN layer 3 was evaluated by SEM (Scanning Electron Microscope) image and X-ray diffraction. The results of Example 1 are shown on the left side of the figure, and the results of Comparative Example 4 are shown on the right side of the figure.
　図２に示したように、ＡｌＮバッファ層２に含まれる不純物濃度は、実施例１では酸素濃度が６．５８×１０20ａｔｏｍｓ／ｃｍ3、炭素濃度が２．１９×１０19ａｔｏｍｓ／ｃｍ3であった。また、比較例４では酸素濃度が２．６６×１０21ａｔｏｍｓ／ｃｍ3であり、炭素が９．７２×１０19ａｔｏｍｓ／ｃｍ3であった。ＳＥＭ像およびＸ線回折の結果から、実施例１ではＡｌＮバッファ層２上に単結晶のａ面ＧａＮ層３を成長できているが、比較例４では単結晶のａ面ＧａＮ層３を成長できていないことわかる。したがって、スパッタ条件が５００℃以上であると、到達真空度が低いため不純物濃度が高くなり、単結晶のａ面ＧａＮ層を成長させにくいことがわかる。 As shown in FIG. 2, the concentration of impurities contained in the AlN buffer layer 2 was 6.58 × 10 20 atoms / cm 3 in Example 1 and 2.19 × 10 19 atoms / cm 3 in carbon concentration. Met. In Comparative Example 4, the oxygen concentration was 2.66 × 10 21 atoms / cm 3 and the carbon concentration was 9.72 × 10 19 atoms / cm 3 . From the results of the SEM image and the X-ray diffraction, in Example 1, the single crystal a-plane GaN layer 3 could be grown on the AlN buffer layer 2, but in Comparative Example 4, the single crystal a-plane GaN layer 3 could be grown. I know I haven't. Therefore, it is understood that when the sputtering condition is 500 ° C. or higher, the ultimate vacuum degree is low and the impurity concentration is high, so that it is difficult to grow the single crystal a-plane GaN layer.
　（ＡｌＮバッファ層２の評価）
　図３Ａ及び図３Ｂは、ＡｌＮバッファ層２のＸＲＣ（Ｘ－ｒａｙ　Ｒｏｃｋｉｎｇ　Ｃｕｒｖｅ）測定結果を示すグラフである。図３Ａはａ面での半値幅を示し、図３Ｂはｍ面での半値幅を示している。グラフ中のａｎｎｅａｌｅｄ　ｓｐ－ＡｌＮは実施例１～３を示し、ｓｐ－ＡｌＮは比較例１～３を示し、ｅｐ－ＡｌＮは比較例５～７を示している。 (Evaluation of AlN buffer layer 2)
3A and 3B are graphs showing XRC (X-ray Rocking Curve) measurement results of the AlN buffer layer 2. FIG. 3A shows the full width at half maximum on the a-plane, and FIG. 3B shows the full width at half maximum on the m-plane. In the graph, annealed sp-AlN indicates Examples 1 to 3, sp-AlN indicates Comparative Examples 1 to 3, and ep-AlN indicates Comparative Examples 5 to 7.
　図３Ａ及び図３Ｂに示したように、ａ面およびｍ面での半値幅は比較例１～３で最も大きく、実施例１～３が最も小さい。したがって、スパッタ法で形成した後に、アニール工程を経た実施例１～３は、ＡｌＮバッファ層２の結晶性が最も良好であることがわかる。 As shown in FIGS. 3A and 3B, the FWHMs on the a-plane and the m-plane are the largest in Comparative Examples 1 to 3, and the smallest in Examples 1 to 3. Therefore, it can be seen that the crystallinity of the AlN buffer layer 2 is the best in Examples 1 to 3 which have undergone the annealing process after being formed by the sputtering method.
　図４は、ＡｌＮバッファ層２のＸ線回折測定結果を示すグラフである。図４の（Ａ－１）は２θ／θ測定結果を示し、図４の（Ｂ－１）は２θχ／φ測定結果を示し、図４の（Ａ－２）は膜厚とａ面でのピーク回折強度の関係を示し、図４の（Ｂ－２）は膜厚とｍ面でのピーク回折強度の関係を示している。 FIG. 4 is a graph showing the X-ray diffraction measurement result of the AlN buffer layer 2. 4A-1 shows the 2θ / θ measurement result, FIG. 4B-1 shows the 2θχ / φ measurement result, and FIG. 4A-2 shows the film thickness and the a-plane. The relationship between the peak diffraction intensities is shown, and FIG. 4B-2 shows the relationship between the film thickness and the peak diffraction intensities on the m-plane.
　図４の（Ａ－１）では、全ての測定結果で５３°付近と５９°付近に回折ピークが確認できる。５３°付近のピークはサファイア基板１のｒ面に対応し、５９°付近のピークはＡｌＮバッファ層２のａ面に対応している。また実施例１～３では、バルクのＡｌＮ単結晶での理論的なピーク角度よりも、ピーク角度が０．２～０．８度の範囲で低角側にシフトしている。２θ／θ測定における低角側へのピーク角度は、ＡｌＮバッファ層２の積層方向における格子面間隔の広がりを示しており、実施例１～３では積層方向に引張応力が働いていると思われる。 In (A-1) of FIG. 4, diffraction peaks can be confirmed around 53 ° and around 59 ° in all measurement results. The peak near 53 ° corresponds to the r-plane of the sapphire substrate 1, and the peak near 59 ° corresponds to the a-plane of the AlN buffer layer 2. Further, in Examples 1 to 3, the peak angle was shifted to the lower angle side in the range of 0.2 to 0.8 degrees than the theoretical peak angle of the bulk AlN single crystal. The peak angle to the low angle side in the 2θ / θ measurement shows the spread of the lattice plane spacing in the stacking direction of the AlN buffer layer 2, and it is considered that tensile stress acts in the stacking direction in Examples 1 to 3. .
　また図４の（Ａ－２）に示すように、実施例１～３では比較例１～３よりもピーク強度が著しく大きく、実施例１，２では比較例５，６よりもピーク強度が大きい。したがって、実施例１，２では、ＡｌＮバッファ層２が積層方向に良好にａ軸配向していることがわかる。 Further, as shown in (A-2) of FIG. 4, the peak intensities of Examples 1 to 3 are significantly higher than those of Comparative Examples 1 to 3, and the peak intensities of Examples 1 and 2 are higher than those of Comparative Examples 5 and 6. . Therefore, it can be seen that in Examples 1 and 2, the AlN buffer layer 2 is favorably a-axis oriented in the stacking direction.
　図４の（Ｂ－１）では、全ての測定結果で３３°付近に回折ピークが確認できる。３３°付近のピークはＡｌＮバッファ層２のｍ面に対応している。また実施例１～３では、バルクのＡｌＮ単結晶での理論的なピーク角度よりも、ピーク角度が０．２～０．８度の範囲で高角側にシフトしている。２θχ／φ測定における高角側へのピーク角度は、ＡｌＮバッファ層２の面内方向における格子面間隔の狭まりを示しており、実施例１～３では面内圧縮応力が働いていると思われる。 In (B-1) of Fig. 4, a diffraction peak can be confirmed around 33 ° in all the measurement results. The peak near 33 ° corresponds to the m-plane of the AlN buffer layer 2. Further, in Examples 1 to 3, the peak angle was shifted to a higher angle side within a range of 0.2 to 0.8 degrees than the theoretical peak angle of the bulk AlN single crystal. The peak angle to the high angle side in the 2θχ / φ measurement indicates the narrowing of the lattice plane spacing in the in-plane direction of the AlN buffer layer 2, and it is considered that the in-plane compressive stress is working in Examples 1 to 3.
　また図４の（Ｂ－２）に示すように、実施例１，２では比較例１，２よりもピーク強度が著しく大きく、実施例１では比較例５よりもピーク強度が大きい。したがって、実施例１，２では、ＡｌＮバッファ層２が面内方向に良好にｍ軸配向していることがわかる。 Further, as shown in (B-2) of FIG. 4, the peak intensities of Examples 1 and 2 are significantly larger than those of Comparative Examples 1 and 2, and the peak intensity of Example 1 is larger than that of Comparative Example 5. Therefore, in Examples 1 and 2, it can be seen that the AlN buffer layer 2 is favorably oriented in the in-plane m-axis.
　図４で示したように、ＡｌＮバッファ層２の面内方向および積層方向での一軸配向性は実施例１，２が最も高く、面内方向の一軸配向性は膜厚が小さいほど良好であると言える。また実施例１～３では、バルクのＡｌＮ単結晶での理論的なピーク角度よりも積層方向で０．２～０．８度の範囲で低角側にシフトし、面内方向で０．２～０．８度の範囲で高角側にシフトしており、ＡｌＮバッファ層２に面内圧縮応力が加わっている。 As shown in FIG. 4, the uniaxial orientation in the in-plane direction and the stacking direction of the AlN buffer layer 2 is highest in Examples 1 and 2, and the uniaxial orientation in the in-plane direction is better as the film thickness is smaller. Can be said. Further, in Examples 1 to 3, the angle was shifted to the lower angle side in the range of 0.2 to 0.8 degrees in the stacking direction from the theoretical peak angle in the bulk AlN single crystal, and 0.2 in the in-plane direction. The angle shifts to the high angle side in the range of up to 0.8 degrees, and the in-plane compressive stress is applied to the AlN buffer layer 2.
　（ａ面ＧａＮ層３の結晶性評価）
　図５は、ａ面ＧａＮ層３のＸＲＣ測定の回折スペクトルを示すグラフである。図５の（Ａ）はａ面内のｃ軸方向での結果を示し、図５の（Ｂ）はａ面内のｍ軸方向での結果を示し、図５の（Ｃ）は｛１０－１１｝面内での結果を示している。図５の（Ａ）～（Ｃ）では、ＡｌＮバッファ層２の膜厚を３０ｎｍとした実施例１、比較例１、比較例５の測定結果を示している。 (Crystallinity evaluation of a-plane GaN layer 3)
FIG. 5 is a graph showing a diffraction spectrum of the a-plane GaN layer 3 measured by XRC. 5A shows the result in the c-axis direction in the a-plane, FIG. 5B shows the result in the m-axis direction in the a-plane, and FIG. 5C shows {10- 11} shows the results in the plane. 5A to 5C show the measurement results of Example 1, Comparative Example 1, and Comparative Example 5 in which the thickness of the AlN buffer layer 2 was 30 nm.
　図５の（Ａ）に示した測定結果における半値幅（単位：ａｒｃｓｅｃ）は、実施例１が５０５、比較例１が６０９、比較例５が５６２であった。図５の（Ｂ）では、実施例１が７２９、比較例１が７５８、比較例５が９９５であった。図５の（Ｃ）では、実施例１が１０７１、比較例１が１４７２、比較例５が１４０４であった。 The full width at half maximum (unit: arcsec) in the measurement result shown in FIG. 5A was 505 in Example 1, 609 in Comparative Example 1, and 562 in Comparative Example 5. In FIG. 5 (B), Example 1 was 729, Comparative Example 1 was 758, and Comparative Example 5 was 995. In FIG. 5C, the result was 1071 in Example 1, 1472 in Comparative Example 1, and 1404 in Comparative Example 5.
　図５の（Ａ）～（Ｃ）に示したように、実施例１の結晶性は比較例１，５よりも良好である。実施例１のように、面内方向および積層方向での一軸配向性を有するＡｌＮバッファ層２を用いることで、ａ面ＧａＮ層３の結晶性と表面平坦性を良好にすることができる。 As shown in (A) to (C) of FIG. 5, the crystallinity of Example 1 is better than that of Comparative Examples 1 and 5. By using the AlN buffer layer 2 having the uniaxial orientation in the in-plane direction and the stacking direction as in Example 1, the crystallinity and surface flatness of the a-plane GaN layer 3 can be improved.
　以上に述べたように、本実施形態の半導体成長用基板では、ＡｌＮバッファ層が積層方向および面内方向に一軸配向性を有することで、異常成長を抑制し結晶性が良好で表面平坦性に優れた高品質なａ面ＧａＮ層を成長させることが可能となる。 As described above, in the semiconductor growth substrate of the present embodiment, the AlN buffer layer has the uniaxial orientation in the stacking direction and the in-plane direction, so that abnormal growth is suppressed and crystallinity is good and surface flatness is improved. It becomes possible to grow an excellent and high quality a-plane GaN layer.
　（第２実施形態）
　次に、本発明の第２実施形態について図６を用いて説明する。図６は第２実施形態の半導体装置であるＬＥＤ１０を示す模式断面図である。図６に示すようにＬＥＤ１０は、ｒ面を主面とするサファイア基板１１、ＡｌＮバッファ層１２、ａ面ＧａＮ層１３、ｎ型半導体層１４、発光層（活性層）１５、ｐ型半導体層１６、ｎ側電極１７、ｐ側電極１８を有している。 (2nd Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 6 is a schematic cross-sectional view showing the LED 10 which is the semiconductor device of the second embodiment. As shown in FIG. 6, the LED 10 includes a sapphire substrate 11 having an r-plane as a main surface, an AlN buffer layer 12, an a-plane GaN layer 13, an n-type semiconductor layer 14, a light emitting layer (active layer) 15, and a p-type semiconductor layer 16. , N-side electrode 17 and p-side electrode 18.
　第１実施形態と同様に、ｒ面を主面とするサファイア基板１１を用意し、スパッタ工程でＡｌＮバッファ層１２をサファイア基板１１上に形成する。次に、アニール工程でＡｌＮバッファ層１２をアニールして単結晶化し、積層方向および面内方向に一軸配向性をもたせる。次に、半導体層成長工程でａ面ＧａＮ層１３をＡｌＮバッファ層１２上にエピタキシャル成長させ、続けてＭＯＣＶＤ法でｎ型半導体層１４、発光層１５、ｐ型半導体層１６を順次成長させて半導体基板を得る。 Similar to the first embodiment, a sapphire substrate 11 whose main surface is the r-plane is prepared, and an AlN buffer layer 12 is formed on the sapphire substrate 11 by a sputtering process. Next, in the annealing step, the AlN buffer layer 12 is annealed to be a single crystal, and has uniaxial orientation in the stacking direction and the in-plane direction. Next, the a-plane GaN layer 13 is epitaxially grown on the AlN buffer layer 12 in the semiconductor layer growth step, and then the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 are sequentially grown by the MOCVD method to form a semiconductor substrate. To get
　次に、所定のパターンを用いてフォトリソグラフィーとエッチングによりｐ型半導体層１６と発光層１５の一部を除去してｎ型半導体層１４の一部を露出させる。次に、ｎ型半導体層１４とｐ型半導体層１６の露出面に蒸着等により電極材料を形成し、ダイシングして個別チップ化することでＬＥＤ１０を得る。 Next, a part of the p-type semiconductor layer 16 and the light emitting layer 15 is removed by photolithography and etching using a predetermined pattern to expose a part of the n-type semiconductor layer 14. Next, an LED 10 is obtained by forming an electrode material on the exposed surfaces of the n-type semiconductor layer 14 and the p-type semiconductor layer 16 by vapor deposition or the like, and dicing it into individual chips.
　ここではｎ型半導体層１４、ｐ型半導体層１６をそれぞれ単層で説明したが、それぞれ材料や組成の異なる複数の層を含んでいるとしてもよい。例えば、ｎ型半導体層１４とｐ型半導体層１６にクラッド層、コンタクト層、電流拡散層、電子ブロック層、導波路層などを含めてもよい。また、発光層１５も単層で説明したが、多重量子井戸構造（ＭＱＷ：Ｍｕｌｔｉ　Ｑｕａｎｔｕｍ　Ｗｅｌｌ）などの複数層で構成してもよい。 Here, although the n-type semiconductor layer 14 and the p-type semiconductor layer 16 have been described as single layers, respectively, a plurality of layers having different materials and compositions may be included. For example, the n-type semiconductor layer 14 and the p-type semiconductor layer 16 may include a clad layer, a contact layer, a current diffusion layer, an electron block layer, a waveguide layer, and the like. Although the light emitting layer 15 has been described as a single layer, it may be formed of a plurality of layers such as a multi quantum well structure (MQW: Multi Quantum Well).
　ｎ型半導体層１４は、ａ面ＧａＮ層１３上でエピタキシャル成長したａ面を主面とする層である。また、ｎ型半導体層１４は、ｎ型不純物がドープされた半導体層であり、ｎ側電極１７から電子が注入されて発光層１５に電子を供給する層である。ｎ型半導体層１４を構成する材料は、ＩＩＩ－Ｖ族化合物半導体層としては、例えばＧａＮ、ＡｌＧａＮ、ＩｎＧａＮ、ＡｌＩｎＧａＮなどが挙げられ、ｎ型不純物としてはＳｉなどが挙げられる。 The n-type semiconductor layer 14 is a layer whose main surface is the a-plane epitaxially grown on the a-plane GaN layer 13. The n-type semiconductor layer 14 is a semiconductor layer doped with an n-type impurity, and is a layer into which electrons are injected from the n-side electrode 17 and supplies the electrons to the light emitting layer 15. Examples of the material forming the n-type semiconductor layer 14 include GaN, AlGaN, InGaN, and AlInGaN as the III-V compound semiconductor layer, and Si as the n-type impurity.
　発光層１５は、ｎ型半導体層１４上でエピタキシャル成長したａ面を主面とする半導体層である。発光層１５の層内で電子と正孔が発光再結合することでＬＥＤ１０が発光する。発光層１５は、ｎ型半導体層１４とｐ型半導体層１６よりもバンドギャップが小さい材料で構成されている。このような材料としては、例えばＩｎＧａＮ、ＡｌＩｎＧａＮなどが挙げられる。発光層１５は意図的に不純物を含まないノンドープとしてもよく、ｎ型不純物を含むｎ型やｐ型不純物を含むｐ型としてもよい。発光層１５は、ａ面を主面とする半導体層なので、厚膜化してもピエゾ電界による電子と正孔の空間的な分離は生じにくく、電流密度を高くしても効率的に電子と正孔が発光再結合できる。 The light emitting layer 15 is a semiconductor layer whose main surface is an a-plane epitaxially grown on the n-type semiconductor layer 14. The LED 10 emits light when the electrons and the holes are radiatively recombined in the light emitting layer 15. The light emitting layer 15 is made of a material having a smaller band gap than the n-type semiconductor layer 14 and the p-type semiconductor layer 16. Examples of such a material include InGaN and AlInGaN. The light emitting layer 15 may be non-doped intentionally containing no impurities, n-type containing n-type impurities or p-type containing p-type impurities. Since the light-emitting layer 15 is a semiconductor layer having the a-plane as the main surface, even if the light-emitting layer 15 is made thicker, spatial separation of electrons and holes due to the piezoelectric field is less likely to occur, and even if the current density is increased, positive electrons and holes are efficiently generated. The holes can be radiatively recombined.
　ｐ型半導体層１６は、発光層１５上でエピタキシャル成長したａ面を主面とする半導体層である。ｐ型半導体層１６には、ｐ側電極１８から正孔が注入される。そして、ｐ型半導体層１６は、注入された正孔を発光層１５に供給する。ｐ型半導体層１６を構成する材料は、ＩＩＩ－Ｖ族化合物半導体層としては、例えばＧａＮ、ＡｌＧａＮ、ＩｎＧａＮ、ＡｌＩｎＧａＮなどが挙げられ、ｐ型不純物としてはＺｎやＭｇなどが挙げられる。 The p-type semiconductor layer 16 is a semiconductor layer whose main surface is the a-plane epitaxially grown on the light emitting layer 15. Holes are injected from the p-side electrode 18 into the p-type semiconductor layer 16. Then, the p-type semiconductor layer 16 supplies the injected holes to the light emitting layer 15. Examples of the material forming the p-type semiconductor layer 16 include GaN, AlGaN, InGaN, and AlInGaN for the III-V group compound semiconductor layer, and Zn, Mg, and the like for the p-type impurity.
　本実施の形態でも、積層方向および面内方向に一軸配向性を有するＡｌＮバッファ層１２上に、ａ面ＧａＮ層１３を下地層としてｎ型半導体層１４、発光層１５、ｐ型半導体層１６をエピタキシャル成長させている。したがって、第１実施形態で述べたようにａ面ＧａＮ層１３は結晶性も表面平坦性も良好であり、その上に成長されたｎ型半導体層１４、発光層１５、ｐ型半導体層１６も結晶性と表面平坦性が良好となる。これにより、ｎ型半導体層１４、発光層１５、ｐ型半導体層１６の特性も良好になり、ＬＥＤ１０の外部量子効率の向上などが見込まれる。なお、本実施形態は、機能層として、ｎ型半導体層１４、発光層１５、及びｐ型半導体層１６を備えた例である。ここで、機能層とは、半導体素子において所定の電気的、化学的な機能を発揮するための層である。ある局面において、半導体素子は、発光層１５を備えていなくてもよい。 Also in the present embodiment, the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 are formed on the AlN buffer layer 12 having a uniaxial orientation in the stacking direction and the in-plane direction with the a-plane GaN layer 13 as a base layer. It is epitaxially grown. Therefore, as described in the first embodiment, the a-plane GaN layer 13 has good crystallinity and surface flatness, and the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 grown on the a-plane GaN layer 13 are also good. Good crystallinity and surface flatness. As a result, the characteristics of the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 are improved, and the external quantum efficiency of the LED 10 is expected to be improved. The present embodiment is an example in which the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 are provided as the functional layers. Here, the functional layer is a layer for exhibiting predetermined electrical and chemical functions in the semiconductor element. In one aspect, the semiconductor element may not include the light emitting layer 15.
　（第３実施形態）
　本発明の半導体装置であるＬＥＤ１０は、上述したようにピエゾ電界によるドループが少なく、且つａ面内での異方性が小さく良好な結晶品質であることから高輝度化を実現できるので、車両用灯具などの灯具に用いることでチップ数の低減や高出力化を図ることが可能となる。 (Third embodiment)
As described above, the LED 10 which is the semiconductor device of the present invention can achieve high brightness because it has little droop due to the piezoelectric field and has small anisotropy in the a-plane and good crystal quality. By using it for a lamp such as a lamp, it is possible to reduce the number of chips and increase the output.
　さらに、半導体装置はＬＥＤに限定されず、半導体レーザや高電子移動度トランジスタ（ＨＥＭＴ：Ｈｉｇｈ　Ｅｌｅｃｔｒｏｎ　Ｍｏｂｉｌｉｔｙ　Ｔｒａｎｓｉｓｔｏｒ）等の他の用途であってもよい。これらの半導体装置においても、機能層とは、半導体素子において所定の電気的、化学的な機能を発揮するための層である。 Further, the semiconductor device is not limited to the LED, and may be other applications such as a semiconductor laser and a high electron mobility transistor (HEMT: High Electron Mobility Transistor). Also in these semiconductor devices, the functional layer is a layer for exhibiting a predetermined electrical and chemical function in the semiconductor element.
　本発明は上述した各実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。 The present invention is not limited to the embodiments described above, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.
　本出願は、２０１８年１０月１２日出願の日本国特許出願（特願２０１８－１９３５６９号）に基づくものであり、その内容はここに参照として取り込まれる。 This application is based on a Japanese patent application filed on October 12, 2018 (Japanese Patent Application No. 2018-193569), the contents of which are incorporated herein by reference.
１０…ＬＥＤ
１，１１…サファイア基板
２，１２…ＡｌＮバッファ層
３，１３…ａ面ＧａＮ層
１４…ｎ型半導体層
１５…発光層
１６…ｐ型半導体層
１７…ｎ側電極
１８…ｐ側電極 10 ... LED
1, 11 ... Sapphire substrate 2, 12 ... AlN buffer layers 3, 13 ... a-plane GaN layer 14 ... N-type semiconductor layer 15 ... Light-emitting layer 16 ... P-type semiconductor layer 17 ... N-side electrode 18 ... P-side electrode

Claims (8)

  1. 　ｒ面を主面とするサファイア基板と、
    　前記主面上に形成されたＡｌＮバッファ層と、を備え、
    　前記ＡｌＮバッファ層は、積層方向および面内方向に一軸配向性を有する、半導体成長用基板。     a sapphire substrate whose main surface is the r-plane,
    An AlN buffer layer formed on the main surface,
    The substrate for semiconductor growth, wherein the AlN buffer layer has a uniaxial orientation in the stacking direction and the in-plane direction.
  2. 　請求項１に記載の半導体成長用基板であって、
    　前記ＡｌＮバッファ層は、積層方向におけるＸ線回折のピーク角度が、バルクＡｌＮ単結晶よりも０．２～０．８度の範囲で低角側にシフトしている、半導体成長用基板。     The semiconductor growth substrate according to claim 1, wherein
    The AlN buffer layer is a substrate for semiconductor growth, wherein the peak angle of X-ray diffraction in the stacking direction is shifted to a lower angle side in the range of 0.2 to 0.8 degrees than that of the bulk AlN single crystal.
  3. 　請求項１または２に記載の半導体成長用基板であって、
    　前記ＡｌＮバッファ層は、面内方向におけるＸ線回折のピーク角度が、バルクＡｌＮ単結晶よりも０．２～０．８度の範囲で高角側にシフトしている、半導体成長用基板。     The semiconductor growth substrate according to claim 1 or 2, wherein
    The AlN buffer layer is a semiconductor growth substrate in which the peak angle of X-ray diffraction in the in-plane direction is shifted to a higher angle side in the range of 0.2 to 0.8 degrees than the bulk AlN single crystal.
  4. 　請求項１から３のいずれか一項に記載の半導体成長用基板であって、
    　前記ＡｌＮバッファ層に含まれる炭素の不純物濃度が、２．５×１０19ａｔｏｍｓ／ｃｍ3未満である、半導体成長用基板。     The semiconductor growth substrate according to any one of claims 1 to 3,
    A substrate for semiconductor growth, wherein the impurity concentration of carbon contained in the AlN buffer layer is less than 2.5 × 10 19 atoms / cm 3 .
  5. 　請求項１から４のいずれか一項に記載の半導体成長用基板であって、
    　前記ＡｌＮバッファ層に含まれる酸素の不純物濃度が、７．０×１０20ａｔｏｍｓ／ｃｍ3未満である、半導体成長用基板。     The semiconductor growth substrate according to any one of claims 1 to 4,
    A substrate for semiconductor growth, wherein the impurity concentration of oxygen contained in the AlN buffer layer is less than 7.0 × 10 20 atoms / cm 3 .
  6. 　請求項１から５のいずれか一項に記載の半導体成長用基板を用い、
    　前記半導体成長用基板上に機能層を備える、半導体素子。     Using the semiconductor growth substrate according to claim 1,
    A semiconductor device comprising a functional layer on the semiconductor growth substrate.
  7. 　請求項１から５の何れか一つに記載の半導体成長用基板を用い、
    　前記半導体成長用基板上に活性層を備える、半導体発光素子。     The semiconductor growth substrate according to claim 1,
    A semiconductor light emitting device comprising an active layer on the semiconductor growth substrate.
  8. 　ｒ面を主面とするサファイア基板上にスパッタ法を用いてＡｌＮバッファ層を形成するスパッタ工程と、
    　前記ＡｌＮバッファ層をアニールして、積層方向および面内方向に一軸配向性を有する単結晶化するアニール工程と、
    　前記ＡｌＮバッファ層上にａ面ＧａＮ層を成長させる半導体層成長工程と、を備える、半導体素子製造方法。     a sputtering step of forming an AlN buffer layer on the sapphire substrate whose main surface is the r-plane by a sputtering method;
    An annealing step of annealing the AlN buffer layer to form a single crystal having uniaxial orientation in the stacking direction and the in-plane direction;
    A semiconductor layer growing step of growing an a-plane GaN layer on the AlN buffer layer.
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JP2010183050A (en) * 2009-02-04 2010-08-19 Jiaotong Univ Multilayered structure having non-polar group iii nitride layer, and method of manufacturing the same
JP2011082570A (en) * 2011-01-11 2011-04-21 Showa Denko Kk Method of manufacturing group iii nitride semiconductor light emitting device
JP2017154964A (en) * 2016-02-26 2017-09-07 国立研究開発法人理化学研究所 Crystal substrate, ultraviolet emission element, and manufacturing method thereof
JP2018065733A (en) * 2016-03-02 2018-04-26 株式会社小糸製作所 Semiconductor substrate, semiconductor light emitting element and lamp fitting

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010183050A (en) * 2009-02-04 2010-08-19 Jiaotong Univ Multilayered structure having non-polar group iii nitride layer, and method of manufacturing the same
JP2011082570A (en) * 2011-01-11 2011-04-21 Showa Denko Kk Method of manufacturing group iii nitride semiconductor light emitting device
JP2017154964A (en) * 2016-02-26 2017-09-07 国立研究開発法人理化学研究所 Crystal substrate, ultraviolet emission element, and manufacturing method thereof
JP2018065733A (en) * 2016-03-02 2018-04-26 株式会社小糸製作所 Semiconductor substrate, semiconductor light emitting element and lamp fitting

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