WO2020073691A1 - 闪存自检的方法、固态硬盘以及存储装置 - Google Patents

闪存自检的方法、固态硬盘以及存储装置 Download PDF

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WO2020073691A1
WO2020073691A1 PCT/CN2019/093313 CN2019093313W WO2020073691A1 WO 2020073691 A1 WO2020073691 A1 WO 2020073691A1 CN 2019093313 W CN2019093313 W CN 2019093313W WO 2020073691 A1 WO2020073691 A1 WO 2020073691A1
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flash memory
self
data
test
perform
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PCT/CN2019/093313
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English (en)
French (fr)
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张吉兴
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深圳大普微电子科技有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

Definitions

  • the invention relates to the field of storage technology, in particular to a flash memory self-test method, a solid-state hard disk, and a storage device.
  • the flash memory cell (Flash) in the flash memory uses the voltage value of the floating gate transistor (Floating Gate Transistor) to represent the stored data.
  • Floating Gate Transistor floating gate transistor
  • MLC Multi Level Cell
  • each flash memory cell can store two bits of data: LSB (Least Significant Bit) and MSB (Most Significant Bit). Therefore, each flash memory cell has four types of work
  • the states are State 1, State 2, State 3, and State 4, respectively.
  • state 1 is the erased state, the voltage value is the smallest, the data stored in the flash memory unit is 11; state 2 or state 3 is the incomplete write state, the voltage value is between the erased state and the complete state, the flash memory unit stores The data is 10 or 01; state 4 is the complete state, the voltage is the largest, and the data stored in the flash memory unit is 00.
  • the data stored in the flash memory cell is 11; if the voltage value of the floating gate transistor is between the reference voltage 1 and the reference voltage 2, the data stored in the flash memory cell is considered Is 10, if the voltage value of the floating gate transistor is between the reference voltage 2 and the reference voltage 3, the data stored in the flash memory cell is considered to be 01, and if the voltage value of the floating gate transistor is greater than the reference voltage 3, the data stored in the flash memory cell is considered to be 00.
  • the electrons in the flash memory cell When the flash memory is not used for a long time (such as a long-term power-off state), the electrons in the flash memory cell will leak, its voltage value will decrease, and the distribution state will shift, resulting in a retention error (Retention Error).
  • the initial data written to a flash memory unit is 01, which is state 3, and the voltage value is between the reference voltage 2 and the reference voltage 3, and then the flash memory in the solid state drive is in an occasional use state, that is, occasionally At power-on, and the flash memory unit is not read or written during power-on, the electrons on the flash memory unit will gradually leak and the voltage value will gradually decrease.
  • the voltage value will decrease to less than the reference voltage 2, that is, the flash memory cell is changed from state 3 to state 2.
  • the voltage value read may be between the reference voltage 1 and the reference voltage 2, and the stored data is determined to be 10, that is, a retention error has occurred.
  • the current method to combat stuck errors is to use an error correction algorithm in the solid state drive. Specifically, when the host reads data from the flash memory of the solid state drive, when the read data has a retention error, that is, the bit is flipped, the error correction algorithm is enabled to try to correct it, and if it can be corrected, the corrected data is passed to If the host has a large number of stuck errors and the error correction algorithm cannot correct it, the host is reported as having an uncorrectable error.
  • an error correction algorithm is used to correct the retention error when reading data. If the data retention time in the flash memory of the solid state drive is long, the number of bits where the retention error occurs will increase with the retention time, then it will be large. The probability of an uncorrectable error occurs, causing the host to lose data, which the user cannot tolerate. In particular, if the host does not read for a long time after writing a piece of data (such as not for several years), then 100% uncorrectable errors will occur, which needs to be avoided.
  • the present application provides a flash memory self-checking method, a solid-state hard disk, and a storage device, which can reduce the retention error of the flash memory, thereby greatly reducing the probability of data loss in the flash memory.
  • a technical solution adopted in this application is to provide a method of self-testing of flash memory, which includes: detecting whether to trigger flash memory to perform self-test; The working state triggers the flash memory to perform a self-test.
  • the step of detecting whether to trigger the flash memory to perform the self-test includes: detecting the working state of the flash memory; if the detection result is that the flash memory is in the first working state, triggering the flash memory to perform a self-test during the idle period.
  • the step of detecting whether to trigger the flash memory to perform a self-test includes: detecting the working state of the flash memory; if the detection result is that the flash memory is in the second working state, detecting whether the working time of the flash memory exceeds a predetermined time threshold; If the threshold exceeds a predetermined time, the flash memory is triggered to perform a self-test.
  • the threshold value of the predetermined time is determined by the number of erasing times of the flash memory and the error correction capability of the error correction algorithm.
  • the step of triggering the flash memory to perform a self-test according to the working state of the flash memory includes: dividing the data in the flash memory into a plurality of data segments of a first predetermined amount of data; The data in each data segment is self-checked.
  • the steps of self-checking the data in each data segment in different idle periods include: after completing the self-check operation on the data in the previous data segment, check whether the flash memory is in the idle period; if the test result If the flash memory is in the idle period, continue to perform self-test on the data of the next data segment.
  • the step of triggering the flash memory to perform a self-test according to the working state of the flash memory includes: dividing the data in the flash memory into a plurality of data segments of a second predetermined amount of data; The data in the data segment is self-checked.
  • the steps of self-checking the data in each data segment include: reading the data stored in the data segment sequentially in units of physical pages; obtaining the number of error correction bits for error correction of the read data; detecting corrections Whether the number of error bits is greater than the predetermined number of bits threshold; if the detection result is that the number of error correction bits is greater than the predetermined number of bits threshold, the data in the physical page is corrected.
  • a solid-state hard disk which includes a processor, a storage controller coupled to the processor, and a flash memory, where the storage controller stores storage The program instructions of the flash memory self-test method of any one of the above; the processor is used to execute the program instructions stored by the storage controller to perform self-test on the flash memory.
  • Another technical solution adopted by the present application is to provide a storage device that stores a program file capable of implementing any of the above methods.
  • the flash memory self-test method, solid-state hard disk, and storage device of the present invention trigger the flash memory to perform a self-test according to the working state of the flash memory, can adaptively adjust the self-test, find and eliminate retention errors in advance, and greatly reduce the flash memory Retention error, which greatly reduces the probability of data loss in flash memory.
  • FIG. 1 is a schematic diagram of the working state of the flash memory unit in the prior art
  • FIG. 2 is a schematic diagram of a retention error of a flash memory unit in the prior art
  • FIG. 3 is a schematic flowchart of the flash memory self-test method according to the first embodiment of the present invention.
  • FIG. 4 is a schematic flowchart of a flash memory self-test method according to a second embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the sub-process of FIG. 4 for self-checking the data in each data segment;
  • FIG. 6 is a schematic flowchart of a flash memory self-test method according to a third embodiment of the present invention.
  • Figure 7 is a schematic diagram of factors affecting retention errors
  • FIG. 8 is a schematic structural diagram of a solid-state hard disk according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a storage device according to an embodiment of the present invention.
  • first”, “second”, and “third” in this application are for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as “first”, “second”, and “third” may explicitly or implicitly include at least one of the features.
  • the meaning of “plurality” is at least two, such as two, three, etc., unless otherwise specifically limited. All directional indicators (such as up, down, left, right, front, back %) in the embodiments of the present application are only used to explain the relative positional relationship between the components in a certain posture (as shown in the drawings) , Movement, etc., if the specific posture changes, the directional indication changes accordingly.
  • FIG. 3 is a flowchart of the flash memory self-test method according to the first embodiment of the present invention. As shown in FIG. 3, the method includes steps:
  • Step S101 Detect whether the flash memory is triggered for self-test.
  • step S101 the stuck error in the flash memory gradually accumulates over time and gradually exceeds the error correction capability of the error correction algorithm. Then, when the data in the flash memory has not been used for a long time, the flash memory can be triggered in the background according to a predetermined rule. In order to avoid the problem that the retention time is too long and the retention error occurs, that is, the number of bits flipped is too many to be corrected.
  • the predetermined rule may be to trigger the flash memory to perform a self-test every predetermined time interval, the predetermined time interval may remain the same all the time, or may gradually become shorter as the working time of the flash memory.
  • Step S102 If the detection result is to trigger the flash memory to perform a self-test, then trigger the flash memory to perform a self-test according to the working state of the flash memory.
  • the working state of the flash memory includes a first working state and a second working state, where the first working state is a state in which the host has no read and write requests so that the flash memory has an idle period, and the second working state is that the host continues to have read and write The request causes the flash memory to have no idle period.
  • the step of self-checking the flash memory includes: self-checking the data in all physical blocks stored in the flash memory.
  • the step of the flash memory performing the self-test includes: acquiring the time stamp of the last accessed each physical block in the flash memory; acquiring the current time and the time stamp of the last accessed corresponding to each physical block Difference; self-check the data of each physical block whose difference exceeds a predetermined threshold.
  • the flash memory when the flash memory is triggered to perform a self-test in the background, it only performs self-test on the data in the physical blocks that the flash memory has not accessed for a long time, and does not need to perform a self-test on the data of all physical blocks in the flash memory, which can avoid the entire disk. Self-test, which can reduce the power consumption consumed by the self-test.
  • the step of self-checking the data of each physical block whose difference exceeds a predetermined threshold includes: judging whether each physical block whose difference exceeds the predetermined threshold is a physical block that has not been written with data after erasing, which can be understood as being erased A physical block without valid data after the division; if it is, the data in the physical block is not self-checked, otherwise the data in the physical block is self-checked.
  • the self-check process is directly skipped over the physical blocks without valid data, which can avoid the full-disk self-check, thereby reducing the power consumption consumed by the self-check.
  • the self-test of the flash memory When the self-test of the flash memory is triggered, the self-test is triggered according to the working state of the flash memory, which will ensure the normal operation of the background self-test operation without affecting the read and write operations of the flash memory.
  • the first embodiment of the present invention triggers the self-test of the flash memory according to the working state of the flash memory, which can adaptively adjust the self-test, find and eliminate the retention error in advance, greatly reduce the retention error of the flash memory, and thereby greatly reduce the data loss in the flash memory Probability.
  • FIG. 4 is a flowchart of a flash memory self-test method according to a second embodiment of the present invention. It should be noted that if there are substantially the same results, the method of the present invention is not limited to the sequence shown in FIG. 4. As shown in Figure 4, the method includes the following steps:
  • Step S201 Detect the working state of the flash memory.
  • the working state of the flash memory includes a first working state and a second working state, where the first working state is a state where the host has no read / write request so that the flash memory has an idle period, and the second working state is that the host continues to read and write The request causes the flash memory to have no idle period.
  • Step S202 If the detection result is that the flash memory is in the first working state, trigger the flash memory to perform a self-test during the idle period.
  • step S202 the flash memory self-test is triggered during the idle period, that is, the flash memory self-test is started when there is no host read / write request.
  • Step S203 After the flash memory self-test is triggered, the data in the flash memory is divided into multiple data segments of a first predetermined data amount.
  • step S203 after the flash memory self-test is triggered during the idle period, the data stored in the flash memory is divided into a plurality of data segments of a first predetermined data amount.
  • the first predetermined data amount is preferably a 10 MB data amount. That is to say, in order not to affect the performance indicators of subsequent read and write requests of the flash memory by the host, it is preferable to perform background self-check on the data stored in the flash memory in units of data segments.
  • Step S204 Perform self-check on the data in each data segment in different idle periods.
  • step S204 the steps of performing self-check on the data in each data segment in different idle periods respectively include: after completing the self-check operation on the data in the previous data segment, detecting whether the flash memory is in the idle period; If the detection result is that the flash memory is in an idle period, the self-test of the data in the next data segment is continued.
  • FIG. 5 is a schematic diagram of the sub-process of FIG. 4 for self-checking the data in each data segment.
  • the operation of self-checking the data in each data segment includes the following steps:
  • Step S301 Read the data stored in the data segment sequentially in units of physical pages.
  • step S301 first read the data in one physical page, after completing the subsequent self-check operations in steps S302 to S303, continue reading the data in the next physical page until the data in one data segment is completed Read all data.
  • Step S302 Acquire the number of error correction bits for correcting the read data.
  • step S302 if there is no error in the data read in one physical page, that is, there is no bit flip, then continue to execute step S301. If there is an error in the read data, the number of error correction bits for correcting the read data, that is, the number of bit flips, is obtained, and step S303 is continued.
  • Step S303 Detect whether the number of error correction bits is greater than a predetermined number of bits threshold.
  • the threshold of the predetermined number of bits is determined by the error correction capability of the error correction algorithm, which may be, for example, the BCH (Bose, Ray-Chaudhuri, and Hocquenghem) algorithm.
  • the error correction capability of the selected BCH error correction algorithm is 50bit / 1024B
  • the threshold of the predetermined number of bits here can be selected as 45bit / 1024B. That is to say, the threshold of the predetermined number of bits is less than or equal to the error correction capability of the error correction algorithm, because when the number of error correction bits is greater than the error correction capability of the error correction algorithm, the error correction algorithm cannot perform error correction and data will be lost.
  • Step S304 If the detection result is that the number of error correction bits is greater than the predetermined number of bits threshold, then perform error correction on the data in the physical page.
  • step S304 when the number of error correction bits in the read physical page, that is, the number of error bits reaches a predetermined number of bits threshold, an error correction algorithm is started to correct the data on the physical page, and The data after the error correction is transferred to the new physical address, so that the retention error can be prevented.
  • the second embodiment of the present invention triggers the flash memory to perform a self-test during the idle period when the flash memory has an idle period, where the flash memory self-test is to perform segmented self-test on the data stored in the flash memory in different idle periods, thereby You can avoid retention errors in flash memory.
  • the segmented self-test of the second embodiment of the present invention is performed during the idle period of the flash memory, which can ensure that the host's read and write performance of the flash memory is not affected.
  • FIG. 6 is a flowchart of a flash memory self-test method according to a third embodiment of the present invention. It should be noted that if there are substantially the same results, the method of the present invention is not limited to the sequence of the flow shown in FIG. 6. As shown in Figure 6, the method includes the following steps:
  • Step S401 Detect the working state of the flash memory.
  • the working state of the flash memory includes a first working state and a second working state, where the first working state is a state where the host has no read / write request so that the flash memory has an idle period, and the second working state is that the host continues to read and write The request causes the flash memory to have no idle period.
  • Step S402 If the detection result is that the flash memory is in the second working state, detect whether the working time of the flash memory exceeds a predetermined time threshold.
  • step S402 when the flash memory is in the second working state, that is, the flash memory is continuously read and written by the host, it is detected whether the working time of the flash memory exceeds a predetermined time threshold.
  • the threshold value of the predetermined time is determined by the number of erasing times of the flash memory and the error correction capability of the error correction algorithm.
  • the X axis is P / E, that is, the number of times the flash memory is erased
  • the Y axis is BER (Bit Error), which is the ratio of bit flips.
  • the characteristic of the flash memory is that the flash memory block must be erased before writing; BER characterizes the data reliability of the flash memory, the smaller the value, the more reliable the data. It can be seen from Figure 7: 1.
  • the retention error is closely related to P / E, and the greater the P / E, the greater the proportion of bit flips. 2.
  • the retention error is closely related to the retention time. The longer the retention time, the greater the proportion of bit flips.
  • a predetermined time threshold can be set to one year, and any stuck errors that occur during the period can be corrected by BCH.
  • the predetermined time threshold can be set to 1 month.
  • the retention error during the period can be corrected by the BCH algorithm.
  • P / E is greater than 1000 and less than 3000
  • the predetermined time threshold can be set to 1 week.
  • the retention error that occurs can be corrected by the BCH algorithm. That is to say, the cycle of triggering the self-test can be dynamically and adaptively adjusted according to the state of the flash memory, thereby ensuring that any retention errors that occur within this cycle can be corrected by the error correction algorithm.
  • Step S403 If the detection result is that the working period of the flash memory exceeds a predetermined time threshold, the flash memory is triggered to perform a self-test.
  • step S403 when the working period of the flash memory exceeds a predetermined time threshold, the flash memory is triggered to perform a self-check to ensure that the retention errors that occur during this period can be corrected by subsequent error correction algorithms.
  • Step S404 After the flash memory self-test is triggered, the data in the flash memory is divided into multiple data segments of a second predetermined data amount.
  • step S404 after the flash memory self-test is triggered, the data stored in the flash memory is divided into a plurality of data segments of a second predetermined data amount.
  • the second predetermined data amount is preferably a 5 MB data amount. That is to say, in order not to affect the efficiency of the host's read and write requests to the flash memory during the self-test, preferably, the background self-test of the data stored in the flash memory is performed in units of data segments.
  • the segmented self-test is performed with the data of the first predetermined data amount
  • the segmented self-test is performed with the data of the second predetermined data amount , Where the first predetermined data amount is greater than the second predetermined data amount.
  • Step S405 Perform self-check on the data in each data segment at predetermined time intervals.
  • step S405 once the flash memory is triggered to perform a self-test, it is necessary to self-check the second predetermined data amount, that is, 5 MB of data, every predetermined time, for example, 1 second.
  • the bandwidth of the host to read and write flash memory will be reduced by 5MB / s, because the performance index of normal host sequential read and write flash memory can reach 500MB / s , So this performance loss is not obvious and will not affect the user experience.
  • step S405 the operation of performing self-check on the data in each data segment in step S405 is similar to the process shown in FIG. 5, for simplicity, it will not be repeated here.
  • the flash memory when the flash memory is continuously read and written and the working time of the flash memory reaches a predetermined time threshold, the flash memory is triggered to perform a self-test.
  • the flash memory self-test is stored in the flash memory at a predetermined time interval.
  • the data is segmented and self-checked to avoid stranding errors.
  • the third embodiment of the present invention can dynamically adaptively control the cycle of triggering the self-test according to the erasure times of the flash memory and the error correction capability of the error correction algorithm to minimize the impact of the host on the read and write performance indicators of the flash memory. So as to ensure the user's experience.
  • FIG. 8 is a schematic structural diagram of a solid-state hard disk according to an embodiment of the present invention.
  • the solid-state hard disk includes a processor 11, a storage controller 12 and a flash memory 13 coupled to the processor.
  • the memory controller 12 stores program instructions for implementing the flash memory self-test method described in any of the above embodiments.
  • the processor 11 is used to execute the program instructions stored by the storage controller 12 to perform self-test on the flash memory 13.
  • the processor 11 may also be called a CPU (Central Processing Unit, central processing unit).
  • the processor 11 may be an integrated circuit chip with signal processing capabilities.
  • the processor 11 may also be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components .
  • the general-purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • FIG. 9 is a schematic structural diagram of a storage device according to an embodiment of the present invention.
  • the storage device in the embodiment of the present invention stores a program file 21 capable of implementing all the above methods, wherein the program file 21 may be stored in the storage device in the form of a software product, including several instructions to make a computer device (may It is a personal computer, server, or network device, etc.) or a processor that executes all or part of the steps of the methods described in the embodiments of the present application.
  • the aforementioned storage devices include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes , Or terminal devices such as computers, servers, mobile phones, and tablets.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of units is only a division of logical functions.
  • there may be other divisions for example, multiple units or components may be combined or integrated To another system, or some features can be ignored, or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or software function unit.

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Abstract

一种闪存自检的方法、固态硬盘以及存储装置。该闪存自检的方法包括：检测是否触发闪存进行自检；若检测结果为触发闪存进行自检，则根据闪存的工作状态触发闪存进行自检。通过上述方式，本发明能够根据闪存的工作状态触发闪存进行自检，能够自适应调整自检，提前发现并消除滞留错误，满足主机对闪存进行读写操作的性能指标的同时，避免闪存产生滞留错误。

Description

闪存自检的方法、固态硬盘以及存储装置
本申请要求于2018年10月11日提交至中国专利局、申请号为201811183350.0、发明名称为“闪存自检的方法、固态硬盘以及存储装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及存储技术领域，特别是涉及一种闪存自检的方法、固态硬盘以及存储装置。
背景技术
闪存中的闪存单元(Flash cell)使用浮动栅晶体管(Floating Gate Transistor)的电压值来表示存储的数据。以闪存为MLC(Multi Level Cell)为例来说，每个闪存单元可以存储两个比特的数据：LSB(Least Significant Bit)和MSB(Most Significant Bit)，因此，每个闪存单元有四种工作状态(如图1所示)，分别为状态1、状态2、状态3和状态4。
其中，状态1为擦除态，电压值最小，闪存单元存储的数据为11；状态2或状态3为非完全写入态，电压值介于擦除态和完全态之间，闪存单元存储的数据为10或01；状态4为完全态，电压最大，闪存单元存储的数据为00。具体来说，如果浮动栅晶体管电压值小于参考电压1，则认为闪存单元存储的数据为11，如果浮动栅晶体管电压值介于参考电压1和参考电压2之间，则认为闪存单元存储的数据为10，如果浮动栅晶体管电压值介于参考电压2和参考电压3之间，则认为闪存单元存储的数据是01，如果浮动栅晶体管电压值大于参考电压3，则认为闪存单元存储的数据是00。
当闪存长期不使用(比如长期掉电状态)，那么闪存单元中的电子会发生泄漏，其电压值会降低，分布状态会发生偏移，从而产生滞留错误(Retention Error)。如图2所示，例如某个闪存单元最初写入的数据为01，为状态3，电压值介于参考电压2和参考电压3之间，之后固态硬盘中的闪存处于偶尔使用状态，即偶尔上电，且上电期间没有读写该闪存单元， 那么该闪存单元上的电子会渐渐泄漏，电压值渐渐减小，当这种变化持续的时间足够久，其电压值会降低至小于参考电压2，即该闪存单元由状态3变为了状态2。之后如果读取该闪存单元，则读取到的电压值可能介于参考电压1和参考电压2之间，则判断存储的数据为10，即发生滞留错误。
当前技术中对抗滞留错误的办法是在固态硬盘中使用纠错算法。具体来说，当主机从固态硬盘的闪存中读取数据时，当读出的数据发生了滞留错误也即比特位翻转则启用纠错算法尝试纠正，如果能纠正则把纠正后的数据传给主机，如果发生滞留错误的位数较多，纠错算法无法纠正，则上报主机发生了不可纠正的错误。
现有技术是在读取数据时对滞留错误进行纠错算法纠错，如果固态硬盘的闪存中的数据滞留时间较长，发生滞留错误的位数会随着滞留时间而变多，那么会大概率发生不可纠正的错误，从而使得主机丢失数据，这是用户无法容忍的。特别是，如果主机写了一笔数据后，长期不读(比如几年都不读)，那么百分百会发生不可纠正的错误，这是需要避免的。
发明内容
本申请提供一种闪存自检的方法、固态硬盘以及存储装置，能够降低闪存的滞留错误，进而大大降低闪存中数据丢失的概率。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种闪存自检的方法，该方法包括：检测是否触发闪存进行自检；若检测结果为触发闪存进行自检，则根据闪存的工作状态触发闪存进行自检。
其中，检测是否触发闪存进行自检的步骤包括：检测闪存的工作状态；若检测结果为闪存处于第一工作状态，则在空闲期触发闪存进行自检。
其中，检测是否触发闪存进行自检的步骤包括：检测闪存的工作状态；若检测结果为闪存处于第二工作状态，检测闪存的工作时间是否超过预定时间的阈值；若检测结果为闪存的工作周期超过预定时间的阈值，则触发闪存进行自检。
其中，预定时间的阈值由闪存的擦除次数和纠错算法的纠错能力确定。
其中，当闪存处于第一工作状态时，根据闪存的工作状态触发闪存进 行自检的步骤包括：将闪存中的数据划分为第一预定数据量的多个数据段；分别在不同的空闲期对每一数据段中的数据进行自检。
其中，分别在不同的空闲期对每一数据段中的数据进行自检的步骤包括：在完成对前一数据段中的数据进行自检的操作后，检测闪存是否处于空闲期；若检测结果为闪存处于空闲期，则继续对下一数据段的数据进行自检。
其中，当闪存处于第二工作状态时，根据闪存的工作状态触发闪存进行自检的步骤包括：将闪存中的数据划分为第二预定数据量的多个数据段；以预定时间间隔对每一数据段中的数据进行自检。
其中，对每一数据段中的数据进行自检的步骤包括：以物理页面为单位依次读取保存在数据段中的数据；获取对读取的数据进行纠错的纠错位数；检测纠错位数是否大于预定位数阈值；若检测结果为纠错位数大于预定位数阈值，则对物理页面中的数据进行纠错。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种固态硬盘，该固态硬盘包括处理器、与处理器耦接的存储控制器和闪存，其中，存储控制器存储有用于实现上述任一项的闪存自检的方法的程序指令；处理器用于执行存储控制器存储的程序指令以对闪存进行自检。
为解决上述技术问题，本申请采用的又一个技术方案是：提供一种存储装置，存储有能够实现上述任一方法的程序文件。
本申请的有益效果是：本发明的闪存自检的方法、固态硬盘以及存储装置，根据闪存的工作状态触发闪存进行自检，能够自适应调整自检，提前发现并消除滞留错误，大大降低闪存的滞留错误，进而大大降低闪存中数据丢失的概率。
附图说明
图1是现有技术中闪存单元的工作状态的示意图；
图2是现有技术中闪存单元发生滞留错误的示意图；
图3是本发明第一实施例的闪存自检的方法的流程示意图；
图4是本发明第二实施例的闪存自检的方法的流程示意图；
图5是图4中对每一数据段中的数据进行自检的子流程示意图；
图6是本发明第三实施例的闪存自检的方法的流程示意图；
图7是影响滞留错误的因素的示意图；
图8是本发明实施例的固态硬盘的结构示意图；
图9是本发明实施例的存储装置的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请中的术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”、“第三”的特征可以明示或者隐含地包括至少一个该特征。本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。本申请实施例中所有方向性指示(诸如上、下、左、右、前、后……)仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
图3是本发明第一实施例的闪存自检的方法的流程图。如图3所示，该方法包括步骤：
步骤S101：检测是否触发闪存进行自检。
在步骤S101中，闪存中的滞留错误是随着时间慢慢积累渐渐超出纠错算法的纠错能力的，那么可以在闪存中的数据长期未被使用时，在后台按照预定规则触发闪存进行自检，从而避免出现滞留时间过长而出现发生滞留错误也即比特位翻转的位数过多而无法被纠正的问题。
其中，预定规则可以是每隔预定时间间隔触发闪存进行自检，预定时间间隔可以一直保持相同，也可以随着闪存的工作时间逐步变短。
步骤S102：若检测结果为触发闪存进行自检，则根据闪存的工作状态触发闪存进行自检。
在步骤S102中，闪存的工作状态包括第一工作状态和第二工作状态，其中，第一工作状态为主机没有读写请求使得闪存存在空闲期的状态，第二工作状态为主机持续有读写请求使得闪存不存在空闲期的状态。
在一个实施例中，闪存进行自检的步骤包括：对保存在闪存中的所有物理块中的数据进行自检。
在另一实施例中，闪存进行自检的步骤包括：获取闪存中各物理块最后一次被访问的时间戳；获取当前时间与各物理块对应的最后一次被访问的时间戳两者之间的差值；对差值超过预定阈值的各物理块的数据进行自检。也就是说，当后台触发闪存进行自检后，仅仅对闪存长时间未被访问的物理块中的数据进行自检，而不需要对闪存中所有物理块的数据进行自检，这样可以避免全盘自检，从而可以降低自检所消耗的功耗。
进一步，对差值超过预定阈值的各物理块的数据进行自检的步骤包括：判断差值超过预定阈值的各物理块是否为擦除后还未写入数据的物理块，可以理解为被擦除后没有有效数据的物理块；若是，则不对该物理块内的数据进行自检，否则对该物理块内的数据进行自检。在另一实施例中，对没有有效数据的物理块直接跳过自检流程，这样可以避免全盘自检，从而可以降低自检所消耗的功耗。
当闪存进行自检被触发后，按照闪存的工作状态触发自检，在保证后 台的自检操作正常运行的同时不会影响到闪存的读写操作。
通过上述方式，本发明第一实施例根据闪存的工作状态触发闪存进行自检，能够自适应调整自检，提前发现并消除滞留错误，大大降低闪存的滞留错误，进而大大降低闪存中数据丢失的概率。
图4是本发明第二实施例的闪存自检的方法的流程图。需注意的是，若有实质上相同的结果，本发明的方法并不以图4所示的流程顺序为限。如图4所示，该方法包括如下步骤：
步骤S201：检测闪存的工作状态。
在步骤S201中，闪存的工作状态包括第一工作状态和第二工作状态，其中，第一工作状态为主机没有读写请求使得闪存存在空闲期的状态，第二工作状态为主机持续有读写请求使得闪存不存在空闲期的状态。
步骤S202：若检测结果为闪存处于第一工作状态，则在空闲期触发闪存进行自检。
在步骤S202中，闪存进行自检在空闲期触发，也即闪存进行自检在没有主机读写请求时启动。
步骤S203：当闪存自检被触发后，将闪存中的数据划分为第一预定数据量的多个数据段。
在步骤S203中，当闪存自检在空闲期被触发后，将保存在闪存中的数据划分为第一预定数据量的多个数据段。其中，第一预定数据量优选为10MB数据量。也就是说，为了不影响后续主机对闪存读写请求的性能指标，优选地，对保存在闪存中的数据的后台自检以数据段为单位进行。
步骤S204：分别在不同的空闲期对每一数据段中的数据进行自检。
在步骤S204中，分别在不同的空闲期对每一数据段中的数据进行自检的步骤包括：在完成对前一数据段中的数据进行自检的操作后，检测闪存是否处于空闲期；若检测结果为闪存处于空闲期，则继续对下一数据段的数据进行自检。
也就是说，在空闲期完成一个数据段的自检后退出自检，并尝试响应主机对闪存的读写请求，如果此时主机没有发送对闪存的读写请求，则继续下一数据段的自检，如果此时主机有发送对闪存的读写请求，则响应主 机对闪存的读写请求并在完成该读写请求后的下一个空闲期继续下一数据段的自检。
请一并参考图5，图5是图4中对每一数据段中的数据进行自检的子流程示意图。如图5所示，对每一数据段中的数据进行自检的操作包括如下步骤：
步骤S301：以物理页面为单位依次读取保存在数据段中的数据。
在步骤S301中，首先读取一个物理页面中的数据，当完成后续的步骤S302至步骤S303中的自检操作后，继续读取下一个物理页面中的数据，直至完成对一个数据段中的所有数据的读取。
步骤S302：获取对读取的数据进行纠错的纠错位数。
在步骤S302中，若在一个物理页面中读取的数据中不存在错误也即不存在比特位翻转时，则继续执行步骤S301。若读取的数据中存在错误时，则获取对读取的数据进行纠错的纠错位数也即发生比特位翻转的位数，并继续执行步骤S303。
步骤S303：检测纠错位数是否大于预定位数阈值。
在步骤S303中，预定位数阈值由纠错算法的纠错能力确定，纠错算法例如可以为BCH(Bose、Ray-Chaudhuri与Hocquenghem)算法。举例来说，假设所选定的BCH纠错算法的纠错能力为50bit/1024B，那么这里的预定位数阈值可以选择45bit/1024B。也就是说，预定位数阈值小于等于纠错算法的纠错能力，因为当纠错位数大于纠错算法的纠错能力后，则纠错算法无法进行纠错，数据会被丢失。
步骤S304：若检测结果为纠错位数大于预定位数阈值，则对物理页面中的数据进行纠错。
在步骤S304中，当被读取的物理页面中的纠错位数也即发生错误的位数达到预定位数阈值时，则启动纠错算法对该物理页面中的数据进行纠错，并将纠错后的数据转移到新的物理地址，从而可以防止出现滞留错误。
通过上述方式，本发明第二实施例在闪存存在空闲期时在空闲期触发闪存进行自检，其中闪存自检是分别在不同的空闲期对保存在闪存中的数据进行分段自检，从而可以避免闪存产生滞留错误。另外，本发明第二实 施例的分段自检在闪存的空闲期进行，可以保证主机对闪存的读写性能不受影响。
图6是本发明第三实施例的闪存自检的方法的流程图。需注意的是，若有实质上相同的结果，本发明的方法并不以图6所示的流程顺序为限。如图6所示，该方法包括如下步骤：
步骤S401：检测闪存的工作状态。
在步骤S401中，闪存的工作状态包括第一工作状态和第二工作状态，其中，第一工作状态为主机没有读写请求使得闪存存在空闲期的状态，第二工作状态为主机持续有读写请求使得闪存不存在空闲期的状态。
步骤S402：若检测结果为闪存处于第二工作状态，检测闪存的工作时间是否超过预定时间的阈值。
在步骤S402中，当闪存处于第二工作状态也即闪存持续被主机读写的状态时，检测闪存的工作时间是否超过预定时间的阈值。其中，预定时间的阈值由闪存的擦除次数和纠错算法的纠错能力确定。
如图7所示，X轴为P/E也即闪存的擦除次数，Y轴为BER(Bit Error Rate)也即发生比特位翻转的比例。其中，闪存的特性是闪存块必须擦除后才能写；BER表征了闪存的数据可靠性，该值越小数据越可靠。从图7中可以看出：1、滞留错误与P/E关系密切，P/E越大发生比特位翻转的比例越大。2、滞留错误与滞留时间关系密切，滞留时间越长，发生比特位翻转的比例越大。
从图7可以看出，假设纠错算法为BCH算法，BCH纠错能力为0.001，那么当P/E小于300时可以设置预定时间阈值为一年，期间发生的滞留错误都能被BCH纠正，当P/E大于300小于1000时可以设置预定时间阈值为1个月，期间发生的滞留错误能被BCH算法纠正，当P/E大于1000小于3000时可以设置预定时间阈值为1个星期，期间发生的滞留错误能被BCH算法纠正。也就是说，可以根据闪存的状态动态自适应调整触发自检的周期，从而可以保证在此周期内发生的滞留错误都能被纠错算法纠正。
步骤S403：若检测结果为闪存的工作周期超过预定时间的阈值，则触发闪存进行自检。
在步骤S403中，当闪存的工作周期超过预定时间的阈值，触发闪存进行自检，以保证在此周期内发生的滞留错误都能被后续的纠错算法纠正。
步骤S404：当闪存自检被触发后，将闪存中的数据划分为第二预定数据量的多个数据段。
在步骤S404中，当闪存自检被触发后，将保存在闪存中的数据划分为第二预定数据量的多个数据段。其中，第二预定数据量优选为5MB数据量。也就是说，为了不影响自检的过程中主机对闪存读写请求的效率，优选地，对保存在闪存中的数据的后台自检以数据段为单位进行。
需要强调的是，当闪存处于第一工作状态时，以第一预定数据量的数据进行分段自检，当闪存处于第二工作状态时，以第二预定数据量的数据进行分段自检，其中，第一预定数据量大于第二预定数据量。
步骤S405：以预定时间间隔对每一数据段中的数据进行自检。
在步骤S405中，一旦触发闪存进行自检，需要每隔预定时间例如1秒钟自检第二预定数据量也即5MB的数据。换个角度来说，在自检期间，以1秒钟自检5MB的数据量来说，主机读写闪存的带宽会降低5MB/s，由于正常主机顺序读写闪存的性能指标可以达到500MB/s，因此这个性能损失并不明显，不会影响用户体验。
其中，在步骤S405中对每一数据段中的数据进行自检的操作和图5所示的流程类似，为简约起见，在此不再赘述。
通过上述方式，本发明第三实施例在闪存处于持续被读写的状态且闪存的工作时间达到预定时间的阈值时，触发闪存进行自检，其中闪存自检是以预定时间间隔对保存在闪存的数据进行分段自检，从而可以避免产生滞留错误。与此同时，本发明第三实施例可以根据闪存的擦除次数和纠错算法的纠错能力动态自适应控制触发自检的周期，将主机对闪存的读写性能指标的影响降至最低，从而保证了用户的体验度。
请参阅图8，图8为本发明实施例的固态硬盘的结构示意图。如图8所示，该固态硬盘包括处理器11及和处理器耦接的存储控制器12和闪存13。
存储控制器12存储有用于实现上述任一实施例所述的闪存自检的方 法的程序指令。
处理器11用于执行存储控制器12存储的程序指令以对闪存13进行自检。
其中，处理器11还可以称为CPU(Central Processing Unit，中央处理单元)。处理器11可能是一种集成电路芯片，具有信号的处理能力。处理器11还可以是通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
参阅图9，图9为本发明实施例的存储装置的结构示意图。本发明实施例的存储装置存储有能够实现上述所有方法的程序文件21，其中，该程序文件21可以以软件产品的形式存储在上述存储装置中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(processor)执行本申请各个实施方式所述方法的全部或部分步骤。而前述的存储装置包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质，或者是计算机、服务器、手机、平板等终端设备。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (10)

  1. 一种闪存自检的方法，其特征在于，所述方法包括：
    检测是否触发所述闪存进行自检；
    若检测结果为触发所述闪存进行自检，则根据所述闪存的工作状态触发所述闪存进行自检。
  2. 根据权利要求1所述的方法，其特征在于，检测是否触发所述闪存进行自检的步骤包括：
    检测所述闪存的工作状态；
    若检测结果为所述闪存处于第一工作状态，则在空闲期触发所述闪存进行自检。
  3. 根据权利要求1所述的方法，其特征在于，检测是否触发所述闪存进行自检的步骤包括：
    检测所述闪存的工作状态；
    若检测结果为所述闪存处于第二工作状态，检测所述闪存的工作时间是否超过预定时间的阈值；
    若检测结果为所述闪存的工作周期超过所述预定时间的阈值，则触发所述闪存进行自检。
  4. 根据权利要求3所述的方法，其特征在于，所述预定时间的阈值由所述闪存的擦除次数和纠错算法的纠错能力确定。
  5. 根据权利要求2所述的方法，其特征在于，当所述闪存处于第一工作状态时，根据所述闪存的工作状态触发所述闪存进行自检的步骤包括：
    将所述闪存中的数据划分为第一预定数据量的多个数据段；
    分别在不同的空闲期对每一数据段中的数据进行自检。
  6. 根据权利要求5所述的方法，其特征在于，分别在不同的空闲期对每一数据段中的数据进行自检的步骤包括：
    在完成对前一数据段中的数据进行自检的操作后，检测所述闪存是否处于所述空闲期；
    若检测结果为所述闪存处于所述空闲期，则继续对下一数据段的数据进行自检。
  7. 根据权利要求3所述的方法，其特征在于，当所述闪存处于第二工作状态时，根据所述闪存的工作状态触发所述闪存进行自检的步骤包括：
    将所述闪存中的数据划分为第二预定数据量的多个数据段；
    以预定时间间隔对每一数据段中的数据进行自检。
  8. 根据权利要求5或7所述的方法，其特征在于，对每一数据段中的数据进行自检的步骤包括：
    以物理页面为单位依次读取保存在所述数据段中的数据；
    获取对读取的数据进行纠错的纠错位数；
    检测所述纠错位数是否大于预定位数阈值；
    若检测结果为所述纠错位数大于预定位数阈值，则对所述物理页面中的所述数据进行纠错。
  9. 一种固态硬盘，其特征在于，所述固态硬盘包括处理器、与所述处理器耦接的存储控制器和闪存，其中，
    所述存储控制器存储有用于实现如权利要求1-8中任一项所述的闪存自检的方法的程序指令；
    所述处理器用于执行所述存储控制器存储的所述程序指令以对所述闪存进行自检。
  10. 一种存储装置，其特征在于，存储有能够实现如权利要求1-8中任一项所述方法的程序文件。
PCT/CN2019/093313 2018-10-11 2019-06-27 闪存自检的方法、固态硬盘以及存储装置 WO2020073691A1 (zh)

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