WO2020073558A1 - 具有静电防护的显示面板及其制造方法 - Google Patents

具有静电防护的显示面板及其制造方法 Download PDF

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Publication number
WO2020073558A1
WO2020073558A1 PCT/CN2019/072523 CN2019072523W WO2020073558A1 WO 2020073558 A1 WO2020073558 A1 WO 2020073558A1 CN 2019072523 W CN2019072523 W CN 2019072523W WO 2020073558 A1 WO2020073558 A1 WO 2020073558A1
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WIPO (PCT)
Prior art keywords
transparent electrode
metal layer
substrate
display panel
circuit
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PCT/CN2019/072523
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English (en)
French (fr)
Inventor
吕晓文
王添鸿
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2020073558A1 publication Critical patent/WO2020073558A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements

Definitions

  • the present invention relates to the field of display technology, and in particular to a display panel with electrostatic protection and a manufacturing method thereof.
  • the GOA technology is a technology that directly integrates the gate drive circuit on the array substrate to drive multiple scan lines of the display panel, eliminating the need to manufacture an external silicon chip driver chip And reduce the manufacturing process, product cost and the area around the panel, which is beneficial to the manufacture of display products with narrow borders or no borders, improve the high integration of the display panel, and make the panel thinner.
  • the operation of the GOA circuit generally requires synchronization signals, clock signals, or low-voltage signals.
  • the signal lines that transmit these signals are distributed on the metal traces around the panel, which increases the risk of electrostatic discharge. Burning the circuit will have a great influence on the display and cause abnormal images.
  • a display panel in the prior art has an electrostatic damage between the two transparent electrodes of the upper substrate and the lower substrate in the display area. Therefore, in the process of designing the array substrate, an anti-electrostatic discharge design is further added to the non-display area to prevent electrostatic damage from electrostatic discharge.
  • the strict electrostatic discharge test conditions are often used to test the electrostatic protection performance of the signal line, and the GOA signal line is directly tested with an electrostatic discharge gun at a voltage of +/- 10 kV to test the display panel
  • the electrostatic protection performance of the GOA signal line After continuous research, the inventor analyzed the display panel that failed the electrostatic discharge test after inspection, and found that most of the display panels are because of the design of preventing electrostatic discharge in the non-display area (not shown) with a small spacing A short circuit still occurs between the transparent electrodes on the upper substrate and the lower substrate. Therefore, even in the case of an electrostatic discharge prevention design, it still fails to effectively prevent the display panel from being burned due to electrostatic discharge, resulting in abnormal images, and the product is directly scrapped, so this is a situation that must be avoided.
  • the general method in the prior art is to remove the via holes of the lower substrate, increase the distance between the upper and lower substrates, and prevent the short circuit of the upper and lower substrates.
  • removing the transparent electrodes of the lower substrate will cause insufficient via protection and corrosion damage.
  • a total of three masks need to be changed to remove the via hole and the transparent electrode together, which increases the manufacturing cost.
  • Factors such as tight wiring, semiconductor pad layer and gate tip structure due to high pixel density, narrow borders and other requirements.
  • the present invention provides a method for manufacturing a display panel, to solve the problem of the signal line at the metal trace of the GOA circuit in the prior art being burned due to electrostatic discharge, thereby reducing the display panel due to electrostatic discharge Defective rate.
  • an embodiment of the present invention provides a display panel, the display panel including:
  • a first metal layer, the first metal layer is disposed on the first substrate;
  • a first isolation layer, the first isolation layer is disposed on the first metal layer
  • a second metal layer, the second metal layer is disposed on the first isolation layer
  • a second isolation layer, the second isolation layer is disposed on the second metal layer
  • a second transparent electrode is provided on the second substrate, the first region in the second transparent electrode is etched away, and the first region corresponds to the first transparent electrode.
  • a first photo-etching material is provided on the first transparent electrode
  • a second photo-etching material is provided on the second transparent electrode
  • the first photo-etching material And the second photo-etching material is mutually reversible, so that the first transparent electrode is formed at the same time, and the portion corresponding to the first transparent electrode in the second transparent electrode is etched away.
  • the static electricity protection circuit is disposed in a non-display area of the display panel, the first area of the second transparent electrode is located at the short-circuit ring, the The short-circuit ring also includes a plurality of capacitors, and two ends of the short-circuit ring are connected to the GOA circuit and a common electrode.
  • the short-circuit ring has a first capacitor, a second capacitor, and a third capacitor, the first capacitor is connected in series with the second capacitor, and the third capacitor is connected in parallel to all The first capacitor and the second capacitor.
  • the display panel includes:
  • a first metal layer, the first metal layer is disposed on the first substrate;
  • a first isolation layer, the first isolation layer is disposed on the first metal layer
  • a second metal layer, the second metal layer is disposed on the first isolation layer
  • a second isolation layer, the second isolation layer is disposed on the second metal layer
  • a second transparent electrode provided on the second substrate.
  • a photoresist spacer covers the first transparent electrode and blocks the electrical connection between the first transparent electrode and the second transparent electrode.
  • the static electricity protection circuit is disposed in a non-display area of the display panel, and the photoresist spacer of the second transparent electrode is located at the short-circuit ring.
  • the short-circuit ring further includes a plurality of capacitors, and two ends of the short-circuit ring are connected to the GOA circuit and a common electrode.
  • the short-circuit ring has a first capacitor, a second capacitor, and a third capacitor, the first capacitor is connected in series with the second capacitor, and the third capacitor is connected in parallel to all The first capacitor and the second capacitor.
  • Another embodiment of the present invention provides another method for manufacturing a display panel.
  • the manufacturing method includes the steps of:
  • a first photomask is used to etch the first isolation layer, the second metal layer, and the second isolation layer to form a via, and a first transparent is provided at a position corresponding to the via An electrode, the first transparent electrode is connected to the first metal layer and the second metal layer through the via;
  • the second transparent electrode is etched using a second photomask, and at the same time, a first region of the second transparent electrode corresponding to the position of the first transparent electrode is removed to block the first transparent electrode and The electrical connection between the second transparent electrodes.
  • an electrostatic protection circuit is provided on a non-display area of the display panel on the first substrate to connect to a GOA circuit, and the electrostatic protection circuit is connected to the GOA circuit A short-circuit ring is connected to one end of.
  • the manufacturing method further includes: respectively disposing a first photo-etching material on the first transparent electrode, and disposing a second photo-etching material on the second transparent electrode ,
  • the first photo-etching material and the second photo-etching material are mutually reciprocal, so that when the second photomask is used for etching, a pattern of the first transparent electrode is simultaneously formed and etched with The first region of the second transparent electrode opposite to the pattern of the first transparent electrode.
  • the present invention provides a method for manufacturing a display panel, which can improve the electrostatic protection performance of the signal lines at the metal traces of the GOA circuit.
  • a method for manufacturing a display panel which can improve the electrostatic protection performance of the signal lines at the metal traces of the GOA circuit.
  • They may explode.
  • the damaged area prevents the display panel from being burned due to electrostatic discharge at the short-circuit ring, improves the electrostatic protection performance of the display panel, reduces the process and cost of using the photomask, and improves the competitiveness of the product.
  • FIG. 1 is a schematic diagram of the position of a short-circuit ring of a display panel of the present invention
  • FIG. 2 is an equivalent circuit diagram of a short circuit ring of a display panel of the present invention
  • FIG. 3 is a schematic diagram of a display panel according to the first embodiment of the invention.
  • FIG. 4 is a schematic diagram of a display panel according to a second embodiment of the invention.
  • FIG. 5 is a flowchart of a method of manufacturing a display panel according to the first embodiment of the present invention.
  • FIG. 6 is a flowchart of a method for manufacturing a display panel according to a second embodiment of the invention.
  • the vast majority of existing solutions are to provide vias to remove the lower substrate or increase the distance between the upper and lower substrates to prevent short circuit of the upper and lower substrates.
  • removing the transparent electrode of the lower substrate will cause insufficient via protection and cause corrosion, damage, etc., and if removing the lower substrate via and the transparent electrode together requires a total of three masks, requiring multiple processes and increased manufacturing Cost, and increasing the distance between the upper and lower substrates is not conducive to reducing the thickness of the existing display panel.
  • FIG. 1 is a schematic diagram of the positions of a short-circuit ring 24, 25 of a display panel 20 of the present invention
  • FIG. 2 is an equivalent of a short-circuit ring 24, 25 of a display panel 20 of the present invention.
  • a display panel 20 of the present invention includes a display area 21 and a non-display area 22, in which a GOA circuit 23, a plurality of GOA signal lines 28, 29, 30 and a plurality of common electrode lines 26, 27 are provided , The plurality of GOA signal lines 28, 29, 30 are connected to the GOA circuit 23 and transmit GOA signals to the gate, source and drain of the display area 21, the common electrode line is connected to a common electrode and transmits driving Signal to drive the display panel.
  • Each of the first and second ends of the GOA signal line is provided with an electrostatic protection circuit 31, 32, the electrostatic protection circuit 31, 32 is connected to a GOA signal line and a common electrode line to form a short circuit ring 24, 25.
  • the electrostatic protection circuits 31 and 32 include a capacitor, and optionally at least two capacitors connected in parallel with each other.
  • the short-circuit rings 24 and 25 may further include at least one capacitor.
  • the short-circuit ring has a first capacitor 33, a second capacitor 34 and a third capacitor 35.
  • a capacitor 33 is connected in series with the second capacitor 34, and the third capacitor 35 is connected in parallel to the first capacitor 33 and the second capacitor 34.
  • the capacitors 33, 34, 35 are connected to the GOA circuit 23 and a common electrode line 26, 27 to prevent the excessive voltage from damaging the circuit.
  • FIG. 3 is a schematic diagram of a display panel 200 according to the first embodiment of the present invention.
  • a first substrate 210 is provided in a display panel 200 of the present invention; a first metal layer 230, a first isolation layer 240, a second metal layer 250 and a second isolation are sequentially formed on the first substrate 210 Floor 280.
  • the first metal layer 230 is a signal line layer
  • the first isolation layer 240 is an insulating layer
  • the second isolation layer 280 is a protective layer to avoid filling The incoming liquid crystal is contaminated or flows out.
  • a first photomask is used to etch the first isolation layer 240, the second metal layer 250 and the second isolation layer 280 to form a via 260 at a position corresponding to the via 260
  • a first transparent electrode 261 is provided, the first transparent electrode 261 is connected to the first metal layer 230 and the second metal layer 250 through the via 260, and an electrostatic protection circuit is provided on the first substrate 210 31 and 32 are connected to a GOA circuit, and a short-circuit ring is provided at one end of the electrostatic protection circuit connected to the GOA circuit.
  • the static electricity protection circuit may be disposed in a non-display area of the display panel 200, and the first area 270 of the second transparent electrode 270 is located at the short-circuit ring.
  • the first substrate 210 may be an array substrate
  • the second substrate may be a color filter substrate
  • the material of the substrate may be glass.
  • one end of the signal line on the first metal layer 230 is connected to a signal line of the GOA circuit, and a frequency signal line formed on the second metal layer 250 is connected to the second The second transparent electrode 270 of the substrate 220.
  • the second transparent electrode is a common electrode located on a surface of the second substrate 220 facing the first substrate 210, so that when static electricity appears on the display panel, the The second metal layer 250 discharges static electricity in the display area of the display panel 200 to the non-display area, so as to prevent the static electricity from entering the display area and causing a short circuit between the metal layer or the transparent electrode for protection Circuits and components inside the panel.
  • the first isolation layer 240 and the second isolation layer 280 above the first metal layer 230 and the second metal layer 250 can be excavated by various methods, for example : Etching and the like, the first transparent electrode 261 is formed in the via hole 260 and extends beyond the via hole 260 to route metal layers of different layers (that is, the first metal layer 230 and the The second metal layer 250) is connected.
  • the manufacturing method further includes disposing a first photo-etching material on the first transparent electrode 261 and disposing a second photo-etching material on the second transparent electrode 270 ,
  • the first photo-etching material and the second photo-etching material are mutually opposite, so that when the second photomask is used for etching, the first transparent electrode 261 forms the first transparent electrode Pattern of 361, and at the same time, the first region 271 of the second transparent electrode 270 corresponding to the pattern of the first transparent electrode 261 is etched.
  • a liquid crystal layer is provided between the first substrate 210 and the second substrate 220 290; and aligning and bonding the first substrate 210 and the second substrate 220.
  • the present invention uses only one photomask to simultaneously etch the first transparent electrode 261 and the first region 271 of the second transparent electrode 270, effectively preventing the first transparent electrode 261 and the second transparent electrode 270 There is electrostatic discharge between them and burning, which effectively reduces the width of the frame of the display panel, which is conducive to the display panel to achieve a complex GOA layout in a narrow frame without being burned by electrostatic discharge.
  • the first photoetching material is a positive photoetching material
  • the second photoetching material is a negative photoetching material, so that after UV irradiation , The positive photo-etching material on the first transparent electrode 261 is washed away, the positive photo-etching material remains on the portion other than the first transparent electrode 261 to be etched, and The first region 271 of the second transparent electrode 270 is etched while retaining the negative photoetching material. Therefore, the first transparent electrode 261 and the first region 271 of the second transparent electrode 270 corresponding to the first transparent electrode 261 are etched at the same time.
  • the first photoetching material is a negative photoetching material
  • the second photoetching material is a positive photoetching material, so that after UV irradiation The portion of the first transparent electrode 261 other than the negative photoetching material is retained to cause etching, while the second transparent electrode 270 is retained in the first region 271 of the positive
  • the photo-etching material is etched, and the photo-etching material on the second transparent electrode 270 is washed away. Therefore, the first transparent electrode 261 and the first region 271 of the second transparent electrode 270 corresponding to the first transparent electrode 261 are etched at the same time.
  • the positive photoetching material is removed by photochemical reaction after UV irradiation, and the negative photoetching material is cross-linked and cured after UV irradiation to be retained.
  • the display panel 300 of the second embodiment of the present invention is similar to the display panel 200 of the first embodiment of the present invention, and generally uses the same element names, but the difference of the second embodiment is that the display panel 300 of the second embodiment further Add a photoresist spacer 400.
  • the advantage of the above feature is that the photoresist spacer 400 prevents the first transparent electrode 361 and the second transparent electrode 370 that are close to each other at the short-circuit ring from being short-circuited, and does not require an additional mask process. It can be applied to a display panel without patterning requirements on a second substrate. Therefore, the second transparent electrode can not only share the photomask with the first transparent electrode 361, but also can save multiple processes and its costs, and further relatively increase the yield of the product, overcoming the short circuit caused by electrostatic discharge in general technology The problem.
  • FIG. 4 is a schematic diagram of a display panel 300 according to a second embodiment of the invention.
  • a first substrate 310 is provided in a display panel 300 of the present invention; a first metal layer 330, a first isolation layer 340, a second metal layer 350 and a second isolation are sequentially formed on the first substrate 310 Floor 380.
  • the first metal layer 330 is a signal line layer
  • the first isolation layer 340 is an insulating layer
  • the second isolation layer 380 is a protective layer to avoid filling The incoming liquid crystal is contaminated or flows out.
  • a first photomask is used to etch the first isolation layer 340, the second metal layer 350 and the second isolation layer 380 to form a via 360 at a position corresponding to the via 360
  • a first transparent electrode 361 is formed, the first transparent electrode 361 is connected to the first metal layer 330 and the second metal layer 350 through the via 360; an electrostatic protection is provided on the first substrate 310
  • the circuit is connected to a GOA circuit, and a short-circuit ring is provided at one end of the electrostatic protection circuit connected to the GOA circuit.
  • an area of the photoresist spacer 400 corresponds to an area of the first transparent electrode 361;
  • a second substrate 320 is provided, and a second transparent electrode 370 is formed on the second substrate 320; between the first substrate 310 and the second substrate 320 Providing a liquid crystal layer 390; and aligning and bonding the first substrate 310 and the second substrate 320.
  • the static electricity protection circuit may be disposed in a non-display area of the display panel 300, and the photoresist spacer 400 is located at the short-circuit ring.
  • the first substrate 310 may be an array substrate
  • the second substrate 320 may be a color filter substrate
  • the material of the substrate may be glass.
  • one end of the signal line on the first metal layer 330 is connected to the signal line of the GOA circuit, and the frequency signal line formed on the second metal layer 350 is connected to the first ⁇ transparent electrode 370.
  • the second transparent electrode 370 is a common electrode located on a surface of the second substrate 320 facing the first substrate 310, so that when static electricity appears on the display panel, the second metal layer 330 Discharge the static electricity in the display area of the display panel 300 to the non-display area, so as to prevent the static electricity from entering the display area and causing a short circuit between metal layers or transparent electrodes, so as to protect the display panel Circuits and components.
  • the first isolation layer 340 and the second isolation layer 380 above the first metal layer 330 and the second metal layer 350 can be excavated by etching or the like, so
  • the first transparent electrode 361 is formed in the via 360 and extends beyond the via 360 to route metal layers of different layers (ie, the first metal layer 330 and the second metal layer 350 )connect them.
  • the photoresist gap 400 not only covers the entire via 360, but also covers the furthest portion of the first transparent electrode 361 extending outward to cover all On the entire surface of the first transparent electrode 361.
  • the pattern of the photoresist gap 400 is larger than the size of the first transparent electrode 361 at the via 360, so it can completely cover the entire first transparent electrode 361 .
  • the photoresist gap 400 is insulated, so the photoresist gap 400 can isolate the first transparent electrode 361 from the second transparent electrode 370, Preventing them from short-circuiting is very beneficial to the reduction of the size of the GOA panel frame and the design of the narrow frame.
  • the photoresist spacer exists between the first transparent electrode 361 and the second transparent electrode 370, which greatly reduces the first transparent electrode 361 and the second transparent electrode 370
  • the probability of electrostatic discharge occurring at the areas overlapping each other and at adjacent positions also enables the short-circuit ring in the electrostatic protection circuit to function normally.
  • no additional process is required, and the photoresist spacer 400 only needs to be formed on the first substrate 310 together with the first transparent electrode 361, thus eliminating multiple processes and costs.
  • the material of the first metal layer and the second metal layer may be selected from gold, silver, copper, iron, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc and other metals, the above alloys or The above combination.
  • the transparent conductive material used for the first transparent electrode and the second transparent electrode may be selected from indium tin oxide, indium zinc oxide, indium tin zinc oxide, hafnium oxide, zinc oxide, aluminum oxide, aluminum tin oxide Substances, aluminum zinc oxide, cadmium tin oxide, cadmium zinc oxide, etc. or a combination of the above.
  • FIG. 5 is a flowchart of a method for manufacturing the display panel according to the first embodiment of the present invention. The method includes:
  • Step S101 providing a first substrate 210
  • Step S102 forming a first metal layer 230, a first isolation layer 280, a second metal layer 250 and a second isolation layer 280 on the first substrate 210 in sequence;
  • Step S103 using a first photomask to etch the first isolation layer 240, the second metal layer 250, and the second gold isolation layer 280 to form a via 260 corresponding to the via
  • a first transparent electrode 261 is provided at the position of 260, and the first transparent electrode 261 is connected to the first metal layer 230 and the second metal layer 250 through the via 260;
  • Step S104 providing a second substrate 220, and forming a second transparent electrode 270 on the second substrate 220;
  • Step S105 Use a second photomask to etch the second transparent electrode 270 and remove a first region 271 of the second transparent electrode 270 corresponding to the position of the first transparent electrode 261 to block
  • the first transparent electrode 261 is electrically connected to the second transparent electrode 270.
  • the manufacturing method further includes:
  • Step S106 An electrostatic protection circuit is provided on the first substrate 210 to connect to a GOA circuit, and a short-circuit ring is provided at an end of the electrostatic protection circuit connected to the GOA circuit.
  • the manufacturing method further includes:
  • Step S107 A first photoetching material is provided on the first transparent electrode 261, a second photoetching material is provided on the second transparent electrode 270, the first photoetching material and all The second photo-etching materials are mutually opposite, so that when the second photomask is used for etching, a pattern of the first transparent electrode 261 is simultaneously formed and the pattern with the first transparent electrode is etched The first region of the second transparent electrode 270 opposite.
  • FIG. 6 is a flowchart of a method for manufacturing the display panel according to the second embodiment of the present invention. The method includes:
  • Step S201 providing a first substrate 310
  • Step S202 forming a first metal layer 330, a first isolation layer 340, a second metal layer 350 and a second isolation layer 380 on the first substrate 310 in sequence;
  • Step S203 etching the first isolation layer 340, the second metal layer 350, and the second isolation layer 380 using a first photomask to form a via 360 corresponding to the via 360
  • a first transparent electrode 400 at the position of the first transparent electrode 400, the first transparent electrode 400 is connected to the first metal layer 330 and the second metal layer 350 through the via 360;
  • Step S204 forming a photoresist layer 400 at a position corresponding to the first transparent electrode 361;
  • Step S205 Etching the photoresist layer 400 and the first transparent electrode 361 at the same time with a second photomask to form a photoresist spacer 400, the size of the photoresist spacer 400 corresponds to the The size of the first transparent electrode 361 is to block the electrical connection between the first transparent electrode and the second transparent electrode, to more effectively avoid the phenomenon of light leakage on the display screen and improve the display effect of the display screen. .
  • the display panels described in various embodiments of the present invention A short-circuit ring is formed in the non-display area, and a capacitor is provided on the short-circuit ring to simultaneously connect the common electrode and the GOA signal line to prevent the GOA circuit from being damaged by static electricity.
  • the present invention further avoids the problem by removing a first area of the second transparent electrode of the second substrate or forming a photoresist spacer at a position corresponding to the first transparent electrode A short circuit occurs between the first substrate and the second substrate under a strong voltage, so the display panel is protected from short circuit due to the voltage generated by the electrostatic discharge test, or even damaged and is directly scrapped, thereby improving the yield and stability of the display panel Performance, the photoresist spacer at the insulating ring is more effective to avoid the phenomenon of light leakage in the display screen, and the display effect of the display screen is improved.

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Abstract

一种显示面板（200）及其制造方法，显示面板（200）包括：一第一基板（210）、一第二基板（220）、GOA电路、一第一金属层（230）、一第二金属层（250）、一过孔（260）、一第一透明电极（261）以及一第二透明电极（270），第一基板（210）上设置一静电防护电路（31、32）连接一GOA电路，第一金属层（230）设置在第一基板（210）上，过孔（260）设置在第一金属层（230）上，第一透明电极（261）设置在过孔（260）内，第二透明电极（270）设置在第二基板（220）上，第二透明电极（270）中的第一区域（271）被蚀刻去除，第一区域（271）与第一透明电极（261）相对应。

Description

具有静电防护的显示面板及其制造方法 技术领域
本发明是涉及显示技术领域，特别是有关于一种具有静电防护的显示面板及其制造方法。
 背景技术
GOA技术即阵列基板行驱动技术(Gate Driver on Array)，是直接将栅极驱动电路整合在阵列基板上以驱动显示面板的多条扫描线的一种技术，省去制作外接硅晶片的驱动晶片，并且减少制作程序、产品成本以及面板周围面积，有利于制造窄边框或无边框的显示产品，提高显示面板的高集成度，使面板能更薄型化。
GOA电路的运作一般需要有同步信号、时钟信号或低压信号等，传输这些信号的信号线分布在面板周围的金属走线处，增加了静电放电风险，且这些信号线若在显示区发生静电放电造成线路烧毁，将会对显示构成很大的影响，造成画面异常，现有技术中的一显示面板在显示区中上基板及下基板的两个透明电极之间出现静电炸伤的情形。因此，在设计阵列基板的过程中会进一步在非显示区设计一增加防止静电放电设计以防止静电放电的静电击伤。
然而，在实际检验中，常常会使用比较严苛的静电放电测试条件对信号线的静电防护性能进行测试，直接以+/-10千伏特的电压用静电放电枪打GOA信号线来测试显示面板的GOA信号线的静电防护性能。发明人经过不断的研究，针对检验后未通过静电放电测试的显示面板进行分析，发现在显示面板中，大多是因为在非显示区(未绘出)具有防止静电放电设计且间距较小处的上基板与下基板上的透明电极之间仍会发生短路所导致。因此，即使在设置有防止静电放电设计的情况下，仍未能有效地防止显示面板因静电放电而线路烧毁，造成画面异常，产品直接报废，因此这是一种必须避免的情况。
现有技术的一般方法是移除下基板的过孔，增加上下基板距离，防止上下基板发生短路，但是移除下基板的透明电极会使过孔保护不足而腐蚀损坏等问题, 而且将下基板过孔及透明电极一并移除共需要改三道光罩，增加制造成本，由于高像素密度、窄边框等要求导致的布线紧密、半导体垫层和栅极尖端结构等因素。
 技术问题
因此，需要一种能够克服以上技术问题的改进型GOA电路设计。
 技术解决方案
有鉴于此，本发明提供一种显示面板的制造方法，以解决现有技术中GOA 电路的金属走线处的信号线因静电放电而线路烧毁的问题，降低了显示面板由于静电放电所导致的不良率。
为达成本发明的前述目的，本发明一实施例提供一种显示面板，所述显示面板包括：
一第一基板和一第二基板，所述第一基板上设置一静电防护电路连接一GOA电路，所述静电防护电路与所述GOA电路连接的一末端设有一短路环；
一第一金属层，所述第一金属层设置在所述第一基板上；
一第一隔离层，所述第一隔离层设置在所述第一金属层上；
一第二金属层，所述第二金属层设置在所述第一隔离层上；
一第二隔离层，所述第二隔离层设置在所述第二金属层上；
一过孔，设置在所述第一金属层上；
一第一透明电极，设置在所述过孔内，所述第一透明电极通过所述过孔连接所述第一金属层及所述第二金属层；及
一第二透明电极，设置在所述第二基板上，所述第二透明电极中的第一区域被蚀刻去除，所述第一区域与所述第一透明电极相对应。
在本发明的一实施例中，所述第一透明电极上设置一第一光致蚀刻材料，在所述第二透明电极上设置一第二光致蚀刻材料，所述第一光致蚀刻材料及所述第二光致蚀刻材料互为反性，使得同时形成所述第一透明电极，并且使所述第二透明电极中与所述第一透明电极相对应处被蚀刻去除。
在本发明的一实施例中，所述静电防护电路是设置在所述显示面板的一非显示区域中，所述第二透明电极的所述第一区域是位于所述短路环处，所述短路环还包括多个电容，所述短路环的两端连接所述GOA电路及一公共电极。
在本发明的一实施例中，所述短路环具有一第一电容、一第二电容以及一第三电容，所述第一电容与所述第二电容串联，所述第三电容并联于所述第一电容及所述第二电容。
本发明另一实施例提供另一种显示面板，所述显示面板包括：
一第一基板和一第二基板，所述第一基板上设置一静电防护电路连接一GOA电路，所述静电防护电路与所述GOA电路连接的一末端设有一短路环；
一第一金属层，所述第一金属层设置在所述第一基板上；
一第一隔离层，所述第一隔离层设置在所述第一金属层上；
一第二金属层，所述第二金属层设置在所述第一隔离层上；
一第二隔离层，所述第二隔离层设置在所述第二金属层上；
一过孔，位于所述第一金属层上；
一第一透明电极，设置在所述过孔内，所述第一透明电极通过所述过孔连接所述第一金属层及所述第二金属层；
一第二透明电极，设置在所述第二基板上；及
一光阻间隔物，覆盖在所述第一透明电极上，阻隔所述第一透明电极与所述第二透明电极之间的电性连接。
在本发明的一实施例中，所述静电防护电路是设置在所述显示面板的一非显示区域中，所述第二透明电极的所述光阻间隔物是位于所述短路环处，所述短路环还包括多个电容，所述短路环的两端连接所述GOA电路及一公共电极。
在本发明的一实施例中，所述短路环具有一第一电容、一第二电容以及一第三电容，所述第一电容与所述第二电容串联，所述第三电容并联于所述第一电容及所述第二电容。
本发明另一实施例提供另一种显示面板的制造方法，所述制造方法包括步骤：
依次在一第一基板上形成一第一金属层、一第一隔离层、一第二金属层及一第二隔离层；
使用一第一光罩对所述第一隔离层、所述第二金属层以及所述第二隔离层进行蚀刻，形成一过孔，在对应于所述过孔的位置上设置一第一透明电极，所述第一透明电极通过所述过孔连接所述第一金属层及所述第二金属层；
提供一第二基板，并在所述第二基板上形成一第二透明电极；以及
使用一第二光罩对所述第二透明电极进行蚀刻，同时去除对应于所述第一透明电极的位置的所述第二透明电极的一第一区域，以阻隔所述第一透明电极与所述第二透明电极之间的电性连接。
在本发明的一实施例中，在所述第一基板上在所述显示面板的一非显示区域中设置一静电防护电路连接一GOA电路，并且在所述静电防护电路与所述GOA电路连接的一末端连接一短路环。
在本发明的一实施例中，所述制造方法还包括：分别在所述第一透明电极上设置一第一光致蚀刻材料，在所述第二透明电极上设置一第二光致蚀刻材料，所述第一光致蚀刻材料及所述第二光致蚀刻材料互为反性，使得当使用所述第二光罩进行蚀刻时，同时形成所述第一透明电极的一图案并且蚀刻与所述第一透明电极的所述图案相反的所述第二透明电极的所述第一区域。
 有益效果
与现有技术相比较，本发明提供一种显示面板的制造方法，其可以改善GOA 电路的金属走线处的信号线的静电防护性能的新方法，通过移除上基板的透明电极可能互相炸伤处的区域，防止显示面板在短路环处因静电放电而线路烧毁，提高显示面板的静电防护性能，减少使用光罩的工序及成本，提高产品的竞争力。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
图1是本发明的一显示面板的一短路环的位置的示意图；
图2是本发明的一显示面板的一短路环的等效电路图；
图3是本发明第一实施例的一显示面板的示意图；
图4是本发明第二实施例的一显示面板的示意图；
图5是本发明第一实施例的一显示面板的一制造方法的流程图；及
图6是本发明第二实施例的一显示面板的一制造方法的流程图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧面、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
需要说明的是，本发明实施例中所有使用“第一”和“第二”的表述均是为了区分两个相同名称非相同的实体或者非相同的参量，可见“第一”、“第二”仅为了表述的方便，不应理解为对本发明实施例的限定，后续实施例对此不再一一说明。
如背景技术所述，现有的解决方案绝大多数是在于设置移除下基板的过孔或增加上下基板距离，以防止上下基板发生短路。但是，移除下基板的透明电极会使过孔保护不足而发生腐蚀、损坏等问题, 而且若将下基板过孔及透明电极一并移除一共需要三道光罩，需要多道工序及增加制造成本，而增加上下基板距离则不利于减少现有的显示面板的厚度。
请参阅图1和图2，图1是本发明的一显示面板20的一短路环24、25的位置的示意图，图2是本发明的一显示面板20的一短路环24、25的等效电路图。本发明的一显示面板20包括显示区21及非显示区22，在所述非显示区22中设有一GOA电路23、多条GOA信号线28、29、30以及多条公共电极线26、27，所述多条GOA信号线28、29、30连接所述GOA电路23并且传输GOA信号至所述显示区21中的栅极、源漏极，所述公共电极线连接一公共电极并且传输驱动信号以驱动所述显示面板。每一所述GOA信号线的第一端和第二端上各设有一静电防护电路31、32，所述静电防护电路31、32连接一GOA信号线及一公共电极线，以形成一短路环24、25。所述静电防护电路31、32包括一电容，可选地包括至少两个互相并联的电容。在本发明的另一实施方式中，所述短路环24、25还可以包括至少一电容，所述短路环具有一第一电容33、一第二电容34以及一第三电容35，所述第一电容33与所述第二电容34串联，所述第三电容35并联于所述第一电容33及所述第二电容34。所述电容33、34、35连接所述GOA电路23及一公共电极线26、27，防止过大的电压炸伤电路。
请参阅图3，图3是本发明第一实施例的一显示面板200的示意图。在本发明一显示面板200中提供一第一基板210；依次在所述第一基板210上形成一第一金属层230、一第一隔离层240、一第二金属层250及一第二隔离层280。
在本发明的一实施方式中，其中所述第一金属层230为一信号线层，所述第一隔离层240为一绝缘层，所述第二隔离层280为一保护层，以避免灌入之液晶受到污染或流出。
使用一第一光罩对所述第一隔离层240、所述第二金属层250以及所述第二隔离层280进行蚀刻，形成一过孔260，在对应于所述过孔260的位置上设置一第一透明电极261，所述第一透明电极261通过所述过孔260连接所述第一金属层230、所述第二金属层250，所述第一基板210上设置一静电防护电路31、32连接一GOA电路，所述静电防护电路与所述GOA电路连接的一末端设有一短路环。
提供一第二基板220，并在所述第二基板220上形成一第二透明电极270；使用一第二光罩对所述第二透明电极270进行蚀刻，同时去除对应于所述第一透明电极261的位置的所述第二透明电极270的一第一区域271。
所述静电防护电路可设置在所述显示面板200的一非显示区域中，所述第二透明电极270的所述第一区域270是位于所述短路环处。所述第一基板210可以是一阵列基板，所述第二基板可以是一彩膜基板，所述基板的材料可以是玻璃。
在本发明的一实施方式中，所述第一金属层230上的信号线的一端连接所述GOA电路的一信号线，所述第二金属层250上所形成的一频率信号线连接第二基板220的第二透明电极270。在本发明的一实施方式中，所述第二透明电极为一公共电极，位于所述第二基板220的朝向第一基板210的一表面，使得当显示面板上出现静电时，藉由所述第二金属层250将所述显示面板200的所述显示区中的静电释放至所述非显示区，从而避免静电进入所述显示区内部造成金属层或透明电极间发生短路的情形，以便保护面板内的电路及组件。
在所述过孔260处，所述第一金属层230及所述第二金属层250上方的所述第一隔离层240及所述第二隔离层280可通过多种方法被挖开，例如：蚀刻等，所述第一透明电极261形成在所述过孔260中并延伸至所述过孔260之外，以将不同层的金属走线(即所述第一金属层230和所述第二金属层250)连接起来。
在本发明的一实施方式中，所述制造方法还包括在所述第一透明电极261上设置一第一光致蚀刻材料，在所述第二透明电极270上设置一第二光致蚀刻材料，所述第一光致蚀刻材料及所述第二光致蚀刻材料互为反性，使得当使用所述第二光罩进行蚀刻时，所述第一透明电极261形成所述第一透明电极361的图案，并且同时对对应于所述第一透明电极261的图案的所述第二透明电极270的所述第一区域271进行蚀刻。
在去除对应于所述第一透明电极270的位置的所述第二透明电极270的所述第一区域271后，在所述第一基板210与所述第二基板220之间提供一液晶层290；以及将所述第一基板210与所述第二基板220对齐贴合。
本发明仅使用一个光罩同时蚀刻所述第一透明电极261以及所述第二透明电极270的所述第一区域271，有效地防止所述第一透明电极261与所述第二透明电极270之间发生静电放电而烧毁，有效减少显示面板的边框的宽度，有利于显示面板能在窄边框中实现复杂GOA布局而不受静电放电而烧毁。
在本发明的另一实施方法中，所述第一光致蚀刻材料为正性的光致蚀刻材料，而所述第二光致蚀刻材料为负性的光致蚀刻材料，使得在UV照射后，所述第一透明电极261上的所述正性的光致蚀刻材料被洗去，所述第一透明电极261以外的部分上保留有所述正性的光致蚀刻材料而被蚀刻，而所述第二透明电极270的所述第一区域271保留有所述负性的光致蚀刻材料而被蚀刻。因此，同时形成所述第一透明电极261及蚀刻所述第一透明电极261对应的所述第二透明电极270的所述第一区域271。
在本发明的另一实施方法中，所述第一光致蚀刻材料为负性的光致蚀刻材料，而所述第二光致蚀刻材料为正性的光致蚀刻材料，使得在UV照射后，所述第一透明电极261以外的部分上保留有所述负性的光致蚀刻材料被保留而产生蚀刻，而所述第二透明电极270的所述第一区域271上保留有所述正性的光致蚀刻材料而被蚀刻，所述第二透明电极270上的所述正性的光致蚀刻材料被洗去。因此，同时形成所述第一透明电极261及蚀刻所述第一透明电极261对应的所述第二透明电极270的所述第一区域271。
所述正性的光致蚀刻材料在UV照射后发生光化学反应被去除，而所述负性的光致蚀刻材料在UV照射后发生交联固化而被保留。
从图3可看出，所述第一透明电极261与所述第二透明电极270之间没有重叠的区域，大幅降低了所述第一透明电极261与所述第二透明电极270在相互重叠的区域处以及邻近位置处发生静电放电的几率，使所述静电防护电路中的短路环在强静电下能正常发挥作用。此外，对应于所述第一透明电极261的区域的所述第二透明电极270的第一区域271的去除并不需要增加额外的工序，仅需使用与所述第一透明电极270相对应的光罩对所述第二透明电极270的第一区域271同时进行刻蚀，因此省去多道工序及成本。
本发明第二实施例的显示面板300相似于本发明第一实施例的显示面板200，并大致沿用相同元件名称，但第二实施例的差异在于：所述第二实施例的显示面板300进一步增设一光阻间隔物400。上述特征的优点在于：所述光阻间隔物400防止在所述短路环处互相靠近的所述第一透明电极361及所述第二透明电极370发生短路，而且不需要额外增加光罩工序，可应用在一第二基板上没有图案化需求的一显示面板中。因此，所述第二透明电极不仅能与所述第一透明电极361共用光罩，并且可省去多道工序及其成本，更进一步相对增加产品的良率，克服一般技术因静电放电而短路的问题。
图4是本发明第二实施例的显示面板300的示意图。在本发明一显示面板300中提供一第一基板310；依次在所述第一基板310上形成一第一金属层330、一第一隔离层340、一第二金属层350及一第二隔离层380。
在本发明的一实施方式中，其中所述第一金属层330为一信号线层，所述第一隔离层340为一绝缘层，所述第二隔离层380为一保护层，以避免灌入之液晶受到污染或流出。
使用一第一光罩对所述第一隔离层340、所述第二金属层350以及所述第二隔离层380进行蚀刻，形成一过孔360，在对应于所述过孔360的位置上形成一第一透明电极361，所述第一透明电极361通过所述过孔360与所述第一金属层330、所述第二金属层350连接；所述第一基板310上设置一静电防护电路连接一GOA电路，所述静电防护电路与所述GOA电路连接的一末端设有一短路环。
在对应于所述第一透明电极361的位置上形成一光阻层；以及使用一第二光罩同时对所述光阻层以及所述第一透明电极361进行蚀刻，以形成一光阻间隔物400，所述光阻间隔物400的一区域对应于所述第一透明电极361的一区域；
在形成所述光阻间隔物后，提供一第二基板320，并在所述第二基板320上形成一第二透明电极370；在所述第一基板310与所述第二基板320之间提供一液晶层390；以及将所述第一基板310与所述第二基板320对齐贴合。
所述静电防护电路可设置在所述显示面板300的一非显示区域中，所述光阻间隔物400是位于所述短路环处。所述第一基板310可以是一阵列基板，所述第二基板320可以是一彩膜基板，所述基板的材料可以是玻璃。
在本发明的一实施方式中，所述第一金属层330上的信号线的一端连接GOA电路的信号线，所述第二金属层350上所形成的频率信号线连接第二基板320的第二透明电极370。可选地，所述第二透明电极370为一公共电极，位于所述第二基板320的朝向第一基板310的一表面，使得当显示面板上出现静电时，藉由所述第二金属层330将所述显示面板300的所述显示区中的静电释放至所述非显示区，从而避免静电进入所述显示区内部造成金属层或透明电极间发生短路的情形，以便保护显示面板内的电路及组件。
在所述过孔360处，所述第一金属层330及所述第二金属层350上方的所述第一隔离层340及所述第二隔离层380可通过蚀刻等方法被挖开，所述第一透明电极361形成在所述过孔360中并延伸至所述过孔360之外，以将不同层的金属走线(即所述第一金属层330和所述第二金属层350)连接起来。
在本发明的一实施方式中，所述光阻间隙子400不仅将整个所述过孔360都全部覆盖，同时亦覆盖所述第一透明电极361向外延伸的最远程处，以覆盖在所述第一透明电极361的整个表面上。
在本发明的一实施方式中，所述光阻间隙子400的图案比所述过孔360处的所述第一透明电极361的尺寸更大，因此可完全覆盖整个所述第一透明电极361。在本发明的一实施方式中，所述光阻间隙子400是绝缘的，因此所述光阻间隙子400就可以将所述第一透明电极361与所述第二透明电极370隔离开来，防止它们发生短路，对GOA面板边框尺寸的缩减和窄边框的设计是非常有利的。
从图4可看出，所述第一透明电极361与所述第二透明电极370之间存在所述光阻间隔子，大幅降低了所述第一透明电极361与所述第二透明电极370相互重叠的区域处以及邻近位置处发生静电放电的几率，也使所述静电防护电路中的所述短路环能正常作用。此外，不需要增加额外的工序，仅需在所述第一基板310上与所述第一透明电极361一起形成所述光阻间隔物400，因此省去多道工序及成本。
所述第一金属层及第二金属层的材质可选自于金、银、铜、铁、锡、铅、铪、钨、钥、钕、钛、钽、铝、锌等金属、上述合金或上述的组合。
所述第一透明电极及所述第二透明电极采用的透明导电材料可选自于铟锡氧化物、铟锌氧化物、铟锡锌氧化物、氧化铪、氧化锌、氧化铝、铝锡氧化物、铝锌氧化物、镉锡氧化物、镉锌氧化物等或上述的组合。
图5是本发明第一实施例的所述显示面板的一制造方法的一流程图，所述制造方法包括：
步骤S101：提供一第一基板210；
步骤S102：依次在所述第一基板210上形成一第一金属层230、一第一隔离层280、一第二金属层250及一第二隔离层280；
步骤S103：使用一第一光罩对所述第一隔离层240、所述第二金属层250以及所述第二金隔离层280进行蚀刻，形成一过孔260，在对应于所述过孔260的位置上设置一第一透明电极261，所述第一透明电极261通过所述过孔260连接所述第一金属层230及所述第二金属层250；
步骤S104：，提供一第二基板220，在所述第二基板220上形成一第二透明电极270；以及
步骤S105：使用一第二光罩对所述第二透明电极270进行蚀刻，同时去除对应于所述第一透明电极261的位置的所述第二透明电极270的一第一区域271，以阻隔所述第一透明电极261与所述第二透明电极270之间的电性连接。
在本发明的一实施例中，所述制造方法还包括：
步骤S106：所述第一基板210上设置一静电防护电路连接一GOA电路，所述静电防护电路与所述GOA电路连接的一末端设有一短路环。
在本发明的一实施例中，所述制造方法还包括：
步骤S107：分别在所述第一透明电极261上设置一第一光致蚀刻材料，在所述第二透明电极270上设置一第二光致蚀刻材料，所述第一光致蚀刻材料及所述第二光致蚀刻材料互为反性，使得当使用所述第二光罩进行蚀刻时，同时形成所述第一透明电极261的一图案并且蚀刻与所述第一透明电极的所述图案相反的所述第二透明电极270的所述第一区域。
图6是本发明第二实施例的所述显示面板的一制造方法的一流程图，所述制造方法包括：
步骤S201：提供一第一基板310；
步骤S202：依次在所述第一基板310上形成一第一金属层330、一第一隔离层340、一第二金属层350及一第二隔离层380；
步骤S203：使用一第一光罩对所述第一隔离层340、所述第二金属层350以及所述第二隔离层380进行蚀刻，形成一过孔360，在对应于所述过孔360的位置上形成一第一透明电极400，所述第一透明电极400通过所述过孔360与所述第一金属层330及所述第二金属层350连接；
步骤S204：在对应于所述第一透明电极361的位置上形成一光阻层400；以及
步骤S205：使用一第二光罩同时对所述光阻层400以及所述第一透明电极361进行蚀刻，以形成一光阻间隔物400，所述光阻间隔物400的尺寸对应于所述第一透明电极361的尺寸，以阻隔所述第一透明电极与所述第二透明电极之间的电性连接，更有效避免显示屏出现漏光的现象，提高了显示屏的显示效果。。
如上所述，相较于现有显示面板在进行+/-10千伏的电压下常常发生静电击伤，而导致画面异常、电路损毁等缺点，本发明的多个实施例所述的显示面板在非显示区形成一短路环，并在短路环上设置电容同时连接公共电极及GOA信号线，防止GOA电路受到静电击伤。此外，本发明进一步通过移除所述第二基板的所述第二透明电极的一第一区域，或是在所述第一透明电极相对应的位置形成一光阻间隔物，有效避免所述第一基板及所述第二基板之间在强电压下发生短路，因此保护显示面板不因静电放电测试所产生的电压而发生短路、甚至损毁而直接报废，进而提高显示面板的良率及稳定性，在绝缘环处的所述光阻间隔物更有效避免显示屏出现漏光的现象，提高了显示屏的显示效果。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (10)

  1.   一种显示面板，其特征在于：所述显示面板包括：
    一第一基板和一第二基板，所述第一基板上设置一静电防护电路连接一GOA电路，所述静电防护电路与所述GOA电路连接的一末端设有一短路环；
    一第一金属层，所述第一金属层设置在所述第一基板上；
    一第一隔离层，所述第一隔离层设置在所述第一金属层上；
    一第二金属层，所述第二金属层设置在所述第一隔离层上；
    一第二隔离层，所述第二隔离层设置在所述第二金属层上；
    一过孔，设置在所述第一金属层上；
    一第一透明电极，设置在所述过孔内，所述第一透明电极通过所述过孔连接所述第一金属层及所述第二金属层；及
    一第二透明电极，设置在所述第二基板上，所述第二透明电极中的第一区域被蚀刻去除，所述第一区域与所述第一透明电极相对应。
  2.   如权利要求1所述的显示面板，其特征在于：所述第一透明电极上设置一第一光致蚀刻材料，在所述第二透明电极上设置一第二光致蚀刻材料，所述第一光致蚀刻材料及所述第二光致蚀刻材料互为反性，使得同时形成所述第一透明电极，并且使所述第二透明电极中与所述第一透明电极相对应处被蚀刻去除。
  3.   如权利要求1所述的显示面板，其特征在于：所述静电防护电路是设置在所述显示面板的一非显示区域中，所述第二透明电极的所述第一区域是位于所述短路环处，所述短路环还包括多个电容，所述短路环的两端连接所述GOA电路及一公共电极。
  4.   如权利要求3所述的显示面板，其特征在于：所述短路环具有一第一电容、一第二电容以及一第三电容，所述第一电容与所述第二电容串联，所述第三电容并联于所述第一电容及所述第二电容。
  5.   一种显示面板，其特征在于：所述显示面板包括：
    一第一基板和一第二基板，所述第一基板上设置一静电防护电路连接一GOA电路，所述静电防护电路与所述GOA电路连接的一末端设有一短路环；
    一第一金属层，所述第一金属层设置在所述第一基板上；
    一第一隔离层，所述第一隔离层设置在所述第一金属层上；
    一第二金属层，所述第二金属层设置在所述第一隔离层上；
    一第二隔离层，所述第二隔离层设置在所述第二金属层上；
    一过孔，位于所述第一金属层上；
    一第一透明电极，设置在所述过孔内，所述第一透明电极通过所述过孔连接所述第一金属层及所述第二金属层；
    一第二透明电极，设置在所述第二基板上；及
    一光阻间隔物，覆盖在所述第一透明电极上，阻隔所述第一透明电极与所述第二透明电极之间的电性连接。
  6.   如权利要求5所述的显示面板，其特征在于：所述静电防护电路是设置在所述显示面板的一非显示区域中，所述第二透明电极的所述光阻间隔物是位于所述短路环处，所述短路环还包括多个电容，所述短路环的两端连接所述GOA电路及一公共电极。
  7.   如权利要求6所述的显示面板，其特征在于：所述短路环具有一第一电容、一第二电容以及一第三电容，所述第一电容与所述第二电容串联，所述第三电容并联于所述第一电容及所述第二电容。
  8.   一种显示面板的制造方法，其特征在于：所述制造方法包括步骤：
    依次在一第一基板上形成一第一金属层、一第一隔离层、一第二金属层及一第二隔离层；
    使用一第一光罩对所述第一隔离层、所述第二金属层以及所述第二隔离层进行蚀刻，形成一过孔，在对应于所述过孔的位置上设置一第一透明电极，所述第一透明电极通过所述过孔连接所述第一金属层及所述第二金属层；
    提供一第二基板，并在所述第二基板上形成一第二透明电极；以及
    使用一第二光罩对所述第二透明电极进行蚀刻，同时去除对应于所述第一透明电极的位置的所述第二透明电极的一第一区域，以阻隔所述第一透明电极与所述第二透明电极之间的电性连接。
  9.   如权利要求8所述的制造方法，其特征在于：在所述第一基板上在所述显示面板的一非显示区域中设置一静电防护电路连接一GOA电路，并且在所述静电防护电路与所述GOA电路连接的一末端连接一短路环。
  10. 如权利要求8所述的制造方法，其特征在于：所述制造方法还包括：分别在所述第一透明电极上设置一第一光致蚀刻材料，在所述第二透明电极上设置一第二光致蚀刻材料，所述第一光致蚀刻材料及所述第二光致蚀刻材料互为反性，使得当使用所述第二光罩进行蚀刻时，同时形成所述第一透明电极的一图案并且蚀刻与所述第一透明电极的所述图案相反的所述第二透明电极的所述第一区域。
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CN112071862A (zh) * 2020-09-03 2020-12-11 Tcl华星光电技术有限公司 发光面板及其制备方法、显示面板

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109976049A (zh) * 2019-04-08 2019-07-05 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
CN110071119B (zh) * 2019-04-09 2021-07-06 深圳市华星光电半导体显示技术有限公司 阵列基板及显示面板
CN110376805A (zh) * 2019-07-22 2019-10-25 深圳市华星光电技术有限公司 一种液晶显示面板及其显示装置
CN110609407B (zh) * 2019-08-27 2021-01-01 深圳市华星光电技术有限公司 液晶显示面板及制备方法
CN110930921B (zh) * 2019-11-25 2021-05-07 深圳市华星光电半导体显示技术有限公司 一种goa电路及包含所述goa电路的显示面板
CN111129036B (zh) * 2019-12-25 2022-07-26 Tcl华星光电技术有限公司 阵列基板及其制备方法、显示面板
CN112666764A (zh) * 2020-12-30 2021-04-16 深圳市华星光电半导体显示技术有限公司 一种液晶显示面板及其制作方法、显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203218262U (zh) * 2013-03-06 2013-09-25 京东方科技集团股份有限公司 静电防护单元、静电防护结构及阵列基板和显示面板
CN103513459A (zh) * 2013-10-14 2014-01-15 北京京东方光电科技有限公司 阵列基板及其制备方法、显示装置及其制备方法
CN104238823A (zh) * 2014-09-26 2014-12-24 上海天马微电子有限公司 一种触控显示面板及其制备方法、触控显示装置
CN104571758A (zh) * 2014-12-23 2015-04-29 上海天马微电子有限公司 一种阵列基板和显示面板
US20160018706A1 (en) * 2014-07-18 2016-01-21 Mitsubishi Electric Corporation Liquid crystal display
CN107863340A (zh) * 2017-10-25 2018-03-30 上海中航光电子有限公司 一种阵列基板、其制作方法、显示面板及显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1649110A (zh) * 2004-01-19 2005-08-03 财团法人工业技术研究院 具有静电放电防护的薄膜晶体管元件的形成方法
KR102145390B1 (ko) * 2013-10-25 2020-08-19 삼성디스플레이 주식회사 정전기 방전 회로를 포함하는 표시 장치
CN105633114A (zh) * 2014-11-20 2016-06-01 群创光电股份有限公司 显示面板及包含其的显示设备

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203218262U (zh) * 2013-03-06 2013-09-25 京东方科技集团股份有限公司 静电防护单元、静电防护结构及阵列基板和显示面板
CN103513459A (zh) * 2013-10-14 2014-01-15 北京京东方光电科技有限公司 阵列基板及其制备方法、显示装置及其制备方法
US20160018706A1 (en) * 2014-07-18 2016-01-21 Mitsubishi Electric Corporation Liquid crystal display
CN104238823A (zh) * 2014-09-26 2014-12-24 上海天马微电子有限公司 一种触控显示面板及其制备方法、触控显示装置
CN104571758A (zh) * 2014-12-23 2015-04-29 上海天马微电子有限公司 一种阵列基板和显示面板
CN107863340A (zh) * 2017-10-25 2018-03-30 上海中航光电子有限公司 一种阵列基板、其制作方法、显示面板及显示装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112071862A (zh) * 2020-09-03 2020-12-11 Tcl华星光电技术有限公司 发光面板及其制备方法、显示面板
US20220320143A1 (en) * 2020-09-03 2022-10-06 Tcl China Star Optoelectronics Technology Co., Ltd. Light-emitting panel, method manufacturing the same, and display device having the same
US11817461B2 (en) 2020-09-03 2023-11-14 Tcl China Star Optoelectronics Technology Co., Ltd. Light-emitting panel, method manufacturing the same, and display device having the same with connection portion
CN112071862B (zh) * 2020-09-03 2024-01-19 Tcl华星光电技术有限公司 发光面板及其制备方法、显示面板

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