WO2020073548A1 - 用于提高器件稳定性的goa单元 - Google Patents

用于提高器件稳定性的goa单元 Download PDF

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Publication number
WO2020073548A1
WO2020073548A1 PCT/CN2019/070555 CN2019070555W WO2020073548A1 WO 2020073548 A1 WO2020073548 A1 WO 2020073548A1 CN 2019070555 W CN2019070555 W CN 2019070555W WO 2020073548 A1 WO2020073548 A1 WO 2020073548A1
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Prior art keywords
electrically connected
gate
thin film
film transistor
unit
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PCT/CN2019/070555
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English (en)
French (fr)
Inventor
吕晓文
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Publication of WO2020073548A1 publication Critical patent/WO2020073548A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the invention relates to a GOA unit, in particular to a GOA unit for improving the stability of the device.
  • Liquid crystal display (Liquid Crystal Display, LCD), referred to as liquid crystal panel, has many advantages such as thin body, power saving, no radiation, etc. It has been widely used, for example: LCD TV, smart phone, digital camera, tablet computer, computer Screens, or laptop screens, dominate the field of flat panel displays.
  • the working principle of a liquid crystal panel is to inject liquid crystal molecules between a thin film transistor array substrate (Thin Film Transistor Array Substrate, TFT Array Substrate) and a color filter substrate (Color Filter, CF), and apply a driving voltage to the two substrates To control the rotation direction of the liquid crystal molecules, refract the light from the backlight module to produce a picture.
  • a thin film transistor array substrate Thin Film Transistor Array Substrate, TFT Array Substrate
  • Color Filter Color Filter
  • the liquid crystal panel has a plurality of pixels arranged in an array, each pixel is electrically connected to a thin film transistor (TFT), the gate of the thin film transistor is connected to the horizontal scanning line, and the source is connected to the vertical direction The drain of the data line is connected to the pixel electrode. Applying sufficient voltage on the horizontal scanning line will turn on all the TFTs electrically connected to the horizontal scanning line, so that the signal voltage on the data line can be written to the pixels, control the transmittance of different liquid crystals and then control the color With brightness effect.
  • Gate Driver on Array abbreviated as GOA, is to use the existing Array manufacturing process of the thin film transistor liquid crystal panel to integrate the gate row scanning driving circuit on the TFT array substrate to realize the driving method of scanning the gate.
  • GOA driver circuits to replace traditional gate drive chips (ICs) has the opportunity to increase production capacity and reduce product costs, and can make LCD panels more suitable for making narrow-frame or borderless display products.
  • the existing GOA circuit usually includes a plurality of cascaded GOA units, and each stage of the GOA unit corresponds to driving one level of horizontal scanning lines.
  • the main structure of the GOA unit includes a pull-up unit, a pull-up control unit, a pull-down unit and a pull-down maintenance unit, and a boost strap (Boast strap) capacitor, etc .;
  • the pull-up unit is mainly responsible for outputting the clock signal (Clock) as Gate signal;
  • the pull-up control unit is responsible for controlling the opening time of the pull-up unit, generally connected to the stage signal or gate signal passed from the previous stage GOA circuit;
  • the pull-down unit is responsible for pulling the gate signal to a low potential at the first time , That is, turn off the gate signal;
  • the pull-down maintenance unit is responsible for maintaining the gate output signal and the gate signal of the pull-up unit (usually called Q point) in the off state (ie, negative potential);
  • the bootstrap capacitor is responsible for Q point
  • the initial stage GOA unit starts the entire GOA circuit through a start signal of the stage transmission signal output terminal STV, wherein the stage transmission signal output terminal STV is electrically connected to the film of a pull-up control unit
  • the gate (gate) and source (source) of the transistor, the gate-source voltage Vgs 0 at this time.
  • the gate signal and the source of the thin-film transistor of the pull-up control unit are electrically connected to the cascade signal output terminal ST (n) and the gate signal output terminal G (n), respectively Source, where the low potential of the cascade signal output terminal ST (n) is an operating voltage VSSQ, and the low potential of the gate signal output terminal G (n) is an operating voltage VSSG, where VSSQ-VSSG ⁇ -2V, That is, at this time, the gate-source voltage Vgs is less than -2V, and under extreme conditions, for example, operating in a high-temperature or high-pressure environment for a long time, it is easy to cause the thin film transistor of the pull-up control unit in the GOA circuit to fail.
  • the object of the present invention is to provide a GOA unit for improving the stability of the device, which uses the potential design of the reset signal terminal to reduce the gate-source voltage of the GOA unit of the initial stage and make it consistent with the gate-source voltage of the GOA unit of the nth stage. Therefore, it is possible to prevent the failure of the GOA unit at the initial stage under extreme conditions and improve the stability of the device.
  • an embodiment of the present invention provides a GOA unit for improving device stability.
  • the GOA unit includes a pull-up control unit, a pull-up unit, a pull-down unit, and a pull-down maintenance unit And a reset thin film transistor (T12);
  • the pull-up unit, the pull-down unit, and the pull-down sustain unit are electrically connected to the gate signal output terminal (G (n)) of the n-th stage GOA unit;
  • the pull-up control unit and the pull-down unit are electrically connected to the gate signal point (Q (n)) of the n-th stage GOA unit, and the gate of the reset thin film transistor (T12) is electrically connected to a reset signal terminal (RESET), the source of the reset thin film transistor (T12) is electrically connected to an operating voltage (VSSQ), and the drain of the reset thin film transistor (T12) is electrically connected to the gate signal of the nth stage GOA cell Point (Q (n)); wherein the pull-up
  • the pull-up control unit further includes: a second thin film transistor (T22) whose gate is electrically connected to the gate signal point (Q (n) of the n-th stage GOA unit ), The source is electrically connected to the output signal ST (n) of the n-stage GOA unit, and the drain is electrically connected to a clock signal (CK).
  • T22 second thin film transistor
  • the pull-up unit includes: a third thin film transistor (T21) whose gate is electrically connected to the gate signal point (Q (n)) of the n-th stage GOA unit, The source is electrically connected to the gate signal output terminal (G (n)) of the n-th stage GOA unit, and the drain is electrically connected to a clock signal (CK).
  • T21 third thin film transistor
  • the pull-down unit includes: a fourth thin film transistor (T41), whose gate is electrically connected to the gate signal output terminal of the n + mth stage GOA unit, m is a natural number, and the drain Electrically connected to the gate signal point (Q (n)) of the n-th stage GOA unit, the source is electrically connected to an operating voltage (VSSQ); and a fifth thin film transistor (T31), the gate of which is connected to the nth The gate signal output terminal of the + m-level GOA unit, the drain is electrically connected to the gate signal output terminal (G (n)), and the source is electrically connected to the operating voltage (VSSG).
  • T41 fourth thin film transistor
  • T41 whose gate is electrically connected to the gate signal output terminal of the n + mth stage GOA unit
  • m is a natural number
  • the drain Electrically connected to the gate signal point (Q (n)) of the n-th stage GOA unit, the source is electrically connected to an operating voltage (VSSQ
  • the pull-down sustaining unit includes: a sixth thin film transistor (T32) whose gate is electrically connected to a node (P (n)), source and drain of the n-th stage GOA unit The electrode is electrically connected to the gate signal output terminal (G (n)) and the operating voltage (VSSQ); a seventh thin film transistor (T42) whose gate is electrically connected to the node (P (n)), The source and the drain are electrically connected to the gate signal point (Q (n)) and the operating voltage (VSSQ) of the n-th stage GOA unit respectively; an eighth thin film transistor (T51) whose gate is electrically connected to a Clock signal (CK), the source and the drain are electrically connected to the clock signal (CK) and the gate of a fourth thin film transistor (T53); a ninth thin film transistor (T53), its source and drain Are electrically connected to the clock signal (CK) and the node (P (n)); a tenth thin film transistor (T52)
  • an embodiment of the present invention provides a GOA unit for improving device stability.
  • the GOA unit includes a pull-up control unit, a pull-up unit, a pull-down unit, and a pull-down maintenance unit And a reset thin film transistor (T12);
  • the pull-up unit, the pull-down unit, and the pull-down sustain unit are electrically connected to the gate signal output terminal (G (n)) of the n-th stage GOA unit;
  • the pull-up control unit and the pull-down unit are electrically connected to the gate signal point (Q (n)) of the n-th stage GOA unit, and the gate of the reset thin film transistor (T12) is electrically connected to a reset signal terminal (RESET), the source of the reset thin film transistor (T12) is electrically connected to an operating voltage (VSSQ), and the drain of the reset thin film transistor (T12) is electrically connected to the gate signal of the nth stage GOA cell Point (Q (n)); wherein the pull-up
  • the pull-up control unit further includes: a second thin film transistor (T22) whose gate is electrically connected to the gate signal point (Q (n) of the n-th stage GOA unit ), The source is electrically connected to the output signal ST (n) of the n-stage GOA unit, and the drain is electrically connected to a clock signal (CK).
  • T22 second thin film transistor
  • the pull-up unit includes: a third thin film transistor (T21) whose gate is electrically connected to the gate signal point (Q (n)) of the n-th stage GOA unit, The source is electrically connected to the gate signal output terminal (G (n)) of the N-th stage GOA unit, and the drain is electrically connected to a clock signal (CK).
  • T21 third thin film transistor
  • the pull-down unit includes: a fourth thin film transistor (T41), whose gate is electrically connected to the gate signal output terminal of the n + mth stage GOA unit, m is a natural number, and the drain Electrically connected to the gate signal point (Q (n)) of the n-th stage GOA unit, the source is electrically connected to an operating voltage (VSSQ); and a fifth thin film transistor (T31), the gate of which is connected to the nth The gate signal output terminal of the + m-level GOA unit, the drain is electrically connected to the gate signal output terminal (G (n)), and the source is electrically connected to the operating voltage (VSSG).
  • T41 fourth thin film transistor
  • T41 whose gate is electrically connected to the gate signal output terminal of the n + mth stage GOA unit
  • m is a natural number
  • the drain Electrically connected to the gate signal point (Q (n)) of the n-th stage GOA unit, the source is electrically connected to an operating voltage (VSSQ
  • the pull-down sustaining unit includes: a sixth thin film transistor (T32) whose gate is electrically connected to a node (P (n)), source and drain of the n-th stage GOA unit The electrode is electrically connected to the gate signal output terminal (G (n)) and the operating voltage (VSSQ); a seventh thin film transistor (T42) whose gate is electrically connected to the node (P (n)), The source and the drain are electrically connected to the gate signal point (Q (n)) and the operating voltage (VSSQ) of the n-th stage GOA unit respectively; an eighth thin film transistor (T51) whose gate is electrically connected to a Clock signal (CK), the source and the drain are electrically connected to the clock signal (CK) and the gate of a fourth thin film transistor (T53); a ninth thin film transistor (T53), its source and drain Are electrically connected to the clock signal (CK) and the node (P (n)); a tenth thin film transistor (T52)
  • an embodiment of the present invention provides a GOA unit for improving device stability.
  • the GOA unit includes a pull-up control unit, a pull-up unit, a pull-down unit, and a pull-down maintenance unit And a reset thin film transistor (T12);
  • the pull-up unit, the pull-down unit, and the pull-down sustain unit are electrically connected to the gate signal output terminal (G (n)) of the n-th stage GOA unit;
  • the pull-up control unit and the pull-down unit are electrically connected to the gate signal point (Q (n)) of the n-th stage GOA unit, and the gate of the reset thin film transistor (T12) is electrically connected to a reset signal terminal (RESET), the source of the reset thin film transistor (T12) is electrically connected to an operating voltage (VSSQ), and the drain of the reset thin film transistor (T12) is electrically connected to the gate signal of the nth stage GOA cell Point (Q (n)); wherein the pull-up
  • the pull-up control unit further includes: a second thin film transistor (T22) whose gate is electrically connected to the gate signal point (Q (n) of the n-th stage GOA unit ), The source is electrically connected to the output signal ST (n) of the n-stage GOA unit, and the drain is electrically connected to a clock signal (CK).
  • T22 second thin film transistor
  • the pull-up unit includes: a third thin film transistor (T21) whose gate is electrically connected to the gate signal point (Q (n)) of the n-th stage GOA unit, The source is electrically connected to the gate signal output terminal (G (n)) of the n-th stage GOA unit, and the drain is electrically connected to a clock signal (CK).
  • T21 third thin film transistor
  • the pull-down unit includes: a fourth thin film transistor (T41), whose gate is electrically connected to the gate signal output terminal of the n + mth stage GOA unit, m is a natural number, and the drain Electrically connected to the gate signal point (Q (n)) of the n-th stage GOA unit, the source is electrically connected to an operating voltage (VSSQ); and a fifth thin film transistor (T31), the gate of which is connected to the nth The gate signal output terminal of the + m-level GOA unit, the drain is electrically connected to the gate signal output terminal (G (n)), and the source is electrically connected to the operating voltage (VSSG).
  • T41 fourth thin film transistor
  • T41 whose gate is electrically connected to the gate signal output terminal of the n + mth stage GOA unit
  • m is a natural number
  • the drain Electrically connected to the gate signal point (Q (n)) of the n-th stage GOA unit, the source is electrically connected to an operating voltage (VSSQ
  • the pull-down sustaining unit includes: a sixth thin film transistor (T32) whose gate is electrically connected to a node (P (n)), source and drain of the n-th stage GOA unit The electrode is electrically connected to the gate signal output terminal (G (n)) and the operating voltage (VSSQ); a seventh thin film transistor (T42) whose gate is electrically connected to the node (P (n)), The source and the drain are electrically connected to the gate signal point (Q (n)) and the operating voltage (VSSQ) of the n-th stage GOA unit respectively; an eighth thin film transistor (T51) whose gate is electrically connected to a Clock signal (CK), the source and the drain are electrically connected to the clock signal (CK) and the gate of a fourth thin film transistor (T53); a ninth thin film transistor (T53), its source and drain Are electrically connected to the clock signal (CK) and the node (P (n)); a tenth thin film transistor (T52)
  • the GOA unit of the present invention uses the potential design of the reset signal terminal to achieve the problem of reducing the leakage of the thin film transistor of the pull-up control unit of the GOA unit of the initial stage, that is, to reduce the gate-source voltage of the GOA unit of the initial stage, Make it the same as the gate-source voltage of the nth-level GOA cell, thus preventing the failure of the initial-level GOA cell under extreme conditions and improving the stability of the device.
  • FIG. 1 is a schematic structural diagram of a first preferred embodiment of the GOA unit of the present invention for improving device stability.
  • FIG. 2 is a schematic structural diagram of a second preferred embodiment of the GOA unit of the present invention for improving device stability.
  • FIG. 1 is a schematic structural diagram of a first preferred embodiment of the GOA unit of the present invention.
  • the GOA circuit of the present invention includes a plurality of cascaded GOA units, wherein the nth stage GOA unit controls the charging of the nth stage horizontal scanning line, and the nth stage GOA unit includes a pull-up control unit 2 and a pull-up The unit 3, the pull-down unit 4, the pull-down sustain unit 5 and a reset thin film transistor T12.
  • the present invention will describe in detail the detailed structure, assembly relationship and operation principle of the above-mentioned components of each embodiment in the following.
  • the pull-up unit 3, the pull-down unit 4 and the pull-down sustain unit 5 are electrically connected to the gate signal output terminal G (n) of the n-th stage GOA unit, and the The pull-up control unit 2 and the pull-down unit 4 are electrically connected to the gate signal point Q (n) of the n-th stage GOA unit.
  • a gate of the reset thin film transistor T12 is electrically connected to a reset signal terminal RESET, a source of the reset thin film transistor T12 is electrically connected to an operating voltage VSSQ, and a drain of the reset thin film transistor T12 is electrically The gate signal point Q (n) of the GOA cell of the nth stage is connected.
  • the pull-up control unit 2 mainly implements pre-charging for the gate signal point Q (n), wherein the pull-up control unit 2 includes a first thin film transistor T11 and a second thin film transistor T22 , Wherein a gate of the first thin film transistor T11 is electrically connected to a start signal STV, a drain of the first thin film transistor T11 is electrically connected to the reset signal terminal RESET, and the first thin film transistor T11 A source is electrically connected to the gate signal point Q (n) of the nth stage GOA cell, and a gate of the second thin film transistor T22 is electrically connected to the gate signal of the nth stage GOA cell At point Q (n), a source of the second thin-film transistor T22 is electrically connected to the stage-transmitted signal output terminal ST (n) of the n-th stage GOA unit, and a drain of the second thin-film transistor T22 is electrically A clock signal CK is connected. It is worth mentioning that the second thin film transistor T22 is a signal downloading circuit, which
  • the pull-up unit 3 mainly raises a potential of the gate signal output terminal G (n), wherein the pull-up unit 3 includes a third thin film transistor T21, wherein the third thin film A gate of the transistor T21 is electrically connected to the gate signal point Q (n) of the nth stage GOA cell, and a source of the third thin film transistor T21 is electrically connected to the gate of the nth stage GOA cell At the signal output terminal G (n), a drain of the third thin film transistor T21 is electrically connected to a clock signal CK.
  • the pull-down unit 4 mainly pulls down the gate signal point Q (n) and increases the potential of the gate signal output terminal G (n).
  • the pull-down unit 4 includes a fourth A thin film transistor T41 and a fifth thin film transistor T31, wherein a gate of the fourth thin film transistor T41 is electrically connected to the gate signal output terminal of the n + mth stage GOA unit, for example: G (n + 4), wherein m is a natural number, a drain of the fourth thin film transistor T41 is electrically connected to the gate signal point Q (n) of the nth stage GOA unit, and a source of the fourth thin film transistor T41 is electrically connected to a Operating voltage VSSQ.
  • a gate of the fifth thin film transistor T31 is connected to the gate signal output terminal of the n + mth stage GOA unit, for example: G (n + 4), a gate of the fifth thin film transistor T31 The drain is electrically connected to the gate signal output terminal G (n), and a source of the fifth thin film transistor T31 is electrically connected to the operating voltage VSSG.
  • the pull-down sustain unit 5 mainly controls the gate signal point Q (n), and maintains the potential of the gate signal output terminal G (n) at a voltage value
  • the pull-down sustain unit 5 includes a sixth thin film transistor T32, a seventh thin film transistor T42, an eighth thin film transistor T51, a ninth thin film transistor T53, a tenth thin film transistor T52 and an eleventh thin film transistor T54, wherein the sixth A gate of the thin film transistor T32 is electrically connected to a node P (n) of the n-th stage GOA unit, and a source of the sixth thin film transistor T32 is electrically connected to the gate signal output terminal G (n), so A drain of the sixth thin film transistor T32 is electrically connected to the operating voltage VSSQ; a gate of the seventh thin film transistor T42 is electrically connected to the node P (n), a The source is electrically connected to the gate signal point Q (n) of the n-th stage GOA unit, a drain of the seventh thin film transistor T42 is electrical
  • a RESET circuit and a signal are provided in a large current in the device.
  • the GOA unit designs the reset signal terminal RESET signal to be the same signal as the start signal STV Each time the GOA unit is started, the signal remaining at the gate signal point Q (n) is pulled to a low potential signal through the reset signal terminal RESET / start signal STV. Further, first, the signal of the reset signal terminal RESET is connected to the source of the GOA circuit at the initial stage of the GOA circuit, and the signal to which the gate is connected still uses the start signal STV.
  • the start signal STV and the reset signal terminal RESET input different signals respectively.
  • the low potential of the start signal STV is generally the low potential of the operating voltage VSSQ, and the reset signal terminal RESET is generally -8V.
  • the low potential is set to the low potential of the operating voltage VSSG-6V .
  • the gate-source voltage Vgs of the GOA unit in the initial stage and the gate-source voltage Vgs of the n-th stage GOA unit are the same and -2v, which can reduce the extreme conditions, such as: high temperature or high voltage for a long time Operation under the environment of the environment, the problem of the failure of the initial GOA unit, and improve the stability of the device.
  • the GOA unit of the present invention uses the potential design of the reset signal terminal RESET to reduce the leakage of the thin film transistor of the pull-up control unit of the GOA unit of the initial stage, that is, to reduce the gate-source voltage Vgs of the GOA unit of the initial stage. It is consistent with the gate-source voltage Vgs of the n-th stage GOA cell, so that the initial stage GOA cell can be prevented from failing under extreme conditions, and the stability of the device can be improved.
  • FIG. 2 is a schematic structural diagram of a second preferred embodiment of the GOA unit of the present invention for improving device stability.
  • the components therein are similar to the first preferred embodiment of the present invention, and generally use the same components.
  • the difference between the second preferred embodiment is that the pull-up control unit 2 includes a first thin film transistor T11, and a gate of the first thin film transistor T11 is electrically connected to a start signal STV , A drain of the first thin film transistor T11 is electrically connected to a load resistor R, and the load resistor R is electrically connected to the reset signal terminal RESET, and a source of the first thin film transistor T11 is electrically connected The gate signal point Q (n) of the n-th stage GOA cell.
  • the reset signal terminal RESET is connected to the source of the GOA unit of the starting stage, and the gate (Gate) still uses the start signal STV, wherein the start signal STV and the reset signal terminal RESET are input differently Signal, and further, the resistance-capacitance delay (RC delay) of the reset signal terminal RESET is changed. That is to say, in the actual circuit, G (n) usually produces a larger resistance delay, the load external to the start signal STV is smaller, and the resistance delay is smaller. Therefore, the reset signal terminal can be reset by The load resistor R is connected to increase the load of the reset signal terminal RESET.
  • the GOA unit of the second preferred embodiment of the present invention can also use the potential design of the reset signal terminal RESET to achieve the problem of reducing the leakage of the thin film transistor of the pull-up control unit of the GOA unit of the initial stage, that is, to reduce the initial stage
  • the gate-source voltage Vgs of the GOA unit is made to be the same as the gate-source voltage Vgs of the n-th stage GOA unit, thus preventing the failure of the initial stage GOA unit under extreme conditions and improving the stability of the device.

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Abstract

一种用于提高器件稳定性的GOA单元，GOA单元包括一上拉控制单元（2）、一上拉单元（3）、一下拉单元（4）、一下拉维持单元（5）以及一复位薄膜晶体管（T12）；复位薄膜晶体管（T12）的栅极电性连接一复位信号端（RESET），复位薄膜晶体管（T12）的源极电性连接一工作电压（VSSQ）。利用复位信号端（RESET）的电位设计，减少起始级GOA单元的栅源电压，使其和第n级GOA单元的栅源电压一致，因而能够防止在极端条件下起始级GOA单元失效，并提高器件的稳定性。

Description

用于提高器件稳定性的GOA单元 技术领域
本发明是有关于一种GOA单元，特别是有关于一种用于提高器件稳定性的GOA单元。
 背景技术
液晶显示面板(Liquid Crystal Display，LCD)，简称液晶面板，具有机身薄、省电、无辐射等众多优点，得到了广泛地应用，例如：液晶电视、智能手机、数字相机、平板电脑、计算机屏幕、或笔记本电脑屏幕等，在平板显示领域中占主导地位。
液晶面板的工作原理是在薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)与彩色滤光片基板(Color Filter，CF)之间灌入液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，将背光模组的光线折射出来产生画面。
液晶面板内具有多个呈阵列式排布的像素，每个像素电性连接一个薄膜晶体管(TFT)，薄膜晶体管的栅极(Gate)连接至水平扫描线，源极(Source)连接至垂直方向的数据线，漏极(Drain)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制不同液晶的透光度进而达到控制色彩与亮度的效果。Gate Driver on Array，简称GOA，是利用现有的薄膜晶体管液晶面板的阵列(Array)制程将栅极行扫描驱动电路集成制作在TFT阵列基 板上，实现对栅极进行扫描的驱动方式。使用GOA驱动电路来代替传统的栅极驱动芯片(IC)，有机会提升产能并降低产品成本，而且可以使液晶面板更适合制作窄边框或无边框的显示产品。
现有的GOA电路，通常包括级联的多个GOA单元，每一级GOA单元对应驱动一级水平扫描线。GOA单元的主要结构包括上拉单元，上拉控制单元、下拉单元及下拉维持单元，以及负责电位抬高的自举(Boast strap)电容等；上拉单元主要负责将时钟信号(Clock)输出为栅极信号；上拉控制单元负责控制上拉单元的打开时间，一般连接前面级GOA电路传递过来的级传 信号或者栅极信号；下拉单元负责在第一时间将栅极信号拉低为低电位，即关闭栅极信号；下拉维持单元则负责将栅极输出信号和上拉单元的栅极信号(通常称为Q点)维持在关闭状态(即负电位）；自举电容则负责Q点的二次抬升，这样有利于上拉单元的G(n)输出。
然而，在GOA电路中，起始级GOA单元是通过级传信号输出端STV的一启动信号来启动整个GOA电路，其中所述级传信号输出端STV同时电性连接一上拉控制单元的薄膜晶体管的栅极(Gate)及源极(Source)，此时栅源电压Vgs=0。在第n级电路中，是通过将级传信号输出端ST(n)及栅极信号输出端G(n)分别电性连接所述上拉控制单元的薄膜晶体管的栅极(Gate)及源极(Source)，其中级传信号输出端ST(n)的低电位是一工作电压VSSQ，栅极信号输出端G(n)的低电位是一工作电压VSSG，其中VSSQ-VSSG<-2V，即是此时栅源电压Vgs小于-2V，在极端条件下，例如：长时间在高温或高压的环境下操作，容易造成所述GOA电路中的上拉控制单元的薄膜晶体管失效。
 技术问题
本发明的目的在于提供一种用于提高器件稳定性的GOA单元，利用复位信号端的电位设计，减少起始级GOA单元的栅源电压，使其和第n级GOA单元的栅源电压一致，因而能够防止在极端条件下所述起始级GOA单元失效，并提高器件的稳定性。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
为达成本发明的前述目的，本发明一实施例提供一种用于提高器件稳定性的GOA单元，所述GOA单元包括一上拉控制单元、一上拉单元、一下拉单元、一下拉维持单元以及一复位薄膜晶体管(T12)；所述上拉单元、所述下拉单元及所述下拉维持单元分别与第n级GOA单元的栅极信号输出端(G(n))电性连接；所述上拉控制单元及所述下拉单元与所述第n级GOA单元的栅极信号点(Q(n))电性连接，所述复位薄膜晶体管(T12)的栅极电性连接一复位信号端(RESET)，所述复位薄膜晶体管(T12)的源极电性连接一工作电压(VSSQ)，所述复位薄膜晶体管(T12)的漏极电性连接所述第n级GOA单元的栅极信号点(Q(n))；其中所述上拉控制单元包括一第一薄膜晶体管(T11)，其栅极电性连接一启动信号(STV)，漏极电性连接所述复位信号端(RESET)，源极电性连接所述第n级GOA单元的栅极信号点(Q(n))；所述下拉维持单元配置用以控制所述栅极信号点(Q(n))，并且让所述栅极信号输出端(G(n))的电位维持在一电压值。
在本发明的一实施例中，所述上拉控制单元还包括：一第二薄膜晶体管(T22)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性连接第n级GOA单元的级传信号输出端ST(n)，漏极电性连接一时钟信号(CK)。
在本发明的一实施例中，所述上拉单元包括：一第三薄膜晶体管(T21)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性接所述第n级GOA单元的栅极信号输出端(G(n))，漏极电性连接一时钟信号(CK)。
在本发明的一实施例中，所述下拉单元包括：一第四薄膜晶体管(T41)，其栅极电性连接第n+m级GOA单元的栅极信号输出端，m为自然数，漏极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性连接一工作电压(VSSQ)；及一第五薄膜晶体管(T31)，其栅极连接第n+m级GOA单元的栅极信号输出端，漏极电性连接所述栅极信号输出端(G(n))，源极电性连接所述工作电压(VSSG)。
在本发明的一实施例中，所述下拉维持单元包括：一第六薄膜晶体管(T32)，其栅极电性连接第n级GOA单元的一节点(P(n))，源极及漏极分别电性连接所述栅极信号输出端(G(n))及工作电压(VSSQ)；一第七薄膜晶体管(T42)，其栅极电性连接所述节点(P(n))，源极及漏极分别电性连接所述第n级GOA单元的栅极信号点(Q(n))及工作电压(VSSQ)；一第八薄膜晶体管(T51)，其栅极电性连接一时钟信号(CK)，源极及漏极分别电性连接所述时钟信号(CK)及一第四薄膜晶体管(T53)的栅极；一第九薄膜晶体管(T53)，其源极及漏极分别电性连接所述时钟信号(CK)及所述节点(P(n))；一第十薄膜晶体管(T52)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极及漏极分别电性连接一工作电压(VSSG)及第四薄膜晶体管(T53)的栅极；及一第十一薄膜晶体管(T54)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极及漏极分别电性连接所述工作电压(VSSG)及所述节点(P(n))。
为达成本发明的前述目的，本发明一实施例提供一种用于提高器件稳定性的GOA单元，所述GOA单元包括一上拉控制单元、一上拉单元、一下拉单元、一下拉维持单元以及一复位薄膜晶体管(T12)；所述上拉单元、所述下拉单元及所述下拉维持单元分别与第n级GOA单元的栅极信号输出端(G(n))电性连接；所述上拉控制单元及所述下拉单元与所述第n级GOA单元的栅极信号点(Q(n))电性连接，所述复位薄膜晶体管(T12)的栅极电性连接一复位信号端(RESET)，所述复位薄膜晶体管(T12)的源极电性连接一工作电压(VSSQ)，所述复位薄膜晶体管(T12)的漏极电性连接所述第n级GOA单元的栅极信号点(Q(n))；其中所述上拉控制单元包括一第一薄膜晶体管(T11)，其栅极电性连接一启动信号(STV)，漏极电性连接一负载电阻而且所述负载电阻电性连接所述复位信号端(RESET)，源极电性连接所述第n级GOA单元的栅极信号点(Q(n))。
在本发明的一实施例中，所述上拉控制单元还包括：一第二薄膜晶体管(T22)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性连接第n级GOA单元的级传信号输出端ST(n)，漏极电性连接一时钟信号(CK)。
在本发明的一实施例中，所述上拉单元包括：一第三薄膜晶体管(T21)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性接所述第N级GOA单元的栅极信号输出端(G(n))，漏极电性连接一时钟信号(CK)。
在本发明的一实施例中，所述下拉单元包括：一第四薄膜晶体管(T41)，其栅极电性连接第n+m级GOA单元的栅极信号输出端，m为自然数，漏极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性连接一工作电压(VSSQ)；及一第五薄膜晶体管(T31)，其栅极连接第n+m级GOA单元的栅极信号输出端，漏极电性连接所述栅极信号输出端(G(n))，源极电性连接所述工作电压(VSSG)。
在本发明的一实施例中，所述下拉维持单元包括：一第六薄膜晶体管(T32)，其栅极电性连接第n级GOA单元的一节点(P(n))，源极及漏极分别电性连接所述栅极信号输出端(G(n))及工作电压(VSSQ)；一第七薄膜晶体管(T42)，其栅极电性连接所述节点(P(n))，源极及漏极分别电性连接所述第n级GOA单元的栅极信号点(Q(n))及工作电压(VSSQ)；一第八薄膜晶体管(T51)，其栅极电性连接一时钟信号(CK)，源极及漏极分别电性连接所述时钟信号(CK)及一第四薄膜晶体管(T53)的栅极；一第九薄膜晶体管(T53)，其源极及漏极分别电性连接所述时钟信号(CK)及所述节点(P(n))；一第十薄膜晶体管(T52)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极及漏极分别电性连接一工作电压(VSSG)及第四薄膜晶体管(T53)的栅极；及一第十一薄膜晶体管(T54)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极及漏极分别电性连接所述工作电压(VSSG)及所述节点(P(n))。
为达成本发明的前述目的，本发明一实施例提供一种用于提高器件稳定性的GOA单元，所述GOA单元包括一上拉控制单元、一上拉单元、一下拉单元、一下拉维持单元以及一复位薄膜晶体管(T12)；所述上拉单元、所述下拉单元及所述下拉维持单元分别与第n级GOA单元的栅极信号输出端(G(n))电性连接；所述上拉控制单元及所述下拉单元与所述第n级GOA单元的栅极信号点(Q(n))电性连接，所述复位薄膜晶体管(T12)的栅极电性连接一复位信号端(RESET)，所述复位薄膜晶体管(T12)的源极电性连接一工作电压(VSSQ)，所述复位薄膜晶体管(T12)的漏极电性连接所述第n级GOA单元的栅极信号点(Q(n))；其中所述上拉控制单元包括一第一薄膜晶体管(T11)，其栅极电性连接一启动信号(STV)，漏极电性连接所述复位信号端(RESET)，源极电性连接所述第n级GOA单元的栅极信号点(Q(n))。
在本发明的一实施例中，所述上拉控制单元还包括：一第二薄膜晶体管(T22)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性连接第n级GOA单元的级传信号输出端ST(n)，漏极电性连接一时钟信号(CK)。
在本发明的一实施例中，所述上拉单元包括：一第三薄膜晶体管(T21)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性接所述第n级GOA单元的栅极信号输出端(G(n))，漏极电性连接一时钟信号(CK)。
在本发明的一实施例中，所述下拉单元包括：一第四薄膜晶体管(T41)，其栅极电性连接第n+m级GOA单元的栅极信号输出端，m为自然数，漏极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性连接一工作电压(VSSQ)；及一第五薄膜晶体管(T31)，其栅极连接第n+m级GOA单元的栅极信号输出端，漏极电性连接所述栅极信号输出端(G(n))，源极电性连接所述工作电压(VSSG)。
在本发明的一实施例中，所述下拉维持单元包括：一第六薄膜晶体管(T32)，其栅极电性连接第n级GOA单元的一节点(P(n))，源极及漏极分别电性连接所述栅极信号输出端(G(n))及工作电压(VSSQ)；一第七薄膜晶体管(T42)，其栅极电性连接所述节点(P(n))，源极及漏极分别电性连接所述第n级GOA单元的栅极信号点(Q(n))及工作电压(VSSQ)；一第八薄膜晶体管(T51)，其栅极电性连接一时钟信号(CK)，源极及漏极分别电性连接所述时钟信号(CK)及一第四薄膜晶体管(T53)的栅极；一第九薄膜晶体管(T53)，其源极及漏极分别电性连接所述时钟信号(CK)及所述节点(P(n))；一第十薄膜晶体管(T52)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极及漏极分别电性连接一工作电压(VSSG)及第四薄膜晶体管(T53)的栅极；及一第十一薄膜晶体管(T54)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极及漏极分别电性连接所述工作电压(VSSG)及所述节点(P(n))。
 有益效果
本发明的有益效果为：本发明GOA单元利用复位信号端的电位设计，实现减少起始级GOA单元的上拉控制单元的薄膜晶体管漏电的问题，也就是减少起始级GOA单元的栅源电压，使其和第n级GOA单元的栅源电压一致，因而能够防止在极端条件下所述起始级GOA单元失效，并提高器件的稳定性。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明用于提高器件稳定性的GOA单元的一第一优先实施例的一架构示意图。
图2是本发明用于提高器件稳定性的GOA单元的一第二优先实施例的一架构示意图。
 本发明的实施方式
以上对本发明实施例提供的液晶显示组件进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明。同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
请参照图1所示，为本发明GOA单元的一第一优选实施例的一架构示意图。本发明的GOA电路包括多个级联的GOA单元，其中第n级GOA单元对第n级水平扫描线的充电进行控制，所述第n级GOA单元包括一上拉控制单元2、一上拉单元3、一下拉单元4、一下拉维持单元5以及一复位薄膜晶体管T12，本发明将于下文详细说明各实施例上述各组件的细部构造、组装关系及其运作原理。
续参照图1所示，所述上拉单元3、所述下拉单元4及所述下拉维持单元5分别与第n级GOA单元的栅极信号输出端G(n)电性连接，而且所述上拉控制单元2及所述下拉单元4与所述第n级GOA单元的栅极信号点Q(n)电性连接。另外，所述复位薄膜晶体管T12的一栅极电性连接一复位信号端RESET，所述复位薄膜晶体管T12的一源极电性连接一工作电压VSSQ，所述复位薄膜晶体管T12的一漏极电性连接所述第n级GOA单元的栅极信号点Q(n)。
续参照图1所示，所述上拉控制单元2主要为栅极信号点Q(n)实现预充电，其中所述上拉控制单元2包括一第一薄膜晶体管T11及一第二薄膜晶体管T22，其中所述第一薄膜晶体管T11的一栅极电性连接一启动信号STV，所述第一薄膜晶体管T11的一漏极电性连接所述复位信号端RESET，所述第一薄膜晶体管T11的一源极电性连接所述第n级GOA单元的栅极信号点Q(n)，另外，所述第二薄膜晶体管T22的一栅极电性连接所述第n级GOA单元的栅极信号点Q(n)，所述第二薄膜晶体管T22的一源极电性连接第n级GOA单元的级传信号输出端ST(n)，所述所述第二薄膜晶体管T22的一漏极电性连接一时钟信号CK。值得一提的是，所述第二薄膜晶体管T22为信号下传电路，主要为控制下一级信号的打开及关闭。
续参照图1所示，所述上拉单元3主要为提高栅极信号输出端G(n)的一电位，其中所述上拉单元3包括一第三薄膜晶体管T21，其中所述第三薄膜晶体管T21的一栅极电性连接所述第n级GOA单元的栅极信号点Q(n)，所述第三薄膜晶体管T21的一源极电性接所述第n级GOA单元的栅极信号输出端G(n)，所述第三薄膜晶体管T21的一漏极电性连接一时钟信号CK。
续参照图1所示，所述下拉单元4主要为拉低栅极信号点Q(n)，并且让栅极信号输出端G(n)的电位提高，其中所述下拉单元4包括一第四薄膜晶体管T41及一第五薄膜晶体管T31，其中所述第四薄膜晶体管T41的一栅极电性连接第n+m级GOA单元的栅极信号输出端，例如：G(n+4)，其中m为自然数，所述第四薄膜晶体管T41的一漏极电性连接所述第n级GOA单元的栅极信号点Q(n)，所述第四薄膜晶体管T41的一源极电性连接一工作电压VSSQ，另外，所述第五薄膜晶体管T31的一栅极连接第n+m级GOA单元的栅极信号输出端，例如：G(n+4)，所述第五薄膜晶体管T31的一漏极电性连接所述栅极信号输出端G(n)，而且所述第五薄膜晶体管T31的一源极电性连接所述工作电压VSSG。
续参照图1所示，所述下拉维持单元5主要为控制栅极信号点Q(n)，并且让栅极信号输出端G(n)的电位维持在一电压值，其中所述下拉维持单元5包括一第六薄膜晶体管T32、一第七薄膜晶体管T42、一第八薄膜晶体管T51、一第九薄膜晶体管T53、一第十薄膜晶体管T52及一第十一薄膜晶体管T54，其中所述第六薄膜晶体管T32的一栅极电性连接第n级GOA单元的一节点P(n)，所述第六薄膜晶体管T32的一源极电性连接所述栅极信号输出端G(n)，所述第六薄膜晶体管T32的一漏极电性连接所述工作电压VSSQ；所述第七薄膜晶体管T42的一栅极电性连接所述节点P(n)，所述第七薄膜晶体管T42的一源极电性连接所述第n级GOA单元的栅极信号点Q(n)，所述第七薄膜晶体管T42的一漏极电性连接所述工作电压VSSQ；所述第八薄膜晶体管T51的一栅极电性连接一时钟信号CK，所述第八薄膜晶体管T51的一源极电性连接所述时钟信号CK，所述第八薄膜晶体管T51的一漏极电性连接所述第四薄膜晶体管T53的一栅极；所述第九薄膜晶体管T53的一源极电性连接所述时钟信号CK，所述第九薄膜晶体管T53的一漏极电性连接所述节点P(n)；所述第十薄膜晶体管T52的一栅极电性连接所述第n级GOA单元的栅极信号点Q(n)，所述第十薄膜晶体管T52的一源极电性连接一工作电压VSSG，所述第十薄膜晶体管T52的一漏极电性连接第四薄膜晶体管T53的栅极；所述第十一薄膜晶体管T54的一栅极电性连接所述第n级GOA单元的栅极信号点Q(n)，所述第十一薄膜晶体管T54的一源极电性连接所述工作电压VSSG，及所述第十一薄膜晶体管T54的一漏极电性连接所述节点P(n)。
依据上述的结构，现有的GOA电路为防止启动过电流保护(OCP)，器件中大电流有设置RESET电路及信号，GOA单元将复位信号端RESET的信号设计与所述启动信号STV同信号，在每次启动所述GOA单元时，通过复位信号端RESET/启动信号STV将栅极信号点Q(n)残留的信号拉至一低电位信号。进一步来说，首先将复位信号端RESET的信号接入GOA电路的起始级的GOA电路的源极(Source)，而且栅极(Gate)接入的信号仍然使用所述启动信号STV。所述启动信号STV和所述复位信号端RESET分别输入不同的信号。所述启动信号STV的低电位一般是所述工作电压VSSQ的低电位，所述复位信号端RESET一般为-8V，在本发明GOA单元中，将低电位设为工作电压VSSG的低电位-6V。这样就实现了起始级GOA单元的栅源电压Vgs及第n级GOA单元的栅源电压Vgs一致而为-2v的目的，因而能够可减轻在极端条件下，例如：长时间在高温或高压的环境下操作，起始级GOA单元失效的问题，并且提高器件的稳定性。
如上所述，本发明GOA单元利用复位信号端RESET的电位设计，实现减少起始级GOA单元的上拉控制单元的薄膜晶体管漏电的问题，也就是减少起始级GOA单元的栅源电压Vgs，使其和第n级GOA单元的栅源电压Vgs一致，因而能够防止在极端条件下所述起始级GOA单元失效，而能够提高器件的稳定性。
请参照图2所示，为本发明用于提高器件稳定性的GOA单元的一第二优先实施例的一架构示意图，其中的元件相似于本发明的第一优先实施例，并大致沿用相同元件名称及图号，所述第二优先实施例的差别特征在于：所述上拉控制单元2包括一第一薄膜晶体管T11，所述第一薄膜晶体管T11的一栅极电性连接一启动信号STV，所述第一薄膜晶体管T11的一漏极电性连接一负载电阻R，而且所述负载电阻R电性连接所述复位信号端RESET，所述第一薄膜晶体管T11的一源极电性连接所述第n级GOA单元的栅极信号点Q(n)。
依据上述的结构，将所述复位信号端RESET接入起始级GOA单元的源极，栅极(Gate)仍然使用启动信号STV，其中所述启动信号STV和所述复位信号端RESET分别输入不同的信号，并且更进一步地，改变所述复位信号端RESET的电阻电容延迟(RC delay)。也就是说，在实际电路中，G(n)通常产生的电阻电容延迟较大，所述启动信号STV外接的负载较小，电阻电容延迟较小，因此，可以通过在所述复位信号端RESET接入所述负载电阻R，用以增加所述复位信号端RESET的负载。
如上所述，本发明的第二优先实施例GOA单元同样能够利用复位信号端RESET的电位设计，实现减少起始级GOA单元的上拉控制单元的薄膜晶体管漏电的问题，也就是减少起始级GOA单元的栅源电压Vgs，使其和第n级GOA单元的栅源电压Vgs一致，因而能够防止在极端条件下所述起始级GOA单元失效，而能够提高器件的稳定性。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (15)

  1. 一种用于提高器件稳定性的GOA单元，其特征在于：所述GOA单元包括一上拉控制单元、一上拉单元、一下拉单元、一下拉维持单元以及一复位薄膜晶体管(T12)；
    所述上拉单元、所述下拉单元及所述下拉维持单元分别与第n级GOA单元的栅极信号输出端(G(n))电性连接；所述上拉控制单元及所述下拉单元与所述第n级GOA单元的栅极信号点(Q(n))电性连接，所述复位薄膜晶体管(T12)的栅极电性连接一复位信号端(RESET)，所述复位薄膜晶体管(T12)的源极电性连接一工作电压(VSSQ)，所述复位薄膜晶体管(T12)的漏极电性连接所述第n级GOA单元的栅极信号点(Q(n))；
    其中所述上拉控制单元包括一第一薄膜晶体管(T11)，其栅极电性连接一启动信号(STV)，漏极电性连接所述复位信号端(RESET)，源极电性连接所述第n级GOA单元的栅极信号点(Q(n))；
    其中所述下拉维持单元配置用以控制所述栅极信号点(Q(n))，并且让所述栅极信号输出端(G(n))的电位维持在一电压值。
  2. 如权利要求1所述的用于提高器件稳定性的GOA单元，其特征在于：所述上拉控制单元还包括：一第二薄膜晶体管(T22)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性连接第n级GOA单元的级传信号输出端(ST(n))，漏极电性连接一时钟信号(CK)。
  3. 如权利要求1所述的用于提高器件稳定性的GOA单元，其特征在于：所述上拉单元包括：一第三薄膜晶体管(T21)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性接所述第n级GOA单元的栅极信号输出端(G(n))，漏极电性连接一时钟信号(CK)。
  4. 如权利要求1所述的GOA单元，其特征在于：所述下拉单元包括：
    一第四薄膜晶体管(T41)，其栅极电性连接第n+m级GOA单元的栅极信号输出端，m为自然数，漏极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性连接一工作电压(VSSQ)；及
    一第五薄膜晶体管(T31)，其栅极连接第n+m级GOA单元的栅极信号输出端，漏极电性连接所述栅极信号输出端(G(n))，源极电性连接所述工作电压(VSSG)。
  5. 如权利要求1所述的GOA单元，其特征在于：所述下拉维持单元包括：
    一第六薄膜晶体管(T32)，其栅极电性连接第n级GOA单元的一节点(P(n))，源极及漏极分别电性连接所述栅极信号输出端(G(n))及工作电压(VSSQ)；
    一第七薄膜晶体管(T42)，其栅极电性连接所述节点(P(n))，源极及漏极分别电性连接所述第n级GOA单元的栅极信号点(Q(n))及工作电压(VSSQ)；
    一第八薄膜晶体管(T51)，其栅极电性连接一时钟信号(CK)，源极及漏极分别电性连接所述时钟信号(CK)及一第四薄膜晶体管(T53)的栅极；
    一第九薄膜晶体管(T53)，其源极及漏极分别电性连接所述时钟信号(CK)及所述节点(P(n))；
    一第十薄膜晶体管(T52)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极及漏极分别电性连接一工作电压(VSSG)及第四薄膜晶体管(T53)的栅极；及
    一第十一薄膜晶体管(T54)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极及漏极分别电性连接所述工作电压(VSSG)及所述节点(P(n))。
  6. 一种用于提高器件稳定性的GOA单元，其特征在于：所述GOA单元包括一上拉控制单元、一上拉单元、一下拉单元、一下拉维持单元以及一复位薄膜晶体管(T12)；
    所述上拉单元、所述下拉单元及所述下拉维持单元分别与第n级GOA单元的栅极信号输出端(G(n))电性连接；所述上拉控制单元及所述下拉单元与所述第n级GOA单元的栅极信号点(Q(n))电性连接，所述复位薄膜晶体管(T12)的栅极电性连接一复位信号端(RESET)，所述复位薄膜晶体管(T12)的源极电性连接一工作电压(VSSQ)，所述复位薄膜晶体管(T12)的漏极电性连接所述第n级GOA单元的栅极信号点(Q(n))；
    其中所述上拉控制单元包括一第一薄膜晶体管(T11)，其栅极电性连接一启动信号(STV)，漏极电性连接一负载电阻而且所述负载电阻电性连接所述复位信号端(RESET)，源极电性连接所述第n级GOA单元的栅极信号点(Q(n))。
  7. 如权利要求6所述的用于提高器件稳定性的GOA单元，其特征在于：所述上拉控制单元还包括：一第二薄膜晶体管(T22)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性连接第n级GOA单元的级传信号输出端(ST(n))，漏极电性连接一时钟信号(CK)。
  8. 如权利要求6所述的用于提高器件稳定性的GOA单元，其特征在于：所述上拉单元包括：一第三薄膜晶体管(T21)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性接所述第n级GOA单元的栅极信号输出端(G(n))，漏极电性连接一时钟信号(CK)。
  9. 如权利要求6所述的GOA单元，其特征在于：所述下拉单元包括：
    一第四薄膜晶体管(T41)，其栅极电性连接第n+m级GOA单元的栅极信号输出端，m为自然数，漏极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性连接一工作电压(VSSQ)；及
    一第五薄膜晶体管(T31)，其栅极连接第n+m级GOA单元的栅极信号输出端，漏极电性连接所述栅极信号输出端(G(n))，源极电性连接所述工作电压(VSSG)。
  10. 如权利要求6所述的GOA单元，其特征在于：所述下拉维持单元包括：
    一第六薄膜晶体管(T32)，其栅极电性连接第n级GOA单元的一节点(P(n))，源极及漏极分别电性连接所述栅极信号输出端(G(n))及工作电压(VSSQ)；
    一第七薄膜晶体管(T42)，其栅极电性连接所述节点(P(n))，源极及漏极分别电性连接所述第n级GOA单元的栅极信号点(Q(n))及工作电压(VSSQ)；
    一第八薄膜晶体管(T51)，其栅极电性连接一时钟信号(CK)，源极及漏极分别电性连接所述时钟信号(CK)及一第四薄膜晶体管(T53)的栅极；
    一第九薄膜晶体管(T53)，其源极及漏极分别电性连接所述时钟信号(CK)及所述节点(P(n))；
    一第十薄膜晶体管(T52)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极及漏极分别电性连接一工作电压(VSSG)及第四薄膜晶体管(T53)的栅极；及
    一第十一薄膜晶体管(T54)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极及漏极分别电性连接所述工作电压(VSSG)及所述节点(P(n))。
  11. 一种用于提高器件稳定性的GOA单元，其特征在于：所述GOA单元包括一上拉控制单元、一上拉单元、一下拉单元、一下拉维持单元以及一复位薄膜晶体管(T12)；
    所述上拉单元、所述下拉单元及所述下拉维持单元分别与第n级GOA单元的栅极信号输出端(G(n))电性连接；所述上拉控制单元及所述下拉单元与所述第n级GOA单元的栅极信号点(Q(n))电性连接，所述复位薄膜晶体管(T12)的栅极电性连接一复位信号端(RESET)，所述复位薄膜晶体管(T12)的源极电性连接一工作电压(VSSQ)，所述复位薄膜晶体管(T12)的漏极电性连接所述第n级GOA单元的栅极信号点(Q(n))；
    其中所述上拉控制单元包括一第一薄膜晶体管(T11)，其栅极电性连接一启动信号(STV)，漏极电性连接所述复位信号端(RESET)，源极电性连接所述第n级GOA单元的栅极信号点(Q(n))。
  12. 如权利要求11所述的用于提高器件稳定性的GOA单元，其特征在于：所述上拉控制单元还包括：一第二薄膜晶体管(T22)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性连接第n级GOA单元的级传信号输出端(ST(n))，漏极电性连接一时钟信号(CK)。
  13. 如权利要求11所述的用于提高器件稳定性的GOA单元，其特征在于：所述上拉单元包括：一第三薄膜晶体管(T21)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性接所述第n级GOA单元的栅极信号输出端(G(n))，漏极电性连接一时钟信号(CK)。
  14. 如权利要求11所述的GOA单元，其特征在于：所述下拉单元包括：
    一第四薄膜晶体管(T41)，其栅极电性连接第n+m级GOA单元的栅极信号输出端，m为自然数，漏极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极电性连接一工作电压(VSSQ)；及
    一第五薄膜晶体管(T31)，其栅极连接第n+m级GOA单元的栅极信号输出端，漏极电性连接所述栅极信号输出端(G(n))，源极电性连接所述工作电压(VSSG)。
  15. 如权利要求1所述的GOA单元，其特征在于：所述下拉维持单元包括：
    一第六薄膜晶体管(T32)，其栅极电性连接第n级GOA单元的一节点(P(n))，源极及漏极分别电性连接所述栅极信号输出端(G(n))及工作电压(VSSQ)；
    一第七薄膜晶体管(T42)，其栅极电性连接所述节点(P(n))，源极及漏极分别电性连接所述第n级GOA单元的栅极信号点(Q(n))及工作电压(VSSQ)；
    一第八薄膜晶体管(T51)，其栅极电性连接一时钟信号(CK)，源极及漏极分别电性连接所述时钟信号(CK)及一第四薄膜晶体管(T53)的栅极；
    一第九薄膜晶体管(T53)，其源极及漏极分别电性连接所述时钟信号(CK)及所述节点(P(n))；
    一第十薄膜晶体管(T52)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极及漏极分别电性连接一工作电压(VSSG)及第四薄膜晶体管(T53)的栅极；及
    一第十一薄膜晶体管(T54)，其栅极电性连接所述第n级GOA单元的栅极信号点(Q(n))，源极及漏极分别电性连接所述工作电压(VSSG)及所述节点(P(n))。
PCT/CN2019/070555 2018-10-11 2019-01-07 用于提高器件稳定性的goa单元 Ceased WO2020073548A1 (zh)

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