WO2020072867A1 - Procédés, appareil et systèmes pour une épitaxie à distance à l'aide de graphène cousu - Google Patents

Procédés, appareil et systèmes pour une épitaxie à distance à l'aide de graphène cousu

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Publication number
WO2020072867A1
WO2020072867A1 PCT/US2019/054639 US2019054639W WO2020072867A1 WO 2020072867 A1 WO2020072867 A1 WO 2020072867A1 US 2019054639 W US2019054639 W US 2019054639W WO 2020072867 A1 WO2020072867 A1 WO 2020072867A1
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WO
WIPO (PCT)
Prior art keywords
layer
substrate
target substrate
epitaxial
release layer
Prior art date
Application number
PCT/US2019/054639
Other languages
English (en)
Inventor
Kyusang Lee
Wei Kong
Jeehwan Kim
Original Assignee
Massachusetts Institute Of Technology
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Filing date
Publication date
Application filed by Massachusetts Institute Of Technology filed Critical Massachusetts Institute Of Technology
Publication of WO2020072867A1 publication Critical patent/WO2020072867A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B32/00—Carbon; Compounds thereof
    • C01B32/15—Nano-sized carbon materials
    • C01B32/182—Graphene
    • C01B32/194—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/02444—Carbon, e.g. diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02499—Monolayers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02389—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02485—Other chalcogenide semiconducting materials not being oxides, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides

Definitions

  • Advanced GaN-based electronics rely heavily on the material quality of GaN templates as the initial building blocks.
  • the characteristics of a GaN template such as the dislocation density and surface roughness, affect the performance of active devices epitaxially grown on top of the GaN template.
  • heteroepitaxy of GaN on foreign substrates such as sapphire and Si, is common practice. Even though these foreign substrates (e.g., sapphire and Si) are available in large diameters, the lattice and thermal expansion coefficient mismatch of these substrates to GaN can lead to complexity in the growth process and excess dislocation density.
  • the removal of epitaxial GaN thin films from bulk/foreign substrates is usually very challenging. Existing liftoff processes involving
  • photoelectrochemical etching, mechanical spalling, and laser interface melting suffer from either slow processing speed or significant surface roughening/cracking, thereby limiting the process yield and practicality of reusing the substrate.
  • GaN on a monolayer graphene coated high quality GaN template through remote epitaxy allows for the reuse of costly GaN templates.
  • the processing wafer area is usually equal to or smaller than the diameter of epitaxial graphene area, since the reuse of the substrate is prohibited if homoepitaxy of GaN directly on GaN without graphene occurs. Wafer size scaling is therefore limited by the available SiC substrate that is used to fabricate epitaxial graphene.
  • Embodiments of the present invention include apparatus, systems, and methods for remote epitaxy using stitched graphene.
  • a method of fabricating a semiconductor device comprises disposing a first two-dimensional (2D) layer onto a target substrate, disposing a second 2D layer onto the target substrate and adjacent to the first 2D layer so as to form at least a portion of a release layer, forming a first epitaxial layer on the release layer, and removing the first epitaxial layer from the release layer.
  • 2D two-dimensional
  • a method of fabricating a semiconductor device includes forming a first 2D layer on a first substrate and transferring the first 2D layer onto a target substrate. The method also includes forming a second 2D layer on a second substrate and disposing the second 2D layer onto the target substrate and adjacent to the first 2D layer so as to form at least a portion of a release layer. The method further includes forming a first epitaxial layer on the release layer removing the first epitaxial layer from the release layer.
  • FIGS. 1A-1D illustrate a method of forming a release layer for fabricating
  • FIGS. 2A-2C illustrate a method of fabricating semiconductor devices using a stitched release layer, in accordance with some embodiments.
  • FIG. 3A shows a schematic of a release layer that can be used for fabricating semiconductors via remote epitaxy, in accordance with certain embodiments.
  • FIG. 3B shows a schematic of a stitched release layer including round 2D layers, in accordance with some embodiments.
  • FIGS. 4A-4E illustrate a method of fabricating semiconductor devices on a reusable platform including a stitched release layer, in accordance with certain embodiments.
  • a growth substrate also referred to as a target substrate
  • a release layer including monolayer graphene by stitching graphene.
  • the stitched graphene can be transferred from a different SiC substrate.
  • the release layer therefore can have a larger diameter compared to graphene grown on a single SiC substrate.
  • Remote epitaxy can then be performed on the release layer. Due to the large diameter of the release layer, a large-area epitaxial layer (e.g., GaN) can be fabricated.
  • a large-area epitaxial layer e.g., GaN
  • the epitaxial thin film can be precisely and rapidly exfoliated from the substrate, with the atomic flatness at the released surface mimicking the morphology of the release layer.
  • Such a high quality interface allows for the reuse of the substrate without post processing, as well as the bonding of the epitaxial thin film to any foreign substrate having a flat surface.
  • This technique also allows for novel device design, including the bonding of an active device to an electrically and/or thermally conductive substrate for improved thermal dissipation, serial electrical conductance, and/or current spreading characteristics.
  • epitaxial graphene can be used as the material for the release layer and can be produced by sublimation of Si with SiC substrates.
  • hexagonal boron nitride can be used as the material for the release layer.
  • the release layer comprises a transition metal dichalcogenide (TMD), for example, having the formula MX 2 , where M is a transition metal atom (e.g., Mo, W, etc.) and X is a chalcogen atom (e.g., S, Se, or Te).
  • TMD transition metal dichalcogenide
  • MX a chalcogen atom
  • the release layer comprises M0S2 or WSe 2 .
  • each graphene layer is individually transferred and stitched onto a high quality GaN template, thereby covering the entire GaN template surface.
  • epitaxial GaN thin films are then deposited on the stitched graphene coated GaN template.
  • the thin film GaN is subsequently, in certain embodiments, exfoliated and transferred to a foreign substrate.
  • the stitched graphene coated GaN template is reused for the next cycle of GaN growth, thereby reducing the fabrication cost.
  • FIGS. 1A-1D illustrate a method 100 of forming a release layer 135 for fabricating semiconductor devices.
  • the method 100 includes, as illustrated in FIG. 1A, forming a first two-dimensional (2D) layer 110 on a first substrate (underneath first 2D layer 110, not shown in FIG. 1A).
  • first 2D layer 110 as formed has a round shape.
  • first 2D layer 110 can have any other appropriate shape (e.g., the same shape as the first substrate).
  • FIG. 1B shows an optional step of cleaving first 2D layer 110 into a different shape, referred to as a cleaved first 2D layer 120.
  • first 2D layer 110 as fabricated can have a round shape and cleaved first 2D layer 120 can have a rectangular shape (including square shape).
  • Cleaved first 2D layer 120 can have any other appropriate shape, such as diamond and hexagon.
  • First 2D layer 110 can be processed into different shapes via various methods, such as laser cutting, water jet cutting, and die saw cutting, among others.
  • cleaved first 2D layer 120 is transferred to a target substrate 140 (now referred to as 2D layer 120(1)). Additional 2D layers 120(2)-120(9) are also fabricated and transferred to target substrate 140.
  • a second 2D layer 120(2) can be fabricated on a second substrate, transferred to target substrate 140, and disposed adjacent to first 2D layer 120(1).
  • the same substrate can be used to fabricate multiple 2D layers.
  • These 2D layers 120(1)-120(9) are disposed adjacent to each other to form a preliminary release layer 130, i.e., these 2D layers 120(1)-120(9) are stitched together to form a single piece of 2D layer.
  • 2D layers 120(1)-120(9) can have the same shape (e.g., rectangular, square, hexagon, etc.). In another example, 2D layers 120(1)- 120(9) can have different shapes. In one example, 2D layers 120(1)-120(9) can form a 2D array. In another example, 2D layers 120(1)-120(9) can form a 1D sequence. The total number of 2D layers 120 can be, for example, 2 to 100, including any values and sub ranges in between.
  • each 2D layer in the array of 2D layers 120(1)-120(9) are coupled to an adjacent 2D layer at the edge.
  • at least some of the 2D layers are overlapping with adjacent 2D layers to reinforce the stitching.
  • FIG. 1D shows another optional step of modifying the shape of preliminary release layer 130 into a release layer 135.
  • preliminary release layer 130 can be rectangular or square, and release layer 135 can be round.
  • the shape of release layer 135 can depend on, for example, the desired shape of epitaxial layers to be fabricated on release layer 135.
  • first 2D layer 110 can be made of graphene, in which case first 2D layer 110 is also referred to as graphene layer 110.
  • Graphene layer 110 can be fabricated on the first substrate via various methods.
  • graphene layer 110 can include an epitaxial graphene with a single-crystalline orientation and the substrate can include a (0001) 4H-SiC wafer with a silicon surface.
  • the fabrication of graphene layer 110 can include multistep annealing steps.
  • a first annealing step can be performed in H 2 gas for surface etching and vicinalization, and a second annealing step can be performed in Ar for graphitization at high temperature (e.g., about 1,575 °C).
  • graphene layer 110 can be grown on the first substrate via a chemical vapor deposition (CVD) process.
  • the first substrate can include a nickel substrate or a copper substrate.
  • the substrate can include an insulating substrate of Si0 2 , Hf0 2 , Al 2 0 3 , Si 3 N 4 , and practically any other high temperature compatible planar material by CVD.
  • the first substrate can be any substrate that can hold graphene layer 110 and the fabrication can include a mechanical exfoliation process.
  • the first substrate can function as a temporary holder for graphene layer 110.
  • a carrier film can be attached to graphene layer 110.
  • the carrier film can include a thick film of Poly(methyl methacrylate) (PMMA) or a thermal release tape and the attachment can be achieved via a spin-coating process.
  • PMMA Poly(methyl methacrylate)
  • the carrier film can be dissolved (e.g., in acetone) for further fabrication of the epilayer on graphene layer 110.
  • a stamp layer including an elastomeric material such as polydimethylsiloxane (PDMS) can be attached to graphene layer 110 and the first substrate can be etched away, leaving the combination of the stamp layer and graphene layer 110.
  • PDMS polydimethylsiloxane
  • the stamp layer and graphene layer 110 are placed on target substrate 140, the stamp layer can be removed by mechanical detachment, producing a clean surface of graphene layer 110 for further processing.
  • a self-release transfer method can be used to transfer graphene layer 110 to target substrate 140.
  • a self-release layer is first spun- cast over the graphene layer 110.
  • An elastomeric stamp is then placed in conformal contact with the self-release layer.
  • the first substrate can be etched away to leave the combination of the stamp layer, the self-release layer, and the graphene layer. After this combination is placed on target substrate 140, the stamp layer can be removed mechanically and the self release layer can be dissolved under mild conditions in a suitable solvent.
  • the release layer can include polystyrene (PS), poly(isobutylene) (PIB), and/or Teflon AF (poly[4,5-difluoro- 2,2-bis(trifluoromethyl)-l,3-dioxole-co-tetrafluoroethylene]).
  • PS polystyrene
  • PIB poly(isobutylene)
  • Teflon AF poly[4,5-difluoro- 2,2-bis(trifluoromethyl)-l,3-dioxole-co-tetrafluoroethylene]
  • FIGS. 2A-2C illustrate an example of a method 200 of fabricating an epitaxial layer 230 using a stitched release layer 220.
  • the epitaxial layer can comprise, for example, a semiconductor material.
  • semiconductor materials include, but are not limited to III-V semiconductors (which can be, for example, III-N semiconductors, III-P semiconductors, or III-As semiconductors, examples of which include GaN, A1N, InN, GaP, A1P, InP, AlAs, and GaAs); II- VI semiconductors; and Ge.
  • the semiconductor comprises GaN.
  • release layer 220 is disposed on a target substrate 210.
  • epitaxial layer 230 is fabricated via remote epitaxy, in which the epitaxial growth of epitaxial layer 230 is seeded by target substrate 210.
  • target substrate 210 and epitaxial layer 230 can include the same material, such as GaN or any other appropriate material.
  • target substrate 210 comprises GaN, such as GaN fabricated via hydride vapor phase epitaxy (HVPE).
  • release layer 220 comprises a plurality of sheets of graphene.
  • epitaxial layer 230 comprises GaN, optionally epitaxial GaN such as GaN formed by remote epitaxy.
  • the seeding of epitaxial layer 230 by target substrate 210 can occur, in accordance with certain embodiments, even when there is not direct contact between epitaxial layer 230 and target substrate 210.
  • target substrate 210 may have a potential field (e.g., created by van der Waals forces and/or other atomic or molecular forces) and release layer 220 may be so thin (e.g., in cases where the release layer comprises laterally stitched portions of monolayer graphene) that the potential field of target substrate 210 reaches beyond release layer 220 an interacts with the region within which epitaxial layer 230 is formed.
  • the potential field from target substrate 210 affects the growth of epitaxial layer 230.
  • release layer 220 can have various shapes.
  • FIG. 2B shows a release layer 220a having a round shape.
  • FIG. 2C shows a release layer 220b having a pseudo-square shape.
  • FIG. 3A shows a schematic of an example of a stitched release layer 300 for fabricating semiconductor devices via remote epitaxy.
  • release layer 300 includes a collection of 2D layers 310, and adjacent 2D layers are overlapping with each other to reinforce the stitching.
  • a first 2D layer 310(1) (which can be, in some embodiments, a monolayer of graphene) is overlapping, on the edge, with a second 2D layer 310(2) (which can be, in some embodiments, a second monolayer of graphene) to form an overlap region 315 (in which, in some embodiments, two monolayers of graphene overlap).
  • the ratio of the area of the overlap region 315 with respect to the area of the first 2D layer 310(1) can be, for example, about 1% to about 90% (e.g., about 1%, about 2%, about 5%, about 10%, about 20%, about 30%, about 40%, about 50%, about 60%, about 70%, about 80%, or about 90%, including any values and sub ranges in between).
  • FIG. 3B shows a schematic of a release layer 301 including round 2D layers 330a- 330d.
  • Another round 2D layer 340 is disposed on the gap formed by the array of the four 2D layers 330a-330d. Additional 2D layers can be added similarly to increase the area of the resulting release layer 301.
  • the 2D layer 340 is also round.
  • the 2D layer 340 can have any other shape, as long as the 2D layer 340 can substantially cover the gap between adjacent 2D layers 330a-330d.
  • FIGS. 4A-4E illustrate one example of a method 400 of fabricating semiconductor devices using a reusable platform including a stitched release layer.
  • the method 400 starts with a substrate 410 (e.g., a GaN template) as illustrated in FIG. 4A, followed by forming a release layer 420 (e.g., comprising stitched graphene) on substrate 410 as illustrated in FIG. 4B.
  • substrate 410 can include GaN fabricated via hydride vapor phase epitaxy (HVPE).
  • release layer 420 can be formed directly on substrate 410 (e.g., via the method 100 illustrated in FIGS. 1A-1D).
  • release layer 420 can be formed on another substrate and then transferred to substrate 410.
  • an epitaxial layer 430 is fabricated on the release layer 420 via remote epitaxy, i.e., seeded by substrate 410.
  • epitaxial layer 430 can include a GaN thin film, and substrate 410 includes GaN as well.
  • a handler layer 440 is formed on epitaxial layer 430 to facilitate the removal and transfer of epitaxial layer 430.
  • the platform including substrate 410 and release layer 420 can be reused to grow another epitaxial layer (e.g., via reuse step 460 in FIGS. 4C-4D).
  • the removed epitaxial layer 430 is disposed on a host substrate 450 for further processing, such as in forming a functional device, such as LEDs, lasers, transistors, and/or solar cells, among others. More information about layer transfer technique can be found in PCT Patent Application No.
  • inventive embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed.
  • inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein.
  • embodiments of designing and making the technology disclosed herein may be implemented using hardware, software or a combination thereof.
  • the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.
  • a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a Personal Digital Assistant (PDA), a smart phone or any other suitable portable or fixed electronic device.
  • PDA Personal Digital Assistant
  • a computer may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in another audible format.
  • Such computers may be interconnected by one or more networks in any suitable form, including a local area network or a wide area network, such as an enterprise network, an intelligent network (IN) or the Internet.
  • networks may be based on any suitable technology and may operate according to any suitable protocol and may include wireless networks, wired networks or fiber optic networks.
  • the various methods or processes outlined herein may be coded as software that is executable on one or more processors that employ any one of a variety of operating systems or platforms. Additionally, such software may be written using any of a number of suitable programming languages and/or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework or virtual machine.
  • inventive concepts may be embodied as a computer readable storage medium (or multiple computer readable storage media) (e.g., a computer memory, one or more floppy discs, compact discs, optical discs, magnetic tapes, flash memories, circuit configurations in Field Programmable Gate Arrays or other semiconductor devices, or other non-transitory media or tangible computer storage media) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement the various embodiments of the invention discussed above.
  • the computer readable medium or media can be transportable, such that the program or programs stored thereon can be loaded onto one or more different computers or other processors to implement various aspects of the present invention as discussed above.
  • program or“software” are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that can be employed to program a computer or other processor to implement various aspects of embodiments as discussed above. Additionally, it should be appreciated that according to one aspect, one or more computer programs that when executed perform methods of the present invention need not reside on a single computer or processor, but may be distributed in a modular fashion amongst a number of different computers or processors to implement various aspects of the present invention.
  • Computer-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices.
  • program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types.
  • functionality of the program modules may be combined or distributed as desired in various embodiments.
  • data structures may be stored in computer-readable media in any suitable form.
  • data structures may be shown to have fields that are related through location in the data structure. Such relationships may likewise be achieved by assigning storage for the fields with locations in a computer-readable medium that convey relationships between the fields.
  • any suitable mechanism may be used to establish a relationship between information in fields of a data structure, including through the use of pointers, tags or other mechanisms that establish relationships between data elements.
  • inventive concepts may be embodied as one or more methods, of which examples have been provided.
  • the acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.
  • a reference to“A and/or B”, when used in conjunction with open-ended language such as“comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.
  • “or” should be understood to have the same meaning as“and/or” as defined above.
  • “or” or“and/or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as“only one of’ or“exactly one of,” or, when used in the claims,“consisting of,” will refer to the inclusion of exactly one element of a number or list of elements.
  • the phrase“at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements.
  • This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase“at least one” refers, whether related or unrelated to those elements specifically identified.
  • “at least one of A and B” can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another

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Abstract

L'invention concerne un appareil, des systèmes et des procédés d'épitaxie à distance à l'aide de multiples couches 2D, consistant à : disposer une première couche bidimensionnelle (2D) sur un substrat cible, disposer une seconde couche 2D sur le substrat cible et adjacente à la première couche 2D de façon à former au moins une partie d'une couche de libération, former une première couche épitaxiale sur la couche de libération, et retirer la première couche épitaxiale de la couche de libération.
PCT/US2019/054639 2018-10-05 2019-10-04 Procédés, appareil et systèmes pour une épitaxie à distance à l'aide de graphène cousu WO2020072867A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113421865A (zh) * 2021-06-21 2021-09-21 南通大学 一种氮化镓基器件用散热衬底及其制备方法
EP4158685A4 (fr) * 2020-05-29 2024-10-09 The Government Of The Us Secretary Of The Navy Transfert de matériau semi-conducteur de nitrure du groupe iii à grande surface et de dispositifs vers des substrats arbitraires

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